From: John Garry <john.garry@huawei.com> To: <jolsa@redhat.com>, <ak@linux.intel.com>, <peterz@infradead.org>, <mingo@redhat.com>, <acme@kernel.org>, <alexander.shishkin@linux.intel.com>, <namhyung@kernel.org>, <wcohen@redhat.com>, <will.deacon@arm.com>, <ganapatrao.kulkarni@cavium.com> Cc: <linuxarm@huawei.com>, <linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <zhangshaokun@hisilicon.com>, "John Garry" <john.garry@huawei.com> Subject: [PATCH v3 09/11] perf vendor events arm64: fixup ThunderX2 to use recommended events Date: Thu, 8 Mar 2018 18:58:34 +0800 [thread overview] Message-ID: <1520506716-197429-10-git-send-email-john.garry@huawei.com> (raw) In-Reply-To: <1520506716-197429-1-git-send-email-john.garry@huawei.com> This patch fixes the Cavium ThunderX2 JSON to use event definitions from the ARMv8 recommended events. Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com> Signed-off-by: John Garry <john.garry@huawei.com> --- .../arch/arm64/cavium/thunderx2/core-imp-def.json | 50 +++++----------------- 1 file changed, 10 insertions(+), 40 deletions(-) diff --git a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json index 2db45c4..bc03c06 100644 --- a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json +++ b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json @@ -1,62 +1,32 @@ [ { - "PublicDescription": "Attributable Level 1 data cache access, read", - "EventCode": "0x40", - "EventName": "l1d_cache_rd", - "BriefDescription": "L1D cache read", + "ArchStdEvent": "L1D_CACHE_RD", }, { - "PublicDescription": "Attributable Level 1 data cache access, write ", - "EventCode": "0x41", - "EventName": "l1d_cache_wr", - "BriefDescription": "L1D cache write", + "ArchStdEvent": "L1D_CACHE_WR", }, { - "PublicDescription": "Attributable Level 1 data cache refill, read", - "EventCode": "0x42", - "EventName": "l1d_cache_refill_rd", - "BriefDescription": "L1D cache refill read", + "ArchStdEvent": "L1D_CACHE_REFILL_RD", }, { - "PublicDescription": "Attributable Level 1 data cache refill, write", - "EventCode": "0x43", - "EventName": "l1d_cache_refill_wr", - "BriefDescription": "L1D refill write", + "ArchStdEvent": "L1D_CACHE_REFILL_WR", }, { - "PublicDescription": "Attributable Level 1 data TLB refill, read", - "EventCode": "0x4C", - "EventName": "l1d_tlb_refill_rd", - "BriefDescription": "L1D tlb refill read", + "ArchStdEvent": "L1D_TLB_REFILL_RD", }, { - "PublicDescription": "Attributable Level 1 data TLB refill, write", - "EventCode": "0x4D", - "EventName": "l1d_tlb_refill_wr", - "BriefDescription": "L1D tlb refill write", + "ArchStdEvent": "L1D_TLB_REFILL_WR", }, { - "PublicDescription": "Attributable Level 1 data or unified TLB access, read", - "EventCode": "0x4E", - "EventName": "l1d_tlb_rd", - "BriefDescription": "L1D tlb read", + "ArchStdEvent": "L1D_TLB_RD", }, { - "PublicDescription": "Attributable Level 1 data or unified TLB access, write", - "EventCode": "0x4F", - "EventName": "l1d_tlb_wr", - "BriefDescription": "L1D tlb write", + "ArchStdEvent": "L1D_TLB_WR", }, { - "PublicDescription": "Bus access read", - "EventCode": "0x60", - "EventName": "bus_access_rd", - "BriefDescription": "Bus access read", + "ArchStdEvent": "BUS_ACCESS_RD", }, { - "PublicDescription": "Bus access write", - "EventCode": "0x61", - "EventName": "bus_access_wr", - "BriefDescription": "Bus access write", + "ArchStdEvent": "BUS_ACCESS_WR", } ] -- 1.9.1
WARNING: multiple messages have this Message-ID (diff)
From: john.garry@huawei.com (John Garry) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 09/11] perf vendor events arm64: fixup ThunderX2 to use recommended events Date: Thu, 8 Mar 2018 18:58:34 +0800 [thread overview] Message-ID: <1520506716-197429-10-git-send-email-john.garry@huawei.com> (raw) In-Reply-To: <1520506716-197429-1-git-send-email-john.garry@huawei.com> This patch fixes the Cavium ThunderX2 JSON to use event definitions from the ARMv8 recommended events. Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com> Signed-off-by: John Garry <john.garry@huawei.com> --- .../arch/arm64/cavium/thunderx2/core-imp-def.json | 50 +++++----------------- 1 file changed, 10 insertions(+), 40 deletions(-) diff --git a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json index 2db45c4..bc03c06 100644 --- a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json +++ b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json @@ -1,62 +1,32 @@ [ { - "PublicDescription": "Attributable Level 1 data cache access, read", - "EventCode": "0x40", - "EventName": "l1d_cache_rd", - "BriefDescription": "L1D cache read", + "ArchStdEvent": "L1D_CACHE_RD", }, { - "PublicDescription": "Attributable Level 1 data cache access, write ", - "EventCode": "0x41", - "EventName": "l1d_cache_wr", - "BriefDescription": "L1D cache write", + "ArchStdEvent": "L1D_CACHE_WR", }, { - "PublicDescription": "Attributable Level 1 data cache refill, read", - "EventCode": "0x42", - "EventName": "l1d_cache_refill_rd", - "BriefDescription": "L1D cache refill read", + "ArchStdEvent": "L1D_CACHE_REFILL_RD", }, { - "PublicDescription": "Attributable Level 1 data cache refill, write", - "EventCode": "0x43", - "EventName": "l1d_cache_refill_wr", - "BriefDescription": "L1D refill write", + "ArchStdEvent": "L1D_CACHE_REFILL_WR", }, { - "PublicDescription": "Attributable Level 1 data TLB refill, read", - "EventCode": "0x4C", - "EventName": "l1d_tlb_refill_rd", - "BriefDescription": "L1D tlb refill read", + "ArchStdEvent": "L1D_TLB_REFILL_RD", }, { - "PublicDescription": "Attributable Level 1 data TLB refill, write", - "EventCode": "0x4D", - "EventName": "l1d_tlb_refill_wr", - "BriefDescription": "L1D tlb refill write", + "ArchStdEvent": "L1D_TLB_REFILL_WR", }, { - "PublicDescription": "Attributable Level 1 data or unified TLB access, read", - "EventCode": "0x4E", - "EventName": "l1d_tlb_rd", - "BriefDescription": "L1D tlb read", + "ArchStdEvent": "L1D_TLB_RD", }, { - "PublicDescription": "Attributable Level 1 data or unified TLB access, write", - "EventCode": "0x4F", - "EventName": "l1d_tlb_wr", - "BriefDescription": "L1D tlb write", + "ArchStdEvent": "L1D_TLB_WR", }, { - "PublicDescription": "Bus access read", - "EventCode": "0x60", - "EventName": "bus_access_rd", - "BriefDescription": "Bus access read", + "ArchStdEvent": "BUS_ACCESS_RD", }, { - "PublicDescription": "Bus access write", - "EventCode": "0x61", - "EventName": "bus_access_wr", - "BriefDescription": "Bus access write", + "ArchStdEvent": "BUS_ACCESS_WR", } ] -- 1.9.1
next prev parent reply other threads:[~2018-03-08 11:00 UTC|newest] Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-03-08 10:58 [PATCH v3 00/11] perf events patches for improved ARM64 support John Garry 2018-03-08 10:58 ` John Garry 2018-03-08 10:58 ` [PATCH v3 01/11] perf vendor events: drop incomplete multiple mapfile support John Garry 2018-03-08 10:58 ` John Garry 2018-03-20 6:21 ` [tip:perf/core] perf vendor events: Drop " tip-bot for John Garry 2018-03-08 10:58 ` [PATCH v3 02/11] perf vendor events: fix error code in json_events() John Garry 2018-03-08 10:58 ` John Garry 2018-03-20 6:21 ` [tip:perf/core] perf vendor events: Fix " tip-bot for John Garry 2018-03-08 10:58 ` [PATCH v3 03/11] perf vendor events: drop support for unused topic directories John Garry 2018-03-08 10:58 ` John Garry 2018-03-20 6:22 ` [tip:perf/core] perf vendor events: Drop " tip-bot for John Garry 2018-03-08 10:58 ` [PATCH v3 04/11] perf vendor events: add support for pmu events vendor subdirectory John Garry 2018-03-08 10:58 ` John Garry 2018-03-12 18:28 ` Arnaldo Carvalho de Melo 2018-03-12 18:28 ` Arnaldo Carvalho de Melo 2018-03-13 9:36 ` John Garry 2018-03-13 9:36 ` John Garry 2018-03-14 17:10 ` [PATCH] perf vendor events: fix processing for xfs John Garry 2018-03-14 17:42 ` Sukadev Bhattiprolu 2018-03-14 18:53 ` Arnaldo Carvalho de Melo 2018-03-14 19:39 ` John Garry 2018-03-14 20:26 ` Arnaldo Carvalho de Melo 2018-03-14 20:58 ` John Garry 2018-03-20 6:22 ` [tip:perf/core] perf vendor events: Add support for pmu events vendor subdirectory tip-bot for John Garry 2018-03-08 10:58 ` [PATCH v3 05/11] perf vendor events arm64: Relocate ThunderX2 JSON to cavium subdirectory John Garry 2018-03-08 10:58 ` John Garry 2018-03-20 6:23 ` [tip:perf/core] " tip-bot for John Garry 2018-03-08 10:58 ` [PATCH v3 06/11] perf vendor events arm64: Relocate Cortex A53 JSONs to arm subdirectory John Garry 2018-03-08 10:58 ` John Garry 2018-03-20 6:23 ` [tip:perf/core] " tip-bot for John Garry 2018-03-08 10:58 ` [PATCH v3 07/11] perf vendor events: add support for arch standard events John Garry 2018-03-08 10:58 ` John Garry 2018-03-20 6:24 ` [tip:perf/core] perf vendor events: Add " tip-bot for John Garry 2018-03-08 10:58 ` [PATCH v3 08/11] perf vendor events arm64: add armv8-recommended.json John Garry 2018-03-08 10:58 ` John Garry 2018-03-20 6:24 ` [tip:perf/core] perf vendor events arm64: Add armv8-recommended.json tip-bot for John Garry 2018-03-08 10:58 ` John Garry [this message] 2018-03-08 10:58 ` [PATCH v3 09/11] perf vendor events arm64: fixup ThunderX2 to use recommended events John Garry 2018-03-09 14:36 ` Ganapatrao Kulkarni 2018-03-09 14:36 ` Ganapatrao Kulkarni 2018-03-20 6:25 ` [tip:perf/core] perf vendor events arm64: Fixup " tip-bot for John Garry 2018-03-08 10:58 ` [PATCH v3 10/11] perf vendor events arm64: fixup A53 " John Garry 2018-03-08 10:58 ` John Garry 2018-03-20 6:25 ` [tip:perf/core] " tip-bot for John Garry 2018-03-08 10:58 ` [PATCH v3 11/11] perf vendor events arm64: add HiSilicon hip08 JSON file John Garry 2018-03-08 10:58 ` John Garry 2018-03-20 6:26 ` [tip:perf/core] " tip-bot for John Garry
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=1520506716-197429-10-git-send-email-john.garry@huawei.com \ --to=john.garry@huawei.com \ --cc=acme@kernel.org \ --cc=ak@linux.intel.com \ --cc=alexander.shishkin@linux.intel.com \ --cc=ganapatrao.kulkarni@cavium.com \ --cc=jolsa@redhat.com \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-kernel@vger.kernel.org \ --cc=linuxarm@huawei.com \ --cc=mingo@redhat.com \ --cc=namhyung@kernel.org \ --cc=peterz@infradead.org \ --cc=wcohen@redhat.com \ --cc=will.deacon@arm.com \ --cc=zhangshaokun@hisilicon.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.