* [U-Boot] [PATCH 0/3] ARM: stratix10: initial small patchset
@ 2018-03-09 3:39 Dinh Nguyen
2018-03-09 3:39 ` [U-Boot] [PATCH 1/3] arm: socfpga: stratix10: Add base address map for Statix10 SoC Dinh Nguyen
` (3 more replies)
0 siblings, 4 replies; 6+ messages in thread
From: Dinh Nguyen @ 2018-03-09 3:39 UTC (permalink / raw)
To: u-boot
Hi,
This is a very small initial patchset for the SoCFPGA Stratix10 platform.
This patchset adds a few core address defines that are not obtainable from
DT, pulls in from Linux the base DTS files, and the reset manager bindings.
The DTB is able to compile with this patchset.
Instead of dropping a larger patchset with for SPL and U-Boot, I figure
we start out small first, and allow for a couple of medium size patchset
later for further support.
Thanks,
Dinh
Chin Liang See (1):
arm: socfpga: stratix10: Add base address map for Statix10 SoC
Dinh Nguyen (2):
ARM64: stratix10: add reset manager includes
ARM: dts: stratix10: Add base dtsi and devkit dts
arch/arm/dts/Makefile | 1 +
arch/arm/dts/socfpga_stratix10.dtsi | 381 +++++++++++++++++++++
arch/arm/dts/socfpga_stratix10_socdk.dts | 92 +++++
arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 33 ++
include/dt-bindings/reset/altr,rst-mgr-s10.h | 97 ++++++
5 files changed, 604 insertions(+)
create mode 100644 arch/arm/dts/socfpga_stratix10.dtsi
create mode 100644 arch/arm/dts/socfpga_stratix10_socdk.dts
create mode 100644 arch/arm/mach-socfpga/include/mach/base_addr_s10.h
create mode 100644 include/dt-bindings/reset/altr,rst-mgr-s10.h
--
2.7.4
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 1/3] arm: socfpga: stratix10: Add base address map for Statix10 SoC
2018-03-09 3:39 [U-Boot] [PATCH 0/3] ARM: stratix10: initial small patchset Dinh Nguyen
@ 2018-03-09 3:39 ` Dinh Nguyen
2018-03-17 3:48 ` Marek Vasut
2018-03-09 3:39 ` [U-Boot] [PATCH 2/3] ARM64: stratix10: add reset manager includes Dinh Nguyen
` (2 subsequent siblings)
3 siblings, 1 reply; 6+ messages in thread
From: Dinh Nguyen @ 2018-03-09 3:39 UTC (permalink / raw)
To: u-boot
From: Chin Liang See <chin.liang.see@intel.com>
Add the base address map for Statix10 SoC
Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
v2: removed addresses that can be part of the fdt
---
arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 33 ++++++++++++++++++++++
1 file changed, 33 insertions(+)
create mode 100644 arch/arm/mach-socfpga/include/mach/base_addr_s10.h
diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
new file mode 100644
index 0000000..7052804
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _SOCFPGA_S10_BASE_HARDWARE_H_
+#define _SOCFPGA_S10_BASE_HARDWARE_H_
+
+#define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xf8000400
+#define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xf8010000
+#define SOCFPGA_SDR_ADDRESS 0xf8011000
+#define SOCFPGA_SMMU_ADDRESS 0xfa000000
+#define SOCFPGA_MAILBOX_ADDRESS 0xffa30000
+#define SOCFPGA_UART0_ADDRESS 0xffc02000
+#define SOCFPGA_UART1_ADDRESS 0xffc02100
+#define SOCFPGA_SPTIMER0_ADDRESS 0xffc03000
+#define SOCFPGA_SPTIMER1_ADDRESS 0xffc03100
+#define SOCFPGA_SYSTIMER0_ADDRESS 0xffd00000
+#define SOCFPGA_SYSTIMER1_ADDRESS 0xffd00100
+#define SOCFPGA_GTIMER_SEC_ADDRESS 0xffd01000
+#define SOCFPGA_GTIMER_NSEC_ADDRESS 0xffd02000
+#define SOCFPGA_CLKMGR_ADDRESS 0xffd10000
+#define SOCFPGA_RSTMGR_ADDRESS 0xffd11000
+#define SOCFPGA_SYSMGR_ADDRESS 0xffd12000
+#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS 0xffd13000
+#define SOCFPGA_DMANONSECURE_ADDRESS 0xffda0000
+#define SOCFPGA_DMASECURE_ADDRESS 0xffda1000
+#define SOCFPGA_OCRAM_ADDRESS 0xffe00000
+#define GICD_BASE 0xfffc1000
+#define GICC_BASE 0xfffc2000
+
+#endif /* _SOCFPGA_S10_BASE_HARDWARE_H_ */
--
2.7.4
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 2/3] ARM64: stratix10: add reset manager includes
2018-03-09 3:39 [U-Boot] [PATCH 0/3] ARM: stratix10: initial small patchset Dinh Nguyen
2018-03-09 3:39 ` [U-Boot] [PATCH 1/3] arm: socfpga: stratix10: Add base address map for Statix10 SoC Dinh Nguyen
@ 2018-03-09 3:39 ` Dinh Nguyen
2018-03-09 3:39 ` [U-Boot] [PATCH 3/3] ARM: dts: stratix10: Add base dtsi and devkit dts Dinh Nguyen
2018-03-17 3:49 ` [U-Boot] [PATCH 0/3] ARM: stratix10: initial small patchset Marek Vasut
3 siblings, 0 replies; 6+ messages in thread
From: Dinh Nguyen @ 2018-03-09 3:39 UTC (permalink / raw)
To: u-boot
Pulled from linux v4.16-rc4.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
include/dt-bindings/reset/altr,rst-mgr-s10.h | 97 ++++++++++++++++++++++++++++
1 file changed, 97 insertions(+)
create mode 100644 include/dt-bindings/reset/altr,rst-mgr-s10.h
diff --git a/include/dt-bindings/reset/altr,rst-mgr-s10.h b/include/dt-bindings/reset/altr,rst-mgr-s10.h
new file mode 100644
index 0000000..e3cae08
--- /dev/null
+++ b/include/dt-bindings/reset/altr,rst-mgr-s10.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright (C) 2016-2018 Intel Corporation. All rights reserved
+ * Copyright (C) 2016 Altera Corporation. All rights reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ * derived from Steffen Trumtrar's "altr,rst-mgr-a10.h"
+ */
+
+#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H
+#define _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H
+
+/* MPUMODRST */
+#define CPU0_RESET 0
+#define CPU1_RESET 1
+#define CPU2_RESET 2
+#define CPU3_RESET 3
+
+/* PER0MODRST */
+#define EMAC0_RESET 32
+#define EMAC1_RESET 33
+#define EMAC2_RESET 34
+#define USB0_RESET 35
+#define USB1_RESET 36
+#define NAND_RESET 37
+/* 38 is empty */
+#define SDMMC_RESET 39
+#define EMAC0_OCP_RESET 40
+#define EMAC1_OCP_RESET 41
+#define EMAC2_OCP_RESET 42
+#define USB0_OCP_RESET 43
+#define USB1_OCP_RESET 44
+#define NAND_OCP_RESET 45
+/* 46 is empty */
+#define SDMMC_OCP_RESET 47
+#define DMA_RESET 48
+#define SPIM0_RESET 49
+#define SPIM1_RESET 50
+#define SPIS0_RESET 51
+#define SPIS1_RESET 52
+#define DMA_OCP_RESET 53
+#define EMAC_PTP_RESET 54
+/* 55 is empty*/
+#define DMAIF0_RESET 56
+#define DMAIF1_RESET 57
+#define DMAIF2_RESET 58
+#define DMAIF3_RESET 59
+#define DMAIF4_RESET 60
+#define DMAIF5_RESET 61
+#define DMAIF6_RESET 62
+#define DMAIF7_RESET 63
+
+/* PER1MODRST */
+#define WATCHDOG0_RESET 64
+#define WATCHDOG1_RESET 65
+#define WATCHDOG2_RESET 66
+#define WATCHDOG3_RESET 67
+#define L4SYSTIMER0_RESET 68
+#define L4SYSTIMER1_RESET 69
+#define SPTIMER0_RESET 70
+#define SPTIMER1_RESET 71
+#define I2C0_RESET 72
+#define I2C1_RESET 73
+#define I2C2_RESET 74
+#define I2C3_RESET 75
+#define I2C4_RESET 76
+/* 77-79 is empty */
+#define UART0_RESET 80
+#define UART1_RESET 81
+/* 82-87 is empty */
+#define GPIO0_RESET 88
+#define GPIO1_RESET 89
+
+/* BRGMODRST */
+#define SOC2FPGA_RESET 96
+#define LWHPS2FPGA_RESET 97
+#define FPGA2SOC_RESET 98
+#define F2SSDRAM0_RESET 99
+#define F2SSDRAM1_RESET 100
+#define F2SSDRAM2_RESET 101
+#define DDRSCH_RESET 102
+
+/* COLDMODRST */
+#define CPUPO0_RESET 160
+#define CPUPO1_RESET 161
+#define CPUPO2_RESET 162
+#define CPUPO3_RESET 163
+/* 164-167 is empty */
+#define L2_RESET 168
+
+/* DBGMODRST */
+#define DBG_RESET 224
+#define CSDAP_RESET 225
+
+/* TAPMODRST */
+#define TAP_RESET 256
+
+#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 3/3] ARM: dts: stratix10: Add base dtsi and devkit dts
2018-03-09 3:39 [U-Boot] [PATCH 0/3] ARM: stratix10: initial small patchset Dinh Nguyen
2018-03-09 3:39 ` [U-Boot] [PATCH 1/3] arm: socfpga: stratix10: Add base address map for Statix10 SoC Dinh Nguyen
2018-03-09 3:39 ` [U-Boot] [PATCH 2/3] ARM64: stratix10: add reset manager includes Dinh Nguyen
@ 2018-03-09 3:39 ` Dinh Nguyen
2018-03-17 3:49 ` [U-Boot] [PATCH 0/3] ARM: stratix10: initial small patchset Marek Vasut
3 siblings, 0 replies; 6+ messages in thread
From: Dinh Nguyen @ 2018-03-09 3:39 UTC (permalink / raw)
To: u-boot
From the Linux v4.16-rc4, add the base dtsi and devkit dts files for
the Stratix10 SoCFPGA platform.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/socfpga_stratix10.dtsi | 381 +++++++++++++++++++++++++++++++
arch/arm/dts/socfpga_stratix10_socdk.dts | 92 ++++++++
3 files changed, 474 insertions(+)
create mode 100644 arch/arm/dts/socfpga_stratix10.dtsi
create mode 100644 arch/arm/dts/socfpga_stratix10_socdk.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 20a4c37..5170487 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -184,6 +184,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \
socfpga_cyclone5_sockit.dtb \
socfpga_cyclone5_socrates.dtb \
socfpga_cyclone5_sr1500.dtb \
+ socfpga_stratix10_socdk.dtb \
socfpga_cyclone5_vining_fpga.dtb
dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \
diff --git a/arch/arm/dts/socfpga_stratix10.dtsi b/arch/arm/dts/socfpga_stratix10.dtsi
new file mode 100644
index 0000000..ddf8032
--- /dev/null
+++ b/arch/arm/dts/socfpga_stratix10.dtsi
@@ -0,0 +1,381 @@
+/*
+ * Copyright (C) 2018 Intel Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+/dts-v1/;
+#include <dt-bindings/reset/altr,rst-mgr-s10.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ compatible = "altr,socfpga-stratix10";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu at 0 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ enable-method = "psci";
+ reg = <0x0>;
+ };
+
+ cpu1: cpu at 1 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ enable-method = "psci";
+ reg = <0x1>;
+ };
+
+ cpu2: cpu at 2 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ enable-method = "psci";
+ reg = <0x2>;
+ };
+
+ cpu3: cpu at 3 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ enable-method = "psci";
+ reg = <0x3>;
+ };
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <0 120 8>,
+ <0 121 8>,
+ <0 122 8>,
+ <0 123 8>;
+ interrupt-affinity = <&cpu0>,
+ <&cpu1>,
+ <&cpu2>,
+ <&cpu3>;
+ interrupt-parent = <&intc>;
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ intc: intc at fffc1000 {
+ compatible = "arm,gic-400", "arm,cortex-a15-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x0 0xfffc1000 0x0 0x1000>,
+ <0x0 0xfffc2000 0x0 0x2000>,
+ <0x0 0xfffc4000 0x0 0x2000>,
+ <0x0 0xfffc6000 0x0 0x2000>;
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ device_type = "soc";
+ interrupt-parent = <&intc>;
+ ranges = <0 0 0 0xffffffff>;
+
+ clkmgr at ffd1000 {
+ compatible = "altr,clk-mgr";
+ reg = <0xffd10000 0x1000>;
+ };
+
+ gmac0: ethernet at ff800000 {
+ compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
+ reg = <0xff800000 0x2000>;
+ interrupts = <0 90 4>;
+ interrupt-names = "macirq";
+ mac-address = [00 00 00 00 00 00];
+ resets = <&rst EMAC0_RESET>;
+ reset-names = "stmmaceth";
+ status = "disabled";
+ };
+
+ gmac1: ethernet at ff802000 {
+ compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
+ reg = <0xff802000 0x2000>;
+ interrupts = <0 91 4>;
+ interrupt-names = "macirq";
+ mac-address = [00 00 00 00 00 00];
+ resets = <&rst EMAC1_RESET>;
+ reset-names = "stmmaceth";
+ status = "disabled";
+ };
+
+ gmac2: ethernet at ff804000 {
+ compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
+ reg = <0xff804000 0x2000>;
+ interrupts = <0 92 4>;
+ interrupt-names = "macirq";
+ mac-address = [00 00 00 00 00 00];
+ resets = <&rst EMAC2_RESET>;
+ reset-names = "stmmaceth";
+ status = "disabled";
+ };
+
+ gpio0: gpio at ffc03200 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dw-apb-gpio";
+ reg = <0xffc03200 0x100>;
+ resets = <&rst GPIO0_RESET>;
+ status = "disabled";
+
+ porta: gpio-controller at 0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <24>;
+ reg = <0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <0 110 4>;
+ };
+ };
+
+ gpio1: gpio at ffc03300 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dw-apb-gpio";
+ reg = <0xffc03300 0x100>;
+ resets = <&rst GPIO1_RESET>;
+ status = "disabled";
+
+ portb: gpio-controller at 0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <24>;
+ reg = <0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <0 111 4>;
+ };
+ };
+
+ i2c0: i2c at ffc02800 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,designware-i2c";
+ reg = <0xffc02800 0x100>;
+ interrupts = <0 103 4>;
+ resets = <&rst I2C0_RESET>;
+ status = "disabled";
+ };
+
+ i2c1: i2c at ffc02900 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,designware-i2c";
+ reg = <0xffc02900 0x100>;
+ interrupts = <0 104 4>;
+ resets = <&rst I2C1_RESET>;
+ status = "disabled";
+ };
+
+ i2c2: i2c at ffc02a00 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,designware-i2c";
+ reg = <0xffc02a00 0x100>;
+ interrupts = <0 105 4>;
+ resets = <&rst I2C2_RESET>;
+ status = "disabled";
+ };
+
+ i2c3: i2c at ffc02b00 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,designware-i2c";
+ reg = <0xffc02b00 0x100>;
+ interrupts = <0 106 4>;
+ resets = <&rst I2C3_RESET>;
+ status = "disabled";
+ };
+
+ i2c4: i2c at ffc02c00 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,designware-i2c";
+ reg = <0xffc02c00 0x100>;
+ interrupts = <0 107 4>;
+ resets = <&rst I2C4_RESET>;
+ status = "disabled";
+ };
+
+ mmc: dwmmc0 at ff808000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "altr,socfpga-dw-mshc";
+ reg = <0xff808000 0x1000>;
+ interrupts = <0 96 4>;
+ fifo-depth = <0x400>;
+ resets = <&rst SDMMC_RESET>;
+ reset-names = "reset";
+ status = "disabled";
+ };
+
+ ocram: sram at ffe00000 {
+ compatible = "mmio-sram";
+ reg = <0xffe00000 0x100000>;
+ };
+
+ rst: rstmgr at ffd11000 {
+ #reset-cells = <1>;
+ compatible = "altr,rst-mgr";
+ reg = <0xffd11000 0x1000>;
+ altr,modrst-offset = <0x20>;
+ };
+
+ spi0: spi at ffda4000 {
+ compatible = "snps,dw-apb-ssi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xffda4000 0x1000>;
+ interrupts = <0 99 4>;
+ resets = <&rst SPIM0_RESET>;
+ reg-io-width = <4>;
+ num-chipselect = <4>;
+ bus-num = <0>;
+ status = "disabled";
+ };
+
+ spi1: spi at ffda5000 {
+ compatible = "snps,dw-apb-ssi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xffda5000 0x1000>;
+ interrupts = <0 100 4>;
+ resets = <&rst SPIM1_RESET>;
+ reg-io-width = <4>;
+ num-chipselect = <4>;
+ bus-num = <0>;
+ status = "disabled";
+ };
+
+ sysmgr: sysmgr at ffd12000 {
+ compatible = "altr,sys-mgr", "syscon";
+ reg = <0xffd12000 0x1000>;
+ };
+
+ /* Local timer */
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <1 13 0xf08>,
+ <1 14 0xf08>,
+ <1 11 0xf08>,
+ <1 10 0xf08>;
+ };
+
+ timer0: timer0 at ffc03000 {
+ compatible = "snps,dw-apb-timer";
+ interrupts = <0 113 4>;
+ reg = <0xffc03000 0x100>;
+ };
+
+ timer1: timer1 at ffc03100 {
+ compatible = "snps,dw-apb-timer";
+ interrupts = <0 114 4>;
+ reg = <0xffc03100 0x100>;
+ };
+
+ timer2: timer2 at ffd00000 {
+ compatible = "snps,dw-apb-timer";
+ interrupts = <0 115 4>;
+ reg = <0xffd00000 0x100>;
+ };
+
+ timer3: timer3 at ffd00100 {
+ compatible = "snps,dw-apb-timer";
+ interrupts = <0 116 4>;
+ reg = <0xffd00100 0x100>;
+ };
+
+ uart0: serial0 at ffc02000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0xffc02000 0x100>;
+ interrupts = <0 108 4>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ resets = <&rst UART0_RESET>;
+ status = "disabled";
+ };
+
+ uart1: serial1 at ffc02100 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0xffc02100 0x100>;
+ interrupts = <0 109 4>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ resets = <&rst UART1_RESET>;
+ status = "disabled";
+ };
+
+ usbphy0: usbphy at 0 {
+ #phy-cells = <0>;
+ compatible = "usb-nop-xceiv";
+ status = "okay";
+ };
+
+ usb0: usb at ffb00000 {
+ compatible = "snps,dwc2";
+ reg = <0xffb00000 0x40000>;
+ interrupts = <0 93 4>;
+ phys = <&usbphy0>;
+ phy-names = "usb2-phy";
+ resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
+ reset-names = "dwc2", "dwc2-ecc";
+ status = "disabled";
+ };
+
+ usb1: usb at ffb40000 {
+ compatible = "snps,dwc2";
+ reg = <0xffb40000 0x40000>;
+ interrupts = <0 94 4>;
+ phys = <&usbphy0>;
+ phy-names = "usb2-phy";
+ resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
+ reset-names = "dwc2", "dwc2-ecc";
+ status = "disabled";
+ };
+
+ watchdog0: watchdog at ffd00200 {
+ compatible = "snps,dw-wdt";
+ reg = <0xffd00200 0x100>;
+ interrupts = <0 117 4>;
+ resets = <&rst WATCHDOG0_RESET>;
+ status = "disabled";
+ };
+
+ watchdog1: watchdog at ffd00300 {
+ compatible = "snps,dw-wdt";
+ reg = <0xffd00300 0x100>;
+ interrupts = <0 118 4>;
+ resets = <&rst WATCHDOG1_RESET>;
+ status = "disabled";
+ };
+
+ watchdog2: watchdog at ffd00400 {
+ compatible = "snps,dw-wdt";
+ reg = <0xffd00400 0x100>;
+ interrupts = <0 125 4>;
+ resets = <&rst WATCHDOG2_RESET>;
+ status = "disabled";
+ };
+
+ watchdog3: watchdog at ffd00500 {
+ compatible = "snps,dw-wdt";
+ reg = <0xffd00500 0x100>;
+ interrupts = <0 126 4>;
+ resets = <&rst WATCHDOG3_RESET>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts
new file mode 100644
index 0000000..5e5ae62
--- /dev/null
+++ b/arch/arm/dts/socfpga_stratix10_socdk.dts
@@ -0,0 +1,92 @@
+/*
+ * Copyright (C) 2018 Intel Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include "socfpga_stratix10.dtsi"
+
+/ {
+ model = "SoCFPGA Stratix 10 SoCDK";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ hps0 {
+ label = "hps_led0";
+ gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
+ };
+
+ hps1 {
+ label = "hps_led1";
+ gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
+ };
+
+ hps2 {
+ label = "hps_led2";
+ gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the reg */
+ reg = <0 0 0 0>;
+ };
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&gmac0 {
+ status = "okay";
+ phy-mode = "rgmii";
+ phy-handle = <&phy0>;
+
+ max-frame-size = <3800>;
+
+ mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ phy0: ethernet-phy at 0 {
+ reg = <4>;
+
+ txd0-skew-ps = <0>; /* -420ps */
+ txd1-skew-ps = <0>; /* -420ps */
+ txd2-skew-ps = <0>; /* -420ps */
+ txd3-skew-ps = <0>; /* -420ps */
+ rxd0-skew-ps = <420>; /* 0ps */
+ rxd1-skew-ps = <420>; /* 0ps */
+ rxd2-skew-ps = <420>; /* 0ps */
+ rxd3-skew-ps = <420>; /* 0ps */
+ txen-skew-ps = <0>; /* -420ps */
+ txc-skew-ps = <1860>; /* 960ps */
+ rxdv-skew-ps = <420>; /* 0ps */
+ rxc-skew-ps = <1680>; /* 780ps */
+ };
+ };
+};
+
+&mmc {
+ status = "okay";
+ cap-sd-highspeed;
+ broken-cd;
+ bus-width = <4>;
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
--
2.7.4
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 1/3] arm: socfpga: stratix10: Add base address map for Statix10 SoC
2018-03-09 3:39 ` [U-Boot] [PATCH 1/3] arm: socfpga: stratix10: Add base address map for Statix10 SoC Dinh Nguyen
@ 2018-03-17 3:48 ` Marek Vasut
0 siblings, 0 replies; 6+ messages in thread
From: Marek Vasut @ 2018-03-17 3:48 UTC (permalink / raw)
To: u-boot
On 03/09/2018 04:39 AM, Dinh Nguyen wrote:
> From: Chin Liang See <chin.liang.see@intel.com>
>
> Add the base address map for Statix10 SoC
Stratix ...
> Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
> ---
> v2: removed addresses that can be part of the fdt
> ---
> arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 33 ++++++++++++++++++++++
> 1 file changed, 33 insertions(+)
> create mode 100644 arch/arm/mach-socfpga/include/mach/base_addr_s10.h
>
> diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
> new file mode 100644
> index 0000000..7052804
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
> @@ -0,0 +1,33 @@
> +/*
> + * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0
> + */
> +
> +#ifndef _SOCFPGA_S10_BASE_HARDWARE_H_
> +#define _SOCFPGA_S10_BASE_HARDWARE_H_
> +
> +#define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xf8000400
> +#define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xf8010000
> +#define SOCFPGA_SDR_ADDRESS 0xf8011000
> +#define SOCFPGA_SMMU_ADDRESS 0xfa000000
> +#define SOCFPGA_MAILBOX_ADDRESS 0xffa30000
> +#define SOCFPGA_UART0_ADDRESS 0xffc02000
> +#define SOCFPGA_UART1_ADDRESS 0xffc02100
> +#define SOCFPGA_SPTIMER0_ADDRESS 0xffc03000
> +#define SOCFPGA_SPTIMER1_ADDRESS 0xffc03100
> +#define SOCFPGA_SYSTIMER0_ADDRESS 0xffd00000
> +#define SOCFPGA_SYSTIMER1_ADDRESS 0xffd00100
> +#define SOCFPGA_GTIMER_SEC_ADDRESS 0xffd01000
> +#define SOCFPGA_GTIMER_NSEC_ADDRESS 0xffd02000
> +#define SOCFPGA_CLKMGR_ADDRESS 0xffd10000
> +#define SOCFPGA_RSTMGR_ADDRESS 0xffd11000
> +#define SOCFPGA_SYSMGR_ADDRESS 0xffd12000
> +#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS 0xffd13000
> +#define SOCFPGA_DMANONSECURE_ADDRESS 0xffda0000
> +#define SOCFPGA_DMASECURE_ADDRESS 0xffda1000
> +#define SOCFPGA_OCRAM_ADDRESS 0xffe00000
> +#define GICD_BASE 0xfffc1000
> +#define GICC_BASE 0xfffc2000
> +
> +#endif /* _SOCFPGA_S10_BASE_HARDWARE_H_ */
>
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 0/3] ARM: stratix10: initial small patchset
2018-03-09 3:39 [U-Boot] [PATCH 0/3] ARM: stratix10: initial small patchset Dinh Nguyen
` (2 preceding siblings ...)
2018-03-09 3:39 ` [U-Boot] [PATCH 3/3] ARM: dts: stratix10: Add base dtsi and devkit dts Dinh Nguyen
@ 2018-03-17 3:49 ` Marek Vasut
3 siblings, 0 replies; 6+ messages in thread
From: Marek Vasut @ 2018-03-17 3:49 UTC (permalink / raw)
To: u-boot
On 03/09/2018 04:39 AM, Dinh Nguyen wrote:
> Hi,
>
> This is a very small initial patchset for the SoCFPGA Stratix10 platform.
> This patchset adds a few core address defines that are not obtainable from
> DT, pulls in from Linux the base DTS files, and the reset manager bindings.
> The DTB is able to compile with this patchset.
>
> Instead of dropping a larger patchset with for SPL and U-Boot, I figure
> we start out small first, and allow for a couple of medium size patchset
> later for further support.
>
> Thanks,
> Dinh
>
> Chin Liang See (1):
> arm: socfpga: stratix10: Add base address map for Statix10 SoC
>
> Dinh Nguyen (2):
> ARM64: stratix10: add reset manager includes
> ARM: dts: stratix10: Add base dtsi and devkit dts
>
> arch/arm/dts/Makefile | 1 +
> arch/arm/dts/socfpga_stratix10.dtsi | 381 +++++++++++++++++++++
> arch/arm/dts/socfpga_stratix10_socdk.dts | 92 +++++
> arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 33 ++
> include/dt-bindings/reset/altr,rst-mgr-s10.h | 97 ++++++
> 5 files changed, 604 insertions(+)
> create mode 100644 arch/arm/dts/socfpga_stratix10.dtsi
> create mode 100644 arch/arm/dts/socfpga_stratix10_socdk.dts
> create mode 100644 arch/arm/mach-socfpga/include/mach/base_addr_s10.h
> create mode 100644 include/dt-bindings/reset/altr,rst-mgr-s10.h
>
I hope this will not become a pile of dead code ...
Applied all, thanks
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2018-03-17 3:49 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-03-09 3:39 [U-Boot] [PATCH 0/3] ARM: stratix10: initial small patchset Dinh Nguyen
2018-03-09 3:39 ` [U-Boot] [PATCH 1/3] arm: socfpga: stratix10: Add base address map for Statix10 SoC Dinh Nguyen
2018-03-17 3:48 ` Marek Vasut
2018-03-09 3:39 ` [U-Boot] [PATCH 2/3] ARM64: stratix10: add reset manager includes Dinh Nguyen
2018-03-09 3:39 ` [U-Boot] [PATCH 3/3] ARM: dts: stratix10: Add base dtsi and devkit dts Dinh Nguyen
2018-03-17 3:49 ` [U-Boot] [PATCH 0/3] ARM: stratix10: initial small patchset Marek Vasut
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