[PATCH] drm/i915/dp: Do not set the eDP link rate/lane count to max

[PATCH] drm/i915/dp: Do not set the eDP link rate/lane count to max

[Manasi Navare]

The panels are generally designed to support only a single
clock and lane configuration, and typically these values
correspond to the native resolution of the panel. But some
panels advertise the MAX_LINK_RATE in DPCD higher than what
is required to support the native resolution.
So optimize and set the link rate and lane count to the
least values required by the panel to support the native
resolution. This will also be an effective power saving
for such eDP panels.

Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 15 +++++++--------
 1 file changed, 7 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 8d1d7af..ba1114b 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1812,15 +1812,14 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 			bpp = dev_priv->vbt.edp.bpp;
 		}
 
-		/*
-		 * Use the maximum clock and number of lanes the eDP panel
-		 * advertizes being capable of. The panels are generally
-		 * designed to support only a single clock and lane
-		 * configuration, and typically these values correspond to the
-		 * native resolution of the panel.
+		/* The panels are generally designed to support only a single
+		 * clock and lane configuration, and typically these values
+		 * correspond to the native resolution of the panel. But some
+		 * panels advertise higher link rates that might not be required
+		 * for the native resolution of the panel. So use the least
+		 * required link rate/lane count for the panel's native
+		 * resolution.
 		 */
-		min_lane_count = max_lane_count;
-		min_clock = max_clock;
 	}
 
 	for (; bpp >= 6*3; bpp -= 2*3) {
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.BAT: success for drm/i915/dp: Do not set the eDP link rate/lane count to max

[Patchwork]

== Series Details ==

Series: drm/i915/dp: Do not set the eDP link rate/lane count to max
URL   : https://patchwork.freedesktop.org/series/39662/
State : success

== Summary ==

Series 39662v1 drm/i915/dp: Do not set the eDP link rate/lane count to max
https://patchwork.freedesktop.org/api/1.0/series/39662/revisions/1/mbox/

---- Known issues:

Test gem_mmap_gtt:
        Subgroup basic-small-bo-tiledx:
                pass       -> FAIL       (fi-gdg-551) fdo#102575
Test prime_vgem:
        Subgroup basic-fence-flip:
                pass       -> FAIL       (fi-ilk-650) fdo#104008

fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008

fi-bdw-5557u     total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  time:421s
fi-bdw-gvtdvm    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:422s
fi-blb-e6850     total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  time:367s
fi-bsw-n3050     total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  time:498s
fi-bwr-2160      total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 time:278s
fi-bxt-dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  time:486s
fi-bxt-j4205     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:491s
fi-byt-j1900     total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  time:486s
fi-byt-n2820     total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  time:470s
fi-cfl-8700k     total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:406s
fi-cfl-s2        total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:572s
fi-cnl-y3        total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:578s
fi-elk-e7500     total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  time:416s
fi-gdg-551       total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 time:288s
fi-glk-1         total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:515s
fi-hsw-4770      total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:395s
fi-ilk-650       total:288  pass:227  dwarn:0   dfail:0   fail:1   skip:60  time:407s
fi-ivb-3520m     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:463s
fi-ivb-3770      total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  time:422s
fi-kbl-7500u     total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  time:469s
fi-kbl-7567u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:460s
fi-kbl-r         total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:509s
fi-pnv-d510      total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  time:580s
fi-skl-6260u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:431s
fi-skl-6600u     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:523s
fi-skl-6700hq    total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:536s
fi-skl-6700k2    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:495s
fi-skl-6770hq    total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:487s
fi-skl-guc       total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:419s
fi-snb-2520m     total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:522s
fi-snb-2600      total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:395s
Blacklisted hosts:
fi-cnl-drrs      total:288  pass:257  dwarn:3   dfail:0   fail:0   skip:19  time:512s

469c28df8d66d3cc0a4a2e4e12433a5c92102022 drm-tip: 2018y-03m-08d-22h-40m-12s UTC integration manifest
80276b812f47 drm/i915/dp: Do not set the eDP link rate/lane count to max

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8286/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.IGT: failure for drm/i915/dp: Do not set the eDP link rate/lane count to max

[Patchwork]

== Series Details ==

Series: drm/i915/dp: Do not set the eDP link rate/lane count to max
URL   : https://patchwork.freedesktop.org/series/39662/
State : failure

== Summary ==

---- Possible new issues:

Test kms_cursor_crc:
        Subgroup cursor-64x64-suspend:
                pass       -> FAIL       (shard-apl)

---- Known issues:

Test gem_eio:
        Subgroup in-flight-contexts:
                pass       -> INCOMPLETE (shard-apl) fdo#105341
Test kms_sysfs_edid_timing:
                pass       -> WARN       (shard-apl) fdo#100047

fdo#105341 https://bugs.freedesktop.org/show_bug.cgi?id=105341
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047

shard-apl        total:3381 pass:1778 dwarn:1   dfail:0   fail:9   skip:1591 time:11692s
shard-hsw        total:3467 pass:1773 dwarn:1   dfail:0   fail:1   skip:1691 time:11685s
shard-snb        total:3467 pass:1363 dwarn:1   dfail:0   fail:2   skip:2101 time:6806s
Blacklisted hosts:
shard-kbl        total:3394 pass:1857 dwarn:2   dfail:0   fail:9   skip:1525 time:8586s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8286/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH] drm/i915/dp: Do not set the eDP link rate/lane count to max

[Jani Nikula]

On Thu, 08 Mar 2018, Manasi Navare <manasi.d.navare@intel.com> wrote:
> The panels are generally designed to support only a single
> clock and lane configuration, and typically these values
> correspond to the native resolution of the panel. But some
> panels advertise the MAX_LINK_RATE in DPCD higher than what
> is required to support the native resolution.
> So optimize and set the link rate and lane count to the
> least values required by the panel to support the native
> resolution. This will also be an effective power saving
> for such eDP panels.

I'm afraid this will lead to flickering on plenty of laptops. It will
just get reverted when it hits end users. We've been down this path
before. If we decide to try to do this again, we need to figure out how
*not* to regress those machines. We can't just talk our way out of this.

As a tip, it's often useful to have a look at git blame and git log when
you're considering changes to code that seems odd or contentious or
something. In this case that leads to commit 344c5bbcb7a2
("drm/i915/edp: use lane count and link rate from DPCD for eDP"), which
in turn leads to commit 56071a207602 ("drm/i915: use lane count and link
rate from VBT as minimums for eDP") and a bunch of bugzilla links.

That stuff was done by yours truly years ago, so I'd rather not repeat
my mistakes now. ;)


BR,
Jani.

>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: Matt Atwood <matthew.s.atwood@intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 15 +++++++--------
>  1 file changed, 7 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 8d1d7af..ba1114b 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1812,15 +1812,14 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>  			bpp = dev_priv->vbt.edp.bpp;
>  		}
>  
> -		/*
> -		 * Use the maximum clock and number of lanes the eDP panel
> -		 * advertizes being capable of. The panels are generally
> -		 * designed to support only a single clock and lane
> -		 * configuration, and typically these values correspond to the
> -		 * native resolution of the panel.
> +		/* The panels are generally designed to support only a single
> +		 * clock and lane configuration, and typically these values
> +		 * correspond to the native resolution of the panel. But some
> +		 * panels advertise higher link rates that might not be required
> +		 * for the native resolution of the panel. So use the least
> +		 * required link rate/lane count for the panel's native
> +		 * resolution.
>  		 */
> -		min_lane_count = max_lane_count;
> -		min_clock = max_clock;
>  	}
>  
>  	for (; bpp >= 6*3; bpp -= 2*3) {

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH] drm/i915/dp: Do not set the eDP link rate/lane count to max

[Chris Wilson]

Quoting Jani Nikula (2018-03-09 10:20:37)
> On Thu, 08 Mar 2018, Manasi Navare <manasi.d.navare@intel.com> wrote:
> > The panels are generally designed to support only a single
> > clock and lane configuration, and typically these values
> > correspond to the native resolution of the panel. But some
> > panels advertise the MAX_LINK_RATE in DPCD higher than what
> > is required to support the native resolution.
> > So optimize and set the link rate and lane count to the
> > least values required by the panel to support the native
> > resolution. This will also be an effective power saving
> > for such eDP panels.
> 
> I'm afraid this will lead to flickering on plenty of laptops. It will
> just get reverted when it hits end users. We've been down this path
> before. If we decide to try to do this again, we need to figure out how
> *not* to regress those machines. We can't just talk our way out of this.
> 
> As a tip, it's often useful to have a look at git blame and git log when
> you're considering changes to code that seems odd or contentious or
> something. In this case that leads to commit 344c5bbcb7a2
> ("drm/i915/edp: use lane count and link rate from DPCD for eDP"), which
> in turn leads to commit 56071a207602 ("drm/i915: use lane count and link
> rate from VBT as minimums for eDP") and a bunch of bugzilla links.

Also include a bit of rationale in the comment about what happens if we
don't have that block. 

* Use the maximum clock and number of lanes the eDP panel
* advertizes being capable of. The panels are generally
* designed to support only a single clock and lane
* configuration, and typically these values correspond to the
* native resolution of the panel.

+ On some? many? panels, failure to force the maximum bandwidth results
+ in flickering, hence we unconditionally apply this w/a.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx