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* [PATCH v12 1/6] drm/i915/guc: Rename guc_ggtt_offset to intel_guc_ggtt_offset
@ 2018-03-02  0:16 Jackie Li
  2018-03-02  0:16 ` [PATCH v12 2/6] drm/i915: Implement dynamic GuC WOPCM offset and size calculation Jackie Li
                   ` (7 more replies)
  0 siblings, 8 replies; 17+ messages in thread
From: Jackie Li @ 2018-03-02  0:16 UTC (permalink / raw)
  To: intel-gfx

GuC related exported functions should start with "intel_guc_" prefix and
pass intel_guc as the first parameter since its GuC related. Current
guc_ggtt_offset() failed to follow this code convention and this is a
problem for future patches that needs to access intel_guc data to verify
the GGTT offset against the GuC WOPCM top.

This patch renames the guc_ggtt_offset to intel_guc_ggtt_offset and updates
the related code to pass intel_guc pointer to this function call, so that
we can have a unified coding style for GuC code and also enable the future
patches to get GuC related data from intel_guc to do the offset
verification. Meanwhile, this patch also moves the GUC_GGTT_TOP from
intel_guc_regs.h to intel_guc.h since it is not GuC register related
definition.

v8:
 - Fixed coding style issues and moved GUC_GGTT_TOP to intel_guc.h (Sagar)
 - Updated commit message to explain to reason and motivation to add
   intel_guc as the first parameter of intel_guc_ggtt_offset (Chris)

v9:
 - Fixed code alignment issue due to line break (Chris)

v10:
 - Removed unnecessary comments, redundant code and avoided reuse variable
   to avoid potential issues (Joonas)

Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com> (v8)
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> (v9)
Signed-off-by: Jackie Li <yaodong.li@intel.com>
Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com> (v11)
---
 drivers/gpu/drm/i915/intel_guc.c            | 11 ++++++-----
 drivers/gpu/drm/i915/intel_guc.h            | 14 ++++++++++++--
 drivers/gpu/drm/i915/intel_guc_ads.c        |  8 ++++----
 drivers/gpu/drm/i915/intel_guc_ct.c         |  5 +++--
 drivers/gpu/drm/i915/intel_guc_fw.c         |  2 +-
 drivers/gpu/drm/i915/intel_guc_log.c        |  2 +-
 drivers/gpu/drm/i915/intel_guc_reg.h        |  3 ---
 drivers/gpu/drm/i915/intel_guc_submission.c | 10 +++++-----
 drivers/gpu/drm/i915/intel_huc.c            |  6 ++++--
 9 files changed, 36 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index e6512cc..a788e15 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -269,8 +269,9 @@ void intel_guc_init_params(struct intel_guc *guc)
 
 	/* If GuC submission is enabled, set up additional parameters here */
 	if (USES_GUC_SUBMISSION(dev_priv)) {
-		u32 ads = guc_ggtt_offset(guc->ads_vma) >> PAGE_SHIFT;
-		u32 pgs = guc_ggtt_offset(dev_priv->guc.stage_desc_pool);
+		u32 ads = intel_guc_ggtt_offset(guc,
+						guc->ads_vma) >> PAGE_SHIFT;
+		u32 pgs = intel_guc_ggtt_offset(guc, guc->stage_desc_pool);
 		u32 ctx_in_16 = GUC_MAX_STAGE_DESCRIPTORS / 16;
 
 		params[GUC_CTL_DEBUG] |= ads << GUC_ADS_ADDR_SHIFT;
@@ -418,7 +419,7 @@ int intel_guc_suspend(struct drm_i915_private *dev_priv)
 	data[0] = INTEL_GUC_ACTION_ENTER_S_STATE;
 	/* any value greater than GUC_POWER_D0 */
 	data[1] = GUC_POWER_D1;
-	data[2] = guc_ggtt_offset(guc->shared_data);
+	data[2] = intel_guc_ggtt_offset(guc, guc->shared_data);
 
 	return intel_guc_send(guc, data, ARRAY_SIZE(data));
 }
@@ -441,7 +442,7 @@ int intel_guc_reset_engine(struct intel_guc *guc,
 	data[3] = 0;
 	data[4] = 0;
 	data[5] = guc->execbuf_client->stage_id;
-	data[6] = guc_ggtt_offset(guc->shared_data);
+	data[6] = intel_guc_ggtt_offset(guc, guc->shared_data);
 
 	return intel_guc_send(guc, data, ARRAY_SIZE(data));
 }
@@ -463,7 +464,7 @@ int intel_guc_resume(struct drm_i915_private *dev_priv)
 
 	data[0] = INTEL_GUC_ACTION_EXIT_S_STATE;
 	data[1] = GUC_POWER_D0;
-	data[2] = guc_ggtt_offset(guc->shared_data);
+	data[2] = intel_guc_ggtt_offset(guc, guc->shared_data);
 
 	return intel_guc_send(guc, data, ARRAY_SIZE(data));
 }
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 52856a9..0c8b10a 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -100,13 +100,23 @@ static inline void intel_guc_notify(struct intel_guc *guc)
 	guc->notify(guc);
 }
 
-/*
+/* GuC addresses above GUC_GGTT_TOP also don't map through the GTT */
+#define GUC_GGTT_TOP	0xFEE00000
+
+/**
+ * intel_guc_ggtt_offset() - Get and validate the GGTT offset of @vma
+ * @guc: intel_guc structure.
+ * @vma: i915 graphics virtual memory area.
+ *
  * GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP),
  * which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is
  * 512K. In order to exclude 0-512K address space from GGTT, all gfx objects
  * used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM.
+ *
+ * Return: GGTT offset that meets the GuC gfx address requirement.
  */
-static inline u32 guc_ggtt_offset(struct i915_vma *vma)
+static inline u32 intel_guc_ggtt_offset(struct intel_guc *guc,
+					struct i915_vma *vma)
 {
 	u32 offset = i915_ggtt_offset(vma);
 
diff --git a/drivers/gpu/drm/i915/intel_guc_ads.c b/drivers/gpu/drm/i915/intel_guc_ads.c
index ac62753..334cb52 100644
--- a/drivers/gpu/drm/i915/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/intel_guc_ads.c
@@ -75,7 +75,7 @@ static void guc_policies_init(struct guc_policies *policies)
 int intel_guc_ads_create(struct intel_guc *guc)
 {
 	struct drm_i915_private *dev_priv = guc_to_i915(guc);
-	struct i915_vma *vma;
+	struct i915_vma *vma, *kernel_ctx_vma;
 	struct page *page;
 	/* The ads obj includes the struct itself and buffers passed to GuC */
 	struct {
@@ -121,9 +121,9 @@ int intel_guc_ads_create(struct intel_guc *guc)
 	 * to find it. Note that we have to skip our header (1 page),
 	 * because our GuC shared data is there.
 	 */
+	kernel_ctx_vma = dev_priv->kernel_context->engine[RCS].state;
 	blob->ads.golden_context_lrca =
-		guc_ggtt_offset(dev_priv->kernel_context->engine[RCS].state) +
-		skipped_offset;
+		intel_guc_ggtt_offset(guc, kernel_ctx_vma) + skipped_offset;
 
 	/*
 	 * The GuC expects us to exclude the portion of the context image that
@@ -135,7 +135,7 @@ int intel_guc_ads_create(struct intel_guc *guc)
 		blob->ads.eng_state_size[engine->guc_id] =
 			engine->context_size - skipped_size;
 
-	base = guc_ggtt_offset(vma);
+	base = intel_guc_ggtt_offset(guc, vma);
 	blob->ads.scheduler_policies = base + ptr_offset(blob, policies);
 	blob->ads.reg_state_buffer = base + ptr_offset(blob, reg_state_buffer);
 	blob->ads.reg_state_addr = base + ptr_offset(blob, reg_state);
diff --git a/drivers/gpu/drm/i915/intel_guc_ct.c b/drivers/gpu/drm/i915/intel_guc_ct.c
index 24ad557..0a0d3d5 100644
--- a/drivers/gpu/drm/i915/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/intel_guc_ct.c
@@ -156,7 +156,8 @@ static int ctch_init(struct intel_guc *guc,
 		err = PTR_ERR(blob);
 		goto err_vma;
 	}
-	DRM_DEBUG_DRIVER("CT: vma base=%#x\n", guc_ggtt_offset(ctch->vma));
+	DRM_DEBUG_DRIVER("CT: vma base=%#x\n",
+			 intel_guc_ggtt_offset(guc, ctch->vma));
 
 	/* store pointers to desc and cmds */
 	for (i = 0; i < ARRAY_SIZE(ctch->ctbs); i++) {
@@ -202,7 +203,7 @@ static int ctch_open(struct intel_guc *guc,
 	}
 
 	/* vma should be already allocated and map'ed */
-	base = guc_ggtt_offset(ctch->vma);
+	base = intel_guc_ggtt_offset(guc, ctch->vma);
 
 	/* (re)initialize descriptors
 	 * cmds buffers are in the second half of the blob page
diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c b/drivers/gpu/drm/i915/intel_guc_fw.c
index 3b09329..178d339 100644
--- a/drivers/gpu/drm/i915/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/intel_guc_fw.c
@@ -165,7 +165,7 @@ static int guc_xfer_ucode(struct intel_guc *guc, struct i915_vma *vma)
 	I915_WRITE(DMA_COPY_SIZE, guc_fw->header_size + guc_fw->ucode_size);
 
 	/* Set the source address for the new blob */
-	offset = guc_ggtt_offset(vma) + guc_fw->header_offset;
+	offset = intel_guc_ggtt_offset(guc, vma) + guc_fw->header_offset;
 	I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
 	I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
 
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c b/drivers/gpu/drm/i915/intel_guc_log.c
index 7b5074e..33636de 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -638,7 +638,7 @@ int intel_guc_log_create(struct intel_guc *guc)
 		(GUC_LOG_ISR_PAGES << GUC_LOG_ISR_SHIFT) |
 		(GUC_LOG_CRASH_PAGES << GUC_LOG_CRASH_SHIFT);
 
-	offset = guc_ggtt_offset(vma) >> PAGE_SHIFT; /* in pages */
+	offset = intel_guc_ggtt_offset(guc, vma) >> PAGE_SHIFT;
 	guc->log.flags = (offset << GUC_LOG_BUF_ADDR_SHIFT) | flags;
 
 	return 0;
diff --git a/drivers/gpu/drm/i915/intel_guc_reg.h b/drivers/gpu/drm/i915/intel_guc_reg.h
index 19a9247..711e9e9 100644
--- a/drivers/gpu/drm/i915/intel_guc_reg.h
+++ b/drivers/gpu/drm/i915/intel_guc_reg.h
@@ -80,9 +80,6 @@
 #define   GUC_WOPCM_TOP			  (0x80 << 12)	/* 512KB */
 #define   BXT_GUC_WOPCM_RC6_RESERVED	  (0x10 << 12)	/* 64KB  */
 
-/* GuC addresses above GUC_GGTT_TOP also don't map through the GTT */
-#define GUC_GGTT_TOP			0xFEE00000
-
 #define GEN8_GT_PM_CONFIG		_MMIO(0x138140)
 #define GEN9LP_GT_PM_CONFIG		_MMIO(0x138140)
 #define GEN9_GT_PM_CONFIG		_MMIO(0x13816c)
diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c b/drivers/gpu/drm/i915/intel_guc_submission.c
index 8a8ad2f..33af293 100644
--- a/drivers/gpu/drm/i915/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/intel_guc_submission.c
@@ -386,8 +386,8 @@ static void guc_stage_desc_init(struct intel_guc *guc,
 		lrc->context_desc = lower_32_bits(ce->lrc_desc);
 
 		/* The state page is after PPHWSP */
-		lrc->ring_lrca =
-			guc_ggtt_offset(ce->state) + LRC_STATE_PN * PAGE_SIZE;
+		lrc->ring_lrca = intel_guc_ggtt_offset(guc, ce->state) +
+				 LRC_STATE_PN * PAGE_SIZE;
 
 		/* XXX: In direct submission, the GuC wants the HW context id
 		 * here. In proxy submission, it wants the stage id
@@ -395,7 +395,7 @@ static void guc_stage_desc_init(struct intel_guc *guc,
 		lrc->context_id = (client->stage_id << GUC_ELC_CTXID_OFFSET) |
 				(guc_engine_id << GUC_ELC_ENGINE_OFFSET);
 
-		lrc->ring_begin = guc_ggtt_offset(ce->ring->vma);
+		lrc->ring_begin = intel_guc_ggtt_offset(guc, ce->ring->vma);
 		lrc->ring_end = lrc->ring_begin + ce->ring->size - 1;
 		lrc->ring_next_free_location = lrc->ring_begin;
 		lrc->ring_current_tail_pointer_value = 0;
@@ -411,7 +411,7 @@ static void guc_stage_desc_init(struct intel_guc *guc,
 	 * The doorbell, process descriptor, and workqueue are all parts
 	 * of the client object, which the GuC will reference via the GGTT
 	 */
-	gfx_addr = guc_ggtt_offset(client->vma);
+	gfx_addr = intel_guc_ggtt_offset(guc, client->vma);
 	desc->db_trigger_phy = sg_dma_address(client->vma->pages->sgl) +
 				client->doorbell_offset;
 	desc->db_trigger_cpu = ptr_to_u64(__get_doorbell(client));
@@ -584,7 +584,7 @@ static void inject_preempt_context(struct work_struct *work)
 	data[3] = engine->guc_id;
 	data[4] = guc->execbuf_client->priority;
 	data[5] = guc->execbuf_client->stage_id;
-	data[6] = guc_ggtt_offset(guc->shared_data);
+	data[6] = intel_guc_ggtt_offset(guc, guc->shared_data);
 
 	if (WARN_ON(intel_guc_send(guc, data, ARRAY_SIZE(data)))) {
 		execlists_clear_active(&engine->execlists,
diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
index ef9a05d..70a5282 100644
--- a/drivers/gpu/drm/i915/intel_huc.c
+++ b/drivers/gpu/drm/i915/intel_huc.c
@@ -138,7 +138,8 @@ static int huc_ucode_xfer(struct intel_uc_fw *huc_fw, struct i915_vma *vma)
 	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 
 	/* Set the source address for the uCode */
-	offset = guc_ggtt_offset(vma) + huc_fw->header_offset;
+	offset = intel_guc_ggtt_offset(&dev_priv->guc, vma) +
+		 huc_fw->header_offset;
 	I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
 	I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
 
@@ -214,7 +215,8 @@ int intel_huc_auth(struct intel_huc *huc)
 	}
 
 	ret = intel_guc_auth_huc(guc,
-				 guc_ggtt_offset(vma) + huc->fw.rsa_offset);
+				 intel_guc_ggtt_offset(guc, vma) +
+				 huc->fw.rsa_offset);
 	if (ret) {
 		DRM_ERROR("HuC: GuC did not ack Auth request %d\n", ret);
 		goto out;
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 17+ messages in thread
* [PATCH v12 2/6] drm/i915: Implement dynamic GuC WOPCM offset and size calculation
  2018-03-02  0:16 [PATCH v12 1/6] drm/i915/guc: Rename guc_ggtt_offset to intel_guc_ggtt_offset Jackie Li
@ 2018-03-02  0:16 ` Jackie Li
  2018-03-02  8:04   ` Sagar Arun Kamble
  2018-03-13 11:00   ` Joonas Lahtinen
  2018-03-02  0:16 ` [PATCH v12 3/6] drm/i915: Add support to return CNL specific reserved WOPCM size Jackie Li
                   ` (6 subsequent siblings)
  7 siblings, 2 replies; 17+ messages in thread
From: Jackie Li @ 2018-03-02  0:16 UTC (permalink / raw)
  To: intel-gfx; +Cc: Sujaritha Sundaresan

Hardware may have specific restrictions on GuC WOPCM offset and size. On
Gen9, the value of the GuC WOPCM size register needs to be larger than the
value of GuC WOPCM offset register + a Gen9 specific offset (144KB) for
reserved GuC WOPCM. Fail to enforce such a restriction on GuC WOPCM size
will lead to GuC firmware execution failures. On the other hand, with
current static GuC WOPCM offset and size values (512KB for both offset and
size), the GuC WOPCM size verification will fail on Gen9 even if it can be
fixed by lowering the GuC WOPCM offset by calculating its value based on
HuC firmware size (which is likely less than 200KB on Gen9), so that we can
have a GuC WOPCM size value which is large enough to pass the GuC WOPCM
size check.

This patch updates the reserved GuC WOPCM size for RC6 context on Gen9 to
24KB to strictly align with the Gen9 GuC WOPCM layout. It also adds support
to verify the GuC WOPCM size aganist the Gen9 hardware restrictions. To
meet all above requirements, let's provide dynamic partitioning of the
WOPCM that will be based on platform specific HuC/GuC firmware sizes.

v2:
 - Removed intel_wopcm_init (Ville/Sagar/Joonas)
 - Renamed and Moved the intel_wopcm_partition into intel_guc (Sagar)
 - Removed unnecessary function calls (Joonas)
 - Init GuC WOPCM partition as soon as firmware fetching is completed

v3:
 - Fixed indentation issues (Chris)
 - Removed layering violation code (Chris/Michal)
 - Created separat files for GuC wopcm code  (Michal)
 - Used inline function to avoid code duplication (Michal)

v4:
 - Preset the GuC WOPCM top during early GuC init (Chris)
 - Fail intel_uc_init_hw() as soon as GuC WOPCM partitioning failed

v5:
 - Moved GuC DMA WOPCM register updating code into intel_wopcm.c
 - Took care of the locking status before writing to GuC DMA
   Write-Once registers. (Joonas)

v6:
 - Made sure the GuC WOPCM size to be multiple of 4K (4K aligned)

v8:
 - Updated comments and fixed naming issues (Sagar/Joonas)
 - Updated commit message to include more description about the hardware
   restriction on GuC WOPCM size (Sagar)

v9:
 - Minor changes variable names and code comments (Sagar)
 - Added detailed GuC WOPCM layout drawing (Sagar/Michal)
 - Refined macro definitions to be reader friendly (Michal)
 - Removed redundent check to valid flag (Michal)
 - Unified first parameter for exported GuC WOPCM functions (Michal)
 - Refined the name and parameter list of hardware restriction checking
   functions (Michal)

v10:
 - Used shorter function name for internal functions (Joonas)
 - Moved init-ealry function into c file (Joonas)
 - Consolidated and removed redundant size checks (Joonas/Michal)
 - Removed unnecessary unlikely() from code which is only called once
   during boot (Joonas)
 - More fixes to kernel-doc format and content (Michal)
 - Avoided the use of PAGE_MASK for 4K pages (Michal)
 - Added error log messages to error paths (Michal)

v11:
 - Replaced intel_guc_wopcm with more generic intel_wopcm and attached
   intel_wopcm to drm_i915_private instead intel_guc (Michal)
 - dynamic calculation of GuC non-wopcm memory start (a.k.a WOPCM Top
   offset from GuC WOPCM base) (Michal)
 - Moved WOPCM marco definitions into .c source file (Michal)
 - Exported WOPCM layout diagram as kernel-doc (Michal)

v12:
 - Updated naming, function kernel-doc to align with new changes (Michal)

Bspec: 12690

Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: John Spotswood <john.a.spotswood@intel.com>
Cc: Oscar Mateo <oscar.mateo@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com> (v8)
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> (v9)
Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com> (v11)
Signed-off-by: Jackie Li <yaodong.li@intel.com>
---
 drivers/gpu/drm/i915/Makefile           |   3 +-
 drivers/gpu/drm/i915/i915_drv.c         |   1 +
 drivers/gpu/drm/i915/i915_drv.h         |   8 ++
 drivers/gpu/drm/i915/i915_gem.c         |   4 +
 drivers/gpu/drm/i915/i915_gem_context.c |   5 +-
 drivers/gpu/drm/i915/intel_guc.c        |  66 ++++++++---
 drivers/gpu/drm/i915/intel_guc.h        |  16 ++-
 drivers/gpu/drm/i915/intel_guc_reg.h    |   8 +-
 drivers/gpu/drm/i915/intel_huc.c        |   2 +-
 drivers/gpu/drm/i915/intel_uc.c         |   6 +-
 drivers/gpu/drm/i915/intel_uc_fw.c      |  13 +--
 drivers/gpu/drm/i915/intel_uc_fw.h      |  16 +++
 drivers/gpu/drm/i915/intel_wopcm.c      | 195 ++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_wopcm.h      |  34 ++++++
 14 files changed, 337 insertions(+), 40 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_wopcm.c
 create mode 100644 drivers/gpu/drm/i915/intel_wopcm.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 881d712..652549e 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -78,7 +78,8 @@ i915-y += i915_cmd_parser.o \
 	  intel_lrc.o \
 	  intel_mocs.o \
 	  intel_ringbuffer.o \
-	  intel_uncore.o
+	  intel_uncore.o \
+	  intel_wopcm.o
 
 # general-purpose microcontroller (GuC) support
 i915-y += intel_uc.o \
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index aaa861b..4c093bc 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -918,6 +918,7 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv,
 	mutex_init(&dev_priv->wm.wm_mutex);
 	mutex_init(&dev_priv->pps_mutex);
 
+	intel_wopcm_init_early(&dev_priv->wopcm);
 	intel_uc_init_early(dev_priv);
 	i915_memcpy_init_early(dev_priv);
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 10c9e5e..f43edb8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -64,6 +64,7 @@
 #include "intel_opregion.h"
 #include "intel_ringbuffer.h"
 #include "intel_uncore.h"
+#include "intel_wopcm.h"
 #include "intel_uc.h"
 
 #include "i915_gem.h"
@@ -1860,6 +1861,8 @@ struct drm_i915_private {
 
 	struct intel_gvt *gvt;
 
+	struct intel_wopcm wopcm;
+
 	struct intel_huc huc;
 	struct intel_guc guc;
 
@@ -2391,6 +2394,11 @@ static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
 	return to_i915(dev_get_drvdata(kdev));
 }
 
+static inline struct drm_i915_private *wopcm_to_i915(struct intel_wopcm *wopcm)
+{
+	return container_of(wopcm, struct drm_i915_private, wopcm);
+}
+
 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
 {
 	return container_of(guc, struct drm_i915_private, guc);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 14c855b..d31ad0b 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5279,6 +5279,10 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
 	if (ret)
 		return ret;
 
+	ret = intel_wopcm_init(&dev_priv->wopcm);
+	if (ret)
+		return ret;
+
 	ret = intel_uc_init_misc(dev_priv);
 	if (ret)
 		return ret;
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index a73340ae..285e80c 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -312,12 +312,13 @@ __create_hw_context(struct drm_i915_private *dev_priv,
 	ctx->desc_template =
 		default_desc_template(dev_priv, dev_priv->mm.aliasing_ppgtt);
 
-	/* GuC requires the ring to be placed above GUC_WOPCM_TOP. If GuC is not
+	/*
+	 * GuC requires the ring to be placed in Non-WOPCM memory. If GuC is not
 	 * present or not in use we still need a small bias as ring wraparound
 	 * at offset 0 sometimes hangs. No idea why.
 	 */
 	if (USES_GUC(dev_priv))
-		ctx->ggtt_offset_bias = GUC_WOPCM_TOP;
+		ctx->ggtt_offset_bias = dev_priv->guc.ggtt_pin_bias;
 	else
 		ctx->ggtt_offset_bias = I915_GTT_PAGE_SIZE;
 
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index a788e15..67f412a 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -470,6 +470,57 @@ int intel_guc_resume(struct drm_i915_private *dev_priv)
 }
 
 /**
+ * DOC: GuC Address Space
+ *
+ * The layout of GuC address space is shown as below:
+ *
+ *    +==============> +====================+ <== GUC_GGTT_TOP
+ *    ^                |                    |
+ *    |                |                    |
+ *    |                |        DRAM        |
+ *    |                |       Memory       |
+ *    |                |                    |
+ *   GuC               |                    |
+ * Address  +========> +====================+ <== WOPCM Top
+ *  Space   ^          |   HW contexts RSVD |
+ *    |     |          |        WOPCM       |
+ *    |     |     +==> +--------------------+ <== GuC WOPCM Top
+ *    |    GuC    ^    |                    |
+ *    |    GGTT   |    |                    |
+ *    |    Pin   GuC   |        GuC         |
+ *    |    Bias WOPCM  |       WOPCM        |
+ *    |     |    Size  |                    |
+ *    |     |     |    |                    |
+ *    v     v     v    |                    |
+ *    +=====+=====+==> +====================+ <== GuC WOPCM Base
+ *                     |   Non-GuC WOPCM    |
+ *                     |   (HuC/Reserved)   |
+ *                     +====================+ <== WOPCM Base
+ *
+ * The lower part [0, GuC ggtt_pin_bias) was mapped to WOPCM which consists of
+ * GuC WOPCM and WOPCM reserved for other usage (e.g.RC6 context). The value of
+ * the GuC ggtt_pin_bias is determined by the actually GuC WOPCM size which is
+ * set in GUC_WOPCM_SIZE register.
+ */
+
+/**
+ * intel_guc_init_ggtt_pin_bias() - Initialize the GuC ggtt_pin_bias value.
+ * @guc: intel_guc structure.
+ *
+ * This functional will calculate and initialize the ggtt_pin_bias value based
+ * on overall WOPCM size and GuC WOPCM size.
+ */
+void intel_guc_init_ggtt_pin_bias(struct intel_guc *guc)
+{
+	struct drm_i915_private *i915 = guc_to_i915(guc);
+
+	GEM_BUG_ON(!i915->wopcm.size);
+	GEM_BUG_ON(i915->wopcm.size < i915->wopcm.guc.base);
+
+	guc->ggtt_pin_bias = i915->wopcm.size - i915->wopcm.guc.base;
+}
+
+/**
  * intel_guc_allocate_vma() - Allocate a GGTT VMA for GuC usage
  * @guc:	the guc
  * @size:	size of area to allocate (both virtual space and memory)
@@ -477,7 +528,7 @@ int intel_guc_resume(struct drm_i915_private *dev_priv)
  * This is a wrapper to create an object for use with the GuC. In order to
  * use it inside the GuC, an object needs to be pinned lifetime, so we allocate
  * both some backing storage and a range inside the Global GTT. We must pin
- * it in the GGTT somewhere other than than [0, GUC_WOPCM_TOP) because that
+ * it in the GGTT somewhere other than than [0, GUC ggtt_pin_bias) because that
  * range is reserved inside GuC.
  *
  * Return:	A i915_vma if successful, otherwise an ERR_PTR.
@@ -498,7 +549,7 @@ struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)
 		goto err;
 
 	ret = i915_vma_pin(vma, 0, PAGE_SIZE,
-			   PIN_GLOBAL | PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
+			   PIN_GLOBAL | PIN_OFFSET_BIAS | guc->ggtt_pin_bias);
 	if (ret) {
 		vma = ERR_PTR(ret);
 		goto err;
@@ -510,14 +561,3 @@ struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)
 	i915_gem_object_put(obj);
 	return vma;
 }
-
-u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv)
-{
-	u32 wopcm_size = GUC_WOPCM_TOP;
-
-	/* On BXT, the top of WOPCM is reserved for RC6 context */
-	if (IS_GEN9_LP(dev_priv))
-		wopcm_size -= BXT_GUC_WOPCM_RC6_RESERVED;
-
-	return wopcm_size;
-}
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 0c8b10a..d5077c6 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -49,6 +49,9 @@ struct intel_guc {
 	struct intel_guc_log log;
 	struct intel_guc_ct ct;
 
+	/** @ggtt_pin_bias: offset where Non-WOPCM memory starts. */
+	u32 ggtt_pin_bias;
+
 	/* Log snapshot if GuC errors during load */
 	struct drm_i915_gem_object *load_err_log;
 
@@ -108,10 +111,11 @@ static inline void intel_guc_notify(struct intel_guc *guc)
  * @guc: intel_guc structure.
  * @vma: i915 graphics virtual memory area.
  *
- * GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP),
- * which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is
- * 512K. In order to exclude 0-512K address space from GGTT, all gfx objects
- * used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM.
+ * GuC does not allow any gfx GGTT address that falls into range
+ * [0, GuC ggtt_pin_bias), which is reserved for Boot ROM, SRAM and WOPCM.
+ * Currently, in order to exclude [0, GuC ggtt_pin_bias) address space from
+ * GGTT, all gfx objects used by GuC is allocated with intel_guc_allocate_vma()
+ * and pinned with PIN_OFFSET_BIAS along with the value of GuC ggtt_pin_bias.
  *
  * Return: GGTT offset that meets the GuC gfx address requirement.
  */
@@ -120,7 +124,7 @@ static inline u32 intel_guc_ggtt_offset(struct intel_guc *guc,
 {
 	u32 offset = i915_ggtt_offset(vma);
 
-	GEM_BUG_ON(offset < GUC_WOPCM_TOP);
+	GEM_BUG_ON(offset < guc->ggtt_pin_bias);
 	GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, GUC_GGTT_TOP));
 
 	return offset;
@@ -129,6 +133,7 @@ static inline u32 intel_guc_ggtt_offset(struct intel_guc *guc,
 void intel_guc_init_early(struct intel_guc *guc);
 void intel_guc_init_send_regs(struct intel_guc *guc);
 void intel_guc_init_params(struct intel_guc *guc);
+void intel_guc_init_ggtt_pin_bias(struct intel_guc *guc);
 int intel_guc_init_wq(struct intel_guc *guc);
 void intel_guc_fini_wq(struct intel_guc *guc);
 int intel_guc_init(struct intel_guc *guc);
@@ -140,6 +145,5 @@ int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset);
 int intel_guc_suspend(struct drm_i915_private *dev_priv);
 int intel_guc_resume(struct drm_i915_private *dev_priv);
 struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);
-u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv);
 
 #endif
diff --git a/drivers/gpu/drm/i915/intel_guc_reg.h b/drivers/gpu/drm/i915/intel_guc_reg.h
index 711e9e9..01963d0 100644
--- a/drivers/gpu/drm/i915/intel_guc_reg.h
+++ b/drivers/gpu/drm/i915/intel_guc_reg.h
@@ -68,17 +68,15 @@
 #define DMA_GUC_WOPCM_OFFSET		_MMIO(0xc340)
 #define   HUC_LOADING_AGENT_VCR		  (0<<1)
 #define   HUC_LOADING_AGENT_GUC		  (1<<1)
-#define   GUC_WOPCM_OFFSET_VALUE	  0x80000	/* 512KB */
+#define   GUC_WOPCM_OFFSET_SHIFT	14
 #define GUC_MAX_IDLE_COUNT		_MMIO(0xC3E4)
 
 #define HUC_STATUS2             _MMIO(0xD3B0)
 #define   HUC_FW_VERIFIED       (1<<7)
 
-/* Defines WOPCM space available to GuC firmware */
 #define GUC_WOPCM_SIZE			_MMIO(0xc050)
-/* GuC addresses below GUC_WOPCM_TOP don't map through the GTT */
-#define   GUC_WOPCM_TOP			  (0x80 << 12)	/* 512KB */
-#define   BXT_GUC_WOPCM_RC6_RESERVED	  (0x10 << 12)	/* 64KB  */
+#define   GUC_WOPCM_SIZE_SHIFT		12
+#define   GUC_WOPCM_SIZE_MASK		  (0xfffff << GUC_WOPCM_SIZE_SHIFT)
 
 #define GEN8_GT_PM_CONFIG		_MMIO(0x138140)
 #define GEN9LP_GT_PM_CONFIG		_MMIO(0x138140)
diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
index 70a5282..258a488 100644
--- a/drivers/gpu/drm/i915/intel_huc.c
+++ b/drivers/gpu/drm/i915/intel_huc.c
@@ -207,7 +207,7 @@ int intel_huc_auth(struct intel_huc *huc)
 		return -ENOEXEC;
 
 	vma = i915_gem_object_ggtt_pin(huc->fw.obj, NULL, 0, 0,
-				PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
+				PIN_OFFSET_BIAS | guc->ggtt_pin_bias);
 	if (IS_ERR(vma)) {
 		ret = PTR_ERR(vma);
 		DRM_ERROR("HuC: Failed to pin huc fw object %d\n", ret);
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 9f1bac6..964e49f 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -248,6 +248,8 @@ int intel_uc_init_misc(struct drm_i915_private *dev_priv)
 	if (!USES_GUC(dev_priv))
 		return 0;
 
+	intel_guc_init_ggtt_pin_bias(guc);
+
 	ret = intel_guc_init_wq(guc);
 	if (ret) {
 		DRM_ERROR("Couldn't allocate workqueues for GuC\n");
@@ -340,9 +342,9 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
 	gen9_reset_guc_interrupts(dev_priv);
 
 	/* init WOPCM */
-	I915_WRITE(GUC_WOPCM_SIZE, intel_guc_wopcm_size(dev_priv));
+	I915_WRITE(GUC_WOPCM_SIZE, dev_priv->wopcm.guc.size);
 	I915_WRITE(DMA_GUC_WOPCM_OFFSET,
-		   GUC_WOPCM_OFFSET_VALUE | HUC_LOADING_AGENT_GUC);
+		   dev_priv->wopcm.guc.base | HUC_LOADING_AGENT_GUC);
 
 	/* WaEnableuKernelHeaderValidFix:skl */
 	/* WaEnableGuCBootHashCheckNotSet:skl,bxt,kbl */
diff --git a/drivers/gpu/drm/i915/intel_uc_fw.c b/drivers/gpu/drm/i915/intel_uc_fw.c
index 3ec0ce5..30c7324 100644
--- a/drivers/gpu/drm/i915/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/intel_uc_fw.c
@@ -95,15 +95,6 @@ void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
 	uc_fw->ucode_offset = uc_fw->header_offset + uc_fw->header_size;
 	uc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);
 
-	/* Header and uCode will be loaded to WOPCM */
-	size = uc_fw->header_size + uc_fw->ucode_size;
-	if (size > intel_guc_wopcm_size(dev_priv)) {
-		DRM_WARN("%s: Firmware is too large to fit in WOPCM\n",
-			 intel_uc_fw_type_repr(uc_fw->type));
-		err = -E2BIG;
-		goto fail;
-	}
-
 	/* now RSA */
 	if (css->key_size_dw != UOS_RSA_SCRATCH_COUNT) {
 		DRM_WARN("%s: Mismatched firmware RSA key size (%u)\n",
@@ -208,6 +199,7 @@ int intel_uc_fw_upload(struct intel_uc_fw *uc_fw,
 		       int (*xfer)(struct intel_uc_fw *uc_fw,
 				   struct i915_vma *vma))
 {
+	struct drm_i915_private *i915 = to_i915(uc_fw->obj->base.dev);
 	struct i915_vma *vma;
 	int err;
 
@@ -231,7 +223,8 @@ int intel_uc_fw_upload(struct intel_uc_fw *uc_fw,
 	}
 
 	vma = i915_gem_object_ggtt_pin(uc_fw->obj, NULL, 0, 0,
-				       PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
+				       PIN_OFFSET_BIAS |
+				       i915->guc.ggtt_pin_bias);
 	if (IS_ERR(vma)) {
 		err = PTR_ERR(vma);
 		DRM_DEBUG_DRIVER("%s fw ggtt-pin err=%d\n",
diff --git a/drivers/gpu/drm/i915/intel_uc_fw.h b/drivers/gpu/drm/i915/intel_uc_fw.h
index d5fd460..95a209b 100644
--- a/drivers/gpu/drm/i915/intel_uc_fw.h
+++ b/drivers/gpu/drm/i915/intel_uc_fw.h
@@ -115,6 +115,22 @@ static inline bool intel_uc_fw_is_selected(struct intel_uc_fw *uc_fw)
 	return uc_fw->path != NULL;
 }
 
+/**
+ * intel_uc_fw_get_upload_size()() - Get size of firmware needed to be uploaded.
+ * @uc_fw: uC firmware.
+ *
+ * Get the size of the firmware that will be uploaded to WOPCM.
+ *
+ * Return: Upload firmware size, or zero on firmware fetch failure.
+ */
+static inline u32 intel_uc_fw_get_upload_size(struct intel_uc_fw *uc_fw)
+{
+	if (uc_fw->fetch_status != INTEL_UC_FIRMWARE_SUCCESS)
+		return 0;
+
+	return uc_fw->header_size + uc_fw->ucode_size;
+}
+
 void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
 		       struct intel_uc_fw *uc_fw);
 int intel_uc_fw_upload(struct intel_uc_fw *uc_fw,
diff --git a/drivers/gpu/drm/i915/intel_wopcm.c b/drivers/gpu/drm/i915/intel_wopcm.c
new file mode 100644
index 0000000..8b2f177
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_wopcm.c
@@ -0,0 +1,195 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2017-2018 Intel Corporation
+ */
+
+#include "intel_wopcm.h"
+#include "i915_drv.h"
+
+/**
+ * DOC: WOPCM Layout.
+ *
+ * The layout of the WOPCM will be fixed after writing to GuC WOPCM size and
+ * offset registers whose are calculated are determined by size of HuC/GuC
+ * firmware size and set of hw requirements/restrictions as shown below:.
+ *
+ *   +=========> +====================+ <== WOPCM Top
+ *   ^           |  HW contexts RSVD  |
+ *   |     +===> +====================+ <== GuC WOPCM Top
+ *   |     ^     |                    |
+ *   |     |     |                    |
+ *   |     |     |                    |
+ *   |    GuC    |                    |
+ *   |   WOPCM   |                    |
+ *   |    Size   +--------------------+
+ * WOPCM   |     |    GuC FW RSVD     |
+ *   |     |     +--------------------+
+ *   |     |     |   GuC Stack RSVD   |
+ *   |     |     +------------------- +
+ *   |     v     |   GuC WOPCM RSVD   |
+ *   |     +===> +====================+ <== GuC WOPCM base
+ *   |           |     WOPCM RSVD     |
+ *   |           +------------------- + <== HuC Firmware Top
+ *   v           |      HuC FW        |
+ *   +=========> +====================+ <== WOPCM Base
+ *
+ * GuC accessible WOPCM starts at GuC WOPCM base and ends at GuC WOPCM top.
+ * The top part of the WOPCM is reserved for hardware contexts (e.g. RC6
+ * context).
+ */
+
+/* Default WOPCM size 1MB. */
+#define GEN9_WOPCM_SIZE			(1024 * 1024)
+/* 16KB WOPCM (RSVD WOPCM) is reserved from HuC firmware top. */
+#define WOPCM_RESERVED_SIZE		(16 * 1024)
+
+/* 16KB reserved at the beginning of GuC WOPCM. */
+#define GUC_WOPCM_RESERVED		(16 * 1024)
+/* 8KB from GUC_WOPCM_RESERVED is reserved for GuC stack. */
+#define GUC_WOPCM_STACK_RESERVED	(8 * 1024)
+
+/* GuC WOPCM Offset value needs to be aligned to 16KB. */
+#define GUC_WOPCM_OFFSET_ALIGNMENT	(1UL << GUC_WOPCM_OFFSET_SHIFT)
+
+/* 24KB at the end of WOPCM is reserved for RC6 CTX on BXT. */
+#define BXT_WOPCM_RC6_CTX_RESERVED	(24 * 1024)
+
+/* 128KB from GUC_WOPCM_RESERVED is reserved for FW on Gen9. */
+#define GEN9_GUC_FW_RESERVED	(128 * 1024)
+#define GEN9_GUC_WOPCM_OFFSET	(GUC_WOPCM_RESERVED + GEN9_GUC_FW_RESERVED)
+
+/**
+ * intel_wopcm_init_early() - Early initialization of the WOPCM.
+ * @wopcm: pointer to intel_wopcm.
+ *
+ * Setup the size of WOPCM which will be used by later on WOPCM partitioning.
+ */
+void intel_wopcm_init_early(struct intel_wopcm *wopcm)
+{
+	wopcm->size = GEN9_WOPCM_SIZE;
+
+	DRM_DEBUG_DRIVER("WOPCM size: %uKiB\n", wopcm->size / 1024);
+}
+
+static inline u32 context_reserved_size(struct drm_i915_private *i915)
+{
+	if (IS_GEN9_LP(i915))
+		return BXT_WOPCM_RC6_CTX_RESERVED;
+	else
+		return 0;
+}
+
+static inline int gen9_check_dword_gap(u32 guc_wopcm_base, u32 guc_wopcm_size)
+{
+	u32 offset;
+
+	/*
+	 * GuC WOPCM size shall be at least a dword larger than the offset from
+	 * WOPCM base (GuC WOPCM offset from WOPCM base + GEN9_GUC_WOPCM_OFFSET)
+	 * due to hardware limitation on Gen9.
+	 */
+	offset = guc_wopcm_base + GEN9_GUC_WOPCM_OFFSET;
+	if (offset > guc_wopcm_size ||
+	    (guc_wopcm_size - offset) < sizeof(u32)) {
+		DRM_ERROR("GuC WOPCM size (%uKiB) is too small.%uKiB needed.\n",
+			  guc_wopcm_size / 1024,
+			  (u32)(offset + sizeof(u32)) / 1024);
+		return -E2BIG;
+	}
+
+	return 0;
+}
+
+static inline int check_hw_restriction(struct drm_i915_private *i915,
+				       u32 guc_wopcm_base, u32 guc_wopcm_size)
+{
+	int err = 0;
+
+	if (IS_GEN9(i915))
+		err = gen9_check_dword_gap(guc_wopcm_base, guc_wopcm_size);
+	if (err)
+		return err;
+
+	return 0;
+}
+
+/**
+ * intel_wopcm_init() - Initialize the WOPCM structure.
+ * @wopcm: pointer to intel_wopcm.
+ *
+ * This function will partition WOPCM space based on GuC and HuC firmware sizes
+ * and will allocate max remaining for use by GuC. This function will also
+ * enforce platform dependent hardware restrictions on GuC WOPCM offset and
+ * size. It will fail the WOPCM init if any of these checks were failed, so that
+ * the following GuC firmware uploading would be aborted.
+ *
+ * Return: 0 on success, non-zero error code on failure.
+ */
+int intel_wopcm_init(struct intel_wopcm *wopcm)
+{
+	struct drm_i915_private *i915 = wopcm_to_i915(wopcm);
+	u32 guc_fw_size = intel_uc_fw_get_upload_size(&i915->guc.fw);
+	u32 huc_fw_size = intel_uc_fw_get_upload_size(&i915->huc.fw);
+	u32 ctx_rsvd = context_reserved_size(i915);
+	u32 guc_wopcm_base;
+	u32 guc_wopcm_size;
+	u32 guc_wopcm_rsvd;
+	int err;
+
+	GEM_BUG_ON(!wopcm->size);
+
+	if (guc_fw_size >= wopcm->size) {
+		DRM_ERROR("GuC FW (%uKiB) is too big to fit in WOPCM.",
+			  guc_fw_size / 1024);
+		return -E2BIG;
+	}
+
+	if (huc_fw_size >= wopcm->size) {
+		DRM_ERROR("HuC FW (%uKiB) is too big to fit in WOPCM.",
+			  huc_fw_size / 1024);
+		return -E2BIG;
+	}
+
+	/* Hardware requires GuC WOPCM base to be 16K aligned. */
+	guc_wopcm_base = ALIGN(huc_fw_size + WOPCM_RESERVED_SIZE,
+			       GUC_WOPCM_OFFSET_ALIGNMENT);
+	if ((guc_wopcm_base + ctx_rsvd) >= wopcm->size) {
+		DRM_ERROR("GuC WOPCM base (%uKiB) is too big.\n",
+			  guc_wopcm_base / 1024);
+		return -E2BIG;
+	}
+
+	guc_wopcm_size = wopcm->size - guc_wopcm_base - ctx_rsvd;
+	/*
+	 * GuC WOPCM size must be multiple of 4K pages. We've got the maximum
+	 * WOPCM size available for GuC. Trim the size value to 4K boundary.
+	 */
+	guc_wopcm_size &= GUC_WOPCM_SIZE_MASK;
+
+	DRM_DEBUG_DRIVER("Calculated GuC WOPCM Region: [%uKiB, %uKiB)\n",
+			 guc_wopcm_base / 1024, guc_wopcm_size / 1024);
+
+	/*
+	 * GuC WOPCM size needs to be big enough to include all GuC firmware,
+	 * extra 8KiB stack for GuC firmware and GUC_WOPCM_RESERVED.
+	 */
+	guc_wopcm_rsvd = GUC_WOPCM_RESERVED + GUC_WOPCM_STACK_RESERVED;
+	if ((guc_fw_size + guc_wopcm_rsvd) > guc_wopcm_size) {
+		DRM_ERROR("Need %uKiB WOPCM for GuC, %uKiB available.\n",
+			  (guc_fw_size + guc_wopcm_rsvd) / 1024,
+			  guc_wopcm_size / 1024);
+		return -E2BIG;
+	}
+
+	err = check_hw_restriction(i915, guc_wopcm_base, guc_wopcm_size);
+	if (err) {
+		DRM_ERROR("Failed to meet HW restriction.\n");
+		return err;
+	}
+
+	wopcm->guc.base = guc_wopcm_base;
+	wopcm->guc.size = guc_wopcm_size;
+
+	return 0;
+}
diff --git a/drivers/gpu/drm/i915/intel_wopcm.h b/drivers/gpu/drm/i915/intel_wopcm.h
new file mode 100644
index 0000000..39d4847
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_wopcm.h
@@ -0,0 +1,34 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2017-2018 Intel Corporation
+ */
+
+#ifndef _INTEL_WOPCM_H_
+#define _INTEL_WOPCM_H_
+
+#include <linux/types.h>
+
+/**
+ * struct intel_wopcm - overall WOPCM info and WOPCM regions.
+ * @size: size of overall WOPCM.
+ * @guc: GuC WOPCM Region info.
+ */
+struct intel_wopcm {
+	u32 size;
+	struct {
+		/**
+		 * @base: GuC WOPCM base which is offset from WOPCM base.
+		 */
+		u32 base;
+		/**
+		 * @size: size of the GuC WOPCM region.
+		 */
+		u32 size;
+	} guc;
+};
+
+void intel_wopcm_init_early(struct intel_wopcm *wopcm);
+int intel_wopcm_init(struct intel_wopcm *wopcm);
+
+#endif
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 17+ messages in thread
* [PATCH v12 3/6] drm/i915: Add support to return CNL specific reserved WOPCM size
  2018-03-02  0:16 [PATCH v12 1/6] drm/i915/guc: Rename guc_ggtt_offset to intel_guc_ggtt_offset Jackie Li
  2018-03-02  0:16 ` [PATCH v12 2/6] drm/i915: Implement dynamic GuC WOPCM offset and size calculation Jackie Li
@ 2018-03-02  0:16 ` Jackie Li
  2018-03-13 12:11   ` Joonas Lahtinen
  2018-03-02  0:16 ` [PATCH v12 4/6] drm/i915: Add HuC firmware size related restriction for Gen9 and CNL A0 Jackie Li
                   ` (5 subsequent siblings)
  7 siblings, 1 reply; 17+ messages in thread
From: Jackie Li @ 2018-03-02  0:16 UTC (permalink / raw)
  To: intel-gfx

CNL has its specific reserved GuC WOPCM size for RC6 and other hardware
contexts.

This patch updates the code to return CNL specific reserved GuC WOPCM size
for RC6 and other hardware contexts so that the GuC WOPCM size can be
calculated correctly for CNL.

v9:
 - Created a new patch for these changes originally made in v8 4/6 patch of
   this series (Sagar/Michal)

v10:
 - Used if-else ladder to the returning of context sizes (Joonas)

v11:
 - Removed GUC_ prefix from context size macro (Michal)

Bspec: 12690

Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> (v9)
Signed-off-by: Jackie Li <yaodong.li@intel.com>
Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com> (v11)
---
 drivers/gpu/drm/i915/intel_wopcm.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_wopcm.c b/drivers/gpu/drm/i915/intel_wopcm.c
index 8b2f177..237ca03 100644
--- a/drivers/gpu/drm/i915/intel_wopcm.c
+++ b/drivers/gpu/drm/i915/intel_wopcm.c
@@ -54,6 +54,8 @@
 
 /* 24KB at the end of WOPCM is reserved for RC6 CTX on BXT. */
 #define BXT_WOPCM_RC6_CTX_RESERVED	(24 * 1024)
+/* 36KB WOPCM reserved at the end of WOPCM on CNL. */
+#define CNL_WOPCM_HW_CTX_RESERVED	(36 * 1024)
 
 /* 128KB from GUC_WOPCM_RESERVED is reserved for FW on Gen9. */
 #define GEN9_GUC_FW_RESERVED	(128 * 1024)
@@ -76,6 +78,8 @@ static inline u32 context_reserved_size(struct drm_i915_private *i915)
 {
 	if (IS_GEN9_LP(i915))
 		return BXT_WOPCM_RC6_CTX_RESERVED;
+	else if (INTEL_GEN(i915) >= 10)
+		return CNL_WOPCM_HW_CTX_RESERVED;
 	else
 		return 0;
 }
-- 
2.7.4

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 17+ messages in thread
* [PATCH v12 4/6] drm/i915: Add HuC firmware size related restriction for Gen9 and CNL A0
  2018-03-02  0:16 [PATCH v12 1/6] drm/i915/guc: Rename guc_ggtt_offset to intel_guc_ggtt_offset Jackie Li
  2018-03-02  0:16 ` [PATCH v12 2/6] drm/i915: Implement dynamic GuC WOPCM offset and size calculation Jackie Li
  2018-03-02  0:16 ` [PATCH v12 3/6] drm/i915: Add support to return CNL specific reserved WOPCM size Jackie Li
@ 2018-03-02  0:16 ` Jackie Li
  2018-03-13 12:12   ` Joonas Lahtinen
  2018-03-02  0:16 ` [PATCH v12 5/6] drm/i915/guc: Check the locking status of GuC WOPCM registers Jackie Li
                   ` (4 subsequent siblings)
  7 siblings, 1 reply; 17+ messages in thread
From: Jackie Li @ 2018-03-02  0:16 UTC (permalink / raw)
  To: intel-gfx

On CNL A0 and Gen9, there's a hardware restriction that requires the
available GuC WOPCM size to be larger than or equal to HuC firmware size.

This patch adds new verification code to ensure the available GuC WOPCM
size to be larger than or equal to HuC firmware size on both Gen9 and CNL
A0.

v6:
 - Extended HuC FW size check against GuC WOPCM size to all
   Gen9 and CNL A0 platforms

v7:
 - Fixed patch format issues

v8:
 - Renamed variables and functions to avoid ambiguity (Joonas)
 - Updated commit message and comments to be more comprehensive (Sagar)

v9:
 - Moved code that is not related to restriction check into a separate
   patch and updated the commit message accordingly (Sagar/Michal)
 - Avoided to call uc_get_fw_size for better layer isolation (Michal)

v10:
 - Shorten function names and reorganized size_check code to have clear
   isolation (Joonas)
 - Removed unnecessary comments (Joonas)

v11:
 - Fixed logic error in size check (Michal)

v12:
 - Add space between "HuC FW" and "(%uKiB)" in error message (Michal)

BSpec: 10875

Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: John Spotswood <john.a.spotswood@intel.com>
Cc: Jeff McGee <jeff.mcgee@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com> (v8)
Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com> (v11)
Signed-off-by: Jackie Li <yaodong.li@intel.com>
---
 drivers/gpu/drm/i915/intel_wopcm.c | 28 +++++++++++++++++++++++++---
 1 file changed, 25 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_wopcm.c b/drivers/gpu/drm/i915/intel_wopcm.c
index 237ca03..a94e8f0 100644
--- a/drivers/gpu/drm/i915/intel_wopcm.c
+++ b/drivers/gpu/drm/i915/intel_wopcm.c
@@ -105,8 +105,26 @@ static inline int gen9_check_dword_gap(u32 guc_wopcm_base, u32 guc_wopcm_size)
 	return 0;
 }
 
+static inline int gen9_check_huc_fw_fits(u32 guc_wopcm_size, u32 huc_fw_size)
+{
+	/*
+	 * On Gen9 & CNL A0, hardware requires the total available GuC WOPCM
+	 * size to be larger than or equal to HuC firmware size. Otherwise,
+	 * firmware uploading would fail.
+	 */
+	if (huc_fw_size > guc_wopcm_size - GUC_WOPCM_RESERVED) {
+		DRM_ERROR("HuC FW (%uKiB) won't fit in GuC WOPCM (%uKiB).\n",
+			  huc_fw_size / 1024,
+			  (guc_wopcm_size - GUC_WOPCM_RESERVED) / 1024);
+		return -E2BIG;
+	}
+
+	return 0;
+}
+
 static inline int check_hw_restriction(struct drm_i915_private *i915,
-				       u32 guc_wopcm_base, u32 guc_wopcm_size)
+				       u32 guc_wopcm_base, u32 guc_wopcm_size,
+				       u32 huc_fw_size)
 {
 	int err = 0;
 
@@ -115,7 +133,10 @@ static inline int check_hw_restriction(struct drm_i915_private *i915,
 	if (err)
 		return err;
 
-	return 0;
+	if (IS_GEN9(i915) || IS_CNL_REVID(i915, CNL_REVID_A0, CNL_REVID_A0))
+		err = gen9_check_huc_fw_fits(guc_wopcm_size, huc_fw_size);
+
+	return err;
 }
 
 /**
@@ -186,7 +207,8 @@ int intel_wopcm_init(struct intel_wopcm *wopcm)
 		return -E2BIG;
 	}
 
-	err = check_hw_restriction(i915, guc_wopcm_base, guc_wopcm_size);
+	err = check_hw_restriction(i915, guc_wopcm_base, guc_wopcm_size,
+				   huc_fw_size);
 	if (err) {
 		DRM_ERROR("Failed to meet HW restriction.\n");
 		return err;
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 17+ messages in thread
* [PATCH v12 5/6] drm/i915/guc: Check the locking status of GuC WOPCM registers
  2018-03-02  0:16 [PATCH v12 1/6] drm/i915/guc: Rename guc_ggtt_offset to intel_guc_ggtt_offset Jackie Li
                   ` (2 preceding siblings ...)
  2018-03-02  0:16 ` [PATCH v12 4/6] drm/i915: Add HuC firmware size related restriction for Gen9 and CNL A0 Jackie Li
@ 2018-03-02  0:16 ` Jackie Li
  2018-03-13 12:20   ` Joonas Lahtinen
       [not found]   ` <466b9074-2716-f3e8-161a-95b9ca03a06a@intel.com>
  2018-03-02  0:16 ` [PATCH v12 6/6] HAX Enable GuC Submission for CI Jackie Li
                   ` (3 subsequent siblings)
  7 siblings, 2 replies; 17+ messages in thread
From: Jackie Li @ 2018-03-02  0:16 UTC (permalink / raw)
  To: intel-gfx

GuC WOPCM registers are write-once registers. Current driver code accesses
these registers without checking the accessibility to these registers which
will lead to unpredictable driver behaviors if these registers were touch
by other components (such as faulty BIOS code).

This patch moves the GuC WOPCM registers updating code into intel_wopcm.c
and adds check before and after the update to GuC WOPCM registers so that
we can make sure the driver is in a known state after writing to these
write-once registers.

v6:
 - Made sure module reloading won't bug the kernel while doing
   locking status checking

v7:
 - Fixed patch format issues

v8:
 - Fixed coding style issue on register lock bit macro definition (Sagar)

v9:
 - Avoided to use redundant !! to cast uint to bool (Chris)
 - Return error code instead of GEM_BUG_ON for locked with invalid register
   values case (Sagar)
 - Updated guc_wopcm_hw_init to use guc_wopcm as first parameter (Michal)
 - Added code to set and validate the HuC_LOADING_AGENT_GUC bit in GuC
   WOPCM offset register based on the presence of HuC firmware (Michal)
 - Use bit fields instead of macros for GuC WOPCM flags (Michal)

v10:
 - Refined variable names, removed redundant comments (Joonas)
 - Introduced lockable_reg to handle the write once register write and
   propagate the write error to caller (Joonas)
 - Used lockable_reg abstraction to avoid locking bit check on generic
   i915_reg_t (Michal)
 - Added log message for error paths (Michal)
 - Removed hw_updated flag and only relies on real hardware status

v11:
 - Replaced lockable_reg with simplified function (Michal)
 - Used new macros for locking bits of WOPCM size/offset registers instead
   of using BIT(0) directly (Michal)
 - use intel_wopcm_init_hw() called from intel_gem_init_hw() to do GuC
   WOPCM register setup instead of calling from intel_uc_init_hw() (Michal)

v12:
 - Updated function kernel-doc to align with code changes (Michal)
 - Updated code to use wopcm pointer directly (Michal)

BSpec: 10875, 10833

Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com> (v11)
Signed-off-by: Jackie Li <yaodong.li@intel.com>
---
 drivers/gpu/drm/i915/i915_gem.c      |  6 ++++
 drivers/gpu/drm/i915/intel_guc_reg.h |  3 ++
 drivers/gpu/drm/i915/intel_uc.c      |  5 ---
 drivers/gpu/drm/i915/intel_wopcm.c   | 64 ++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_wopcm.h   |  1 +
 5 files changed, 74 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index d31ad0b..662d670 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5122,6 +5122,12 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
 		goto out;
 	}
 
+	ret = intel_wopcm_init_hw(&dev_priv->wopcm);
+	if (ret) {
+		DRM_ERROR("Enabling WOPCM failed (%d)\n", ret);
+		goto out;
+	}
+
 	/* We can't enable contexts until all firmware is loaded */
 	ret = intel_uc_init_hw(dev_priv);
 	if (ret) {
diff --git a/drivers/gpu/drm/i915/intel_guc_reg.h b/drivers/gpu/drm/i915/intel_guc_reg.h
index 01963d0..d860847 100644
--- a/drivers/gpu/drm/i915/intel_guc_reg.h
+++ b/drivers/gpu/drm/i915/intel_guc_reg.h
@@ -66,15 +66,18 @@
 #define   UOS_MOVE			  (1<<4)
 #define   START_DMA			  (1<<0)
 #define DMA_GUC_WOPCM_OFFSET		_MMIO(0xc340)
+#define   GUC_WOPCM_OFFSET_VALID	  (1<<0)
 #define   HUC_LOADING_AGENT_VCR		  (0<<1)
 #define   HUC_LOADING_AGENT_GUC		  (1<<1)
 #define   GUC_WOPCM_OFFSET_SHIFT	14
+#define   GUC_WOPCM_OFFSET_MASK		  (0x3ffff << GUC_WOPCM_OFFSET_SHIFT)
 #define GUC_MAX_IDLE_COUNT		_MMIO(0xC3E4)
 
 #define HUC_STATUS2             _MMIO(0xD3B0)
 #define   HUC_FW_VERIFIED       (1<<7)
 
 #define GUC_WOPCM_SIZE			_MMIO(0xc050)
+#define   GUC_WOPCM_SIZE_LOCKED		  (1<<0)
 #define   GUC_WOPCM_SIZE_SHIFT		12
 #define   GUC_WOPCM_SIZE_MASK		  (0xfffff << GUC_WOPCM_SIZE_SHIFT)
 
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 964e49f..58186f2 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -341,11 +341,6 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
 	guc_disable_communication(guc);
 	gen9_reset_guc_interrupts(dev_priv);
 
-	/* init WOPCM */
-	I915_WRITE(GUC_WOPCM_SIZE, dev_priv->wopcm.guc.size);
-	I915_WRITE(DMA_GUC_WOPCM_OFFSET,
-		   dev_priv->wopcm.guc.base | HUC_LOADING_AGENT_GUC);
-
 	/* WaEnableuKernelHeaderValidFix:skl */
 	/* WaEnableGuCBootHashCheckNotSet:skl,bxt,kbl */
 	if (IS_GEN9(dev_priv))
diff --git a/drivers/gpu/drm/i915/intel_wopcm.c b/drivers/gpu/drm/i915/intel_wopcm.c
index a94e8f0..8de42f8 100644
--- a/drivers/gpu/drm/i915/intel_wopcm.c
+++ b/drivers/gpu/drm/i915/intel_wopcm.c
@@ -219,3 +219,67 @@ int intel_wopcm_init(struct intel_wopcm *wopcm)
 
 	return 0;
 }
+
+static inline int write_and_verify(struct drm_i915_private *dev_priv,
+				   i915_reg_t reg, u32 val, u32 mask,
+				   u32 locked_bit)
+{
+	u32 reg_val;
+
+	GEM_BUG_ON(val & ~mask);
+
+	I915_WRITE(reg, val);
+
+	reg_val = I915_READ(reg);
+
+	return (reg_val & mask) != (val | locked_bit) ? -EIO : 0;
+}
+
+/**
+ * intel_wopcm_init_hw() - Setup GuC WOPCM registers.
+ * @wopcm: pointer to intel_wopcm.
+ *
+ * Setup the GuC WOPCM size and offset registers with the calculated values. It
+ * will verify the register values to make sure the registers are locked with
+ * correct values.
+ *
+ * Return: 0 on success. -EIO if registers were locked with incorrect values.
+ */
+int intel_wopcm_init_hw(struct intel_wopcm *wopcm)
+{
+	struct drm_i915_private *dev_priv = wopcm_to_i915(wopcm);
+	u32 huc_agent;
+	u32 mask;
+	int err;
+
+	if (!USES_GUC(dev_priv))
+		return 0;
+
+	GEM_BUG_ON(!HAS_GUC(dev_priv));
+	GEM_BUG_ON(!wopcm->guc.size);
+	GEM_BUG_ON(!wopcm->guc.base);
+
+	err = write_and_verify(dev_priv, GUC_WOPCM_SIZE, wopcm->guc.size,
+			       GUC_WOPCM_SIZE_MASK | GUC_WOPCM_SIZE_LOCKED,
+			       GUC_WOPCM_SIZE_LOCKED);
+	if (err)
+		goto err_out;
+
+	huc_agent = USES_HUC(dev_priv) ? HUC_LOADING_AGENT_GUC : 0;
+	mask = GUC_WOPCM_OFFSET_MASK | GUC_WOPCM_OFFSET_VALID | huc_agent;
+	err = write_and_verify(dev_priv, DMA_GUC_WOPCM_OFFSET,
+			       wopcm->guc.base | huc_agent, mask,
+			       GUC_WOPCM_OFFSET_VALID);
+	if (err)
+		goto err_out;
+
+	return 0;
+
+err_out:
+	DRM_ERROR("Failed to init WOPCM registers:\n");
+	DRM_ERROR("DMA_GUC_WOPCM_OFFSET=%#x\n",
+		  I915_READ(DMA_GUC_WOPCM_OFFSET));
+	DRM_ERROR("GUC_WOPCM_SIZE=%#x\n", I915_READ(GUC_WOPCM_SIZE));
+
+	return err;
+}
diff --git a/drivers/gpu/drm/i915/intel_wopcm.h b/drivers/gpu/drm/i915/intel_wopcm.h
index 39d4847..882f54b 100644
--- a/drivers/gpu/drm/i915/intel_wopcm.h
+++ b/drivers/gpu/drm/i915/intel_wopcm.h
@@ -30,5 +30,6 @@ struct intel_wopcm {
 
 void intel_wopcm_init_early(struct intel_wopcm *wopcm);
 int intel_wopcm_init(struct intel_wopcm *wopcm);
+int intel_wopcm_init_hw(struct intel_wopcm *wopcm);
 
 #endif
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 17+ messages in thread
* [PATCH v12 6/6] HAX Enable GuC Submission for CI
  2018-03-02  0:16 [PATCH v12 1/6] drm/i915/guc: Rename guc_ggtt_offset to intel_guc_ggtt_offset Jackie Li
                   ` (3 preceding siblings ...)
  2018-03-02  0:16 ` [PATCH v12 5/6] drm/i915/guc: Check the locking status of GuC WOPCM registers Jackie Li
@ 2018-03-02  0:16 ` Jackie Li
  2018-03-02  0:59 ` ✗ Fi.CI.BAT: failure for series starting with [v12,1/6] drm/i915/guc: Rename guc_ggtt_offset to intel_guc_ggtt_offset Patchwork
                   ` (2 subsequent siblings)
  7 siblings, 0 replies; 17+ messages in thread
From: Jackie Li @ 2018-03-02  0:16 UTC (permalink / raw)
  To: intel-gfx

Signed-off-by: Jackie Li <yaodong.li@intel.com>
---
 drivers/gpu/drm/i915/i915_params.c | 2 +-
 drivers/gpu/drm/i915/i915_params.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index 08108ce..b49ae20 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -152,7 +152,7 @@ i915_param_named_unsafe(edp_vswing, int, 0400,
 i915_param_named_unsafe(enable_guc, int, 0400,
 	"Enable GuC load for GuC submission and/or HuC load. "
 	"Required functionality can be selected using bitmask values. "
-	"(-1=auto, 0=disable [default], 1=GuC submission, 2=HuC load)");
+	"(-1=auto [default], 0=disable, 1=GuC submission, 2=HuC load)");
 
 i915_param_named(guc_log_level, int, 0400,
 	"GuC firmware logging level. Requires GuC to be loaded. "
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index 430f5f9..3deae1e 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -47,7 +47,7 @@ struct drm_printer;
 	param(int, disable_power_well, -1) \
 	param(int, enable_ips, 1) \
 	param(int, invert_brightness, 0) \
-	param(int, enable_guc, 0) \
+	param(int, enable_guc, -1) \
 	param(int, guc_log_level, 0) \
 	param(char *, guc_firmware_path, NULL) \
 	param(char *, huc_firmware_path, NULL) \
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 17+ messages in thread
* ✗ Fi.CI.BAT: failure for series starting with [v12,1/6] drm/i915/guc: Rename guc_ggtt_offset to intel_guc_ggtt_offset
  2018-03-02  0:16 [PATCH v12 1/6] drm/i915/guc: Rename guc_ggtt_offset to intel_guc_ggtt_offset Jackie Li
                   ` (4 preceding siblings ...)
  2018-03-02  0:16 ` [PATCH v12 6/6] HAX Enable GuC Submission for CI Jackie Li
@ 2018-03-02  0:59 ` Patchwork
  2018-03-02  8:04 ` [PATCH v12 1/6] " Sagar Arun Kamble
  2018-03-13 10:21 ` Joonas Lahtinen
  7 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2018-03-02  0:59 UTC (permalink / raw)
  To: Jackie Li; +Cc: intel-gfx

== Series Details ==

Series: series starting with [v12,1/6] drm/i915/guc: Rename guc_ggtt_offset to intel_guc_ggtt_offset
URL   : https://patchwork.freedesktop.org/series/39246/
State : failure

== Summary ==

Series 39246v1 series starting with [v12,1/6] drm/i915/guc: Rename guc_ggtt_offset to intel_guc_ggtt_offset
https://patchwork.freedesktop.org/api/1.0/series/39246/revisions/1/mbox/

---- Possible new issues:

Test core_auth:
        Subgroup basic-auth:
                pass       -> SKIP       (fi-skl-gvtdvm)
Test core_prop_blob:
        Subgroup basic:
                pass       -> SKIP       (fi-skl-gvtdvm)
Test debugfs_test:
        Subgroup read_all_entries:
                pass       -> SKIP       (fi-skl-gvtdvm)
Test drv_getparams_basic:
        Subgroup basic-eu-total:
                pass       -> SKIP       (fi-skl-gvtdvm)
        Subgroup basic-subslice-total:
                pass       -> SKIP       (fi-skl-gvtdvm)
Test drv_hangman:
        Subgroup error-state-basic:
                pass       -> SKIP       (fi-skl-gvtdvm)
Test drv_module_reload:
        Subgroup basic-no-display:
                pass       -> DMESG-FAIL (fi-skl-gvtdvm)
        Subgroup basic-reload:
                pass       -> DMESG-FAIL (fi-skl-gvtdvm)
        Subgroup basic-reload-inject:
                pass       -> DMESG-FAIL (fi-skl-gvtdvm)
Test gem_basic:
        Subgroup bad-close:
                pass       -> SKIP       (fi-skl-gvtdvm)
        Subgroup create-close:
                pass       -> SKIP       (fi-skl-gvtdvm)
        Subgroup create-fd-close:
                pass       -> SKIP       (fi-skl-gvtdvm)
Test gem_busy:
        Subgroup basic-busy-default:
                pass       -> SKIP       (fi-skl-gvtdvm)
Test gem_close_race:
        Subgroup basic-process:
                pass       -> SKIP       (fi-skl-gvtdvm)
        Subgroup basic-threads:
                pass       -> SKIP       (fi-skl-gvtdvm)
Test gem_cpu_reloc:
        Subgroup basic:
                pass       -> SKIP       (fi-skl-gvtdvm)
Test gem_cs_tlb:
        Subgroup basic-default:
                pass       -> SKIP       (fi-skl-gvtdvm)
Test gem_ctx_create:
        Subgroup basic:
                pass       -> SKIP       (fi-skl-gvtdvm)
        Subgroup basic-files:
                pass       -> SKIP       (fi-skl-gvtdvm)
Test gem_ctx_exec:
        Subgroup basic:
                pass       -> SKIP       (fi-skl-gvtdvm)
Test gem_ctx_param:
        Subgroup basic:
                pass       -> SKIP       (fi-skl-gvtdvm)
        Subgroup basic-default:
                pass       -> SKIP       (fi-skl-gvtdvm)
Test gem_ctx_switch:
        Subgroup basic-default:
                pass       -> SKIP       (fi-skl-gvtdvm)
        Subgroup basic-default-heavy:
                pass       -> SKIP       (fi-skl-gvtdvm)
Test gem_exec_basic:
        Subgroup basic-blt:
                pass       -> SKIP       (fi-skl-gvtdvm)
        Subgroup basic-bsd:
                pass       -> SKIP       (fi-skl-gvtdvm)
        Subgroup basic-bsd1:
                pass       -> SKIP       (fi-skl-gvtdvm)
        Subgroup basic-bsd2:
                pass       -> SKIP       (fi-skl-gvtdvm)
        Subgroup basic-default:
                pass       -> SKIP       (fi-skl-gvtdvm)
        Subgroup basic-render:
                pass       -> SKIP       (fi-skl-gvtdvm)
        Subgroup basic-vebox:
                pass       -> SKIP       (fi-skl-gvtdvm)
        Subgroup gtt-blt:
                pass       -> SKIP       (fi-skl-gvtdvm)
        Subgroup gtt-bsd:
                pass       -> SKIP       (fi-skl-gvtdvm)
        Subgroup gtt-bsd1:
                pass       -> SKIP       (fi-skl-gvtdvm)
        Subgroup gtt-bsd2:
                pass       -> SKIP       (fi-skl-gvtdvm)
        Subgroup gtt-default:
                pass       -> SKIP       (fi-skl-gvtdvm)
        Subgroup gtt-render:
                pass       -> SKIP       (fi-skl-gvtdvm)
        Subgroup gtt-vebox:
                pass       -> SKIP       (fi-skl-gvtdvm)
        Subgroup readonly-blt:
                pass       -> SKIP       (fi-skl-gvtdvm)
        Subgroup readonly-bsd:
WARNING: Long output truncated
fi-cnl-y3 failed to collect. IGT log at Patchwork_8206/fi-cnl-y3/run0.log

f9dfffd99a0eece6e115bf1f678108dac871ef04 drm-tip: 2018y-03m-02d-00h-00m-27s UTC integration manifest
d3be383a46d3 HAX Enable GuC Submission for CI
ed66365a5cb6 drm/i915/guc: Check the locking status of GuC WOPCM registers
69b1615bf155 drm/i915: Add HuC firmware size related restriction for Gen9 and CNL A0
4b9ff5708835 drm/i915: Add support to return CNL specific reserved WOPCM size
9b8cd81ac573 drm/i915: Implement dynamic GuC WOPCM offset and size calculation
009573200501 drm/i915/guc: Rename guc_ggtt_offset to intel_guc_ggtt_offset

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8206/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 17+ messages in thread
* Re: [PATCH v12 1/6] drm/i915/guc: Rename guc_ggtt_offset to intel_guc_ggtt_offset
  2018-03-02  0:16 [PATCH v12 1/6] drm/i915/guc: Rename guc_ggtt_offset to intel_guc_ggtt_offset Jackie Li
                   ` (5 preceding siblings ...)
  2018-03-02  0:59 ` ✗ Fi.CI.BAT: failure for series starting with [v12,1/6] drm/i915/guc: Rename guc_ggtt_offset to intel_guc_ggtt_offset Patchwork
@ 2018-03-02  8:04 ` Sagar Arun Kamble
  2018-03-05 21:49   ` Yaodong Li
  2018-03-13 10:21 ` Joonas Lahtinen
  7 siblings, 1 reply; 17+ messages in thread
From: Sagar Arun Kamble @ 2018-03-02  8:04 UTC (permalink / raw)
  To: Jackie Li, intel-gfx



On 3/2/2018 5:46 AM, Jackie Li wrote:
> GuC related exported functions should start with "intel_guc_" prefix and
> pass intel_guc as the first parameter since its GuC related. Current
> guc_ggtt_offset() failed to follow this code convention and this is a
> problem for future patches that needs to access intel_guc data to verify
> the GGTT offset against the GuC WOPCM top.
>
> This patch renames the guc_ggtt_offset to intel_guc_ggtt_offset and updates
> the related code to pass intel_guc pointer to this function call, so that
> we can have a unified coding style for GuC code and also enable the future
> patches to get GuC related data from intel_guc to do the offset
> verification. Meanwhile, this patch also moves the GUC_GGTT_TOP from
> intel_guc_regs.h to intel_guc.h since it is not GuC register related
> definition.
>
> v8:
>   - Fixed coding style issues and moved GUC_GGTT_TOP to intel_guc.h (Sagar)
>   - Updated commit message to explain to reason and motivation to add
>     intel_guc as the first parameter of intel_guc_ggtt_offset (Chris)
>
> v9:
>   - Fixed code alignment issue due to line break (Chris)
>
> v10:
>   - Removed unnecessary comments, redundant code and avoided reuse variable
>     to avoid potential issues (Joonas)
>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com> (v8)
> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> (v9)
> Signed-off-by: Jackie Li <yaodong.li@intel.com>
I think maintainers will prefer as:
either

Cc:
Cc:
S-o-b:
R-b:

or

S-o-b:
Cc:
Cc:
R-b:

Similar for other patches.
> Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com> (v11)
> ---
>   drivers/gpu/drm/i915/intel_guc.c            | 11 ++++++-----
>   drivers/gpu/drm/i915/intel_guc.h            | 14 ++++++++++++--
>   drivers/gpu/drm/i915/intel_guc_ads.c        |  8 ++++----
>   drivers/gpu/drm/i915/intel_guc_ct.c         |  5 +++--
>   drivers/gpu/drm/i915/intel_guc_fw.c         |  2 +-
>   drivers/gpu/drm/i915/intel_guc_log.c        |  2 +-
>   drivers/gpu/drm/i915/intel_guc_reg.h        |  3 ---
>   drivers/gpu/drm/i915/intel_guc_submission.c | 10 +++++-----
>   drivers/gpu/drm/i915/intel_huc.c            |  6 ++++--
>   9 files changed, 36 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
> index e6512cc..a788e15 100644
> --- a/drivers/gpu/drm/i915/intel_guc.c
> +++ b/drivers/gpu/drm/i915/intel_guc.c
> @@ -269,8 +269,9 @@ void intel_guc_init_params(struct intel_guc *guc)
>   
>   	/* If GuC submission is enabled, set up additional parameters here */
>   	if (USES_GUC_SUBMISSION(dev_priv)) {
> -		u32 ads = guc_ggtt_offset(guc->ads_vma) >> PAGE_SHIFT;
> -		u32 pgs = guc_ggtt_offset(dev_priv->guc.stage_desc_pool);
> +		u32 ads = intel_guc_ggtt_offset(guc,
> +						guc->ads_vma) >> PAGE_SHIFT;
> +		u32 pgs = intel_guc_ggtt_offset(guc, guc->stage_desc_pool);
>   		u32 ctx_in_16 = GUC_MAX_STAGE_DESCRIPTORS / 16;
>   
>   		params[GUC_CTL_DEBUG] |= ads << GUC_ADS_ADDR_SHIFT;
> @@ -418,7 +419,7 @@ int intel_guc_suspend(struct drm_i915_private *dev_priv)
>   	data[0] = INTEL_GUC_ACTION_ENTER_S_STATE;
>   	/* any value greater than GUC_POWER_D0 */
>   	data[1] = GUC_POWER_D1;
> -	data[2] = guc_ggtt_offset(guc->shared_data);
> +	data[2] = intel_guc_ggtt_offset(guc, guc->shared_data);
>   
>   	return intel_guc_send(guc, data, ARRAY_SIZE(data));
>   }
> @@ -441,7 +442,7 @@ int intel_guc_reset_engine(struct intel_guc *guc,
>   	data[3] = 0;
>   	data[4] = 0;
>   	data[5] = guc->execbuf_client->stage_id;
> -	data[6] = guc_ggtt_offset(guc->shared_data);
> +	data[6] = intel_guc_ggtt_offset(guc, guc->shared_data);
>   
>   	return intel_guc_send(guc, data, ARRAY_SIZE(data));
>   }
> @@ -463,7 +464,7 @@ int intel_guc_resume(struct drm_i915_private *dev_priv)
>   
>   	data[0] = INTEL_GUC_ACTION_EXIT_S_STATE;
>   	data[1] = GUC_POWER_D0;
> -	data[2] = guc_ggtt_offset(guc->shared_data);
> +	data[2] = intel_guc_ggtt_offset(guc, guc->shared_data);
>   
>   	return intel_guc_send(guc, data, ARRAY_SIZE(data));
>   }
> diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
> index 52856a9..0c8b10a 100644
> --- a/drivers/gpu/drm/i915/intel_guc.h
> +++ b/drivers/gpu/drm/i915/intel_guc.h
> @@ -100,13 +100,23 @@ static inline void intel_guc_notify(struct intel_guc *guc)
>   	guc->notify(guc);
>   }
>   
> -/*
> +/* GuC addresses above GUC_GGTT_TOP also don't map through the GTT */
> +#define GUC_GGTT_TOP	0xFEE00000
> +
> +/**
> + * intel_guc_ggtt_offset() - Get and validate the GGTT offset of @vma
> + * @guc: intel_guc structure.
> + * @vma: i915 graphics virtual memory area.
> + *
>    * GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP),
>    * which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is
>    * 512K. In order to exclude 0-512K address space from GGTT, all gfx objects
>    * used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM.
> + *
> + * Return: GGTT offset that meets the GuC gfx address requirement.
>    */
> -static inline u32 guc_ggtt_offset(struct i915_vma *vma)
> +static inline u32 intel_guc_ggtt_offset(struct intel_guc *guc,
> +					struct i915_vma *vma)
>   {
>   	u32 offset = i915_ggtt_offset(vma);
>   
> diff --git a/drivers/gpu/drm/i915/intel_guc_ads.c b/drivers/gpu/drm/i915/intel_guc_ads.c
> index ac62753..334cb52 100644
> --- a/drivers/gpu/drm/i915/intel_guc_ads.c
> +++ b/drivers/gpu/drm/i915/intel_guc_ads.c
> @@ -75,7 +75,7 @@ static void guc_policies_init(struct guc_policies *policies)
>   int intel_guc_ads_create(struct intel_guc *guc)
>   {
>   	struct drm_i915_private *dev_priv = guc_to_i915(guc);
> -	struct i915_vma *vma;
> +	struct i915_vma *vma, *kernel_ctx_vma;
>   	struct page *page;
>   	/* The ads obj includes the struct itself and buffers passed to GuC */
>   	struct {
> @@ -121,9 +121,9 @@ int intel_guc_ads_create(struct intel_guc *guc)
>   	 * to find it. Note that we have to skip our header (1 page),
>   	 * because our GuC shared data is there.
>   	 */
> +	kernel_ctx_vma = dev_priv->kernel_context->engine[RCS].state;
>   	blob->ads.golden_context_lrca =
> -		guc_ggtt_offset(dev_priv->kernel_context->engine[RCS].state) +
> -		skipped_offset;
> +		intel_guc_ggtt_offset(guc, kernel_ctx_vma) + skipped_offset;
>   
>   	/*
>   	 * The GuC expects us to exclude the portion of the context image that
> @@ -135,7 +135,7 @@ int intel_guc_ads_create(struct intel_guc *guc)
>   		blob->ads.eng_state_size[engine->guc_id] =
>   			engine->context_size - skipped_size;
>   
> -	base = guc_ggtt_offset(vma);
> +	base = intel_guc_ggtt_offset(guc, vma);
>   	blob->ads.scheduler_policies = base + ptr_offset(blob, policies);
>   	blob->ads.reg_state_buffer = base + ptr_offset(blob, reg_state_buffer);
>   	blob->ads.reg_state_addr = base + ptr_offset(blob, reg_state);
> diff --git a/drivers/gpu/drm/i915/intel_guc_ct.c b/drivers/gpu/drm/i915/intel_guc_ct.c
> index 24ad557..0a0d3d5 100644
> --- a/drivers/gpu/drm/i915/intel_guc_ct.c
> +++ b/drivers/gpu/drm/i915/intel_guc_ct.c
> @@ -156,7 +156,8 @@ static int ctch_init(struct intel_guc *guc,
>   		err = PTR_ERR(blob);
>   		goto err_vma;
>   	}
> -	DRM_DEBUG_DRIVER("CT: vma base=%#x\n", guc_ggtt_offset(ctch->vma));
> +	DRM_DEBUG_DRIVER("CT: vma base=%#x\n",
> +			 intel_guc_ggtt_offset(guc, ctch->vma));
>   
>   	/* store pointers to desc and cmds */
>   	for (i = 0; i < ARRAY_SIZE(ctch->ctbs); i++) {
> @@ -202,7 +203,7 @@ static int ctch_open(struct intel_guc *guc,
>   	}
>   
>   	/* vma should be already allocated and map'ed */
> -	base = guc_ggtt_offset(ctch->vma);
> +	base = intel_guc_ggtt_offset(guc, ctch->vma);
>   
>   	/* (re)initialize descriptors
>   	 * cmds buffers are in the second half of the blob page
> diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c b/drivers/gpu/drm/i915/intel_guc_fw.c
> index 3b09329..178d339 100644
> --- a/drivers/gpu/drm/i915/intel_guc_fw.c
> +++ b/drivers/gpu/drm/i915/intel_guc_fw.c
> @@ -165,7 +165,7 @@ static int guc_xfer_ucode(struct intel_guc *guc, struct i915_vma *vma)
>   	I915_WRITE(DMA_COPY_SIZE, guc_fw->header_size + guc_fw->ucode_size);
>   
>   	/* Set the source address for the new blob */
> -	offset = guc_ggtt_offset(vma) + guc_fw->header_offset;
> +	offset = intel_guc_ggtt_offset(guc, vma) + guc_fw->header_offset;
>   	I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
>   	I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
>   
> diff --git a/drivers/gpu/drm/i915/intel_guc_log.c b/drivers/gpu/drm/i915/intel_guc_log.c
> index 7b5074e..33636de 100644
> --- a/drivers/gpu/drm/i915/intel_guc_log.c
> +++ b/drivers/gpu/drm/i915/intel_guc_log.c
> @@ -638,7 +638,7 @@ int intel_guc_log_create(struct intel_guc *guc)
>   		(GUC_LOG_ISR_PAGES << GUC_LOG_ISR_SHIFT) |
>   		(GUC_LOG_CRASH_PAGES << GUC_LOG_CRASH_SHIFT);
>   
> -	offset = guc_ggtt_offset(vma) >> PAGE_SHIFT; /* in pages */
> +	offset = intel_guc_ggtt_offset(guc, vma) >> PAGE_SHIFT;
>   	guc->log.flags = (offset << GUC_LOG_BUF_ADDR_SHIFT) | flags;
>   
>   	return 0;
> diff --git a/drivers/gpu/drm/i915/intel_guc_reg.h b/drivers/gpu/drm/i915/intel_guc_reg.h
> index 19a9247..711e9e9 100644
> --- a/drivers/gpu/drm/i915/intel_guc_reg.h
> +++ b/drivers/gpu/drm/i915/intel_guc_reg.h
> @@ -80,9 +80,6 @@
>   #define   GUC_WOPCM_TOP			  (0x80 << 12)	/* 512KB */
>   #define   BXT_GUC_WOPCM_RC6_RESERVED	  (0x10 << 12)	/* 64KB  */
>   
> -/* GuC addresses above GUC_GGTT_TOP also don't map through the GTT */
> -#define GUC_GGTT_TOP			0xFEE00000
> -
>   #define GEN8_GT_PM_CONFIG		_MMIO(0x138140)
>   #define GEN9LP_GT_PM_CONFIG		_MMIO(0x138140)
>   #define GEN9_GT_PM_CONFIG		_MMIO(0x13816c)
> diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c b/drivers/gpu/drm/i915/intel_guc_submission.c
> index 8a8ad2f..33af293 100644
> --- a/drivers/gpu/drm/i915/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/intel_guc_submission.c
> @@ -386,8 +386,8 @@ static void guc_stage_desc_init(struct intel_guc *guc,
>   		lrc->context_desc = lower_32_bits(ce->lrc_desc);
>   
>   		/* The state page is after PPHWSP */
> -		lrc->ring_lrca =
> -			guc_ggtt_offset(ce->state) + LRC_STATE_PN * PAGE_SIZE;
> +		lrc->ring_lrca = intel_guc_ggtt_offset(guc, ce->state) +
> +				 LRC_STATE_PN * PAGE_SIZE;
>   
>   		/* XXX: In direct submission, the GuC wants the HW context id
>   		 * here. In proxy submission, it wants the stage id
> @@ -395,7 +395,7 @@ static void guc_stage_desc_init(struct intel_guc *guc,
>   		lrc->context_id = (client->stage_id << GUC_ELC_CTXID_OFFSET) |
>   				(guc_engine_id << GUC_ELC_ENGINE_OFFSET);
>   
> -		lrc->ring_begin = guc_ggtt_offset(ce->ring->vma);
> +		lrc->ring_begin = intel_guc_ggtt_offset(guc, ce->ring->vma);
>   		lrc->ring_end = lrc->ring_begin + ce->ring->size - 1;
>   		lrc->ring_next_free_location = lrc->ring_begin;
>   		lrc->ring_current_tail_pointer_value = 0;
> @@ -411,7 +411,7 @@ static void guc_stage_desc_init(struct intel_guc *guc,
>   	 * The doorbell, process descriptor, and workqueue are all parts
>   	 * of the client object, which the GuC will reference via the GGTT
>   	 */
> -	gfx_addr = guc_ggtt_offset(client->vma);
> +	gfx_addr = intel_guc_ggtt_offset(guc, client->vma);
>   	desc->db_trigger_phy = sg_dma_address(client->vma->pages->sgl) +
>   				client->doorbell_offset;
>   	desc->db_trigger_cpu = ptr_to_u64(__get_doorbell(client));
> @@ -584,7 +584,7 @@ static void inject_preempt_context(struct work_struct *work)
>   	data[3] = engine->guc_id;
>   	data[4] = guc->execbuf_client->priority;
>   	data[5] = guc->execbuf_client->stage_id;
> -	data[6] = guc_ggtt_offset(guc->shared_data);
> +	data[6] = intel_guc_ggtt_offset(guc, guc->shared_data);
>   
>   	if (WARN_ON(intel_guc_send(guc, data, ARRAY_SIZE(data)))) {
>   		execlists_clear_active(&engine->execlists,
> diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
> index ef9a05d..70a5282 100644
> --- a/drivers/gpu/drm/i915/intel_huc.c
> +++ b/drivers/gpu/drm/i915/intel_huc.c
> @@ -138,7 +138,8 @@ static int huc_ucode_xfer(struct intel_uc_fw *huc_fw, struct i915_vma *vma)
>   	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
>   
>   	/* Set the source address for the uCode */
> -	offset = guc_ggtt_offset(vma) + huc_fw->header_offset;
> +	offset = intel_guc_ggtt_offset(&dev_priv->guc, vma) +
> +		 huc_fw->header_offset;
>   	I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
>   	I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
>   
> @@ -214,7 +215,8 @@ int intel_huc_auth(struct intel_huc *huc)
>   	}
>   
>   	ret = intel_guc_auth_huc(guc,
> -				 guc_ggtt_offset(vma) + huc->fw.rsa_offset);
> +				 intel_guc_ggtt_offset(guc, vma) +
> +				 huc->fw.rsa_offset);
>   	if (ret) {
>   		DRM_ERROR("HuC: GuC did not ack Auth request %d\n", ret);
>   		goto out;

-- 
Thanks,
Sagar

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 17+ messages in thread
* Re: [PATCH v12 2/6] drm/i915: Implement dynamic GuC WOPCM offset and size calculation
  2018-03-02  0:16 ` [PATCH v12 2/6] drm/i915: Implement dynamic GuC WOPCM offset and size calculation Jackie Li
@ 2018-03-02  8:04   ` Sagar Arun Kamble
  2018-03-02 18:34     ` Yaodong Li
  2018-03-13 11:00   ` Joonas Lahtinen
  1 sibling, 1 reply; 17+ messages in thread
From: Sagar Arun Kamble @ 2018-03-02  8:04 UTC (permalink / raw)
  To: Jackie Li, intel-gfx; +Cc: Sujaritha Sundaresan



On 3/2/2018 5:46 AM, Jackie Li wrote:
> Hardware may have specific restrictions on GuC WOPCM offset and size. On
> Gen9, the value of the GuC WOPCM size register needs to be larger than the
> value of GuC WOPCM offset register + a Gen9 specific offset (144KB) for
> reserved GuC WOPCM. Fail to enforce such a restriction on GuC WOPCM size
> will lead to GuC firmware execution failures. On the other hand, with
> current static GuC WOPCM offset and size values (512KB for both offset and
> size), the GuC WOPCM size verification will fail on Gen9 even if it can be
> fixed by lowering the GuC WOPCM offset by calculating its value based on
> HuC firmware size (which is likely less than 200KB on Gen9), so that we can
> have a GuC WOPCM size value which is large enough to pass the GuC WOPCM
> size check.
>
> This patch updates the reserved GuC WOPCM size for RC6 context on Gen9 to
> 24KB to strictly align with the Gen9 GuC WOPCM layout. It also adds support
> to verify the GuC WOPCM size aganist the Gen9 hardware restrictions. To
> meet all above requirements, let's provide dynamic partitioning of the
> WOPCM that will be based on platform specific HuC/GuC firmware sizes.
>
> v2:
>   - Removed intel_wopcm_init (Ville/Sagar/Joonas)
>   - Renamed and Moved the intel_wopcm_partition into intel_guc (Sagar)
>   - Removed unnecessary function calls (Joonas)
>   - Init GuC WOPCM partition as soon as firmware fetching is completed
>
> v3:
>   - Fixed indentation issues (Chris)
>   - Removed layering violation code (Chris/Michal)
>   - Created separat files for GuC wopcm code  (Michal)
>   - Used inline function to avoid code duplication (Michal)
>
> v4:
>   - Preset the GuC WOPCM top during early GuC init (Chris)
>   - Fail intel_uc_init_hw() as soon as GuC WOPCM partitioning failed
>
> v5:
>   - Moved GuC DMA WOPCM register updating code into intel_wopcm.c
>   - Took care of the locking status before writing to GuC DMA
>     Write-Once registers. (Joonas)
>
> v6:
>   - Made sure the GuC WOPCM size to be multiple of 4K (4K aligned)
>
> v8:
>   - Updated comments and fixed naming issues (Sagar/Joonas)
>   - Updated commit message to include more description about the hardware
>     restriction on GuC WOPCM size (Sagar)
>
> v9:
>   - Minor changes variable names and code comments (Sagar)
>   - Added detailed GuC WOPCM layout drawing (Sagar/Michal)
>   - Refined macro definitions to be reader friendly (Michal)
>   - Removed redundent check to valid flag (Michal)
>   - Unified first parameter for exported GuC WOPCM functions (Michal)
>   - Refined the name and parameter list of hardware restriction checking
>     functions (Michal)
>
> v10:
>   - Used shorter function name for internal functions (Joonas)
>   - Moved init-ealry function into c file (Joonas)
>   - Consolidated and removed redundant size checks (Joonas/Michal)
>   - Removed unnecessary unlikely() from code which is only called once
>     during boot (Joonas)
>   - More fixes to kernel-doc format and content (Michal)
>   - Avoided the use of PAGE_MASK for 4K pages (Michal)
>   - Added error log messages to error paths (Michal)
>
> v11:
>   - Replaced intel_guc_wopcm with more generic intel_wopcm and attached
>     intel_wopcm to drm_i915_private instead intel_guc (Michal)
>   - dynamic calculation of GuC non-wopcm memory start (a.k.a WOPCM Top
>     offset from GuC WOPCM base) (Michal)
>   - Moved WOPCM marco definitions into .c source file (Michal)
>   - Exported WOPCM layout diagram as kernel-doc (Michal)
>
> v12:
>   - Updated naming, function kernel-doc to align with new changes (Michal)
>
> Bspec: 12690
>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: John Spotswood <john.a.spotswood@intel.com>
> Cc: Oscar Mateo <oscar.mateo@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com> (v8)
> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> (v9)
> Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com> (v11)
> Signed-off-by: Jackie Li <yaodong.li@intel.com>
> ---
>   drivers/gpu/drm/i915/Makefile           |   3 +-
>   drivers/gpu/drm/i915/i915_drv.c         |   1 +
>   drivers/gpu/drm/i915/i915_drv.h         |   8 ++
>   drivers/gpu/drm/i915/i915_gem.c         |   4 +
>   drivers/gpu/drm/i915/i915_gem_context.c |   5 +-
>   drivers/gpu/drm/i915/intel_guc.c        |  66 ++++++++---
>   drivers/gpu/drm/i915/intel_guc.h        |  16 ++-
>   drivers/gpu/drm/i915/intel_guc_reg.h    |   8 +-
>   drivers/gpu/drm/i915/intel_huc.c        |   2 +-
>   drivers/gpu/drm/i915/intel_uc.c         |   6 +-
>   drivers/gpu/drm/i915/intel_uc_fw.c      |  13 +--
>   drivers/gpu/drm/i915/intel_uc_fw.h      |  16 +++
>   drivers/gpu/drm/i915/intel_wopcm.c      | 195 ++++++++++++++++++++++++++++++++
>   drivers/gpu/drm/i915/intel_wopcm.h      |  34 ++++++
>   14 files changed, 337 insertions(+), 40 deletions(-)
>   create mode 100644 drivers/gpu/drm/i915/intel_wopcm.c
>   create mode 100644 drivers/gpu/drm/i915/intel_wopcm.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 881d712..652549e 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -78,7 +78,8 @@ i915-y += i915_cmd_parser.o \
>   	  intel_lrc.o \
>   	  intel_mocs.o \
>   	  intel_ringbuffer.o \
> -	  intel_uncore.o
> +	  intel_uncore.o \
> +	  intel_wopcm.o
>   
>   # general-purpose microcontroller (GuC) support
>   i915-y += intel_uc.o \
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index aaa861b..4c093bc 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -918,6 +918,7 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv,
>   	mutex_init(&dev_priv->wm.wm_mutex);
>   	mutex_init(&dev_priv->pps_mutex);
>   
> +	intel_wopcm_init_early(&dev_priv->wopcm);
>   	intel_uc_init_early(dev_priv);
>   	i915_memcpy_init_early(dev_priv);
>   
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 10c9e5e..f43edb8 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -64,6 +64,7 @@
>   #include "intel_opregion.h"
>   #include "intel_ringbuffer.h"
>   #include "intel_uncore.h"
> +#include "intel_wopcm.h"
>   #include "intel_uc.h"
>   
>   #include "i915_gem.h"
> @@ -1860,6 +1861,8 @@ struct drm_i915_private {
>   
>   	struct intel_gvt *gvt;
>   
> +	struct intel_wopcm wopcm;
> +
>   	struct intel_huc huc;
>   	struct intel_guc guc;
>   
> @@ -2391,6 +2394,11 @@ static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
>   	return to_i915(dev_get_drvdata(kdev));
>   }
>   
> +static inline struct drm_i915_private *wopcm_to_i915(struct intel_wopcm *wopcm)
> +{
> +	return container_of(wopcm, struct drm_i915_private, wopcm);
> +}
> +
>   static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
>   {
>   	return container_of(guc, struct drm_i915_private, guc);
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 14c855b..d31ad0b 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -5279,6 +5279,10 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
>   	if (ret)
>   		return ret;
>   
> +	ret = intel_wopcm_init(&dev_priv->wopcm);
> +	if (ret)
> +		return ret;
> +
>   	ret = intel_uc_init_misc(dev_priv);
>   	if (ret)
>   		return ret;
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
> index a73340ae..285e80c 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -312,12 +312,13 @@ __create_hw_context(struct drm_i915_private *dev_priv,
>   	ctx->desc_template =
>   		default_desc_template(dev_priv, dev_priv->mm.aliasing_ppgtt);
>   
> -	/* GuC requires the ring to be placed above GUC_WOPCM_TOP. If GuC is not
> +	/*
> +	 * GuC requires the ring to be placed in Non-WOPCM memory. If GuC is not
>   	 * present or not in use we still need a small bias as ring wraparound
>   	 * at offset 0 sometimes hangs. No idea why.
>   	 */
>   	if (USES_GUC(dev_priv))
> -		ctx->ggtt_offset_bias = GUC_WOPCM_TOP;
> +		ctx->ggtt_offset_bias = dev_priv->guc.ggtt_pin_bias;
>   	else
>   		ctx->ggtt_offset_bias = I915_GTT_PAGE_SIZE;
>   
> diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
> index a788e15..67f412a 100644
> --- a/drivers/gpu/drm/i915/intel_guc.c
> +++ b/drivers/gpu/drm/i915/intel_guc.c
> @@ -470,6 +470,57 @@ int intel_guc_resume(struct drm_i915_private *dev_priv)
>   }
>   
>   /**
> + * DOC: GuC Address Space
> + *
> + * The layout of GuC address space is shown as below:
> + *
> + *    +==============> +====================+ <== GUC_GGTT_TOP
> + *    ^                |                    |
> + *    |                |                    |
> + *    |                |        DRAM        |
> + *    |                |       Memory       |
> + *    |                |                    |
> + *   GuC               |                    |
> + * Address  +========> +====================+ <== WOPCM Top
> + *  Space   ^          |   HW contexts RSVD |
> + *    |     |          |        WOPCM       |
> + *    |     |     +==> +--------------------+ <== GuC WOPCM Top
> + *    |    GuC    ^    |                    |
> + *    |    GGTT   |    |                    |
> + *    |    Pin   GuC   |        GuC         |
> + *    |    Bias WOPCM  |       WOPCM        |
> + *    |     |    Size  |                    |
> + *    |     |     |    |                    |
> + *    v     v     v    |                    |
> + *    +=====+=====+==> +====================+ <== GuC WOPCM Base
> + *                     |   Non-GuC WOPCM    |
> + *                     |   (HuC/Reserved)   |
> + *                     +====================+ <== WOPCM Base
> + *
> + * The lower part [0, GuC ggtt_pin_bias) was mapped to WOPCM which consists of
Should this be "is mapped to"?
> + * GuC WOPCM and WOPCM reserved for other usage (e.g.RC6 context). The value of
> + * the GuC ggtt_pin_bias is determined by the actually GuC WOPCM size which is
> + * set in GUC_WOPCM_SIZE register.
> + */
> +
> +/**
> + * intel_guc_init_ggtt_pin_bias() - Initialize the GuC ggtt_pin_bias value.
> + * @guc: intel_guc structure.
> + *
> + * This functional will calculate and initialize the ggtt_pin_bias value based
> + * on overall WOPCM size and GuC WOPCM size.
> + */
> +void intel_guc_init_ggtt_pin_bias(struct intel_guc *guc)
> +{
> +	struct drm_i915_private *i915 = guc_to_i915(guc);
> +
> +	GEM_BUG_ON(!i915->wopcm.size);
> +	GEM_BUG_ON(i915->wopcm.size < i915->wopcm.guc.base);
> +
> +	guc->ggtt_pin_bias = i915->wopcm.size - i915->wopcm.guc.base;
> +}
> +
> +/**
>    * intel_guc_allocate_vma() - Allocate a GGTT VMA for GuC usage
>    * @guc:	the guc
>    * @size:	size of area to allocate (both virtual space and memory)
> @@ -477,7 +528,7 @@ int intel_guc_resume(struct drm_i915_private *dev_priv)
>    * This is a wrapper to create an object for use with the GuC. In order to
>    * use it inside the GuC, an object needs to be pinned lifetime, so we allocate
>    * both some backing storage and a range inside the Global GTT. We must pin
> - * it in the GGTT somewhere other than than [0, GUC_WOPCM_TOP) because that
> + * it in the GGTT somewhere other than than [0, GUC ggtt_pin_bias) because that
>    * range is reserved inside GuC.
>    *
>    * Return:	A i915_vma if successful, otherwise an ERR_PTR.
> @@ -498,7 +549,7 @@ struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)
>   		goto err;
>   
>   	ret = i915_vma_pin(vma, 0, PAGE_SIZE,
> -			   PIN_GLOBAL | PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
> +			   PIN_GLOBAL | PIN_OFFSET_BIAS | guc->ggtt_pin_bias);
>   	if (ret) {
>   		vma = ERR_PTR(ret);
>   		goto err;
> @@ -510,14 +561,3 @@ struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)
>   	i915_gem_object_put(obj);
>   	return vma;
>   }
> -
> -u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv)
> -{
> -	u32 wopcm_size = GUC_WOPCM_TOP;
> -
> -	/* On BXT, the top of WOPCM is reserved for RC6 context */
> -	if (IS_GEN9_LP(dev_priv))
> -		wopcm_size -= BXT_GUC_WOPCM_RC6_RESERVED;
> -
> -	return wopcm_size;
> -}
> diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
> index 0c8b10a..d5077c6 100644
> --- a/drivers/gpu/drm/i915/intel_guc.h
> +++ b/drivers/gpu/drm/i915/intel_guc.h
> @@ -49,6 +49,9 @@ struct intel_guc {
>   	struct intel_guc_log log;
>   	struct intel_guc_ct ct;
>   
> +	/** @ggtt_pin_bias: offset where Non-WOPCM memory starts. */
> +	u32 ggtt_pin_bias;
> +
>   	/* Log snapshot if GuC errors during load */
>   	struct drm_i915_gem_object *load_err_log;
>   
> @@ -108,10 +111,11 @@ static inline void intel_guc_notify(struct intel_guc *guc)
>    * @guc: intel_guc structure.
>    * @vma: i915 graphics virtual memory area.
>    *
> - * GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP),
> - * which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is
> - * 512K. In order to exclude 0-512K address space from GGTT, all gfx objects
> - * used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM.
> + * GuC does not allow any gfx GGTT address that falls into range
> + * [0, GuC ggtt_pin_bias), which is reserved for Boot ROM, SRAM and WOPCM.
> + * Currently, in order to exclude [0, GuC ggtt_pin_bias) address space from
> + * GGTT, all gfx objects used by GuC is allocated with intel_guc_allocate_vma()
> + * and pinned with PIN_OFFSET_BIAS along with the value of GuC ggtt_pin_bias.
>    *
>    * Return: GGTT offset that meets the GuC gfx address requirement.
>    */
> @@ -120,7 +124,7 @@ static inline u32 intel_guc_ggtt_offset(struct intel_guc *guc,
>   {
>   	u32 offset = i915_ggtt_offset(vma);
>   
> -	GEM_BUG_ON(offset < GUC_WOPCM_TOP);
> +	GEM_BUG_ON(offset < guc->ggtt_pin_bias);
>   	GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, GUC_GGTT_TOP));
>   
>   	return offset;
> @@ -129,6 +133,7 @@ static inline u32 intel_guc_ggtt_offset(struct intel_guc *guc,
>   void intel_guc_init_early(struct intel_guc *guc);
>   void intel_guc_init_send_regs(struct intel_guc *guc);
>   void intel_guc_init_params(struct intel_guc *guc);
> +void intel_guc_init_ggtt_pin_bias(struct intel_guc *guc);
>   int intel_guc_init_wq(struct intel_guc *guc);
>   void intel_guc_fini_wq(struct intel_guc *guc);
>   int intel_guc_init(struct intel_guc *guc);
> @@ -140,6 +145,5 @@ int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset);
>   int intel_guc_suspend(struct drm_i915_private *dev_priv);
>   int intel_guc_resume(struct drm_i915_private *dev_priv);
>   struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);
> -u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv);
>   
>   #endif
> diff --git a/drivers/gpu/drm/i915/intel_guc_reg.h b/drivers/gpu/drm/i915/intel_guc_reg.h
> index 711e9e9..01963d0 100644
> --- a/drivers/gpu/drm/i915/intel_guc_reg.h
> +++ b/drivers/gpu/drm/i915/intel_guc_reg.h
> @@ -68,17 +68,15 @@
>   #define DMA_GUC_WOPCM_OFFSET		_MMIO(0xc340)
>   #define   HUC_LOADING_AGENT_VCR		  (0<<1)
>   #define   HUC_LOADING_AGENT_GUC		  (1<<1)
> -#define   GUC_WOPCM_OFFSET_VALUE	  0x80000	/* 512KB */
> +#define   GUC_WOPCM_OFFSET_SHIFT	14
>   #define GUC_MAX_IDLE_COUNT		_MMIO(0xC3E4)
>   
>   #define HUC_STATUS2             _MMIO(0xD3B0)
>   #define   HUC_FW_VERIFIED       (1<<7)
>   
> -/* Defines WOPCM space available to GuC firmware */
>   #define GUC_WOPCM_SIZE			_MMIO(0xc050)
> -/* GuC addresses below GUC_WOPCM_TOP don't map through the GTT */
> -#define   GUC_WOPCM_TOP			  (0x80 << 12)	/* 512KB */
> -#define   BXT_GUC_WOPCM_RC6_RESERVED	  (0x10 << 12)	/* 64KB  */
> +#define   GUC_WOPCM_SIZE_SHIFT		12
> +#define   GUC_WOPCM_SIZE_MASK		  (0xfffff << GUC_WOPCM_SIZE_SHIFT)
>   
>   #define GEN8_GT_PM_CONFIG		_MMIO(0x138140)
>   #define GEN9LP_GT_PM_CONFIG		_MMIO(0x138140)
> diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
> index 70a5282..258a488 100644
> --- a/drivers/gpu/drm/i915/intel_huc.c
> +++ b/drivers/gpu/drm/i915/intel_huc.c
> @@ -207,7 +207,7 @@ int intel_huc_auth(struct intel_huc *huc)
>   		return -ENOEXEC;
>   
>   	vma = i915_gem_object_ggtt_pin(huc->fw.obj, NULL, 0, 0,
> -				PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
> +				PIN_OFFSET_BIAS | guc->ggtt_pin_bias);
>   	if (IS_ERR(vma)) {
>   		ret = PTR_ERR(vma);
>   		DRM_ERROR("HuC: Failed to pin huc fw object %d\n", ret);
> diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
> index 9f1bac6..964e49f 100644
> --- a/drivers/gpu/drm/i915/intel_uc.c
> +++ b/drivers/gpu/drm/i915/intel_uc.c
> @@ -248,6 +248,8 @@ int intel_uc_init_misc(struct drm_i915_private *dev_priv)
>   	if (!USES_GUC(dev_priv))
>   		return 0;
>   
> +	intel_guc_init_ggtt_pin_bias(guc);
> +
>   	ret = intel_guc_init_wq(guc);
>   	if (ret) {
>   		DRM_ERROR("Couldn't allocate workqueues for GuC\n");
> @@ -340,9 +342,9 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
>   	gen9_reset_guc_interrupts(dev_priv);
>   
>   	/* init WOPCM */
> -	I915_WRITE(GUC_WOPCM_SIZE, intel_guc_wopcm_size(dev_priv));
> +	I915_WRITE(GUC_WOPCM_SIZE, dev_priv->wopcm.guc.size);
>   	I915_WRITE(DMA_GUC_WOPCM_OFFSET,
> -		   GUC_WOPCM_OFFSET_VALUE | HUC_LOADING_AGENT_GUC);
> +		   dev_priv->wopcm.guc.base | HUC_LOADING_AGENT_GUC);
>   
>   	/* WaEnableuKernelHeaderValidFix:skl */
>   	/* WaEnableGuCBootHashCheckNotSet:skl,bxt,kbl */
> diff --git a/drivers/gpu/drm/i915/intel_uc_fw.c b/drivers/gpu/drm/i915/intel_uc_fw.c
> index 3ec0ce5..30c7324 100644
> --- a/drivers/gpu/drm/i915/intel_uc_fw.c
> +++ b/drivers/gpu/drm/i915/intel_uc_fw.c
> @@ -95,15 +95,6 @@ void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
>   	uc_fw->ucode_offset = uc_fw->header_offset + uc_fw->header_size;
>   	uc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);
>   
> -	/* Header and uCode will be loaded to WOPCM */
> -	size = uc_fw->header_size + uc_fw->ucode_size;
> -	if (size > intel_guc_wopcm_size(dev_priv)) {
> -		DRM_WARN("%s: Firmware is too large to fit in WOPCM\n",
> -			 intel_uc_fw_type_repr(uc_fw->type));
> -		err = -E2BIG;
> -		goto fail;
> -	}
> -
>   	/* now RSA */
>   	if (css->key_size_dw != UOS_RSA_SCRATCH_COUNT) {
>   		DRM_WARN("%s: Mismatched firmware RSA key size (%u)\n",
> @@ -208,6 +199,7 @@ int intel_uc_fw_upload(struct intel_uc_fw *uc_fw,
>   		       int (*xfer)(struct intel_uc_fw *uc_fw,
>   				   struct i915_vma *vma))
>   {
> +	struct drm_i915_private *i915 = to_i915(uc_fw->obj->base.dev);
>   	struct i915_vma *vma;
>   	int err;
>   
> @@ -231,7 +223,8 @@ int intel_uc_fw_upload(struct intel_uc_fw *uc_fw,
>   	}
>   
>   	vma = i915_gem_object_ggtt_pin(uc_fw->obj, NULL, 0, 0,
> -				       PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
> +				       PIN_OFFSET_BIAS |
> +				       i915->guc.ggtt_pin_bias);
>   	if (IS_ERR(vma)) {
>   		err = PTR_ERR(vma);
>   		DRM_DEBUG_DRIVER("%s fw ggtt-pin err=%d\n",
> diff --git a/drivers/gpu/drm/i915/intel_uc_fw.h b/drivers/gpu/drm/i915/intel_uc_fw.h
> index d5fd460..95a209b 100644
> --- a/drivers/gpu/drm/i915/intel_uc_fw.h
> +++ b/drivers/gpu/drm/i915/intel_uc_fw.h
> @@ -115,6 +115,22 @@ static inline bool intel_uc_fw_is_selected(struct intel_uc_fw *uc_fw)
>   	return uc_fw->path != NULL;
>   }
>   
> +/**
> + * intel_uc_fw_get_upload_size()() - Get size of firmware needed to be uploaded.
> + * @uc_fw: uC firmware.
> + *
> + * Get the size of the firmware that will be uploaded to WOPCM.
> + *
> + * Return: Upload firmware size, or zero on firmware fetch failure.
> + */
> +static inline u32 intel_uc_fw_get_upload_size(struct intel_uc_fw *uc_fw)
> +{
> +	if (uc_fw->fetch_status != INTEL_UC_FIRMWARE_SUCCESS)
> +		return 0;
> +
> +	return uc_fw->header_size + uc_fw->ucode_size;
> +}
> +
>   void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
>   		       struct intel_uc_fw *uc_fw);
>   int intel_uc_fw_upload(struct intel_uc_fw *uc_fw,
> diff --git a/drivers/gpu/drm/i915/intel_wopcm.c b/drivers/gpu/drm/i915/intel_wopcm.c
> new file mode 100644
> index 0000000..8b2f177
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/intel_wopcm.c
> @@ -0,0 +1,195 @@
> +/*
> + * SPDX-License-Identifier: MIT
> + *
> + * Copyright © 2017-2018 Intel Corporation
> + */
> +
> +#include "intel_wopcm.h"
> +#include "i915_drv.h"
> +
> +/**
> + * DOC: WOPCM Layout.
> + *
> + * The layout of the WOPCM will be fixed after writing to GuC WOPCM size and
> + * offset registers whose are calculated are determined by size of HuC/GuC
> + * firmware size and set of hw requirements/restrictions as shown below:.
> + *
> + *   +=========> +====================+ <== WOPCM Top
> + *   ^           |  HW contexts RSVD  |
> + *   |     +===> +====================+ <== GuC WOPCM Top
> + *   |     ^     |                    |
> + *   |     |     |                    |
> + *   |     |     |                    |
> + *   |    GuC    |                    |
> + *   |   WOPCM   |                    |
> + *   |    Size   +--------------------+
> + * WOPCM   |     |    GuC FW RSVD     |
> + *   |     |     +--------------------+
> + *   |     |     |   GuC Stack RSVD   |
> + *   |     |     +------------------- +
> + *   |     v     |   GuC WOPCM RSVD   |
> + *   |     +===> +====================+ <== GuC WOPCM base
> + *   |           |     WOPCM RSVD     |
> + *   |           +------------------- + <== HuC Firmware Top
> + *   v           |      HuC FW        |
> + *   +=========> +====================+ <== WOPCM Base
> + *
> + * GuC accessible WOPCM starts at GuC WOPCM base and ends at GuC WOPCM top.
> + * The top part of the WOPCM is reserved for hardware contexts (e.g. RC6
> + * context).
> + */
> +
> +/* Default WOPCM size 1MB. */
> +#define GEN9_WOPCM_SIZE			(1024 * 1024)
> +/* 16KB WOPCM (RSVD WOPCM) is reserved from HuC firmware top. */
> +#define WOPCM_RESERVED_SIZE		(16 * 1024)
> +
> +/* 16KB reserved at the beginning of GuC WOPCM. */
> +#define GUC_WOPCM_RESERVED		(16 * 1024)
> +/* 8KB from GUC_WOPCM_RESERVED is reserved for GuC stack. */
> +#define GUC_WOPCM_STACK_RESERVED	(8 * 1024)
> +
> +/* GuC WOPCM Offset value needs to be aligned to 16KB. */
> +#define GUC_WOPCM_OFFSET_ALIGNMENT	(1UL << GUC_WOPCM_OFFSET_SHIFT)
> +
> +/* 24KB at the end of WOPCM is reserved for RC6 CTX on BXT. */
> +#define BXT_WOPCM_RC6_CTX_RESERVED	(24 * 1024)
> +
> +/* 128KB from GUC_WOPCM_RESERVED is reserved for FW on Gen9. */
> +#define GEN9_GUC_FW_RESERVED	(128 * 1024)
> +#define GEN9_GUC_WOPCM_OFFSET	(GUC_WOPCM_RESERVED + GEN9_GUC_FW_RESERVED)
> +
> +/**
> + * intel_wopcm_init_early() - Early initialization of the WOPCM.
> + * @wopcm: pointer to intel_wopcm.
> + *
> + * Setup the size of WOPCM which will be used by later on WOPCM partitioning.
> + */
> +void intel_wopcm_init_early(struct intel_wopcm *wopcm)
> +{
> +	wopcm->size = GEN9_WOPCM_SIZE;
I am not sure if you plan to do this later but initializing it with 
value from gem_init_stolen now seems more appropriate.
> +
> +	DRM_DEBUG_DRIVER("WOPCM size: %uKiB\n", wopcm->size / 1024);
> +}
> +
> +static inline u32 context_reserved_size(struct drm_i915_private *i915)
> +{
> +	if (IS_GEN9_LP(i915))
> +		return BXT_WOPCM_RC6_CTX_RESERVED;
> +	else
> +		return 0;
> +}
> +
> +static inline int gen9_check_dword_gap(u32 guc_wopcm_base, u32 guc_wopcm_size)
> +{
> +	u32 offset;
> +
> +	/*
> +	 * GuC WOPCM size shall be at least a dword larger than the offset from
> +	 * WOPCM base (GuC WOPCM offset from WOPCM base + GEN9_GUC_WOPCM_OFFSET)
> +	 * due to hardware limitation on Gen9.
> +	 */
> +	offset = guc_wopcm_base + GEN9_GUC_WOPCM_OFFSET;
> +	if (offset > guc_wopcm_size ||
> +	    (guc_wopcm_size - offset) < sizeof(u32)) {
> +		DRM_ERROR("GuC WOPCM size (%uKiB) is too small.%uKiB needed.\n",
> +			  guc_wopcm_size / 1024,
> +			  (u32)(offset + sizeof(u32)) / 1024);
> +		return -E2BIG;
> +	}
> +
> +	return 0;
> +}
> +
> +static inline int check_hw_restriction(struct drm_i915_private *i915,
> +				       u32 guc_wopcm_base, u32 guc_wopcm_size)
> +{
> +	int err = 0;
> +
> +	if (IS_GEN9(i915))
> +		err = gen9_check_dword_gap(guc_wopcm_base, guc_wopcm_size);
> +	if (err)
> +		return err;
> +
> +	return 0;
> +}
> +
> +/**
> + * intel_wopcm_init() - Initialize the WOPCM structure.
> + * @wopcm: pointer to intel_wopcm.
> + *
> + * This function will partition WOPCM space based on GuC and HuC firmware sizes
> + * and will allocate max remaining for use by GuC. This function will also
> + * enforce platform dependent hardware restrictions on GuC WOPCM offset and
> + * size. It will fail the WOPCM init if any of these checks were failed, so that
> + * the following GuC firmware uploading would be aborted.
> + *
> + * Return: 0 on success, non-zero error code on failure.
> + */
> +int intel_wopcm_init(struct intel_wopcm *wopcm)
> +{
> +	struct drm_i915_private *i915 = wopcm_to_i915(wopcm);
> +	u32 guc_fw_size = intel_uc_fw_get_upload_size(&i915->guc.fw);
> +	u32 huc_fw_size = intel_uc_fw_get_upload_size(&i915->huc.fw);
> +	u32 ctx_rsvd = context_reserved_size(i915);
> +	u32 guc_wopcm_base;
> +	u32 guc_wopcm_size;
> +	u32 guc_wopcm_rsvd;
> +	int err;
> +
> +	GEM_BUG_ON(!wopcm->size);
> +
> +	if (guc_fw_size >= wopcm->size) {
> +		DRM_ERROR("GuC FW (%uKiB) is too big to fit in WOPCM.",
> +			  guc_fw_size / 1024);
> +		return -E2BIG;
> +	}
> +
> +	if (huc_fw_size >= wopcm->size) {
> +		DRM_ERROR("HuC FW (%uKiB) is too big to fit in WOPCM.",
> +			  huc_fw_size / 1024);
> +		return -E2BIG;
> +	}
> +
> +	/* Hardware requires GuC WOPCM base to be 16K aligned. */
> +	guc_wopcm_base = ALIGN(huc_fw_size + WOPCM_RESERVED_SIZE,
> +			       GUC_WOPCM_OFFSET_ALIGNMENT);
> +	if ((guc_wopcm_base + ctx_rsvd) >= wopcm->size) {
> +		DRM_ERROR("GuC WOPCM base (%uKiB) is too big.\n",
> +			  guc_wopcm_base / 1024);
> +		return -E2BIG;
> +	}
> +
> +	guc_wopcm_size = wopcm->size - guc_wopcm_base - ctx_rsvd;
> +	/*
> +	 * GuC WOPCM size must be multiple of 4K pages. We've got the maximum
> +	 * WOPCM size available for GuC. Trim the size value to 4K boundary.
> +	 */
> +	guc_wopcm_size &= GUC_WOPCM_SIZE_MASK;
> +
> +	DRM_DEBUG_DRIVER("Calculated GuC WOPCM Region: [%uKiB, %uKiB)\n",
> +			 guc_wopcm_base / 1024, guc_wopcm_size / 1024);
> +
> +	/*
> +	 * GuC WOPCM size needs to be big enough to include all GuC firmware,
> +	 * extra 8KiB stack for GuC firmware and GUC_WOPCM_RESERVED.
> +	 */
> +	guc_wopcm_rsvd = GUC_WOPCM_RESERVED + GUC_WOPCM_STACK_RESERVED;
> +	if ((guc_fw_size + guc_wopcm_rsvd) > guc_wopcm_size) {
> +		DRM_ERROR("Need %uKiB WOPCM for GuC, %uKiB available.\n",
> +			  (guc_fw_size + guc_wopcm_rsvd) / 1024,
> +			  guc_wopcm_size / 1024);
> +		return -E2BIG;
> +	}
> +
> +	err = check_hw_restriction(i915, guc_wopcm_base, guc_wopcm_size);
> +	if (err) {
> +		DRM_ERROR("Failed to meet HW restriction.\n");
> +		return err;
> +	}
> +
> +	wopcm->guc.base = guc_wopcm_base;
> +	wopcm->guc.size = guc_wopcm_size;
> +
> +	return 0;
> +}
> diff --git a/drivers/gpu/drm/i915/intel_wopcm.h b/drivers/gpu/drm/i915/intel_wopcm.h
> new file mode 100644
> index 0000000..39d4847
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/intel_wopcm.h
> @@ -0,0 +1,34 @@
> +/*
> + * SPDX-License-Identifier: MIT
> + *
> + * Copyright © 2017-2018 Intel Corporation
> + */
> +
> +#ifndef _INTEL_WOPCM_H_
> +#define _INTEL_WOPCM_H_
> +
> +#include <linux/types.h>
> +
> +/**
> + * struct intel_wopcm - overall WOPCM info and WOPCM regions.
> + * @size: size of overall WOPCM.
> + * @guc: GuC WOPCM Region info.
> + */
> +struct intel_wopcm {
> +	u32 size;
> +	struct {
> +		/**
> +		 * @base: GuC WOPCM base which is offset from WOPCM base.
> +		 */
> +		u32 base;
> +		/**
> +		 * @size: size of the GuC WOPCM region.
> +		 */
> +		u32 size;
> +	} guc;
> +};
> +
> +void intel_wopcm_init_early(struct intel_wopcm *wopcm);
> +int intel_wopcm_init(struct intel_wopcm *wopcm);
> +
> +#endif

-- 
Thanks,
Sagar

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^ permalink raw reply	[flat|nested] 17+ messages in thread
* Re: [PATCH v12 2/6] drm/i915: Implement dynamic GuC WOPCM offset and size calculation
  2018-03-02  8:04   ` Sagar Arun Kamble
@ 2018-03-02 18:34     ` Yaodong Li
  0 siblings, 0 replies; 17+ messages in thread
From: Yaodong Li @ 2018-03-02 18:34 UTC (permalink / raw)
  To: Sagar Arun Kamble, intel-gfx; +Cc: Sujaritha Sundaresan



On 03/02/2018 12:04 AM, Sagar Arun Kamble wrote:
>  (GUC_WOPCM_RESERVED + GEN9_GUC_FW_RESERVED)
>> +
>> +/**
>> + * intel_wopcm_init_early() - Early initialization of the WOPCM.
>> + * @wopcm: pointer to intel_wopcm.
>> + *
>> + * Setup the size of WOPCM which will be used by later on WOPCM 
>> partitioning.
>> + */
>> +void intel_wopcm_init_early(struct intel_wopcm *wopcm)
>> +{
>> +    wopcm->size = GEN9_WOPCM_SIZE;
> I am not sure if you plan to do this later but initializing it with 
> value from gem_init_stolen now seems more appropriate.
I've been asked this for several times already. Yes. I have a plan, but 
just cannot switch to that plan right now.;-)

Thanks,
-Jackie
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^ permalink raw reply	[flat|nested] 17+ messages in thread
* Re: [PATCH v12 1/6] drm/i915/guc: Rename guc_ggtt_offset to intel_guc_ggtt_offset
  2018-03-02  8:04 ` [PATCH v12 1/6] " Sagar Arun Kamble
@ 2018-03-05 21:49   ` Yaodong Li
  0 siblings, 0 replies; 17+ messages in thread
From: Yaodong Li @ 2018-03-05 21:49 UTC (permalink / raw)
  To: Sagar Arun Kamble, intel-gfx



On 03/02/2018 12:04 AM, Sagar Arun Kamble wrote:
>>
>> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
>> Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>> Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com> (v8)
>> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> (v9)
>> Signed-off-by: Jackie Li <yaodong.li@intel.com>
> I think maintainers will prefer as:
> either
>
> Cc:
> Cc:
> S-o-b:
> R-b:
>
> or
>
> S-o-b:
> Cc:
> Cc:
> R-b:
Thanks Sagar! I will include these changes along with other 
comments/suggestion
from Joonas (if any:-))

Regards,
-Jackie

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^ permalink raw reply	[flat|nested] 17+ messages in thread
* Re: [PATCH v12 1/6] drm/i915/guc: Rename guc_ggtt_offset to intel_guc_ggtt_offset
  2018-03-02  0:16 [PATCH v12 1/6] drm/i915/guc: Rename guc_ggtt_offset to intel_guc_ggtt_offset Jackie Li
                   ` (6 preceding siblings ...)
  2018-03-02  8:04 ` [PATCH v12 1/6] " Sagar Arun Kamble
@ 2018-03-13 10:21 ` Joonas Lahtinen
  7 siblings, 0 replies; 17+ messages in thread
From: Joonas Lahtinen @ 2018-03-13 10:21 UTC (permalink / raw)
  To: Jackie Li, intel-gfx

Quoting Jackie Li (2018-03-02 02:16:41)
> GuC related exported functions should start with "intel_guc_" prefix and
> pass intel_guc as the first parameter since its GuC related. Current
> guc_ggtt_offset() failed to follow this code convention and this is a
> problem for future patches that needs to access intel_guc data to verify
> the GGTT offset against the GuC WOPCM top.
> 
> This patch renames the guc_ggtt_offset to intel_guc_ggtt_offset and updates
> the related code to pass intel_guc pointer to this function call, so that
> we can have a unified coding style for GuC code and also enable the future
> patches to get GuC related data from intel_guc to do the offset
> verification. Meanwhile, this patch also moves the GUC_GGTT_TOP from
> intel_guc_regs.h to intel_guc.h since it is not GuC register related
> definition.
> 
> v8:
>  - Fixed coding style issues and moved GUC_GGTT_TOP to intel_guc.h (Sagar)
>  - Updated commit message to explain to reason and motivation to add
>    intel_guc as the first parameter of intel_guc_ggtt_offset (Chris)
> 
> v9:
>  - Fixed code alignment issue due to line break (Chris)
> 
> v10:
>  - Removed unnecessary comments, redundant code and avoided reuse variable
>    to avoid potential issues (Joonas)
> 
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com> (v8)
> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> (v9)
> Signed-off-by: Jackie Li <yaodong.li@intel.com>
> Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com> (v11)

Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>

Regards, Joonas
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^ permalink raw reply	[flat|nested] 17+ messages in thread
* Re: [PATCH v12 2/6] drm/i915: Implement dynamic GuC WOPCM offset and size calculation
  2018-03-02  0:16 ` [PATCH v12 2/6] drm/i915: Implement dynamic GuC WOPCM offset and size calculation Jackie Li
  2018-03-02  8:04   ` Sagar Arun Kamble
@ 2018-03-13 11:00   ` Joonas Lahtinen
  1 sibling, 0 replies; 17+ messages in thread
From: Joonas Lahtinen @ 2018-03-13 11:00 UTC (permalink / raw)
  To: Jackie Li, intel-gfx; +Cc: Sujaritha Sundaresan

Quoting Jackie Li (2018-03-02 02:16:42)
> +/**
> + * intel_guc_init_ggtt_pin_bias() - Initialize the GuC ggtt_pin_bias value.
> + * @guc: intel_guc structure.
> + *
> + * This functional will calculate and initialize the ggtt_pin_bias value based

s/functional/function/

> + * on overall WOPCM size and GuC WOPCM size.
> + */
> +void intel_guc_init_ggtt_pin_bias(struct intel_guc *guc)

<SNIP>

> +++ b/drivers/gpu/drm/i915/intel_guc.h
> @@ -49,6 +49,9 @@ struct intel_guc {
>         struct intel_guc_log log;
>         struct intel_guc_ct ct;
>  
> +       /** @ggtt_pin_bias: offset where Non-WOPCM memory starts. */

I'm pretty sure /** description */ should be enough. If we really should
have this in the doxygen is the bigger question, maybe make it a normal
comment like the surrounding ones, for the time being.

> +       u32 ggtt_pin_bias;
> +
>         /* Log snapshot if GuC errors during load */
>         struct drm_i915_gem_object *load_err_log;
>  
> @@ -108,10 +111,11 @@ static inline void intel_guc_notify(struct intel_guc *guc)
>   * @guc: intel_guc structure.
>   * @vma: i915 graphics virtual memory area.
>   *
> - * GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP),
> - * which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is
> - * 512K. In order to exclude 0-512K address space from GGTT, all gfx objects
> - * used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM.
> + * GuC does not allow any gfx GGTT address that falls into range
> + * [0, GuC ggtt_pin_bias), which is reserved for Boot ROM, SRAM and WOPCM.
> + * Currently, in order to exclude [0, GuC ggtt_pin_bias) address space from
> + * GGTT, all gfx objects used by GuC is allocated with intel_guc_allocate_vma()

s/is allocated/are allocated/

> + * and pinned with PIN_OFFSET_BIAS along with the value of GuC ggtt_pin_bias.
>   *
>   * Return: GGTT offset that meets the GuC gfx address requirement.

This gives an impression that something is done for the vma to make it
comply, instead of just checking it complies. Is that going to be the
case in future? If not, "Return: GGTT offset of the vma" would be more
correct.

> @@ -129,6 +133,7 @@ static inline u32 intel_guc_ggtt_offset(struct intel_guc *guc,
>  void intel_guc_init_early(struct intel_guc *guc);
>  void intel_guc_init_send_regs(struct intel_guc *guc);
>  void intel_guc_init_params(struct intel_guc *guc);
> +void intel_guc_init_ggtt_pin_bias(struct intel_guc *guc);

Bit unclear why this amount of details about the initialization sequence get
exposed to header files. Lets fix this in the later series.

> +++ b/drivers/gpu/drm/i915/intel_huc.c
> @@ -207,7 +207,7 @@ int intel_huc_auth(struct intel_huc *huc)
>                 return -ENOEXEC;
>  
>         vma = i915_gem_object_ggtt_pin(huc->fw.obj, NULL, 0, 0,
> -                               PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
> +                               PIN_OFFSET_BIAS | guc->ggtt_pin_bias);

Indent should be fixed while here.

> +++ b/drivers/gpu/drm/i915/intel_uc_fw.h
> @@ -115,6 +115,22 @@ static inline bool intel_uc_fw_is_selected(struct intel_uc_fw *uc_fw)
>         return uc_fw->path != NULL;
>  }
>  
> +/**
> + * intel_uc_fw_get_upload_size()() - Get size of firmware needed to be uploaded.

I don't think the "()()" is correct or needed.

> + * @uc_fw: uC firmware.
> + *
> + * Get the size of the firmware that will be uploaded to WOPCM.

"firmware and header"?

> + *
> + * Return: Upload firmware size, or zero on firmware fetch failure.
> + */
> +static inline u32 intel_uc_fw_get_upload_size(struct intel_uc_fw *uc_fw)

<SNIP>

> +static inline int gen9_check_dword_gap(u32 guc_wopcm_base, u32 guc_wopcm_size)
> +{
> +       u32 offset;
> +
> +       /*
> +        * GuC WOPCM size shall be at least a dword larger than the offset from
> +        * WOPCM base (GuC WOPCM offset from WOPCM base + GEN9_GUC_WOPCM_OFFSET)
> +        * due to hardware limitation on Gen9.
> +        */
> +       offset = guc_wopcm_base + GEN9_GUC_WOPCM_OFFSET;
> +       if (offset > guc_wopcm_size ||
> +           (guc_wopcm_size - offset) < sizeof(u32)) {
> +               DRM_ERROR("GuC WOPCM size (%uKiB) is too small.%uKiB needed.\n",

Drop the () and add " " after .

> +                         guc_wopcm_size / 1024,
> +                         (u32)(offset + sizeof(u32)) / 1024);
> +               return -E2BIG;
> +       }
> +
> +       return 0;
> +}
> +
> +static inline int check_hw_restriction(struct drm_i915_private *i915,
> +                                      u32 guc_wopcm_base, u32 guc_wopcm_size)
> +{
> +       int err = 0;
> +
> +       if (IS_GEN9(i915))
> +               err = gen9_check_dword_gap(guc_wopcm_base, guc_wopcm_size);
> +       if (err)
> +               return err;

You can just "return err;" and the extra checks would become:

if (!err && IS_FOO())
	err = ...;
> +
> +       return 0;
> +}
> +
> +/**
> + * intel_wopcm_init() - Initialize the WOPCM structure.
> + * @wopcm: pointer to intel_wopcm.
> + *
> + * This function will partition WOPCM space based on GuC and HuC firmware sizes
> + * and will allocate max remaining for use by GuC. This function will also
> + * enforce platform dependent hardware restrictions on GuC WOPCM offset and
> + * size. It will fail the WOPCM init if any of these checks were failed, so that
> + * the following GuC firmware uploading would be aborted.
> + *
> + * Return: 0 on success, non-zero error code on failure.
> + */
> +int intel_wopcm_init(struct intel_wopcm *wopcm)
> +{
> +       struct drm_i915_private *i915 = wopcm_to_i915(wopcm);
> +       u32 guc_fw_size = intel_uc_fw_get_upload_size(&i915->guc.fw);
> +       u32 huc_fw_size = intel_uc_fw_get_upload_size(&i915->huc.fw);
> +       u32 ctx_rsvd = context_reserved_size(i915);
> +       u32 guc_wopcm_base;
> +       u32 guc_wopcm_size;
> +       u32 guc_wopcm_rsvd;
> +       int err;
> +
> +       GEM_BUG_ON(!wopcm->size);
> +
> +       if (guc_fw_size >= wopcm->size) {
> +               DRM_ERROR("GuC FW (%uKiB) is too big to fit in WOPCM.",
> +                         guc_fw_size / 1024);
> +               return -E2BIG;
> +       }
> +
> +       if (huc_fw_size >= wopcm->size) {
> +               DRM_ERROR("HuC FW (%uKiB) is too big to fit in WOPCM.",
> +                         huc_fw_size / 1024);
> +               return -E2BIG;
> +       }
> +
> +       /* Hardware requires GuC WOPCM base to be 16K aligned. */

Rather spurious comment, especially as it hardcodes the value that
is nicely de-magicalized with a #define ;)

> +       guc_wopcm_base = ALIGN(huc_fw_size + WOPCM_RESERVED_SIZE,
> +                              GUC_WOPCM_OFFSET_ALIGNMENT);
> +       if ((guc_wopcm_base + ctx_rsvd) >= wopcm->size) {
> +               DRM_ERROR("GuC WOPCM base (%uKiB) is too big.\n",
> +                         guc_wopcm_base / 1024);
> +               return -E2BIG;
> +       }
> +
> +       guc_wopcm_size = wopcm->size - guc_wopcm_base - ctx_rsvd;
> +       /*
> +        * GuC WOPCM size must be multiple of 4K pages. We've got the maximum
> +        * WOPCM size available for GuC. Trim the size value to 4K boundary.
> +        */

Ditto.

> +       guc_wopcm_size &= GUC_WOPCM_SIZE_MASK;
> +
> +       DRM_DEBUG_DRIVER("Calculated GuC WOPCM Region: [%uKiB, %uKiB)\n",
> +                        guc_wopcm_base / 1024, guc_wopcm_size / 1024);
> +
> +       /*
> +        * GuC WOPCM size needs to be big enough to include all GuC firmware,
> +        * extra 8KiB stack for GuC firmware and GUC_WOPCM_RESERVED.
> +        */

This comment can be read from the code.

> +       guc_wopcm_rsvd = GUC_WOPCM_RESERVED + GUC_WOPCM_STACK_RESERVED;
> +       if ((guc_fw_size + guc_wopcm_rsvd) > guc_wopcm_size) {
> +               DRM_ERROR("Need %uKiB WOPCM for GuC, %uKiB available.\n",
> +                         (guc_fw_size + guc_wopcm_rsvd) / 1024,
> +                         guc_wopcm_size / 1024);
> +               return -E2BIG;
> +       }
> +
> +       err = check_hw_restriction(i915, guc_wopcm_base, guc_wopcm_size);
> +       if (err) {
> +               DRM_ERROR("Failed to meet HW restriction.\n");

We already get DRM_ERROR for all cases in check_hw_restriction, so this
should not be needed.

> +++ b/drivers/gpu/drm/i915/intel_wopcm.h
> @@ -0,0 +1,34 @@
> +/*
> + * SPDX-License-Identifier: MIT
> + *
> + * Copyright © 2017-2018 Intel Corporation
> + */
> +
> +#ifndef _INTEL_WOPCM_H_
> +#define _INTEL_WOPCM_H_
> +
> +#include <linux/types.h>
> +
> +/**
> + * struct intel_wopcm - overall WOPCM info and WOPCM regions.
> + * @size: size of overall WOPCM.
> + * @guc: GuC WOPCM Region info.
> + */
> +struct intel_wopcm {
> +       u32 size;
> +       struct {
> +               /**
> +                * @base: GuC WOPCM base which is offset from WOPCM base.
> +                */
> +               u32 base;
> +               /**
> +                * @size: size of the GuC WOPCM region.
> +                */
> +               u32 size;

Again, I assume there would be more brief way of writing these comments.

With the typos corrected and spurious comments removed, this is:

Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>

Regards, Joonas
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 17+ messages in thread
* Re: [PATCH v12 3/6] drm/i915: Add support to return CNL specific reserved WOPCM size
  2018-03-02  0:16 ` [PATCH v12 3/6] drm/i915: Add support to return CNL specific reserved WOPCM size Jackie Li
@ 2018-03-13 12:11   ` Joonas Lahtinen
  0 siblings, 0 replies; 17+ messages in thread
From: Joonas Lahtinen @ 2018-03-13 12:11 UTC (permalink / raw)
  To: Jackie Li, intel-gfx

Quoting Jackie Li (2018-03-02 02:16:43)
> CNL has its specific reserved GuC WOPCM size for RC6 and other hardware
> contexts.
> 
> This patch updates the code to return CNL specific reserved GuC WOPCM size
> for RC6 and other hardware contexts so that the GuC WOPCM size can be
> calculated correctly for CNL.
> 
> v9:
>  - Created a new patch for these changes originally made in v8 4/6 patch of
>    this series (Sagar/Michal)
> 
> v10:
>  - Used if-else ladder to the returning of context sizes (Joonas)
> 
> v11:
>  - Removed GUC_ prefix from context size macro (Michal)
> 
> Bspec: 12690
> 
> Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> (v9)

Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>

Regards, Joonas
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 17+ messages in thread
* Re: [PATCH v12 4/6] drm/i915: Add HuC firmware size related restriction for Gen9 and CNL A0
  2018-03-02  0:16 ` [PATCH v12 4/6] drm/i915: Add HuC firmware size related restriction for Gen9 and CNL A0 Jackie Li
@ 2018-03-13 12:12   ` Joonas Lahtinen
  0 siblings, 0 replies; 17+ messages in thread
From: Joonas Lahtinen @ 2018-03-13 12:12 UTC (permalink / raw)
  To: Jackie Li, intel-gfx

Quoting Jackie Li (2018-03-02 02:16:44)
> On CNL A0 and Gen9, there's a hardware restriction that requires the
> available GuC WOPCM size to be larger than or equal to HuC firmware size.
> 
> This patch adds new verification code to ensure the available GuC WOPCM
> size to be larger than or equal to HuC firmware size on both Gen9 and CNL
> A0.
> 
> v6:
>  - Extended HuC FW size check against GuC WOPCM size to all
>    Gen9 and CNL A0 platforms
> 
> v7:
>  - Fixed patch format issues
> 
> v8:
>  - Renamed variables and functions to avoid ambiguity (Joonas)
>  - Updated commit message and comments to be more comprehensive (Sagar)
> 
> v9:
>  - Moved code that is not related to restriction check into a separate
>    patch and updated the commit message accordingly (Sagar/Michal)
>  - Avoided to call uc_get_fw_size for better layer isolation (Michal)
> 
> v10:
>  - Shorten function names and reorganized size_check code to have clear
>    isolation (Joonas)
>  - Removed unnecessary comments (Joonas)
> 
> v11:
>  - Fixed logic error in size check (Michal)
> 
> v12:
>  - Add space between "HuC FW" and "(%uKiB)" in error message (Michal)
> 
> BSpec: 10875
> 
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> Cc: John Spotswood <john.a.spotswood@intel.com>
> Cc: Jeff McGee <jeff.mcgee@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com> (v8)
> Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com> (v11)
> Signed-off-by: Jackie Li <yaodong.li@intel.com>

Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>

Regards, Joonas
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 17+ messages in thread
* Re: [PATCH v12 5/6] drm/i915/guc: Check the locking status of GuC WOPCM registers
  2018-03-02  0:16 ` [PATCH v12 5/6] drm/i915/guc: Check the locking status of GuC WOPCM registers Jackie Li
@ 2018-03-13 12:20   ` Joonas Lahtinen
       [not found]   ` <466b9074-2716-f3e8-161a-95b9ca03a06a@intel.com>
  1 sibling, 0 replies; 17+ messages in thread
From: Joonas Lahtinen @ 2018-03-13 12:20 UTC (permalink / raw)
  To: Jackie Li, intel-gfx

Quoting Jackie Li (2018-03-02 02:16:45)
> +++ b/drivers/gpu/drm/i915/intel_wopcm.c
> @@ -219,3 +219,67 @@ int intel_wopcm_init(struct intel_wopcm *wopcm)
>  
>         return 0;
>  }
> +
> +static inline int write_and_verify(struct drm_i915_private *dev_priv,
> +                                  i915_reg_t reg, u32 val, u32 mask,
> +                                  u32 locked_bit)
> +{
> +       u32 reg_val;
> +
> +       GEM_BUG_ON(val & ~mask);
> +
> +       I915_WRITE(reg, val);
> +
> +       reg_val = I915_READ(reg);

I guess I would have expected the error message here, with the wanted
value vs. what was in the register.

<SNIP>

> +err_out:
> +       DRM_ERROR("Failed to init WOPCM registers:\n");
> +       DRM_ERROR("DMA_GUC_WOPCM_OFFSET=%#x\n",
> +                 I915_READ(DMA_GUC_WOPCM_OFFSET));
> +       DRM_ERROR("GUC_WOPCM_SIZE=%#x\n", I915_READ(GUC_WOPCM_SIZE));

As this doesn't really give information what were the computed write
values. But if you see this is most useful for debuggin, this is;

Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>

Regards, Joonas
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 17+ messages in thread
* Re: [PATCH v12 5/6] drm/i915/guc: Check the locking status of GuC WOPCM registers
       [not found]   ` <466b9074-2716-f3e8-161a-95b9ca03a06a@intel.com>
@ 2018-03-13 16:35     ` Yaodong Li
  0 siblings, 0 replies; 17+ messages in thread
From: Yaodong Li @ 2018-03-13 16:35 UTC (permalink / raw)
  To: Joonas Lahtinen, intel-gfx


[-- Attachment #1.1: Type: text/plain, Size: 1530 bytes --]

Failed to receive this mail for 5/6 patch (couldn't find it in my mailbox).
So pasted the comments from patchwork.
> Quoting Jackie Li (2018-03-02 02:16:45)
> > +++ b/drivers/gpu/drm/i915/intel_wopcm.c
> > @@ -219,3 +219,67 @@ int intel_wopcm_init(struct intel_wopcm *wopcm)
> >  
> >         return 0;
> >  }
> > +
> > +static inline int write_and_verify(struct drm_i915_private *dev_priv,
> > +                                  i915_reg_t reg, u32 val, u32 mask,
> > +                                  u32 locked_bit)
> > +{
> > +       u32 reg_val;
> > +
> > +       GEM_BUG_ON(val & ~mask);
> > +
> > +       I915_WRITE(reg, val);
> > +
> > +       reg_val = I915_READ(reg);
>
> I guess I would have expected the error message here, with the wanted
> value vs. what was in the register.
>
> <SNIP>
> > +err_out:
> > +       DRM_ERROR("Failed to init WOPCM registers:\n");
> > +       DRM_ERROR("DMA_GUC_WOPCM_OFFSET=%#x\n",
> > +                 I915_READ(DMA_GUC_WOPCM_OFFSET));
> > +       DRM_ERROR("GUC_WOPCM_SIZE=%#x\n", I915_READ(GUC_WOPCM_SIZE));
>
> As this doesn't really give information what were the computed write
> values. But if you see this is most useful for debuggin, this is;
Thanks for the comments!

This is for debugging. and the consideration was to print both the
offset and size register values for any reg update errors,  the
calculated values were printed as debug messages during wopcm
partitioning (wopcm_init)

Regards,
-Jackie
> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>



[-- Attachment #1.2: Type: text/html, Size: 2887 bytes --]

[-- Attachment #2: Type: text/plain, Size: 160 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 17+ messages in thread
end of thread, other threads:[~2018-03-13 16:37 UTC | newest]

Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-03-02  0:16 [PATCH v12 1/6] drm/i915/guc: Rename guc_ggtt_offset to intel_guc_ggtt_offset Jackie Li
2018-03-02  0:16 ` [PATCH v12 2/6] drm/i915: Implement dynamic GuC WOPCM offset and size calculation Jackie Li
2018-03-02  8:04   ` Sagar Arun Kamble
2018-03-02 18:34     ` Yaodong Li
2018-03-13 11:00   ` Joonas Lahtinen
2018-03-02  0:16 ` [PATCH v12 3/6] drm/i915: Add support to return CNL specific reserved WOPCM size Jackie Li
2018-03-13 12:11   ` Joonas Lahtinen
2018-03-02  0:16 ` [PATCH v12 4/6] drm/i915: Add HuC firmware size related restriction for Gen9 and CNL A0 Jackie Li
2018-03-13 12:12   ` Joonas Lahtinen
2018-03-02  0:16 ` [PATCH v12 5/6] drm/i915/guc: Check the locking status of GuC WOPCM registers Jackie Li
2018-03-13 12:20   ` Joonas Lahtinen
     [not found]   ` <466b9074-2716-f3e8-161a-95b9ca03a06a@intel.com>
2018-03-13 16:35     ` Yaodong Li
2018-03-02  0:16 ` [PATCH v12 6/6] HAX Enable GuC Submission for CI Jackie Li
2018-03-02  0:59 ` ✗ Fi.CI.BAT: failure for series starting with [v12,1/6] drm/i915/guc: Rename guc_ggtt_offset to intel_guc_ggtt_offset Patchwork
2018-03-02  8:04 ` [PATCH v12 1/6] " Sagar Arun Kamble
2018-03-05 21:49   ` Yaodong Li
2018-03-13 10:21 ` Joonas Lahtinen

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