[PATCH 1/2] drm/i915/psr: Move PSR aux setup to it's own function.

[PATCH 1/2] drm/i915/psr: Move PSR aux setup to it's own function.

[Dhinakaran Pandiyan]

Non-functional change useful for the following patch.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
---
 drivers/gpu/drm/i915/intel_psr.c | 31 ++++++++++++++++++++-----------
 1 file changed, 20 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 975ebb51c7af..86d6c19c9ae6 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -246,7 +246,7 @@ static i915_reg_t psr_aux_data_reg(struct drm_i915_private *dev_priv,
 		return EDP_PSR_AUX_DATA(index);
 }
 
-static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
+static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
 {
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	struct drm_device *dev = dig_port->base.base.dev;
@@ -267,6 +267,24 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
 	BUILD_BUG_ON(sizeof(aux_msg) > 20);
 
 	aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
+	aux_ctl_reg = psr_aux_ctl_reg(dev_priv, port);
+
+	/* Setup AUX registers */
+	for (i = 0; i < sizeof(aux_msg); i += 4)
+		I915_WRITE(psr_aux_data_reg(dev_priv, port, i >> 2),
+			   intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
+
+	aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, 0, sizeof(aux_msg),
+					     aux_clock_divider);
+	I915_WRITE(aux_ctl_reg, aux_ctl);
+}
+
+static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
+{
+	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+	struct drm_device *dev = dig_port->base.base.dev;
+	struct drm_i915_private *dev_priv = to_i915(dev);
+
 
 	/* Enable AUX frame sync at sink */
 	if (dev_priv->psr.aux_frame_sync)
@@ -285,16 +303,7 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
 		drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
 				   DP_PSR_ENABLE);
 
-	aux_ctl_reg = psr_aux_ctl_reg(dev_priv, port);
-
-	/* Setup AUX registers */
-	for (i = 0; i < sizeof(aux_msg); i += 4)
-		I915_WRITE(psr_aux_data_reg(dev_priv, port, i >> 2),
-			   intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
-
-	aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, 0, sizeof(aux_msg),
-					     aux_clock_divider);
-	I915_WRITE(aux_ctl_reg, aux_ctl);
+	hsw_psr_setup_aux(intel_dp);
 }
 
 static void vlv_psr_enable_source(struct intel_dp *intel_dp,
-- 
2.14.1

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[PATCH 2/2] drm/i915/psr: Remove open-coded PSR AUX transactions for SKL+

[Dhinakaran Pandiyan]

HSW and BDW have SRD_AUX_{CTL, STATUS} registers that the driver needs to
setup for the HW to use whenever exiting PSR. SKL+ hardware use hardcoded
values for the same and do not need any registers to be setup. So, use
drm_dp_dpcd_writeb() for a one-time write during PSR enable and setup the
PSR aux registers on HSW and BDW for later use by HW.

We also end up writing to reserved bits in SRD_AUX_CTL by reusing
intel_dp->get_aux_send_ctl() for HSW and BDW, fix this.

Since the AUX register setup is source side programming, move the call
to enable_source() from enable_sink().

Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |  6 +++++
 drivers/gpu/drm/i915/intel_psr.c | 55 ++++++++++++++++------------------------
 2 files changed, 28 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index abdc513a9edd..23c0f9bdf591 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4151,6 +4151,12 @@ enum {
 #define   EDP_PSR_IDLE_FRAME_SHIFT		0
 
 #define EDP_PSR_AUX_CTL				_MMIO(dev_priv->psr_mmio_base + 0x10)
+#define   EDP_PSR_AUX_CTL_TIME_OUT_MASK		(3 << 26)
+#define   EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK	(0x1f << 20)
+#define   EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK	(0xf << 16)
+#define   EDP_PSR_AUX_CTL_ERROR_INTERRUPT	(1 << 11)
+#define   EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK	(0x7ff)
+
 #define EDP_PSR_AUX_DATA(i)			_MMIO(dev_priv->psr_mmio_base + 0x14 + (i) * 4) /* 5 registers */
 
 #define EDP_PSR_STATUS				_MMIO(dev_priv->psr_mmio_base + 0x40)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 86d6c19c9ae6..293a987a1bfd 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -228,31 +228,12 @@ static void vlv_psr_enable_sink(struct intel_dp *intel_dp)
 			   DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
 }
 
-static i915_reg_t psr_aux_ctl_reg(struct drm_i915_private *dev_priv,
-				       enum port port)
-{
-	if (INTEL_GEN(dev_priv) >= 9)
-		return DP_AUX_CH_CTL(port);
-	else
-		return EDP_PSR_AUX_CTL;
-}
-
-static i915_reg_t psr_aux_data_reg(struct drm_i915_private *dev_priv,
-					enum port port, int index)
-{
-	if (INTEL_GEN(dev_priv) >= 9)
-		return DP_AUX_CH_DATA(port, index);
-	else
-		return EDP_PSR_AUX_DATA(index);
-}
-
 static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
 {
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
-	struct drm_device *dev = dig_port->base.base.dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
-	uint32_t aux_clock_divider;
-	i915_reg_t aux_ctl_reg;
+	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
+	u32 aux_clock_divider, aux_ctl;
+	int i;
 	static const uint8_t aux_msg[] = {
 		[0] = DP_AUX_NATIVE_WRITE << 4,
 		[1] = DP_SET_POWER >> 8,
@@ -260,23 +241,25 @@ static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
 		[3] = 1 - 1,
 		[4] = DP_SET_POWER_D0,
 	};
-	enum port port = dig_port->base.port;
-	u32 aux_ctl;
-	int i;
+	u32 psr_aux_mask = EDP_PSR_AUX_CTL_TIME_OUT_MASK |
+			   EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK |
+			   EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK |
+			   EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK;
 
 	BUILD_BUG_ON(sizeof(aux_msg) > 20);
-
-	aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
-	aux_ctl_reg = psr_aux_ctl_reg(dev_priv, port);
-
-	/* Setup AUX registers */
 	for (i = 0; i < sizeof(aux_msg); i += 4)
-		I915_WRITE(psr_aux_data_reg(dev_priv, port, i >> 2),
+		I915_WRITE(EDP_PSR_AUX_DATA(i >> 2),
 			   intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
 
+	aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
+
+	/* Start with bits set for DDI_AUX_CTL register */
 	aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, 0, sizeof(aux_msg),
 					     aux_clock_divider);
-	I915_WRITE(aux_ctl_reg, aux_ctl);
+
+	/* Select only valid bits for SRD_AUX_CTL */
+	aux_ctl &= psr_aux_mask;
+	I915_WRITE(EDP_PSR_AUX_CTL, aux_ctl);
 }
 
 static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
@@ -303,7 +286,7 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
 		drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
 				   DP_PSR_ENABLE);
 
-	hsw_psr_setup_aux(intel_dp);
+	drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
 }
 
 static void vlv_psr_enable_source(struct intel_dp *intel_dp,
@@ -599,6 +582,12 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp,
 
 	psr_aux_io_power_get(intel_dp);
 
+	/* Only HSW and BDW have PSR AUX registers that need to be setup. SKL+
+	 * use hardcoded values PSR AUX transactions
+	 */
+	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
+		hsw_psr_setup_aux(intel_dp);
+
 	if (dev_priv->psr.psr2_support) {
 		chicken = PSR2_VSC_ENABLE_PROG_HEADER;
 		if (dev_priv->psr.y_cord_support)
-- 
2.14.1

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Re: [PATCH 2/2] drm/i915/psr: Remove open-coded PSR AUX transactions for SKL+

[Souza, Jose]

On Mon, 2018-03-12 at 20:46 -0700, Dhinakaran Pandiyan wrote:
> HSW and BDW have SRD_AUX_{CTL, STATUS} registers that the driver
> needs to
> setup for the HW to use whenever exiting PSR. SKL+ hardware use
> hardcoded
> values for the same and do not need any registers to be setup. So,
> use
> drm_dp_dpcd_writeb() for a one-time write during PSR enable and setup
> the
> PSR aux registers on HSW and BDW for later use by HW.
> 
> We also end up writing to reserved bits in SRD_AUX_CTL by reusing
> intel_dp->get_aux_send_ctl() for HSW and BDW, fix this.
> 
> Since the AUX register setup is source side programming, move the
> call
> to enable_source() from enable_sink().
> 
> Cc: José Roberto de Souza <jose.souza@intel.com>

Reviewed-by: Jose Roberto de Souza <jose.souza@intel.com>

> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h  |  6 +++++
>  drivers/gpu/drm/i915/intel_psr.c | 55 ++++++++++++++++------------
> ------------
>  2 files changed, 28 insertions(+), 33 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index abdc513a9edd..23c0f9bdf591 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4151,6 +4151,12 @@ enum {
>  #define   EDP_PSR_IDLE_FRAME_SHIFT		0
>  
>  #define EDP_PSR_AUX_CTL				_MMIO(dev_pri
> v->psr_mmio_base + 0x10)
> +#define   EDP_PSR_AUX_CTL_TIME_OUT_MASK		(3 << 26)
> +#define   EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK	(0x1f << 20)
> +#define   EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK	(0xf << 16)
> +#define   EDP_PSR_AUX_CTL_ERROR_INTERRUPT	(1 << 11)
> +#define   EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK	(0x7ff)
> +
>  #define EDP_PSR_AUX_DATA(i)			_MMIO(dev_priv-
> >psr_mmio_base + 0x14 + (i) * 4) /* 5 registers */
>  
>  #define EDP_PSR_STATUS				_MMIO(dev_priv
> ->psr_mmio_base + 0x40)
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
> index 86d6c19c9ae6..293a987a1bfd 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -228,31 +228,12 @@ static void vlv_psr_enable_sink(struct intel_dp
> *intel_dp)
>  			   DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
>  }
>  
> -static i915_reg_t psr_aux_ctl_reg(struct drm_i915_private *dev_priv,
> -				       enum port port)
> -{
> -	if (INTEL_GEN(dev_priv) >= 9)
> -		return DP_AUX_CH_CTL(port);
> -	else
> -		return EDP_PSR_AUX_CTL;
> -}
> -
> -static i915_reg_t psr_aux_data_reg(struct drm_i915_private
> *dev_priv,
> -					enum port port, int index)
> -{
> -	if (INTEL_GEN(dev_priv) >= 9)
> -		return DP_AUX_CH_DATA(port, index);
> -	else
> -		return EDP_PSR_AUX_DATA(index);
> -}
> -
>  static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
>  {
>  	struct intel_digital_port *dig_port =
> dp_to_dig_port(intel_dp);
> -	struct drm_device *dev = dig_port->base.base.dev;
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> -	uint32_t aux_clock_divider;
> -	i915_reg_t aux_ctl_reg;
> +	struct drm_i915_private *dev_priv = to_i915(dig_port-
> >base.base.dev);
> +	u32 aux_clock_divider, aux_ctl;
> +	int i;
>  	static const uint8_t aux_msg[] = {
>  		[0] = DP_AUX_NATIVE_WRITE << 4,
>  		[1] = DP_SET_POWER >> 8,
> @@ -260,23 +241,25 @@ static void hsw_psr_setup_aux(struct intel_dp
> *intel_dp)
>  		[3] = 1 - 1,
>  		[4] = DP_SET_POWER_D0,
>  	};
> -	enum port port = dig_port->base.port;
> -	u32 aux_ctl;
> -	int i;
> +	u32 psr_aux_mask = EDP_PSR_AUX_CTL_TIME_OUT_MASK |
> +			   EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK |
> +			   EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK |
> +			   EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK;
>  
>  	BUILD_BUG_ON(sizeof(aux_msg) > 20);
> -
> -	aux_clock_divider = intel_dp-
> >get_aux_clock_divider(intel_dp, 0);
> -	aux_ctl_reg = psr_aux_ctl_reg(dev_priv, port);
> -
> -	/* Setup AUX registers */
>  	for (i = 0; i < sizeof(aux_msg); i += 4)
> -		I915_WRITE(psr_aux_data_reg(dev_priv, port, i >> 2),
> +		I915_WRITE(EDP_PSR_AUX_DATA(i >> 2),
>  			   intel_dp_pack_aux(&aux_msg[i],
> sizeof(aux_msg) - i));
>  
> +	aux_clock_divider = intel_dp-
> >get_aux_clock_divider(intel_dp, 0);
> +
> +	/* Start with bits set for DDI_AUX_CTL register */
>  	aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, 0,
> sizeof(aux_msg),
>  					     aux_clock_divider);
> -	I915_WRITE(aux_ctl_reg, aux_ctl);
> +
> +	/* Select only valid bits for SRD_AUX_CTL */
> +	aux_ctl &= psr_aux_mask;
> +	I915_WRITE(EDP_PSR_AUX_CTL, aux_ctl);
>  }
>  
>  static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
> @@ -303,7 +286,7 @@ static void hsw_psr_enable_sink(struct intel_dp
> *intel_dp)
>  		drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
>  				   DP_PSR_ENABLE);
>  
> -	hsw_psr_setup_aux(intel_dp);
> +	drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
> DP_SET_POWER_D0);
>  }
>  
>  static void vlv_psr_enable_source(struct intel_dp *intel_dp,
> @@ -599,6 +582,12 @@ static void hsw_psr_enable_source(struct
> intel_dp *intel_dp,
>  
>  	psr_aux_io_power_get(intel_dp);
>  
> +	/* Only HSW and BDW have PSR AUX registers that need to be
> setup. SKL+
> +	 * use hardcoded values PSR AUX transactions
> +	 */
> +	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> +		hsw_psr_setup_aux(intel_dp);
> +
>  	if (dev_priv->psr.psr2_support) {
>  		chicken = PSR2_VSC_ENABLE_PROG_HEADER;
>  		if (dev_priv->psr.y_cord_support)
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Re: [PATCH 2/2] drm/i915/psr: Remove open-coded PSR AUX transactions for SKL+

[Rodrigo Vivi]

On Tue, Mar 13, 2018 at 08:46:56PM +0000, Souza, Jose wrote:
> On Mon, 2018-03-12 at 20:46 -0700, Dhinakaran Pandiyan wrote:
> > HSW and BDW have SRD_AUX_{CTL, STATUS} registers that the driver
> > needs to
> > setup for the HW to use whenever exiting PSR. SKL+ hardware use
> > hardcoded
> > values for the same and do not need any registers to be setup. So,
> > use
> > drm_dp_dpcd_writeb() for a one-time write during PSR enable and setup
> > the
> > PSR aux registers on HSW and BDW for later use by HW.
> > 
> > We also end up writing to reserved bits in SRD_AUX_CTL by reusing
> > intel_dp->get_aux_send_ctl() for HSW and BDW, fix this.
> > 
> > Since the AUX register setup is source side programming, move the
> > call
> > to enable_source() from enable_sink().
> > 
> > Cc: José Roberto de Souza <jose.souza@intel.com>
> 
> Reviewed-by: Jose Roberto de Souza <jose.souza@intel.com>

pushed to dinq. thanks for patch and review.

> 
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h  |  6 +++++
> >  drivers/gpu/drm/i915/intel_psr.c | 55 ++++++++++++++++------------
> > ------------
> >  2 files changed, 28 insertions(+), 33 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index abdc513a9edd..23c0f9bdf591 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -4151,6 +4151,12 @@ enum {
> >  #define   EDP_PSR_IDLE_FRAME_SHIFT		0
> >  
> >  #define EDP_PSR_AUX_CTL				_MMIO(dev_pri
> > v->psr_mmio_base + 0x10)
> > +#define   EDP_PSR_AUX_CTL_TIME_OUT_MASK		(3 << 26)
> > +#define   EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK	(0x1f << 20)
> > +#define   EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK	(0xf << 16)
> > +#define   EDP_PSR_AUX_CTL_ERROR_INTERRUPT	(1 << 11)
> > +#define   EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK	(0x7ff)
> > +
> >  #define EDP_PSR_AUX_DATA(i)			_MMIO(dev_priv-
> > >psr_mmio_base + 0x14 + (i) * 4) /* 5 registers */
> >  
> >  #define EDP_PSR_STATUS				_MMIO(dev_priv
> > ->psr_mmio_base + 0x40)
> > diff --git a/drivers/gpu/drm/i915/intel_psr.c
> > b/drivers/gpu/drm/i915/intel_psr.c
> > index 86d6c19c9ae6..293a987a1bfd 100644
> > --- a/drivers/gpu/drm/i915/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > @@ -228,31 +228,12 @@ static void vlv_psr_enable_sink(struct intel_dp
> > *intel_dp)
> >  			   DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
> >  }
> >  
> > -static i915_reg_t psr_aux_ctl_reg(struct drm_i915_private *dev_priv,
> > -				       enum port port)
> > -{
> > -	if (INTEL_GEN(dev_priv) >= 9)
> > -		return DP_AUX_CH_CTL(port);
> > -	else
> > -		return EDP_PSR_AUX_CTL;
> > -}
> > -
> > -static i915_reg_t psr_aux_data_reg(struct drm_i915_private
> > *dev_priv,
> > -					enum port port, int index)
> > -{
> > -	if (INTEL_GEN(dev_priv) >= 9)
> > -		return DP_AUX_CH_DATA(port, index);
> > -	else
> > -		return EDP_PSR_AUX_DATA(index);
> > -}
> > -
> >  static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
> >  {
> >  	struct intel_digital_port *dig_port =
> > dp_to_dig_port(intel_dp);
> > -	struct drm_device *dev = dig_port->base.base.dev;
> > -	struct drm_i915_private *dev_priv = to_i915(dev);
> > -	uint32_t aux_clock_divider;
> > -	i915_reg_t aux_ctl_reg;
> > +	struct drm_i915_private *dev_priv = to_i915(dig_port-
> > >base.base.dev);
> > +	u32 aux_clock_divider, aux_ctl;
> > +	int i;
> >  	static const uint8_t aux_msg[] = {
> >  		[0] = DP_AUX_NATIVE_WRITE << 4,
> >  		[1] = DP_SET_POWER >> 8,
> > @@ -260,23 +241,25 @@ static void hsw_psr_setup_aux(struct intel_dp
> > *intel_dp)
> >  		[3] = 1 - 1,
> >  		[4] = DP_SET_POWER_D0,
> >  	};
> > -	enum port port = dig_port->base.port;
> > -	u32 aux_ctl;
> > -	int i;
> > +	u32 psr_aux_mask = EDP_PSR_AUX_CTL_TIME_OUT_MASK |
> > +			   EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK |
> > +			   EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK |
> > +			   EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK;
> >  
> >  	BUILD_BUG_ON(sizeof(aux_msg) > 20);
> > -
> > -	aux_clock_divider = intel_dp-
> > >get_aux_clock_divider(intel_dp, 0);
> > -	aux_ctl_reg = psr_aux_ctl_reg(dev_priv, port);
> > -
> > -	/* Setup AUX registers */
> >  	for (i = 0; i < sizeof(aux_msg); i += 4)
> > -		I915_WRITE(psr_aux_data_reg(dev_priv, port, i >> 2),
> > +		I915_WRITE(EDP_PSR_AUX_DATA(i >> 2),
> >  			   intel_dp_pack_aux(&aux_msg[i],
> > sizeof(aux_msg) - i));
> >  
> > +	aux_clock_divider = intel_dp-
> > >get_aux_clock_divider(intel_dp, 0);
> > +
> > +	/* Start with bits set for DDI_AUX_CTL register */
> >  	aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, 0,
> > sizeof(aux_msg),
> >  					     aux_clock_divider);
> > -	I915_WRITE(aux_ctl_reg, aux_ctl);
> > +
> > +	/* Select only valid bits for SRD_AUX_CTL */
> > +	aux_ctl &= psr_aux_mask;
> > +	I915_WRITE(EDP_PSR_AUX_CTL, aux_ctl);
> >  }
> >  
> >  static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
> > @@ -303,7 +286,7 @@ static void hsw_psr_enable_sink(struct intel_dp
> > *intel_dp)
> >  		drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
> >  				   DP_PSR_ENABLE);
> >  
> > -	hsw_psr_setup_aux(intel_dp);
> > +	drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
> > DP_SET_POWER_D0);
> >  }
> >  
> >  static void vlv_psr_enable_source(struct intel_dp *intel_dp,
> > @@ -599,6 +582,12 @@ static void hsw_psr_enable_source(struct
> > intel_dp *intel_dp,
> >  
> >  	psr_aux_io_power_get(intel_dp);
> >  
> > +	/* Only HSW and BDW have PSR AUX registers that need to be
> > setup. SKL+
> > +	 * use hardcoded values PSR AUX transactions
> > +	 */
> > +	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> > +		hsw_psr_setup_aux(intel_dp);
> > +
> >  	if (dev_priv->psr.psr2_support) {
> >  		chicken = PSR2_VSC_ENABLE_PROG_HEADER;
> >  		if (dev_priv->psr.y_cord_support)
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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✗ Fi.CI.BAT: warning for series starting with [1/2] drm/i915/psr: Move PSR aux setup to it's own function.

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/psr: Move PSR aux setup to it's own function.
URL   : https://patchwork.freedesktop.org/series/39825/
State : warning

== Summary ==

Series 39825v1 series starting with [1/2] drm/i915/psr: Move PSR aux setup to it's own function.
https://patchwork.freedesktop.org/api/1.0/series/39825/revisions/1/mbox/

---- Possible new issues:

Test drv_module_reload:
        Subgroup basic-reload:
                pass       -> DMESG-WARN (fi-elk-e7500)

---- Known issues:

Test drv_module_reload:
        Subgroup basic-no-display:
                pass       -> DMESG-WARN (fi-elk-e7500) fdo#105074
Test kms_pipe_crc_basic:
        Subgroup suspend-read-crc-pipe-b:
                incomplete -> PASS       (fi-snb-2520m) fdo#103713

fdo#105074 https://bugs.freedesktop.org/show_bug.cgi?id=105074
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713

fi-bdw-5557u     total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  time:431s
fi-blb-e6850     total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  time:385s
fi-bsw-n3050     total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  time:532s
fi-bwr-2160      total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 time:298s
fi-bxt-dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  time:509s
fi-bxt-j4205     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:510s
fi-byt-j1900     total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  time:510s
fi-byt-n2820     total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  time:497s
fi-cfl-8700k     total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:410s
fi-cfl-s2        total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:578s
fi-elk-e7500     total:288  pass:227  dwarn:2   dfail:0   fail:0   skip:59  time:471s
fi-gdg-551       total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 time:315s
fi-glk-1         total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:531s
fi-hsw-4770      total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:404s
fi-ilk-650       total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  time:419s
fi-ivb-3520m     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:472s
fi-ivb-3770      total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  time:428s
fi-kbl-7500u     total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  time:473s
fi-kbl-7567u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:469s
fi-kbl-r         total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:514s
fi-skl-6260u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:441s
fi-skl-6600u     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:531s
fi-skl-6700hq    total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:549s
fi-skl-6700k2    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:506s
fi-skl-6770hq    total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:496s
fi-skl-guc       total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:429s
fi-snb-2520m     total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:540s
fi-snb-2600      total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:405s
Blacklisted hosts:
fi-cfl-u         total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:511s
fi-cnl-drrs      total:288  pass:257  dwarn:3   dfail:0   fail:0   skip:28  time:538s
fi-glk-j5005 failed to collect. IGT log at Patchwork_8319/fi-glk-j5005/run0.log

da600bbe24412edd1c46591fd21ef81518e49c5d drm-tip: 2018y-03m-12d-22h-06m-53s UTC integration manifest
394c1ac6f812 drm/i915/psr: Remove open-coded PSR AUX transactions for SKL+
ce00155daecf drm/i915/psr: Move PSR aux setup to it's own function.

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8319/issues.html
_______________________________________________
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Re: ✗ Fi.CI.BAT: warning for series starting with [1/2] drm/i915/psr: Move PSR aux setup to it's own function.

[Pandiyan, Dhinakaran]

On Tue, 2018-03-13 at 04:23 +0000, Patchwork wrote:
> == Series Details ==
> 
> Series: series starting with [1/2] drm/i915/psr: Move PSR aux setup to it's own function.
> URL   : https://patchwork.freedesktop.org/series/39825/
> State : warning
> 
> == Summary ==
> 
> Series 39825v1 series starting with [1/2] drm/i915/psr: Move PSR aux setup to it's own function.
> https://patchwork.freedesktop.org/api/1.0/series/39825/revisions/1/mbox/
> 
> ---- Possible new issues:
> 
> Test drv_module_reload:
>         Subgroup basic-reload:
>                 pass       -> DMESG-WARN (fi-elk-e7500)

Platform does not have PSR, error looks spurious.
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✗ Fi.CI.BAT: warning for series starting with [1/2] drm/i915/psr: Move PSR aux setup to it's own function.

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/psr: Move PSR aux setup to it's own function.
URL   : https://patchwork.freedesktop.org/series/39825/
State : warning

== Summary ==

Series 39825v1 series starting with [1/2] drm/i915/psr: Move PSR aux setup to it's own function.
https://patchwork.freedesktop.org/api/1.0/series/39825/revisions/1/mbox/

---- Possible new issues:

Test kms_busy:
        Subgroup basic-flip-a:
                skip       -> PASS       (fi-ivb-3770)
        Subgroup basic-flip-b:
                skip       -> PASS       (fi-ivb-3770)
        Subgroup basic-flip-c:
                skip       -> PASS       (fi-ivb-3770)
Test kms_cursor_legacy:
        Subgroup basic-busy-flip-before-cursor-atomic:
                skip       -> PASS       (fi-ivb-3770)
        Subgroup basic-busy-flip-before-cursor-legacy:
                skip       -> PASS       (fi-ivb-3770)
        Subgroup basic-flip-after-cursor-atomic:
                skip       -> PASS       (fi-ivb-3770)
        Subgroup basic-flip-after-cursor-legacy:
                skip       -> PASS       (fi-ivb-3770)
        Subgroup basic-flip-after-cursor-varying-size:
                skip       -> PASS       (fi-ivb-3770)
        Subgroup basic-flip-before-cursor-atomic:
                skip       -> PASS       (fi-ivb-3770)
        Subgroup basic-flip-before-cursor-legacy:
                skip       -> PASS       (fi-ivb-3770)
        Subgroup basic-flip-before-cursor-varying-size:
                skip       -> PASS       (fi-ivb-3770)
Test kms_force_connector_basic:
        Subgroup prune-stale-modes:
                pass       -> SKIP       (fi-ivb-3770)
Test kms_frontbuffer_tracking:
        Subgroup basic:
                skip       -> PASS       (fi-ivb-3770)

---- Known issues:

Test kms_chamelium:
        Subgroup dp-crc-fast:
                fail       -> PASS       (fi-kbl-7500u) fdo#103841
Test prime_vgem:
        Subgroup basic-fence-flip:
                pass       -> FAIL       (fi-ilk-650) fdo#104008 +1

fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841
fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008

fi-bdw-5557u     total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  time:432s
fi-bdw-gvtdvm    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:432s
fi-blb-e6850     total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  time:381s
fi-bsw-n3050     total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  time:537s
fi-bwr-2160      total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 time:300s
fi-bxt-dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  time:509s
fi-bxt-j4205     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:512s
fi-byt-j1900     total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  time:506s
fi-byt-n2820     total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  time:495s
fi-cfl-8700k     total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:411s
fi-cfl-s2        total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:586s
fi-cnl-y3        total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:588s
fi-elk-e7500     total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  time:419s
fi-gdg-551       total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 time:313s
fi-glk-1         total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:534s
fi-hsw-4770      total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:402s
fi-ilk-650       total:288  pass:227  dwarn:0   dfail:0   fail:1   skip:60  time:421s
fi-ivb-3520m     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:472s
fi-ivb-3770      total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  time:429s
fi-kbl-7500u     total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  time:475s
fi-kbl-7567u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:469s
fi-kbl-r         total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:515s
fi-pnv-d510      total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  time:645s
fi-skl-6260u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:440s
fi-skl-6600u     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:528s
fi-skl-6700hq    total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:540s
fi-skl-6700k2    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:506s
fi-skl-6770hq    total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:494s
fi-skl-guc       total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:427s
fi-skl-gvtdvm    total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  time:436s
fi-snb-2520m     total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:536s
fi-snb-2600      total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:398s
Blacklisted hosts:
fi-cfl-u         total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:509s
fi-cnl-drrs      total:288  pass:257  dwarn:3   dfail:0   fail:0   skip:28  time:516s

874b86a759851707e26286c22062f6ccc526e46f drm-tip: 2018y-03m-13d-12h-36m-17s UTC integration manifest
a9a40c3cf93a drm/i915/psr: Remove open-coded PSR AUX transactions for SKL+
5cdf4b95cae2 drm/i915/psr: Move PSR aux setup to it's own function.

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8332/issues.html
_______________________________________________
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✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/psr: Move PSR aux setup to it's own function.

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/psr: Move PSR aux setup to it's own function.
URL   : https://patchwork.freedesktop.org/series/39825/
State : success

== Summary ==

Series 39825v1 series starting with [1/2] drm/i915/psr: Move PSR aux setup to it's own function.
https://patchwork.freedesktop.org/api/1.0/series/39825/revisions/1/mbox/

fi-bdw-5557u     total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  time:433s
fi-bdw-gvtdvm    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:434s
fi-blb-e6850     total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  time:382s
fi-bsw-n3050     total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  time:535s
fi-bwr-2160      total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 time:298s
fi-bxt-dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  time:504s
fi-bxt-j4205     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:513s
fi-byt-j1900     total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  time:506s
fi-byt-n2820     total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  time:504s
fi-cfl-8700k     total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:410s
fi-cfl-s2        total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:582s
fi-cnl-y3        total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:588s
fi-elk-e7500     total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  time:434s
fi-gdg-551       total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 time:314s
fi-glk-1         total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:531s
fi-hsw-4770      total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:402s
fi-ilk-650       total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  time:419s
fi-ivb-3520m     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:473s
fi-ivb-3770      total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  time:434s
fi-kbl-7500u     total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  time:477s
fi-kbl-7567u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:469s
fi-kbl-r         total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:515s
fi-pnv-d510      total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  time:643s
fi-skl-6260u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:438s
fi-skl-6600u     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:530s
fi-skl-6700hq    total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:538s
fi-skl-6700k2    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:511s
fi-skl-6770hq    total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:486s
fi-skl-guc       total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:428s
fi-skl-gvtdvm    total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  time:437s
fi-snb-2520m     total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:525s
fi-snb-2600      total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:400s
Blacklisted hosts:
fi-cfl-u         total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:513s
fi-cnl-drrs      total:288  pass:257  dwarn:3   dfail:0   fail:0   skip:28  time:525s

c78cebe28cbdd6d46df0a951adeb74b16af8f6a6 drm-tip: 2018y-03m-13d-21h-48m-45s UTC integration manifest
440984df5c9a drm/i915/psr: Remove open-coded PSR AUX transactions for SKL+
c754d1348290 drm/i915/psr: Move PSR aux setup to it's own function.

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8333/issues.html
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✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/psr: Move PSR aux setup to it's own function.

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/psr: Move PSR aux setup to it's own function.
URL   : https://patchwork.freedesktop.org/series/39825/
State : success

== Summary ==

---- Known issues:

Test gem_eio:
        Subgroup in-flight-contexts:
                pass       -> INCOMPLETE (shard-apl) fdo#105341
Test kms_cursor_crc:
        Subgroup cursor-64x64-suspend:
                skip       -> PASS       (shard-hsw) fdo#103540
Test kms_flip:
        Subgroup flip-vs-expired-vblank:
                fail       -> PASS       (shard-hsw) fdo#102887 +1
        Subgroup plain-flip-ts-check:
                pass       -> FAIL       (shard-hsw) fdo#100368
Test kms_sysfs_edid_timing:
                pass       -> WARN       (shard-apl) fdo#100047
Test perf:
        Subgroup polling:
                pass       -> FAIL       (shard-hsw) fdo#102252

fdo#105341 https://bugs.freedesktop.org/show_bug.cgi?id=105341
fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-apl        total:3360 pass:1778 dwarn:1   dfail:0   fail:6   skip:1573 time:12777s
shard-hsw        total:3444 pass:1768 dwarn:1   dfail:0   fail:3   skip:1671 time:11795s
shard-snb        total:3444 pass:1360 dwarn:1   dfail:0   fail:2   skip:2081 time:7234s
Blacklisted hosts:
shard-kbl        total:3390 pass:1912 dwarn:1   dfail:0   fail:9   skip:1467 time:9643s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8333/shards.html
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Re: [PATCH 1/2] drm/i915/psr: Move PSR aux setup to it's own function.

[Rodrigo Vivi]

On Mon, Mar 12, 2018 at 08:46:45PM -0700, Dhinakaran Pandiyan wrote:
> Non-functional change useful for the following patch.
> 
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_psr.c | 31 ++++++++++++++++++++-----------
>  1 file changed, 20 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 975ebb51c7af..86d6c19c9ae6 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -246,7 +246,7 @@ static i915_reg_t psr_aux_data_reg(struct drm_i915_private *dev_priv,
>  		return EDP_PSR_AUX_DATA(index);
>  }
>  
> -static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
> +static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
>  {
>  	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>  	struct drm_device *dev = dig_port->base.base.dev;
> @@ -267,6 +267,24 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
>  	BUILD_BUG_ON(sizeof(aux_msg) > 20);
>  
>  	aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
> +	aux_ctl_reg = psr_aux_ctl_reg(dev_priv, port);
> +
> +	/* Setup AUX registers */
> +	for (i = 0; i < sizeof(aux_msg); i += 4)
> +		I915_WRITE(psr_aux_data_reg(dev_priv, port, i >> 2),
> +			   intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
> +
> +	aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, 0, sizeof(aux_msg),
> +					     aux_clock_divider);
> +	I915_WRITE(aux_ctl_reg, aux_ctl);
> +}
> +
> +static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
> +{
> +	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> +	struct drm_device *dev = dig_port->base.base.dev;
> +	struct drm_i915_private *dev_priv = to_i915(dev);
> +
>  
>  	/* Enable AUX frame sync at sink */
>  	if (dev_priv->psr.aux_frame_sync)
> @@ -285,16 +303,7 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
>  		drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
>  				   DP_PSR_ENABLE);
>  
> -	aux_ctl_reg = psr_aux_ctl_reg(dev_priv, port);
> -
> -	/* Setup AUX registers */
> -	for (i = 0; i < sizeof(aux_msg); i += 4)
> -		I915_WRITE(psr_aux_data_reg(dev_priv, port, i >> 2),
> -			   intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
> -
> -	aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, 0, sizeof(aux_msg),
> -					     aux_clock_divider);
> -	I915_WRITE(aux_ctl_reg, aux_ctl);
> +	hsw_psr_setup_aux(intel_dp);
>  }
>  
>  static void vlv_psr_enable_source(struct intel_dp *intel_dp,
> -- 
> 2.14.1
> 
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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