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From: Rosen Xu <rosen.xu@intel.com>
To: dev@dpdk.org
Cc: declan.doherty@intel.com, bruce.richardson@intel.com,
	shreyansh.jain@nxp.com, tianfei.zhang@intel.com,
	hao.wu@intel.com, gaetan.rivet@6wind.com
Subject: [PATCH V2 2/5] Add Intel FPGA BUS Probe Code
Date: Wed, 21 Mar 2018 15:51:31 +0800	[thread overview]
Message-ID: <1521618694-140757-3-git-send-email-rosen.xu@intel.com> (raw)
In-Reply-To: <1521618694-140757-1-git-send-email-rosen.xu@intel.com>

Signed-off-by: Rosen Xu <rosen.xu@intel.com>
---
 lib/librte_eal/common/eal_common_bus.c | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/lib/librte_eal/common/eal_common_bus.c b/lib/librte_eal/common/eal_common_bus.c
index 3e022d5..e3bcebe 100644
--- a/lib/librte_eal/common/eal_common_bus.c
+++ b/lib/librte_eal/common/eal_common_bus.c
@@ -87,7 +87,7 @@ struct rte_bus_list rte_bus_list =
 rte_bus_probe(void)
 {
 	int ret;
-	struct rte_bus *bus, *vbus = NULL;
+	struct rte_bus *bus, *vbus = NULL, *ifpga_bus = NULL;
 
 	TAILQ_FOREACH(bus, &rte_bus_list, next) {
 		if (!strcmp(bus->name, "vdev")) {
@@ -95,6 +95,11 @@ struct rte_bus_list rte_bus_list =
 			continue;
 		}
 
+		if (!strcmp(bus->name, "ifpga")) {
+			ifpga_bus = bus;
+			continue;
+		}
+
 		ret = bus->probe();
 		if (ret)
 			RTE_LOG(ERR, EAL, "Bus (%s) probe failed.\n",
@@ -108,6 +113,13 @@ struct rte_bus_list rte_bus_list =
 				vbus->name);
 	}
 
+	if (ifpga_bus) {
+		ret = ifpga_bus->probe();
+		if (ret)
+			RTE_LOG(ERR, EAL, "Scan for (%s) bus failed.\n",
+				ifpga_bus->name);
+	}
+
 	return 0;
 }
 
-- 
1.8.3.1

  parent reply	other threads:[~2018-03-21  7:49 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-21  7:51 [PATCH V2 0/5] Introduce Intel FPGA BUS Rosen Xu
2018-03-21  7:51 ` [PATCH V2 1/5] Add Intel FPGA BUS Command Parse Code Rosen Xu
2018-03-21  7:51 ` Rosen Xu [this message]
2018-03-21  9:07   ` [PATCH V2 2/5] Add Intel FPGA BUS Probe Code Shreyansh Jain
2018-03-21  9:10     ` Shreyansh Jain
2018-03-21 10:05   ` Gaëtan Rivet
2018-03-21  7:51 ` [PATCH V2 3/5] Add Intel FPGA BUS Lib Code Rosen Xu
2018-03-21  9:28   ` Shreyansh Jain
2018-03-21 10:20   ` Gaëtan Rivet
2018-03-21 13:35     ` Bruce Richardson
2018-03-21 14:02       ` Shreyansh Jain
2018-03-21 14:06       ` Xu, Rosen
2018-03-21 14:14       ` Gaëtan Rivet
2018-03-21 14:31         ` Gaëtan Rivet
2018-03-21 15:41           ` Bruce Richardson
2018-03-21 16:21             ` Gaëtan Rivet
2018-03-21  7:51 ` [PATCH V2 4/5] Add Intel FPGA BUS Rawdev Code Rosen Xu
2018-03-21  7:51 ` [PATCH V2 5/5] Add Intel OPAE Share Code Rosen Xu
2018-03-21 10:00 ` [PATCH V2 0/5] Introduce Intel FPGA BUS Gaëtan Rivet

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