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From: Shreyansh Jain <shreyansh.jain@nxp.com>
To: Rosen Xu <rosen.xu@intel.com>
Cc: dev@dpdk.org, declan.doherty@intel.com,
	Bruce Richardson <bruce.richardson@intel.com>,
	tianfei.zhang@intel.com, hao.wu@intel.com,
	gaetan.rivet@6wind.com
Subject: Re: [PATCH V2 2/5] Add Intel FPGA BUS Probe Code
Date: Wed, 21 Mar 2018 14:40:13 +0530	[thread overview]
Message-ID: <CAJ5mUsVm0RLym5puUAcKqswkba+WKD+AivaFeBmS5=NfRx1qkQ@mail.gmail.com> (raw)
In-Reply-To: <CAJ5mUsVsb1H1N-H-C5ArQEL+hUSarXPjjpV4ezMMoEu_sxCf1Q@mail.gmail.com>

On Wed, Mar 21, 2018 at 2:37 PM, Shreyansh Jain <shreyansh.jain@nxp.com> wrote:
> Hello Rosen,
>
> On Wed, Mar 21, 2018 at 1:21 PM, Rosen Xu <rosen.xu@intel.com> wrote:
>> Signed-off-by: Rosen Xu <rosen.xu@intel.com>
>> ---
>>  lib/librte_eal/common/eal_common_bus.c | 14 +++++++++++++-
>>  1 file changed, 13 insertions(+), 1 deletion(-)
>>
>> diff --git a/lib/librte_eal/common/eal_common_bus.c b/lib/librte_eal/common/eal_common_bus.c
>> index 3e022d5..e3bcebe 100644
>> --- a/lib/librte_eal/common/eal_common_bus.c
>> +++ b/lib/librte_eal/common/eal_common_bus.c
>> @@ -87,7 +87,7 @@ struct rte_bus_list rte_bus_list =
>>  rte_bus_probe(void)
>>  {
>>         int ret;
>> -       struct rte_bus *bus, *vbus = NULL;
>> +       struct rte_bus *bus, *vbus = NULL, *ifpga_bus = NULL;
>>
>>         TAILQ_FOREACH(bus, &rte_bus_list, next) {
>>                 if (!strcmp(bus->name, "vdev")) {
>> @@ -95,6 +95,11 @@ struct rte_bus_list rte_bus_list =
>>                         continue;
>>                 }
>>
>> +               if (!strcmp(bus->name, "ifpga")) {
>> +                       ifpga_bus = bus;
>> +                       continue;
>> +               }
>> +
>>                 ret = bus->probe();
>>                 if (ret)
>>                         RTE_LOG(ERR, EAL, "Bus (%s) probe failed.\n",
>> @@ -108,6 +113,13 @@ struct rte_bus_list rte_bus_list =
>>                                 vbus->name);
>>         }
>>
>> +       if (ifpga_bus) {
>> +               ret = ifpga_bus->probe();
>> +               if (ret)
>> +                       RTE_LOG(ERR, EAL, "Scan for (%s) bus failed.\n",
>> +                               ifpga_bus->name);
>> +       }
>> +
>
> Just like my comment on RFC, I still think this is not the right thing to do.
> I understand you want a case where IFPGA bus gets probed only after
> PCI bus is probed.
> There can be multiple ways. Two of them which I can quickly list
> without much deliberation:
>
> 1. A framework which can 'defer probing'
>    So, a bus can register for defer probe and its
> check_if_probe_available() function callback is called through
> rte_bus_probe()
>    If it returns OK, its probe is called, else it is added to a defer
> list which is called once all first register buses are probed.
>
> 2. Modify the priority in RTE_REGISTER_BUS and make it as an argument
> or a new variant which can take an argument.
>
> It is not ok to change this function specifically for a bus is because
> this method is not scalable.

A cross on my own comment - I know vdev is already doing this special
probe but if we have a proper mechanism we can avoid that as well. Or,
continue to consider vdev as special :D

>
> Is there some specific reason you would like to stick to this approach?
>
> [...]
>
> -
> Shreyansh

  reply	other threads:[~2018-03-21  9:10 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-21  7:51 [PATCH V2 0/5] Introduce Intel FPGA BUS Rosen Xu
2018-03-21  7:51 ` [PATCH V2 1/5] Add Intel FPGA BUS Command Parse Code Rosen Xu
2018-03-21  7:51 ` [PATCH V2 2/5] Add Intel FPGA BUS Probe Code Rosen Xu
2018-03-21  9:07   ` Shreyansh Jain
2018-03-21  9:10     ` Shreyansh Jain [this message]
2018-03-21 10:05   ` Gaëtan Rivet
2018-03-21  7:51 ` [PATCH V2 3/5] Add Intel FPGA BUS Lib Code Rosen Xu
2018-03-21  9:28   ` Shreyansh Jain
2018-03-21 10:20   ` Gaëtan Rivet
2018-03-21 13:35     ` Bruce Richardson
2018-03-21 14:02       ` Shreyansh Jain
2018-03-21 14:06       ` Xu, Rosen
2018-03-21 14:14       ` Gaëtan Rivet
2018-03-21 14:31         ` Gaëtan Rivet
2018-03-21 15:41           ` Bruce Richardson
2018-03-21 16:21             ` Gaëtan Rivet
2018-03-21  7:51 ` [PATCH V2 4/5] Add Intel FPGA BUS Rawdev Code Rosen Xu
2018-03-21  7:51 ` [PATCH V2 5/5] Add Intel OPAE Share Code Rosen Xu
2018-03-21 10:00 ` [PATCH V2 0/5] Introduce Intel FPGA BUS Gaëtan Rivet

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