* [Qemu-devel] [PATCH v1 0/2] RISC-V: Important fixes for QEMU 2.12
@ 2018-03-27 19:55 Michael Clark
2018-03-27 19:55 ` [Qemu-devel] [PATCH v1 1/2] RISC-V: Convert cpu definition to future model Michael Clark
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Michael Clark @ 2018-03-27 19:55 UTC (permalink / raw)
To: qemu-devel, Peter Maydell
Cc: patches, Michael Clark, Palmer Dabbelt, Sagar Karandikar,
Bastian Koppelmann
This series includes changes that are considered important.
i.e. correct user-visible bugs that are exercised by common
operations such as -cpu list or -d in_asm
Michael Clark (2):
RISC-V: Convert cpu definition to future model
RISC-V: Fix incorrect disassembly for addiw
disas/riscv.c | 2 +-
target/riscv/cpu.c | 123 ++++++++++++++++++++++++++++++-----------------------
2 files changed, 70 insertions(+), 55 deletions(-)
--
2.7.0
^ permalink raw reply [flat|nested] 7+ messages in thread
* [Qemu-devel] [PATCH v1 1/2] RISC-V: Convert cpu definition to future model
2018-03-27 19:55 [Qemu-devel] [PATCH v1 0/2] RISC-V: Important fixes for QEMU 2.12 Michael Clark
@ 2018-03-27 19:55 ` Michael Clark
2018-03-28 4:38 ` Richard Henderson
2018-03-27 19:55 ` [Qemu-devel] [PATCH v1 2/2] RISC-V: Fix incorrect disassembly for addiw Michael Clark
2018-03-31 7:33 ` [Qemu-devel] [PATCH v1 0/2] RISC-V: Important fixes for QEMU 2.12 no-reply
2 siblings, 1 reply; 7+ messages in thread
From: Michael Clark @ 2018-03-27 19:55 UTC (permalink / raw)
To: qemu-devel
Cc: patches, Michael Clark, Igor Mammedov, Sagar Karandikar,
Bastian Koppelmann, Palmer Dabbelt
- Model borrowed from target/sh4/cpu.c
- Rewrote riscv_cpu_list to use object_class_get_list
- Dropped 'struct RISCVCPUInfo' and used TypeInfo array
- Replaced riscv_cpu_register_types with DEFINE_TYPES
- Marked base class as abstract
- Fixes -cpu list
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
---
target/riscv/cpu.c | 123 ++++++++++++++++++++++++++++++-----------------------
1 file changed, 69 insertions(+), 54 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 9de34d7..5a527fb 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -115,6 +115,8 @@ static void riscv_any_cpu_init(Object *obj)
set_resetvec(env, DEFAULT_RSTVEC);
}
+#if defined(TARGET_RISCV32)
+
static void rv32gcsu_priv1_09_1_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
@@ -141,6 +143,8 @@ static void rv32imacu_nommu_cpu_init(Object *obj)
set_resetvec(env, DEFAULT_RSTVEC);
}
+#elif defined(TARGET_RISCV64)
+
static void rv64gcsu_priv1_09_1_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
@@ -167,20 +171,7 @@ static void rv64imacu_nommu_cpu_init(Object *obj)
set_resetvec(env, DEFAULT_RSTVEC);
}
-static const RISCVCPUInfo riscv_cpus[] = {
- { 96, TYPE_RISCV_CPU_ANY, riscv_any_cpu_init },
- { 32, TYPE_RISCV_CPU_RV32GCSU_V1_09_1, rv32gcsu_priv1_09_1_cpu_init },
- { 32, TYPE_RISCV_CPU_RV32GCSU_V1_10_0, rv32gcsu_priv1_10_0_cpu_init },
- { 32, TYPE_RISCV_CPU_RV32IMACU_NOMMU, rv32imacu_nommu_cpu_init },
- { 32, TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init },
- { 32, TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init },
- { 64, TYPE_RISCV_CPU_RV64GCSU_V1_09_1, rv64gcsu_priv1_09_1_cpu_init },
- { 64, TYPE_RISCV_CPU_RV64GCSU_V1_10_0, rv64gcsu_priv1_10_0_cpu_init },
- { 64, TYPE_RISCV_CPU_RV64IMACU_NOMMU, rv64imacu_nommu_cpu_init },
- { 64, TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init },
- { 64, TYPE_RISCV_CPU_SIFIVE_U54, rv64gcsu_priv1_10_0_cpu_init },
- { 0, NULL, NULL }
-};
+#endif
static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
{
@@ -366,28 +357,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->vmsd = &vmstate_riscv_cpu;
}
-static void cpu_register(const RISCVCPUInfo *info)
-{
- TypeInfo type_info = {
- .name = info->name,
- .parent = TYPE_RISCV_CPU,
- .instance_size = sizeof(RISCVCPU),
- .instance_init = info->initfn,
- };
-
- type_register(&type_info);
-}
-
-static const TypeInfo riscv_cpu_type_info = {
- .name = TYPE_RISCV_CPU,
- .parent = TYPE_CPU,
- .instance_size = sizeof(RISCVCPU),
- .instance_init = riscv_cpu_init,
- .abstract = false,
- .class_size = sizeof(RISCVCPUClass),
- .class_init = riscv_cpu_class_init,
-};
-
char *riscv_isa_string(RISCVCPU *cpu)
{
int i;
@@ -403,30 +372,76 @@ char *riscv_isa_string(RISCVCPU *cpu)
return isa_str;
}
-void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf)
+typedef struct RISCVCPUListState {
+ fprintf_function cpu_fprintf;
+ FILE *file;
+} RISCVCPUListState;
+
+static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b)
{
- const RISCVCPUInfo *info = riscv_cpus;
+ ObjectClass *class_a = (ObjectClass *)a;
+ ObjectClass *class_b = (ObjectClass *)b;
+ const char *name_a, *name_b;
- while (info->name) {
- if (info->bit_widths & TARGET_LONG_BITS) {
- (*cpu_fprintf)(f, "%s\n", info->name);
- }
- info++;
- }
+ name_a = object_class_get_name(class_a);
+ name_b = object_class_get_name(class_b);
+ return strcmp(name_a, name_b);
}
-static void riscv_cpu_register_types(void)
+static void riscv_cpu_list_entry(gpointer data, gpointer user_data)
{
- const RISCVCPUInfo *info = riscv_cpus;
+ RISCVCPUListState *s = user_data;
+ const char *typename = object_class_get_name(OBJECT_CLASS(data));
+ int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX);
- type_register_static(&riscv_cpu_type_info);
+ (*s->cpu_fprintf)(s->file, "%.*s\n", len, typename);
+}
- while (info->name) {
- if (info->bit_widths & TARGET_LONG_BITS) {
- cpu_register(info);
- }
- info++;
- }
+void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf)
+{
+ RISCVCPUListState s = {
+ .cpu_fprintf = cpu_fprintf,
+ .file = f,
+ };
+ GSList *list;
+
+ list = object_class_get_list(TYPE_RISCV_CPU, false);
+ list = g_slist_sort(list, riscv_cpu_list_compare);
+ g_slist_foreach(list, riscv_cpu_list_entry, &s);
+ g_slist_free(list);
}
-type_init(riscv_cpu_register_types)
+#define DEFINE_CPU(type_name, initfn) \
+ { \
+ .name = type_name, \
+ .parent = TYPE_RISCV_CPU, \
+ .instance_init = initfn \
+ }
+
+static const TypeInfo riscv_cpu_type_infos[] = {
+ {
+ .name = TYPE_RISCV_CPU,
+ .parent = TYPE_CPU,
+ .instance_size = sizeof(RISCVCPU),
+ .instance_init = riscv_cpu_init,
+ .abstract = true,
+ .class_size = sizeof(RISCVCPUClass),
+ .class_init = riscv_cpu_class_init,
+ },
+ DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
+#if defined(TARGET_RISCV32)
+ DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_09_1, rv32gcsu_priv1_09_1_cpu_init),
+ DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_10_0, rv32gcsu_priv1_10_0_cpu_init),
+ DEFINE_CPU(TYPE_RISCV_CPU_RV32IMACU_NOMMU, rv32imacu_nommu_cpu_init),
+ DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init),
+ DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init)
+#elif defined(TARGET_RISCV64)
+ DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_09_1, rv64gcsu_priv1_09_1_cpu_init),
+ DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_10_0, rv64gcsu_priv1_10_0_cpu_init),
+ DEFINE_CPU(TYPE_RISCV_CPU_RV64IMACU_NOMMU, rv64imacu_nommu_cpu_init),
+ DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init),
+ DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64gcsu_priv1_10_0_cpu_init)
+#endif
+};
+
+DEFINE_TYPES(riscv_cpu_type_infos)
--
2.7.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [Qemu-devel] [PATCH v1 2/2] RISC-V: Fix incorrect disassembly for addiw
2018-03-27 19:55 [Qemu-devel] [PATCH v1 0/2] RISC-V: Important fixes for QEMU 2.12 Michael Clark
2018-03-27 19:55 ` [Qemu-devel] [PATCH v1 1/2] RISC-V: Convert cpu definition to future model Michael Clark
@ 2018-03-27 19:55 ` Michael Clark
2018-03-27 22:15 ` Philippe Mathieu-Daudé
2018-03-28 4:40 ` Richard Henderson
2018-03-31 7:33 ` [Qemu-devel] [PATCH v1 0/2] RISC-V: Important fixes for QEMU 2.12 no-reply
2 siblings, 2 replies; 7+ messages in thread
From: Michael Clark @ 2018-03-27 19:55 UTC (permalink / raw)
To: qemu-devel
Cc: patches, Michael Clark, Sagar Karandikar, Bastian Koppelmann,
Palmer Dabbelt, Peter Maydell
This fixes a bug in the disassembler constraints used
to lift instructions into pseudo-instructions, whereby
addiw instructions are always lifted to sext.w instead
of just lifting addiw with a zero immediate.
An associated fix has been made to the metadata used to
machine generate the disseasembler:
https://github.com/michaeljclark/riscv-meta/
commit/4a6b2f3898430768acfe201405224d2ea31e1477
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Michael Clark <mjc@sifive.com>
---
disas/riscv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 3c17501..74ad16e 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -600,7 +600,7 @@ static const rvc_constraint rvcc_mv[] = { rvc_imm_eq_zero, rvc_end };
static const rvc_constraint rvcc_not[] = { rvc_imm_eq_n1, rvc_end };
static const rvc_constraint rvcc_neg[] = { rvc_rs1_eq_x0, rvc_end };
static const rvc_constraint rvcc_negw[] = { rvc_rs1_eq_x0, rvc_end };
-static const rvc_constraint rvcc_sext_w[] = { rvc_rs2_eq_x0, rvc_end };
+static const rvc_constraint rvcc_sext_w[] = { rvc_imm_eq_zero, rvc_end };
static const rvc_constraint rvcc_seqz[] = { rvc_imm_eq_p1, rvc_end };
static const rvc_constraint rvcc_snez[] = { rvc_rs1_eq_x0, rvc_end };
static const rvc_constraint rvcc_sltz[] = { rvc_rs2_eq_x0, rvc_end };
--
2.7.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [Qemu-devel] [PATCH v1 2/2] RISC-V: Fix incorrect disassembly for addiw
2018-03-27 19:55 ` [Qemu-devel] [PATCH v1 2/2] RISC-V: Fix incorrect disassembly for addiw Michael Clark
@ 2018-03-27 22:15 ` Philippe Mathieu-Daudé
2018-03-28 4:40 ` Richard Henderson
1 sibling, 0 replies; 7+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-03-27 22:15 UTC (permalink / raw)
To: Michael Clark, qemu-devel
Cc: Peter Maydell, Sagar Karandikar, Bastian Koppelmann,
Palmer Dabbelt, patches
On 03/27/2018 04:55 PM, Michael Clark wrote:
> This fixes a bug in the disassembler constraints used
> to lift instructions into pseudo-instructions, whereby
> addiw instructions are always lifted to sext.w instead
> of just lifting addiw with a zero immediate.
>
> An associated fix has been made to the metadata used to
> machine generate the disseasembler:
>
> https://github.com/michaeljclark/riscv-meta/
> commit/4a6b2f3898430768acfe201405224d2ea31e1477
>
> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Cc: Palmer Dabbelt <palmer@sifive.com>
> Cc: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> disas/riscv.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 3c17501..74ad16e 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -600,7 +600,7 @@ static const rvc_constraint rvcc_mv[] = { rvc_imm_eq_zero, rvc_end };
> static const rvc_constraint rvcc_not[] = { rvc_imm_eq_n1, rvc_end };
> static const rvc_constraint rvcc_neg[] = { rvc_rs1_eq_x0, rvc_end };
> static const rvc_constraint rvcc_negw[] = { rvc_rs1_eq_x0, rvc_end };
> -static const rvc_constraint rvcc_sext_w[] = { rvc_rs2_eq_x0, rvc_end };
> +static const rvc_constraint rvcc_sext_w[] = { rvc_imm_eq_zero, rvc_end };
> static const rvc_constraint rvcc_seqz[] = { rvc_imm_eq_p1, rvc_end };
> static const rvc_constraint rvcc_snez[] = { rvc_rs1_eq_x0, rvc_end };
> static const rvc_constraint rvcc_sltz[] = { rvc_rs2_eq_x0, rvc_end };
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Qemu-devel] [PATCH v1 1/2] RISC-V: Convert cpu definition to future model
2018-03-27 19:55 ` [Qemu-devel] [PATCH v1 1/2] RISC-V: Convert cpu definition to future model Michael Clark
@ 2018-03-28 4:38 ` Richard Henderson
0 siblings, 0 replies; 7+ messages in thread
From: Richard Henderson @ 2018-03-28 4:38 UTC (permalink / raw)
To: Michael Clark, qemu-devel
Cc: Sagar Karandikar, Bastian Koppelmann, Palmer Dabbelt,
Igor Mammedov, patches
On 03/28/2018 03:55 AM, Michael Clark wrote:
> - Model borrowed from target/sh4/cpu.c
> - Rewrote riscv_cpu_list to use object_class_get_list
> - Dropped 'struct RISCVCPUInfo' and used TypeInfo array
> - Replaced riscv_cpu_register_types with DEFINE_TYPES
> - Marked base class as abstract
> - Fixes -cpu list
>
> Cc: Igor Mammedov <imammedo@redhat.com>
> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Cc: Palmer Dabbelt <palmer@sifive.com>
> Signed-off-by: Michael Clark <mjc@sifive.com>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Reviewed-by: Igor Mammedov <imammedo@redhat.com>
> ---
> target/riscv/cpu.c | 123 ++++++++++++++++++++++++++++++-----------------------
> 1 file changed, 69 insertions(+), 54 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Qemu-devel] [PATCH v1 2/2] RISC-V: Fix incorrect disassembly for addiw
2018-03-27 19:55 ` [Qemu-devel] [PATCH v1 2/2] RISC-V: Fix incorrect disassembly for addiw Michael Clark
2018-03-27 22:15 ` Philippe Mathieu-Daudé
@ 2018-03-28 4:40 ` Richard Henderson
1 sibling, 0 replies; 7+ messages in thread
From: Richard Henderson @ 2018-03-28 4:40 UTC (permalink / raw)
To: Michael Clark, qemu-devel
Cc: Peter Maydell, Sagar Karandikar, Bastian Koppelmann,
Palmer Dabbelt, patches
On 03/28/2018 03:55 AM, Michael Clark wrote:
> This fixes a bug in the disassembler constraints used
> to lift instructions into pseudo-instructions, whereby
> addiw instructions are always lifted to sext.w instead
> of just lifting addiw with a zero immediate.
>
> An associated fix has been made to the metadata used to
> machine generate the disseasembler:
>
> https://github.com/michaeljclark/riscv-meta/
> commit/4a6b2f3898430768acfe201405224d2ea31e1477
>
> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Cc: Palmer Dabbelt <palmer@sifive.com>
> Cc: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Michael Clark <mjc@sifive.com>
> ---
> disas/riscv.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Qemu-devel] [PATCH v1 0/2] RISC-V: Important fixes for QEMU 2.12
2018-03-27 19:55 [Qemu-devel] [PATCH v1 0/2] RISC-V: Important fixes for QEMU 2.12 Michael Clark
2018-03-27 19:55 ` [Qemu-devel] [PATCH v1 1/2] RISC-V: Convert cpu definition to future model Michael Clark
2018-03-27 19:55 ` [Qemu-devel] [PATCH v1 2/2] RISC-V: Fix incorrect disassembly for addiw Michael Clark
@ 2018-03-31 7:33 ` no-reply
2 siblings, 0 replies; 7+ messages in thread
From: no-reply @ 2018-03-31 7:33 UTC (permalink / raw)
To: mjc; +Cc: famz, qemu-devel, peter.maydell, patches, palmer, sagark, kbastian
Hi,
This series failed docker-build@min-glib build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
Type: series
Message-id: 1522180547-22956-1-git-send-email-mjc@sifive.com
Subject: [Qemu-devel] [PATCH v1 0/2] RISC-V: Important fixes for QEMU 2.12
=== TEST SCRIPT BEGIN ===
#!/bin/bash
set -e
git submodule update --init dtc
# Let docker tests dump environment info
export SHOW_ENV=1
export J=8
time make docker-test-build@min-glib
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
a344370d6f RISC-V: Fix incorrect disassembly for addiw
bd710df094 RISC-V: Convert cpu definition to future model
=== OUTPUT BEGIN ===
Submodule 'dtc' (git://git.qemu-project.org/dtc.git) registered for path 'dtc'
Cloning into '/var/tmp/patchew-tester-tmp-67j32joq/src/dtc'...
Submodule path 'dtc': checked out 'e54388015af1fb4bf04d0bca99caba1074d9cc42'
BUILD min-glib
make[1]: Entering directory '/var/tmp/patchew-tester-tmp-67j32joq/src'
GEN /var/tmp/patchew-tester-tmp-67j32joq/src/docker-src.2018-03-31-03.33.27.19434/qemu.tar
Cloning into '/var/tmp/patchew-tester-tmp-67j32joq/src/docker-src.2018-03-31-03.33.27.19434/qemu.tar.vroot'...
done.
Checking out files: 41% (2529/6066)
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Checking out files: 100% (6066/6066), done.
Your branch is up-to-date with 'origin/test'.
Submodule 'dtc' (git://git.qemu-project.org/dtc.git) registered for path 'dtc'
Cloning into '/var/tmp/patchew-tester-tmp-67j32joq/src/docker-src.2018-03-31-03.33.27.19434/qemu.tar.vroot/dtc'...
Submodule path 'dtc': checked out 'e54388015af1fb4bf04d0bca99caba1074d9cc42'
Submodule 'ui/keycodemapdb' (git://git.qemu.org/keycodemapdb.git) registered for path 'ui/keycodemapdb'
Cloning into '/var/tmp/patchew-tester-tmp-67j32joq/src/docker-src.2018-03-31-03.33.27.19434/qemu.tar.vroot/ui/keycodemapdb'...
Submodule path 'ui/keycodemapdb': checked out '6b3d716e2b6472eb7189d3220552280ef3d832ce'
tar: /var/tmp/patchew-tester-tmp-67j32joq/src/docker-src.2018-03-31-03.33.27.19434/qemu.tar: Wrote only 4096 of 10240 bytes
tar: Error is not recoverable: exiting now
failed to create tar file
COPY RUNNER
RUN test-build in qemu:min-glib
tar: Unexpected EOF in archive
tar: Unexpected EOF in archive
tar: Error is not recoverable: exiting now
/var/tmp/qemu/run: line 32: prep_fail: command not found
Environment variables:
HOSTNAME=244a59dbb6c9
MAKEFLAGS= -j8
J=8
CCACHE_DIR=/var/tmp/ccache
EXTRA_CONFIGURE_OPTS=
V=
SHOW_ENV=1
PATH=/usr/lib/ccache:/usr/lib64/ccache:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin
PWD=/
TARGET_LIST=
SHLVL=1
HOME=/root
TEST_DIR=/tmp/qemu-test
FEATURES= dtc
DEBUG=
_=/usr/bin/env
/var/tmp/qemu/run: line 52: cd: /tmp/qemu-test/src/tests/docker: No such file or directory
/var/tmp/qemu/run: line 57: /test-build: No such file or directory
/var/tmp/qemu/run: line 57: exec: /test-build: cannot execute: No such file or directory
Traceback (most recent call last):
File "./tests/docker/docker.py", line 407, in <module>
sys.exit(main())
File "./tests/docker/docker.py", line 404, in main
return args.cmdobj.run(args, argv)
File "./tests/docker/docker.py", line 261, in run
return Docker().run(argv, args.keep, quiet=args.quiet)
File "./tests/docker/docker.py", line 229, in run
quiet=quiet)
File "./tests/docker/docker.py", line 147, in _do_check
return subprocess.check_call(self._command + cmd, **kwargs)
File "/usr/lib64/python2.7/subprocess.py", line 186, in check_call
raise CalledProcessError(retcode, cmd)
subprocess.CalledProcessError: Command '['docker', 'run', '--label', 'com.qemu.instance.uuid=d9be002a34b511e891df52540069c830', '-u', '0', '--security-opt', 'seccomp=unconfined', '--rm', '--net=none', '-e', 'TARGET_LIST=', '-e', 'EXTRA_CONFIGURE_OPTS=', '-e', 'V=', '-e', 'J=8', '-e', 'DEBUG=', '-e', 'SHOW_ENV=1', '-e', 'CCACHE_DIR=/var/tmp/ccache', '-v', '/root/.cache/qemu-docker-ccache:/var/tmp/ccache:z', '-v', '/var/tmp/patchew-tester-tmp-67j32joq/src/docker-src.2018-03-31-03.33.27.19434:/var/tmp/qemu:z,ro', 'qemu:min-glib', '/var/tmp/qemu/run', 'test-build']' returned non-zero exit status 126
make[1]: *** [tests/docker/Makefile.include:129: docker-run] Error 1
make[1]: Leaving directory '/var/tmp/patchew-tester-tmp-67j32joq/src'
make: *** [tests/docker/Makefile.include:163: docker-run-test-build@min-glib] Error 2
real 0m34.239s
user 0m9.557s
sys 0m6.924s
=== OUTPUT END ===
Test command exited with code: 2
---
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Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2018-03-31 7:34 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-03-27 19:55 [Qemu-devel] [PATCH v1 0/2] RISC-V: Important fixes for QEMU 2.12 Michael Clark
2018-03-27 19:55 ` [Qemu-devel] [PATCH v1 1/2] RISC-V: Convert cpu definition to future model Michael Clark
2018-03-28 4:38 ` Richard Henderson
2018-03-27 19:55 ` [Qemu-devel] [PATCH v1 2/2] RISC-V: Fix incorrect disassembly for addiw Michael Clark
2018-03-27 22:15 ` Philippe Mathieu-Daudé
2018-03-28 4:40 ` Richard Henderson
2018-03-31 7:33 ` [Qemu-devel] [PATCH v1 0/2] RISC-V: Important fixes for QEMU 2.12 no-reply
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