From: Abel Vesa <abel.vesa@nxp.com> To: Shawn Guo <shawnguo@kernel.org>, Sascha Hauer <kernel@pengutronix.de>, Fabio Estevam <fabio.estevam@nxp.com>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Peter Chen <peter.chen@freescale.com>, Irina Tirdea <irina.tirdea@nxp.com> Cc: linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-imx@nxp.com, Anson Huang <anson.huang@nxp.com>, Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>, Abel Vesa <abelvesa@linux.com>, Daniel Baluta <daniel.baluta@nxp.com>, Anson Huang <b20788@freescale.com>, Abel Vesa <abel.vesa@nxp.com> Subject: [RESEND 2/4] clk: imx7d: Correct dram pll type Date: Wed, 28 Mar 2018 09:46:37 +0300 [thread overview] Message-ID: <1522219599-10831-4-git-send-email-abel.vesa@nxp.com> (raw) In-Reply-To: <1522219599-10831-1-git-send-email-abel.vesa@nxp.com> From: Anson Huang <b20788@freescale.com> DRAM PLL is a audio/video type PLL, need to correct it to get correct ops of PLL. There is a test_div placed before DRAM PLL's gate, so add this test div clk. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Irina Tirdea <irina.tirdea@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com> --- drivers/clk/imx/clk-imx7d.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c index 39d110b..1cc485f 100644 --- a/drivers/clk/imx/clk-imx7d.c +++ b/drivers/clk/imx/clk-imx7d.c @@ -441,11 +441,13 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node) clk_set_parent(clks[IMX7D_PLL_VIDEO_MAIN_BYPASS], clks[IMX7D_PLL_VIDEO_MAIN]); clks[IMX7D_PLL_ARM_MAIN_CLK] = imx_clk_gate("pll_arm_main_clk", "pll_arm_main_bypass", base + 0x60, 13); - clks[IMX7D_PLL_DRAM_MAIN_CLK] = imx_clk_gate("pll_dram_main_clk", "pll_dram_main_bypass", base + 0x70, 13); + clks[IMX7D_PLL_DRAM_MAIN_CLK] = imx_clk_gate("pll_dram_main_clk", "pll_dram_test_div", base + 0x70, 13); clks[IMX7D_PLL_SYS_MAIN_CLK] = imx_clk_gate("pll_sys_main_clk", "pll_sys_main_bypass", base + 0xb0, 13); clks[IMX7D_PLL_AUDIO_MAIN_CLK] = imx_clk_gate("pll_audio_main_clk", "pll_audio_main_bypass", base + 0xf0, 13); clks[IMX7D_PLL_VIDEO_MAIN_CLK] = imx_clk_gate("pll_video_main_clk", "pll_video_main_bypass", base + 0x130, 13); + clks[IMX7D_PLL_DRAM_TEST_DIV] = clk_register_divider_table(NULL, "pll_dram_test_div", "pll_dram_main_bypass", + CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x70, 21, 2, 0, test_div_table, &imx_ccm_lock); clks[IMX7D_PLL_AUDIO_TEST_DIV] = clk_register_divider_table(NULL, "pll_audio_test_div", "pll_audio_main_clk", CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xf0, 19, 2, 0, test_div_table, &imx_ccm_lock); clks[IMX7D_PLL_AUDIO_POST_DIV] = clk_register_divider_table(NULL, "pll_audio_post_div", "pll_audio_test_div", -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: abel.vesa@nxp.com (Abel Vesa) To: linux-arm-kernel@lists.infradead.org Subject: [RESEND 2/4] clk: imx7d: Correct dram pll type Date: Wed, 28 Mar 2018 09:46:37 +0300 [thread overview] Message-ID: <1522219599-10831-4-git-send-email-abel.vesa@nxp.com> (raw) In-Reply-To: <1522219599-10831-1-git-send-email-abel.vesa@nxp.com> From: Anson Huang <b20788@freescale.com> DRAM PLL is a audio/video type PLL, need to correct it to get correct ops of PLL. There is a test_div placed before DRAM PLL's gate, so add this test div clk. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Irina Tirdea <irina.tirdea@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com> --- drivers/clk/imx/clk-imx7d.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c index 39d110b..1cc485f 100644 --- a/drivers/clk/imx/clk-imx7d.c +++ b/drivers/clk/imx/clk-imx7d.c @@ -441,11 +441,13 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node) clk_set_parent(clks[IMX7D_PLL_VIDEO_MAIN_BYPASS], clks[IMX7D_PLL_VIDEO_MAIN]); clks[IMX7D_PLL_ARM_MAIN_CLK] = imx_clk_gate("pll_arm_main_clk", "pll_arm_main_bypass", base + 0x60, 13); - clks[IMX7D_PLL_DRAM_MAIN_CLK] = imx_clk_gate("pll_dram_main_clk", "pll_dram_main_bypass", base + 0x70, 13); + clks[IMX7D_PLL_DRAM_MAIN_CLK] = imx_clk_gate("pll_dram_main_clk", "pll_dram_test_div", base + 0x70, 13); clks[IMX7D_PLL_SYS_MAIN_CLK] = imx_clk_gate("pll_sys_main_clk", "pll_sys_main_bypass", base + 0xb0, 13); clks[IMX7D_PLL_AUDIO_MAIN_CLK] = imx_clk_gate("pll_audio_main_clk", "pll_audio_main_bypass", base + 0xf0, 13); clks[IMX7D_PLL_VIDEO_MAIN_CLK] = imx_clk_gate("pll_video_main_clk", "pll_video_main_bypass", base + 0x130, 13); + clks[IMX7D_PLL_DRAM_TEST_DIV] = clk_register_divider_table(NULL, "pll_dram_test_div", "pll_dram_main_bypass", + CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x70, 21, 2, 0, test_div_table, &imx_ccm_lock); clks[IMX7D_PLL_AUDIO_TEST_DIV] = clk_register_divider_table(NULL, "pll_audio_test_div", "pll_audio_main_clk", CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xf0, 19, 2, 0, test_div_table, &imx_ccm_lock); clks[IMX7D_PLL_AUDIO_POST_DIV] = clk_register_divider_table(NULL, "pll_audio_post_div", "pll_audio_test_div", -- 2.7.4
next prev parent reply other threads:[~2018-03-28 6:47 UTC|newest] Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-03-28 6:46 [RESEND 0/4] Update imx7 clocks Abel Vesa 2018-03-28 6:46 ` Abel Vesa 2018-03-28 6:46 ` [RESEND 1/4] clk: imx7d: Add USB clock information Abel Vesa 2018-03-28 6:46 ` Abel Vesa 2018-04-06 18:20 ` Stephen Boyd 2018-04-06 18:20 ` Stephen Boyd 2018-04-06 18:20 ` Stephen Boyd 2018-03-28 6:46 ` [PATCH] clk: imx7d: Move clks_init_on before any clock operations Abel Vesa 2018-03-28 6:46 ` Abel Vesa 2018-03-28 6:51 ` Abel Vesa 2018-03-28 6:51 ` Abel Vesa 2018-03-28 6:51 ` Abel Vesa 2018-03-28 6:46 ` Abel Vesa [this message] 2018-03-28 6:46 ` [RESEND 2/4] clk: imx7d: Correct dram pll type Abel Vesa 2018-04-06 18:20 ` Stephen Boyd 2018-04-06 18:20 ` Stephen Boyd 2018-04-06 18:20 ` Stephen Boyd 2018-03-28 6:46 ` [RESEND 3/4] clk: imx7d: Correct ahb clk parent select Abel Vesa 2018-03-28 6:46 ` Abel Vesa 2018-04-06 18:20 ` Stephen Boyd 2018-04-06 18:20 ` Stephen Boyd 2018-04-06 18:20 ` Stephen Boyd 2018-03-28 6:46 ` [RESEND 4/4] clk: imx7d: Move clks_init_on before any clock operations Abel Vesa 2018-03-28 6:46 ` Abel Vesa 2018-04-06 18:20 ` Stephen Boyd 2018-04-06 18:20 ` Stephen Boyd 2018-04-06 18:20 ` Stephen Boyd
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