[PATCH v12 00/17] Add support for GuC-based SLPC

[PATCH v12 00/17] Add support for GuC-based SLPC

[Sagar Arun Kamble]

SLPC (Single Loop Power Controller) is a replacement for some host-based
power management features. The SLPC implementation runs in GuC firmware.
This series has been tested with SKL/APL/KBL GuC firmware v9 and v10.

The graphics power management features in SLPC are called GTPERF, BALANCER
and DCC.
	1. GTPERF: Combination of DFPS (Dynamic FPS) and Turbo. DFPS
	   adjusts requested graphics frequency to maintain target
	   framerate. Turbo adjusts requested graphics frequency to
	   maintain target GT busyness.
	2. BALANCER: Adjusts balance between power budgets for IA and GT
	   in power limited scenarios.
	3. DCC (Duty Cycle Control): Adjusts requested graphics frequency
	   and stalls guc-scheduler to maintain actual graphics frequency
	   in efficient range.

This series activates GTPERF Turbo and BALANCER in GuC SLPC. In order to
enable CI/PnP testing of SLPC and to avoid frequent rebase, this series
should be safe for merge with GuC in disabled state by default currently.

v2: Addressed review comments on v1. Removed patch to enable SLPC by
    default.

v3: Addressed WARNING in igt@drv_module_reload_basic flagged by trybot.
    Added change for sanitizing GT PM during reset. Added separate patch
    for sysfs interface to know HW requested frequency.

v4: Changes to multiple patches. CI BAT is passing. Performance run on SKL
    GT2 done and shows perf at parity with Host Turbo. For BXT, SLPC
    improves performance when GuC is enabled compared to Host Turbo.
    This series keeps only support of 9.18 firmware for readability.
    If needed, other SLPC interfaces for different GuC version will be
    added later.

v5: This series incorporates feedback from code reviews on earlier series
    and adds following new changes:
	1. More changes for separation of RPS and RC6 handling for Gen9.
	2. Tied up SLPC enabling with GuC load/GuC submission sequence.
	3. SLPC structures are defined explicitly for event input/output.
	4. Definition of SLPC parameter control and task control functions
	   agnostic to the underlying param definitions as they might
	   change with GuC versions and prepared helpers for common tasks.
	5. Transition of i915 overrides done through host to guc events
	   to shared data and single reset event.
	6. Handling SLPC status post reset through shared memory.
	7. Derived helpers for setting frequency limits.
	8. Removed sysfs interface to know RPNSWREQ as it is available in
	   debugfs interface i915_frequency_info.
	9. Simple igt test to verify SLPC configuration by i915 in various
	   driver scenarios is prepared.

v6: This series adds following new changes:
	1. Updated intel_guc_send for SLPC to receive output data from GuC.
	2. Added task overrides and min frequency overrides in slpc_init.
	   min frequency is set to Rpe.
	3. New debugfs interface added to set/unset/read SLPC parameters
	   other than tasks and frequencies. SLPC reset post parameter
	   update added.
	4. SLPC parameters persist as part of i915-GuC shared data hence
	   not overriding frequency limits while re-enabling SLPC.
	5. Other minor fixes to clear pm_rps_events, clflush the shared
	   data.

v7: This series adds following new changes:
	1. Reordered patches. SLPC communication interfaces (structures
	   and functions) are pulled into patches earlier in the series.
	2. Eliminated dependency on i915.enable_slpc at various functions
	   where rps_enabled is available.
	3. s/i915_ggtt_offset/guc_ggtt_offset and sanitization of params
	   in intel_uc_sanitize_options.

v8: Activated Balancer. Changed prototype of SLPC functions to accept
    struct intel_slpc as parameter instead of drm_i915_private.

v9: Separated RPS, RC6 and Ring frequency configuration for gen6+.
    Added TDR specific handling of SLPC reset. Some more improvements for
    support of function pointers for rps busy, idle, boost functions.
    This series is based on GuC code restructuring and fixes series at
    https://patchwork.freedesktop.org/series/30351/.

v10-11: Rebase.

v12: 1. Rebase. Changed SLPC H2G w.r.t new CTB changes.
     2. Removed has_slpc, enable_guc_slpc modparam, GuC version sanitize
	and platform specific SLPC enabling patches as handling is
	changed. 

VIZ-6889, VIZ-6890

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Beuchat Marc <marc.beuchat@intel.com>
Cc: Wang Zhe1 <zhe1.wang@intel.com>
Cc: Sun Daisy <daisy.sun@intel.com>
Cc: Oscar Mateo <oscar.mateo@intel.com>
Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
Cc: Jeff McGee <jeff.mcgee@intel.com>
Tested-by: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>

Sagar Arun Kamble (12):
  drm/i915/guc/slpc: Disable host RPS
  drm/i915/guc/slpc: Lay out SLPC init/enable/disable/fini helpers
  drm/i915/guc/slpc: Add SLPC communication interfaces
  drm/i915/guc/slpc: Allocate/initialize/release SLPC shared data
  drm/i915/guc/slpc: Send RESET event to restart/enable SLPC tasks
  drm/i915/guc/slpc: Reset SLPC on engine reset with flag TDR_OCCURRED
  drm/i915/guc/slpc: Add parameter set/unset/get, task control/status
    functions
  drm/i915/guc/slpc: Add support for sysfs min/max frequency control
  drm/i915/debugfs: Create generic string tokenize function and update
    CRC control parsing
  drm/i915/guc/slpc: Add debugfs support to read/write/revert the
    parameters
  drm/i915/guc/slpc: Add SLPC banner to RPS debugfs interfaces
  HAX: drm/i915/guc: Enable GuC

Tom O'Rourke (5):
  drm/i915/guc/slpc: Add SLPC control to enable_guc modparam
  drm/i915/guc/slpc: Enable SLPC in GuC load control params
  drm/i915/guc/slpc: Send SHUTDOWN event to stop SLPC tasks
  drm/i915/guc/slpc: Add enable/disable controls for SLPC tasks
  drm/i915/guc/slpc: Add i915_guc_slpc_info to debugfs

 drivers/gpu/drm/i915/Makefile              |    1 +
 drivers/gpu/drm/i915/i915_debugfs.c        |  403 +++++++++++
 drivers/gpu/drm/i915/i915_drv.h            |    7 +
 drivers/gpu/drm/i915/i915_irq.c            |   21 +-
 drivers/gpu/drm/i915/i915_params.c         |    5 +-
 drivers/gpu/drm/i915/i915_params.h         |    3 +-
 drivers/gpu/drm/i915/i915_sysfs.c          |   57 +-
 drivers/gpu/drm/i915/intel_guc.c           |    3 +
 drivers/gpu/drm/i915/intel_guc.h           |    2 +
 drivers/gpu/drm/i915/intel_guc_slpc.c      | 1079 ++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_guc_slpc.h      |   54 ++
 drivers/gpu/drm/i915/intel_guc_slpc_fwif.h |  234 ++++++
 drivers/gpu/drm/i915/intel_pipe_crc.c      |   57 +-
 drivers/gpu/drm/i915/intel_pm.c            |   26 +-
 drivers/gpu/drm/i915/intel_uc.c            |   58 +-
 drivers/gpu/drm/i915/intel_uc.h            |    7 +
 16 files changed, 1946 insertions(+), 71 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_guc_slpc.c
 create mode 100644 drivers/gpu/drm/i915/intel_guc_slpc.h
 create mode 100644 drivers/gpu/drm/i915/intel_guc_slpc_fwif.h

-- 
2.7.4

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[PATCH v12 01/17] drm/i915/guc/slpc: Add SLPC control to enable_guc modparam

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

GuC is currently being used for submission and HuC authentication.
Choices can be configured through enable_guc modparam. GuC SLPC is GT
Power and Performance management feature in GuC. Add another option to
enable_guc modparam to control SLPC.

v1: Add early call to sanitize enable_guc_slpc in intel_guc_ucode_init
    Remove sanitize enable_guc_slpc call before firmware version check
    is performed. (ChrisW)
    Version check is added in next patch and that will be done as part
    of slpc_enable_sanitize function in the next patch. (Sagar) Updated
    slpc option sanitize function call for platforms without GuC support.
    This was caught by CI BAT.

v2: Changed parameter to dev_priv for HAS_SLPC macro. (David)
    Code indentation based on checkpatch.

v3: Rebase.

v4: Moved sanitization of SLPC option post GuC load.

v5: Removed function intel_slpc_enabled. Planning to rely only on kernel
    parameter. Moved sanitization prior to GuC load to use the parameter
    during SLPC state setup during to GuC load. (Sagar)

v6: Commit message update. Rebase.

v7: Moved SLPC option sanitization to intel_uc_sanitize_options.

v8: Clearing SLPC option on GuC load failure. Change moved from later
    patch. (Sagar)

v9: s/enable_slpc/enable_guc_slpc. Rebase w.r.t modparam change.

v10: Rebase. Separate modparam is not needed now that we maintain all
     options in single param enable_guc.

Suggested-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
Cc: Jeff McGee <jeff.mcgee@intel.com>
---
 drivers/gpu/drm/i915/i915_params.c |  5 +++--
 drivers/gpu/drm/i915/i915_params.h |  1 +
 drivers/gpu/drm/i915/intel_uc.c    | 23 +++++++++++++++++++----
 drivers/gpu/drm/i915/intel_uc.h    |  6 ++++++
 4 files changed, 29 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index 08108ce..40b799b 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -150,9 +150,10 @@ i915_param_named_unsafe(edp_vswing, int, 0400,
 	"2=default swing(400mV))");
 
 i915_param_named_unsafe(enable_guc, int, 0400,
-	"Enable GuC load for GuC submission and/or HuC load. "
+	"Enable GuC load for GuC submission and/or HuC load and/or GuC SLPC. "
 	"Required functionality can be selected using bitmask values. "
-	"(-1=auto, 0=disable [default], 1=GuC submission, 2=HuC load)");
+	"(-1=auto, 0=disable [default], 1=GuC submission, 2=HuC load, "
+	"4=GuC SLPC)");
 
 i915_param_named(guc_log_level, int, 0400,
 	"GuC firmware logging level. Requires GuC to be loaded. "
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index c963603..2484925 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -32,6 +32,7 @@ struct drm_printer;
 
 #define ENABLE_GUC_SUBMISSION		BIT(0)
 #define ENABLE_GUC_LOAD_HUC		BIT(1)
+#define ENABLE_GUC_SLPC			BIT(2)
 
 #define I915_PARAMS_FOR_EACH(param) \
 	param(char *, vbt_firmware, NULL) \
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 1cffaf7..0e4a97f 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -56,9 +56,15 @@ static int __get_platform_enable_guc(struct drm_i915_private *dev_priv)
 	struct intel_uc_fw *huc_fw = &dev_priv->huc.fw;
 	int enable_guc = 0;
 
-	/* Default is to enable GuC/HuC if we know their firmwares */
-	if (intel_uc_fw_is_selected(guc_fw))
+	/*
+	 * Default is to enable GuC submission/SLPC/HuC if we know their
+	 * firmwares
+	 */
+	if (intel_uc_fw_is_selected(guc_fw)) {
 		enable_guc |= ENABLE_GUC_SUBMISSION;
+		enable_guc |= ENABLE_GUC_SLPC;
+	}
+
 	if (intel_uc_fw_is_selected(huc_fw))
 		enable_guc |= ENABLE_GUC_LOAD_HUC;
 
@@ -110,10 +116,11 @@ static void sanitize_options_early(struct drm_i915_private *dev_priv)
 	if (i915_modparams.enable_guc < 0)
 		i915_modparams.enable_guc = __get_platform_enable_guc(dev_priv);
 
-	DRM_DEBUG_DRIVER("enable_guc=%d (submission:%s huc:%s)\n",
+	DRM_DEBUG_DRIVER("enable_guc=%d (submission:%s huc:%s slpc:%s)\n",
 			 i915_modparams.enable_guc,
 			 yesno(intel_uc_is_using_guc_submission()),
-			 yesno(intel_uc_is_using_huc()));
+			 yesno(intel_uc_is_using_huc()),
+			 yesno(intel_uc_is_using_guc_slpc()));
 
 	/* Verify GuC firmware availability */
 	if (intel_uc_is_using_guc() && !intel_uc_fw_is_selected(guc_fw)) {
@@ -123,6 +130,14 @@ static void sanitize_options_early(struct drm_i915_private *dev_priv)
 					      "no GuC firmware");
 	}
 
+	/* Verify GuC submission and SLPC dependency */
+	if (intel_uc_is_using_guc_slpc() &&
+	    !intel_uc_is_using_guc_submission()) {
+		DRM_WARN("Incompatible option detected: %s=%d, "
+			 "GuC SLPC enabled without enabling GuC submission!\n",
+			 "enable_guc", i915_modparams.enable_guc);
+	}
+
 	/* Verify HuC firmware availability */
 	if (intel_uc_is_using_huc() && !intel_uc_fw_is_selected(huc_fw)) {
 		DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index 25d73ad..76139d3 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -59,4 +59,10 @@ static inline bool intel_uc_is_using_huc(void)
 	return i915_modparams.enable_guc & ENABLE_GUC_LOAD_HUC;
 }
 
+static inline bool intel_uc_is_using_guc_slpc(void)
+{
+	GEM_BUG_ON(i915_modparams.enable_guc < 0);
+	return i915_modparams.enable_guc & ENABLE_GUC_SLPC;
+}
+
 #endif
-- 
2.7.4

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[PATCH v12 02/17] drm/i915/guc/slpc: Disable host RPS

[Sagar Arun Kamble]

On platforms with GuC SLPC enabled, we need to ensure Host RPS functions
don't update HW RPS state that will be controlled by GuC SLPC then.
Host RPS functions are now gated by either USES_GUC_SLPC() or rps->enabled
checks. If SLPC is enabled following functions will be bypassed
  1. gpu_ips_init
  2. intel_enable|disable_rps
  3. rps portion of sanitize_gt_powersave

gen6_rps_irq_handler, rps_work, gen6_set_rps should not get invoked hence
GEM_BUG_ON(USES_GUC_SLPC()) is added in those functions.
We continue to use the state setup by intel_init_gt_powersave as i915 will
be configuring min/max frequency limits.

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
Cc: Jeff McGee <jeff.mcgee@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h   |  1 +
 drivers/gpu/drm/i915/i915_irq.c   | 18 ++++++++++++------
 drivers/gpu/drm/i915/i915_sysfs.c |  5 +++--
 drivers/gpu/drm/i915/intel_pm.c   | 26 +++++++++++++++++++++++++-
 4 files changed, 41 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 800230b..5176801 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2599,6 +2599,7 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define USES_GUC(dev_priv)		intel_uc_is_using_guc()
 #define USES_GUC_SUBMISSION(dev_priv)	intel_uc_is_using_guc_submission()
 #define USES_HUC(dev_priv)		intel_uc_is_using_huc()
+#define USES_GUC_SLPC(dev_priv)		intel_uc_is_using_guc_slpc()
 
 #define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
 
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 27aee25..cc7dd85 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1192,6 +1192,8 @@ static void gen6_pm_rps_work(struct work_struct *work)
 	int new_delay, adj, min, max;
 	u32 pm_iir = 0;
 
+	GEM_BUG_ON(USES_GUC_SLPC(dev_priv));
+
 	spin_lock_irq(&dev_priv->irq_lock);
 	if (rps->interrupts_enabled) {
 		pm_iir = fetch_and_zero(&rps->pm_iir);
@@ -1742,6 +1744,8 @@ static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
 	struct intel_rps *rps = &dev_priv->gt_pm.rps;
 
 	if (pm_iir & dev_priv->pm_rps_events) {
+		GEM_BUG_ON(USES_GUC_SLPC(dev_priv));
+
 		spin_lock(&dev_priv->irq_lock);
 		gen6_mask_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
 		if (rps->interrupts_enabled) {
@@ -4256,12 +4260,14 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
 	if (HAS_GUC_SCHED(dev_priv))
 		dev_priv->pm_guc_events = GEN9_GUC_TO_HOST_INT_EVENT;
 
-	/* Let's track the enabled rps events */
-	if (IS_VALLEYVIEW(dev_priv))
-		/* WaGsvRC0ResidencyMethod:vlv */
-		dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED;
-	else
-		dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
+	if (!USES_GUC_SLPC(dev_priv)) {
+		/* Let's track the enabled rps events */
+		if (IS_VALLEYVIEW(dev_priv))
+			/* WaGsvRC0ResidencyMethod:vlv */
+			dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED;
+		else
+			dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
+	}
 
 	rps->pm_intrmsk_mbz = 0;
 
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index e5e6f6b..c3083fa 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -322,9 +322,10 @@ static ssize_t gt_boost_freq_mhz_store(struct device *kdev,
 		rps->boost_freq = val;
 		boost = atomic_read(&rps->num_waiters);
 	}
-	mutex_unlock(&dev_priv->pcu_lock);
-	if (boost)
+
+	if (boost && rps->enabled)
 		schedule_work(&rps->work);
+	mutex_unlock(&dev_priv->pcu_lock);
 
 	return count;
 }
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 19e82aa..51bc147e9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6215,6 +6215,8 @@ static int gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
 {
 	struct intel_rps *rps = &dev_priv->gt_pm.rps;
 
+	GEM_BUG_ON(USES_GUC_SLPC(dev_priv));
+
 	/* min/max delay may still have been modified so be sure to
 	 * write the limits value.
 	 */
@@ -6310,6 +6312,9 @@ void gen6_rps_busy(struct drm_i915_private *dev_priv)
 {
 	struct intel_rps *rps = &dev_priv->gt_pm.rps;
 
+	if (USES_GUC_SLPC(dev_priv))
+		return;
+
 	mutex_lock(&dev_priv->pcu_lock);
 	if (rps->enabled) {
 		u8 freq;
@@ -6340,6 +6345,9 @@ void gen6_rps_idle(struct drm_i915_private *dev_priv)
 {
 	struct intel_rps *rps = &dev_priv->gt_pm.rps;
 
+	if (USES_GUC_SLPC(dev_priv))
+		return;
+
 	/* Flush our bottom-half so that it does not race with us
 	 * setting the idle frequency and so that it is bounded by
 	 * our rpm wakeref. And then disable the interrupts to stop any
@@ -6367,6 +6375,9 @@ void gen6_rps_boost(struct i915_request *rq,
 	unsigned long flags;
 	bool boost;
 
+	if (USES_GUC_SLPC(dev_priv))
+		return;
+
 	/* This is intentionally racy! We peek at the state here, then
 	 * validate inside the RPS worker.
 	 */
@@ -7855,6 +7866,9 @@ ips_ping_for_i915_load(void)
 
 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
 {
+	if (USES_GUC_SLPC(dev_priv))
+		return;
+
 	/* We only register the i915 ips part with intel-ips once everything is
 	 * set up, to avoid intel-ips sneaking in and reading bogus values. */
 	spin_lock_irq(&mchdev_lock);
@@ -8024,10 +8038,14 @@ void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
 
 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
 {
-	dev_priv->gt_pm.rps.enabled = true; /* force RPS disabling */
+	if (!USES_GUC_SLPC(dev_priv))
+		dev_priv->gt_pm.rps.enabled = true; /* force RPS disabling */
 	dev_priv->gt_pm.rc6.enabled = true; /* force RC6 disabling */
 	intel_disable_gt_powersave(dev_priv);
 
+	if (USES_GUC_SLPC(dev_priv))
+		return;
+
 	if (INTEL_GEN(dev_priv) < 11)
 		gen6_reset_rps_interrupts(dev_priv);
 	else
@@ -8069,6 +8087,9 @@ static void intel_disable_rps(struct drm_i915_private *dev_priv)
 {
 	lockdep_assert_held(&dev_priv->pcu_lock);
 
+	if (USES_GUC_SLPC(dev_priv))
+		return;
+
 	if (!dev_priv->gt_pm.rps.enabled)
 		return;
 
@@ -8135,6 +8156,9 @@ static void intel_enable_rps(struct drm_i915_private *dev_priv)
 {
 	struct intel_rps *rps = &dev_priv->gt_pm.rps;
 
+	if (USES_GUC_SLPC(dev_priv))
+		return;
+
 	lockdep_assert_held(&dev_priv->pcu_lock);
 
 	if (rps->enabled)
-- 
2.7.4

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[PATCH v12 03/17] drm/i915/guc/slpc: Lay out SLPC init/enable/disable/fini helpers

[Sagar Arun Kamble]

SLPC operates based on parameters setup in shared data between i915 and
GuC SLPC. This is to be created/initialized in intel_guc_slpc_init. From
there onwards i915 can control the SLPC operations by enabling, disabling
complete SLPC or changing SLPC parameters. During cleanup, SLPC shared
data has to be freed.

v1: Return void instead of ignored error code. Replace HAS_SLPC() use with
    intel_slpc_enabled()/ intel_slpc_active() (Paulo)
    Enable/disable RC6 in SLPC flows (Sagar)
    Fix for renaming gen9_disable_rps to gen9_disable_rc6 in
    "drm/i915/bxt: Explicitly clear the Turbo control register"
    Defer RC6 and SLPC enabling to intel_gen6_powersave_work. (Sagar)
    Performance drop with SLPC was happening as ring frequency table was
    not programmed when SLPC was enabled. This patch programs ring
    frequency table with SLPC. Initial reset of SLPC is based on kernel
    parameter as planning to add slpc state in intel_slpc_active. Cleanup
    is also based on kernel parameter as SLPC gets disabled in
    disable/suspend.(Sagar)

v2: Usage of INTEL_GEN instead of INTEL_INFO->gen (David)
    Checkpatch update.

v3: Rebase

v4: Removed reset functions to comply with *_gt_powersave routines.
    (Sagar)

v5: Removed intel_slpc_active. Relying on slpc.active for control flows
    that are based on SLPC active status in GuC. State setup/cleanup needed
    for SLPC is handled using kernel parameter i915.enable_slpc. Moved SLPC
    init and enabling to GuC enable path as SLPC in GuC can start doing the
    setup post GuC init. Commit message update. (Sagar)

v6: Rearranged function definitions.

v7: Makefile rearrangement. Reducing usage of i915.enable_slpc and relying
    mostly on rps.rps_enabled to bypass Host RPS flows. Commit message
    update.

v8: Changed parameters for SLPC functions to struct intel_slpc*.

v9: Reinstated intel_slpc_active and intel_slpc_enabled as they are more
    meaningful.

v10: Rebase changes due to creation of intel_guc.h. Updates in
     intel_guc_cleanup w.r.t slpc cleanup.

v11: s/intel_slpc/intel_guc_slpc. Adjusted place for slpc struct inside
     guc struct. (Michal Wajdeczko)
     Updated comment about intel_slpc_enable as we plan to not defer the
     SLPC status check on enabling later and will have to wait for SLPC
     status as part of intel_slpc_enable itself.
     Prepared guc_slpc_initialized and guc_slpc_enabled to track state
     of SLPC initialization and enabling.

v12: s/guc_slpc_cleanup/guc_slpc_fini. Updated SLPC flows w.r.t uC flows.

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
Cc: Jeff McGee <jeff.mcgee@intel.com>
---
 drivers/gpu/drm/i915/Makefile         |  1 +
 drivers/gpu/drm/i915/intel_guc.h      |  2 ++
 drivers/gpu/drm/i915/intel_guc_slpc.c | 25 +++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_guc_slpc.h | 17 +++++++++++++++++
 drivers/gpu/drm/i915/intel_uc.c       | 30 +++++++++++++++++++++++++++++-
 5 files changed, 74 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/i915/intel_guc_slpc.c
 create mode 100644 drivers/gpu/drm/i915/intel_guc_slpc.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 0c79c19..499cb89 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -90,6 +90,7 @@ i915-y += intel_uc.o \
 	  intel_guc_ct.o \
 	  intel_guc_fw.o \
 	  intel_guc_log.o \
+	  intel_guc_slpc.o \
 	  intel_guc_submission.o \
 	  intel_huc.o \
 	  intel_huc_fw.o
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index f1265e1..2d2451a 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -31,6 +31,7 @@
 #include "intel_guc_ct.h"
 #include "intel_guc_log.h"
 #include "intel_guc_reg.h"
+#include "intel_guc_slpc.h"
 #include "intel_uc_fw.h"
 #include "i915_vma.h"
 
@@ -48,6 +49,7 @@ struct intel_guc {
 	struct intel_uc_fw fw;
 	struct intel_guc_log log;
 	struct intel_guc_ct ct;
+	struct intel_guc_slpc slpc;
 
 	/* Offset where Non-WOPCM memory starts. */
 	u32 ggtt_pin_bias;
diff --git a/drivers/gpu/drm/i915/intel_guc_slpc.c b/drivers/gpu/drm/i915/intel_guc_slpc.c
new file mode 100644
index 0000000..63f100c
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_guc_slpc.c
@@ -0,0 +1,25 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2015-2018 Intel Corporation
+ */
+
+#include "intel_guc_slpc.h"
+
+int intel_guc_slpc_init(struct intel_guc_slpc *slpc)
+{
+	return 0;
+}
+
+int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
+{
+	return 0;
+}
+
+void intel_guc_slpc_disable(struct intel_guc_slpc *slpc)
+{
+}
+
+void intel_guc_slpc_fini(struct intel_guc_slpc *slpc)
+{
+}
diff --git a/drivers/gpu/drm/i915/intel_guc_slpc.h b/drivers/gpu/drm/i915/intel_guc_slpc.h
new file mode 100644
index 0000000..66c76fe
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_guc_slpc.h
@@ -0,0 +1,17 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2015-2018 Intel Corporation
+ */
+#ifndef _INTEL_GUC_SLPC_H_
+#define _INTEL_GUC_SLPC_H_
+
+struct intel_guc_slpc {
+};
+
+int intel_guc_slpc_init(struct intel_guc_slpc *slpc);
+int intel_guc_slpc_enable(struct intel_guc_slpc *slpc);
+void intel_guc_slpc_disable(struct intel_guc_slpc *slpc);
+void intel_guc_slpc_fini(struct intel_guc_slpc *slpc);
+
+#endif
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 0e4a97f..5bf33c8 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -319,6 +319,15 @@ int intel_uc_init(struct drm_i915_private *dev_priv)
 		}
 	}
 
+	if (USES_GUC_SLPC(dev_priv)) {
+		ret = intel_guc_slpc_init(&guc->slpc);
+		if (ret) {
+			intel_guc_submission_fini(guc);
+			intel_guc_fini(guc);
+			return ret;
+		}
+	}
+
 	return 0;
 }
 
@@ -331,6 +340,9 @@ void intel_uc_fini(struct drm_i915_private *dev_priv)
 
 	GEM_BUG_ON(!HAS_GUC(dev_priv));
 
+	if (USES_GUC_SLPC(dev_priv))
+		intel_guc_slpc_fini(&guc->slpc);
+
 	if (USES_GUC_SUBMISSION(dev_priv))
 		intel_guc_submission_fini(guc);
 
@@ -413,10 +425,21 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
 			goto err_communication;
 	}
 
+	/*
+	 * SLPC is enabled by setting up the shared data structure and
+	 * sending reset event to GuC SLPC. Initial data is setup in
+	 * intel_guc_slpc_init. Here we send the reset event.
+	 */
+	if (USES_GUC_SLPC(dev_priv)) {
+		ret = intel_guc_slpc_enable(&guc->slpc);
+		if (ret)
+			goto err_communication;
+	}
+
 	if (USES_GUC_SUBMISSION(dev_priv)) {
 		ret = intel_guc_submission_enable(guc);
 		if (ret)
-			goto err_communication;
+			goto err_slpc;
 	}
 
 	dev_info(dev_priv->drm.dev, "GuC firmware version %u.%u\n",
@@ -431,6 +454,8 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
 	/*
 	 * We've failed to load the firmware :(
 	 */
+err_slpc:
+	intel_guc_slpc_disable(&guc->slpc);
 err_communication:
 	guc_disable_communication(guc);
 err_log_capture:
@@ -459,6 +484,9 @@ void intel_uc_fini_hw(struct drm_i915_private *dev_priv)
 	if (USES_GUC_SUBMISSION(dev_priv))
 		intel_guc_submission_disable(guc);
 
+	if (USES_GUC_SLPC(dev_priv))
+		intel_guc_slpc_disable(&guc->slpc);
+
 	guc_disable_communication(guc);
 }
 
-- 
2.7.4

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[PATCH v12 04/17] drm/i915/guc/slpc: Enable SLPC in GuC load control params

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

If SLPC is to enabled, then set GUC_CTL_ENABLE_SLPC flag in GuC control
param GUC_CTL_FEATURE word during GuC load. This is required for early
SLPC init in GuC init path. SLPC gets enabled fully on sending this flag
during GuC load and on doing SLPC reset through Host to GuC action.

v1: Use intel_slpc_enabled() (Paulo)

v2-v4: Rebase.

v5: Changed intel_slpc_enabled() to i915.enable_slpc. (Sagar)

v6: Changed i915.enable_slpc to intel_slpc_enabled(). (Sagar)

v7: Rebase.

v8: Rebase.

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
Cc: Jeff McGee <jeff.mcgee@intel.com>
---
 drivers/gpu/drm/i915/intel_guc.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index a00a59a..c8d3ffb 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -272,6 +272,9 @@ void intel_guc_init_params(struct intel_guc *guc)
 	params[GUC_CTL_FEATURE] |= GUC_CTL_DISABLE_SCHEDULER |
 			GUC_CTL_VCS2_ENABLED;
 
+	if (USES_GUC_SLPC(dev_priv))
+		params[GUC_CTL_FEATURE] |= GUC_CTL_ENABLE_SLPC;
+
 	params[GUC_CTL_LOG_PARAMS] = guc->log.flags;
 
 	params[GUC_CTL_DEBUG] = get_log_control_flags();
-- 
2.7.4

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[PATCH v12 05/17] drm/i915/guc/slpc: Add SLPC communication interfaces

[Sagar Arun Kamble]

Communication with SLPC is via Host to GuC interrupt through shared data
and parameters. This patch defines the structure of shared data,
parameters, data structure to be passed as input and received as output
from SLPC. This patch also defines the events to be sent as input and
status values output by GuC on processing SLPC events.
SLPC shared data has details of SKU type, Slice count, IA Perf MSR values,
SLPC state, Power source/plan, SLPC tasks status. Parameters allow
overriding task control, frequency range etc.

v1: fix whitespace (Sagar)

v2-v3: Rebase.

v4: Updated with GuC firmware v9.

v5: Added definition of input and output data structures for SLPC
    events. Updated commit message.

v6: Removed definition of host2guc_slpc. Will be added in the next
    patch that uses it. Commit subject update. Rebase.

v7: Added definition of SLPC_RESET_FLAG_TDR_OCCURRED to be sent
    throgh SLPC reset in case of engine reset. Moved all Host/SLPC
    interfaces from later patches to this patch. Commit message update.

v8: Updated value of SLPC_RESET_FLAG_TDR_OCCURRED.

v9: Removed struct slpc_param, slpc_paramlist and corresponding defines.
    Will be added in later patches where they are used.

v10: Rebase. Prepared separate header for SLPC firmware interface.

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
Cc: Jeff McGee <jeff.mcgee@intel.com>
---
 drivers/gpu/drm/i915/intel_guc_slpc.h      |   2 +
 drivers/gpu/drm/i915/intel_guc_slpc_fwif.h | 211 +++++++++++++++++++++++++++++
 2 files changed, 213 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/intel_guc_slpc_fwif.h

diff --git a/drivers/gpu/drm/i915/intel_guc_slpc.h b/drivers/gpu/drm/i915/intel_guc_slpc.h
index 66c76fe..81250c0 100644
--- a/drivers/gpu/drm/i915/intel_guc_slpc.h
+++ b/drivers/gpu/drm/i915/intel_guc_slpc.h
@@ -6,6 +6,8 @@
 #ifndef _INTEL_GUC_SLPC_H_
 #define _INTEL_GUC_SLPC_H_
 
+#include <intel_guc_slpc_fwif.h>
+
 struct intel_guc_slpc {
 };
 
diff --git a/drivers/gpu/drm/i915/intel_guc_slpc_fwif.h b/drivers/gpu/drm/i915/intel_guc_slpc_fwif.h
new file mode 100644
index 0000000..9400af4
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_guc_slpc_fwif.h
@@ -0,0 +1,211 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2015-2018 Intel Corporation
+ */
+#ifndef _INTEL_GUC_SLPC_FWIF_H_
+#define _INTEL_GUC_SLPC_FWIF_H_
+
+#include <linux/types.h>
+
+enum slpc_status {
+	SLPC_STATUS_OK = 0,
+	SLPC_STATUS_ERROR = 1,
+	SLPC_STATUS_ILLEGAL_COMMAND = 2,
+	SLPC_STATUS_INVALID_ARGS = 3,
+	SLPC_STATUS_INVALID_PARAMS = 4,
+	SLPC_STATUS_INVALID_DATA = 5,
+	SLPC_STATUS_OUT_OF_RANGE = 6,
+	SLPC_STATUS_NOT_SUPPORTED = 7,
+	SLPC_STATUS_NOT_IMPLEMENTED = 8,
+	SLPC_STATUS_NO_DATA = 9,
+	SLPC_STATUS_EVENT_NOT_REGISTERED = 10,
+	SLPC_STATUS_REGISTER_LOCKED = 11,
+	SLPC_STATUS_TEMPORARILY_UNAVAILABLE = 12,
+	SLPC_STATUS_VALUE_ALREADY_SET = 13,
+	SLPC_STATUS_VALUE_ALREADY_UNSET = 14,
+	SLPC_STATUS_VALUE_NOT_CHANGED = 15,
+	SLPC_STATUS_MEMIO_ERROR = 16,
+	SLPC_STATUS_EVENT_QUEUED_REQ_DPC = 17,
+	SLPC_STATUS_EVENT_QUEUED_NOREQ_DPC = 18,
+	SLPC_STATUS_NO_EVENT_QUEUED = 19,
+	SLPC_STATUS_OUT_OF_SPACE = 20,
+	SLPC_STATUS_TIMEOUT = 21,
+	SLPC_STATUS_NO_LOCK = 22,
+	SLPC_STATUS_MAX
+};
+
+enum slpc_event_id {
+	SLPC_EVENT_RESET = 0,
+	SLPC_EVENT_SHUTDOWN = 1,
+	SLPC_EVENT_PLATFORM_INFO_CHANGE = 2,
+	SLPC_EVENT_DISPLAY_MODE_CHANGE = 3,
+	SLPC_EVENT_FLIP_COMPLETE = 4,
+	SLPC_EVENT_QUERY_TASK_STATE = 5,
+	SLPC_EVENT_PARAMETER_SET = 6,
+	SLPC_EVENT_PARAMETER_UNSET = 7,
+};
+
+enum slpc_param_id {
+	SLPC_PARAM_TASK_ENABLE_GTPERF = 0,
+	SLPC_PARAM_TASK_DISABLE_GTPERF = 1,
+	SLPC_PARAM_TASK_ENABLE_BALANCER = 2,
+	SLPC_PARAM_TASK_DISABLE_BALANCER = 3,
+	SLPC_PARAM_TASK_ENABLE_DCC = 4,
+	SLPC_PARAM_TASK_DISABLE_DCC = 5,
+	SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ = 6,
+	SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ = 7,
+	SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ = 8,
+	SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ = 9,
+	SLPC_PARAM_GTPERF_THRESHOLD_MAX_FPS = 10,
+	SLPC_PARAM_GLOBAL_DISABLE_GT_FREQ_MANAGEMENT = 11,
+	SLPC_PARAM_GTPERF_ENABLE_FRAMERATE_STALLING = 12,
+	SLPC_PARAM_GLOBAL_DISABLE_RC6_MODE_CHANGE = 13,
+	SLPC_PARAM_GLOBAL_OC_UNSLICE_FREQ_MHZ = 14,
+	SLPC_PARAM_GLOBAL_OC_SLICE_FREQ_MHZ = 15,
+	SLPC_PARAM_GLOBAL_ENABLE_IA_GT_BALANCING = 16,
+	SLPC_PARAM_GLOBAL_ENABLE_ADAPTIVE_BURST_TURBO = 17,
+	SLPC_PARAM_GLOBAL_ENABLE_EVAL_MODE = 18,
+	SLPC_PARAM_GLOBAL_ENABLE_BALANCER_IN_NON_GAMING_MODE = 19,
+	SLPC_MAX_PARAM,
+	SLPC_KMD_MAX_PARAM = 32,
+};
+
+enum slpc_global_state {
+	SLPC_GLOBAL_STATE_NOT_RUNNING = 0,
+	SLPC_GLOBAL_STATE_INITIALIZING = 1,
+	SLPC_GLOBAL_STATE_RESETTING = 2,
+	SLPC_GLOBAL_STATE_RUNNING = 3,
+	SLPC_GLOBAL_STATE_SHUTTING_DOWN = 4,
+	SLPC_GLOBAL_STATE_ERROR = 5
+};
+
+enum slpc_platform_sku {
+	SLPC_PLATFORM_SKU_UNDEFINED = 0,
+	SLPC_PLATFORM_SKU_ULX = 1,
+	SLPC_PLATFORM_SKU_ULT = 2,
+	SLPC_PLATFORM_SKU_T = 3,
+	SLPC_PLATFORM_SKU_MOBL = 4,
+	SLPC_PLATFORM_SKU_DT = 5,
+	SLPC_PLATFORM_SKU_UNKNOWN = 6,
+};
+
+enum slpc_power_source {
+	SLPC_POWER_SOURCE_UNDEFINED = 0,
+	SLPC_POWER_SOURCE_AC = 1,
+	SLPC_POWER_SOURCE_DC = 2,
+	SLPC_POWER_SOURCE_UNKNOWN = 3,
+};
+
+enum slpc_power_plan {
+	SLPC_POWER_PLAN_UNDEFINED = 0,
+	SLPC_POWER_PLAN_BATTERY_SAVER = 1,
+	SLPC_POWER_PLAN_BALANCED = 2,
+	SLPC_POWER_PLAN_PERFORMANCE = 3,
+	SLPC_POWER_PLAN_UNKNOWN = 4,
+};
+
+struct slpc_platform_info {
+	u8 sku;
+	u8 slice_count;
+	u8 reserved;
+	u8 power_plan_source;
+	u8 p0_freq;
+	u8 p1_freq;
+	u8 pe_freq;
+	u8 pn_freq;
+	u32 reserved1;
+	u32 reserved2;
+} __packed;
+
+struct slpc_task_state_data {
+	union {
+		u32 bitfield1;
+		struct {
+			u32 gtperf_task_active:1;
+			u32 gtperf_stall_possible:1;
+			u32 gtperf_gaming_mode:1;
+			u32 gtperf_target_fps:8;
+			u32 dcc_task_active:1;
+			u32 in_dcc:1;
+			u32 in_dct:1;
+			u32 freq_switch_active:1;
+			u32 ibc_enabled:1;
+			u32 ibc_active:1;
+			u32 pg1_enabled:1;
+			u32 pg1_active:1;
+			u32 reserved:13;
+		};
+	};
+	union {
+		u32 bitfield2;
+		struct {
+			u32 max_unslice_freq:8;
+			u32 min_unslice_freq:8;
+			u32 max_slice_freq:8;
+			u32 min_slice_freq:8;
+		};
+	};
+} __packed;
+
+#define SLPC_MAX_OVERRIDE_PARAMETERS 192
+#define SLPC_OVERRIDE_BITFIELD_SIZE \
+		((SLPC_MAX_OVERRIDE_PARAMETERS + 31) / 32)
+
+struct slpc_shared_data {
+	u32 reserved;
+	u32 shared_data_size;
+	u32 global_state;
+	struct slpc_platform_info platform_info;
+	struct slpc_task_state_data task_state_data;
+	u32 override_params_set_bits[SLPC_OVERRIDE_BITFIELD_SIZE];
+	u32 override_params_values[SLPC_MAX_OVERRIDE_PARAMETERS];
+} __packed;
+
+enum slpc_reset_flags {
+	SLPC_RESET_FLAG_TDR_OCCURRED = (1 << 0)
+};
+
+#define SLPC_EVENT_MAX_INPUT_ARGS  7
+#define SLPC_EVENT_MAX_OUTPUT_ARGS 1
+
+union slpc_event_input_header {
+	u32 value;
+	struct {
+		u32 num_args:8;
+		u32 event_id:8;
+	};
+};
+
+struct slpc_event_input {
+	u32 h2g_action_id;
+	union slpc_event_input_header header;
+	u32 args[SLPC_EVENT_MAX_INPUT_ARGS];
+} __packed;
+
+union slpc_event_output_header {
+	u32 value;
+	struct {
+		u32 num_args:8;
+		u32 event_id:8;
+		u32 status:16;
+	};
+};
+
+struct slpc_event_output {
+	u32 reserved;
+	union slpc_event_output_header header;
+	u32 args[SLPC_EVENT_MAX_OUTPUT_ARGS];
+} __packed;
+
+#define SLPC_EVENT(id, argc)		 ((u32)(id) << 8 | (argc))
+#define SLPC_POWER_PLAN_SOURCE(plan, source) ((plan) | ((source) << 6))
+#define SLPC_POWER_PLAN(plan_source)	 ((plan_source) & 0x3F)
+#define SLPC_POWER_SOURCE(plan_source)	 ((plan_source) >> 6)
+
+#define SLPC_PARAM_TASK_DEFAULT  0
+#define SLPC_PARAM_TASK_ENABLED  1
+#define SLPC_PARAM_TASK_DISABLED 2
+#define SLPC_PARAM_TASK_UNKNOWN  3
+
+#endif
-- 
2.7.4

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[PATCH v12 06/17] drm/i915/guc/slpc: Allocate/initialize/release SLPC shared data

[Sagar Arun Kamble]

Populate SLPC shared data with required default values for slice count,
power source/plan, IA perf MSRs.

v1: Update for SLPC interface version 2015.2.4. intel_slpc_active()
    returns 1 if slpc initialized (Paulo)
    change default host_os to "Windows"
    Spelling fixes (Sagar and Nick Hoath). Added WARN for checking if
    upper 32bits of GTT offset of shared object are zero. (Chris)
    Updated commit message and moved POWER_PLAN and POWER_SOURCE defn.
    from later patch. (Akash)
    Add struct_mutex locking while allocating/releasing slpc shared
    object. This was caught by CI BAT. Adding SLPC state variable to
    determine if it is active as it not just dependent on shared data
    setup. Rebase with guc_allocate_vma related changes.

v2: WARN_ON for platform_sku validity and space changes.(David)
    Checkpatch update.

v3: Fixing WARNING in igt@drv_module_reload_basic found in trybot BAT
    with SLPC Enabled.

v4: Updated support for GuC v9. s/slice_total/hweight8(slice_mask)/(Dave).

v5: SLPC vma map changes and removed explicit type conversions.(Chris).
    s/freq_unslice_max|min/unslice__max|min_freq.

v6: Commit message update. s/msr_value/val for reuse later.

v7: Set default values for tasks and min frequency parameters. Moved init
    with allocation of data so that post GuC load earlier params persist.

v8: Added check for SLPC status during cleanup of shared data. SLPC
    disabling is asynchronous and should complete within 10us.

v9: Enabling Balancer task in SLPC.

v10: Rebase.

v11: Rebase. Added lock specific to SLPC.

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
Cc: Jeff McGee <jeff.mcgee@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h       |   5 +
 drivers/gpu/drm/i915/intel_guc_slpc.c | 204 ++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_guc_slpc.h |   3 +
 3 files changed, 212 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5176801..d17e778 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2416,6 +2416,11 @@ intel_info(const struct drm_i915_private *dev_priv)
 
 #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
 
+#define IS_ULX_SKU(dev_priv)	(IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv))
+#define IS_ULT_SKU(dev_priv)	(IS_SKL_ULT(dev_priv) || \
+				 IS_KBL_ULT(dev_priv) || \
+				 IS_CFL_ULT(dev_priv))
+
 #define SKL_REVID_A0		0x0
 #define SKL_REVID_B0		0x1
 #define SKL_REVID_C0		0x2
diff --git a/drivers/gpu/drm/i915/intel_guc_slpc.c b/drivers/gpu/drm/i915/intel_guc_slpc.c
index 63f100c..974a3c0 100644
--- a/drivers/gpu/drm/i915/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/intel_guc_slpc.c
@@ -4,10 +4,203 @@
  * Copyright © 2015-2018 Intel Corporation
  */
 
+#include <asm/msr-index.h>
+
+#include "i915_drv.h"
 #include "intel_guc_slpc.h"
 
+static inline struct intel_guc *slpc_to_guc(struct intel_guc_slpc *slpc)
+{
+	return container_of(slpc, struct intel_guc, slpc);
+}
+
+static unsigned int slpc_get_platform_sku(struct drm_i915_private *dev_priv)
+{
+	enum slpc_platform_sku platform_sku;
+
+	if (IS_ULX_SKU(dev_priv))
+		platform_sku = SLPC_PLATFORM_SKU_ULX;
+	else if (IS_ULT_SKU(dev_priv))
+		platform_sku = SLPC_PLATFORM_SKU_ULT;
+	else
+		platform_sku = SLPC_PLATFORM_SKU_DT;
+
+	WARN_ON(platform_sku > 0xFF);
+
+	return platform_sku;
+}
+
+static unsigned int slpc_get_slice_count(struct drm_i915_private *dev_priv)
+{
+	unsigned int slice_count = 1;
+
+	if (IS_SKYLAKE(dev_priv))
+		slice_count = hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask);
+
+	return slice_count;
+}
+
+static void slpc_mem_set_param(struct slpc_shared_data *data,
+			       u32 id,
+			       u32 value)
+{
+	data->override_params_set_bits[id >> 5] |= (1 << (id % 32));
+	data->override_params_values[id] = value;
+}
+
+static void slpc_mem_unset_param(struct slpc_shared_data *data,
+				 u32 id)
+{
+	data->override_params_set_bits[id >> 5] &= (~(1 << (id % 32)));
+	data->override_params_values[id] = 0;
+}
+
+static int slpc_mem_task_control(struct slpc_shared_data *data,
+				 u64 val, u32 enable_id, u32 disable_id)
+{
+	int ret = 0;
+
+	if (val == SLPC_PARAM_TASK_DEFAULT) {
+		/* set default */
+		slpc_mem_unset_param(data, enable_id);
+		slpc_mem_unset_param(data, disable_id);
+	} else if (val == SLPC_PARAM_TASK_ENABLED) {
+		/* set enable */
+		slpc_mem_set_param(data, enable_id, 1);
+		slpc_mem_unset_param(data, disable_id);
+	} else if (val == SLPC_PARAM_TASK_DISABLED) {
+		/* set disable */
+		slpc_mem_set_param(data, disable_id, 1);
+		slpc_mem_unset_param(data, enable_id);
+	} else {
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+static void slpc_shared_data_init(struct intel_guc_slpc *slpc)
+{
+	struct intel_guc *guc = slpc_to_guc(slpc);
+	struct drm_i915_private *dev_priv = guc_to_i915(guc);
+	struct slpc_platform_info *platform_info;
+	struct slpc_shared_data *data;
+	struct page *page;
+	u64 val;
+
+	lockdep_assert_held(&slpc->lock);
+
+	page = i915_vma_first_page(slpc->vma);
+	data = kmap_atomic(page);
+	platform_info = &data->platform_info;
+
+	memset(data, 0, sizeof(struct slpc_shared_data));
+
+	data->shared_data_size = sizeof(struct slpc_shared_data);
+	data->global_state = SLPC_GLOBAL_STATE_NOT_RUNNING;
+	platform_info->sku = slpc_get_platform_sku(dev_priv);
+	platform_info->slice_count = slpc_get_slice_count(dev_priv);
+	platform_info->power_plan_source =
+			SLPC_POWER_PLAN_SOURCE(SLPC_POWER_PLAN_BALANCED,
+					       SLPC_POWER_SOURCE_AC);
+
+	rdmsrl(MSR_TURBO_RATIO_LIMIT, val);
+	platform_info->p0_freq = val;
+	rdmsrl(MSR_PLATFORM_INFO, val);
+	platform_info->p1_freq = val >> 8;
+	platform_info->pe_freq = val >> 40;
+	platform_info->pn_freq = val >> 48;
+
+	/* Enable only GTPERF task, Disable others */
+	val = SLPC_PARAM_TASK_ENABLED;
+	slpc_mem_task_control(data, val,
+			      SLPC_PARAM_TASK_ENABLE_GTPERF,
+			      SLPC_PARAM_TASK_DISABLE_GTPERF);
+
+	slpc_mem_task_control(data, val,
+			      SLPC_PARAM_TASK_ENABLE_BALANCER,
+			      SLPC_PARAM_TASK_DISABLE_BALANCER);
+
+	val = SLPC_PARAM_TASK_DISABLED;
+	slpc_mem_task_control(data, val,
+			      SLPC_PARAM_TASK_ENABLE_DCC,
+			      SLPC_PARAM_TASK_DISABLE_DCC);
+
+	slpc_mem_set_param(data,
+			   SLPC_PARAM_GTPERF_THRESHOLD_MAX_FPS,
+			   0);
+
+	slpc_mem_set_param(data,
+			   SLPC_PARAM_GTPERF_ENABLE_FRAMERATE_STALLING,
+			   0);
+
+	slpc_mem_set_param(data,
+			   SLPC_PARAM_GLOBAL_ENABLE_IA_GT_BALANCING,
+			   1);
+
+	slpc_mem_set_param(data,
+			   SLPC_PARAM_GLOBAL_ENABLE_ADAPTIVE_BURST_TURBO,
+			   0);
+
+	slpc_mem_set_param(data,
+			   SLPC_PARAM_GLOBAL_ENABLE_EVAL_MODE,
+			   0);
+
+	slpc_mem_set_param(data,
+			   SLPC_PARAM_GLOBAL_ENABLE_BALANCER_IN_NON_GAMING_MODE,
+			   1);
+
+	slpc_mem_set_param(data,
+			   SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
+			   intel_gpu_freq(dev_priv,
+					  dev_priv->gt_pm.rps.efficient_freq));
+
+	slpc_mem_set_param(data,
+			   SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ,
+			   intel_gpu_freq(dev_priv,
+					  dev_priv->gt_pm.rps.efficient_freq));
+
+	kunmap_atomic(data);
+}
+
+/**
+ * intel_guc_slpc_init() - Initialize the SLPC shared data structure.
+ * @slpc: pointer to intel_guc_slpc.
+ *
+ * This function will create object to be shared with GuC SLPC and
+ * initialize it with required initial parameter values for various
+ * SLPC knobs such as min frequency limit, enabling/disabling of SLPC
+ * tasks etc.
+ *
+ * Return: 0 on success, non-zero error code on failure.
+ */
+
 int intel_guc_slpc_init(struct intel_guc_slpc *slpc)
 {
+	struct intel_guc *guc = slpc_to_guc(slpc);
+	u32 size = PAGE_ALIGN(sizeof(struct slpc_shared_data));
+	struct i915_vma *vma;
+
+	mutex_init(&slpc->lock);
+
+	mutex_lock(&slpc->lock);
+
+	vma = slpc->vma;
+	if (!vma) {
+		/* Allocate shared data structure */
+		vma = intel_guc_allocate_vma(guc, size);
+		if (IS_ERR(vma)) {
+			DRM_ERROR("Shared data allocation failed\n");
+			mutex_unlock(&slpc->lock);
+			return PTR_ERR(vma);
+		}
+		slpc->vma = vma;
+	}
+
+	slpc_shared_data_init(slpc);
+
+	mutex_unlock(&slpc->lock);
+
 	return 0;
 }
 
@@ -20,6 +213,17 @@ void intel_guc_slpc_disable(struct intel_guc_slpc *slpc)
 {
 }
 
+/**
+ * intel_guc_slpc_fini() - Release the SLPC shared data structure.
+ * @slpc: pointer to intel_guc_slpc.
+ *
+ * This function will release the shared data. SLPC needs to be disabled
+ * prior to this.
+ */
 void intel_guc_slpc_fini(struct intel_guc_slpc *slpc)
 {
+	/* Release shared data structure */
+	mutex_lock(&slpc->lock);
+	i915_vma_unpin_and_release(&slpc->vma);
+	mutex_unlock(&slpc->lock);
 }
diff --git a/drivers/gpu/drm/i915/intel_guc_slpc.h b/drivers/gpu/drm/i915/intel_guc_slpc.h
index 81250c0..87dac07 100644
--- a/drivers/gpu/drm/i915/intel_guc_slpc.h
+++ b/drivers/gpu/drm/i915/intel_guc_slpc.h
@@ -9,6 +9,9 @@
 #include <intel_guc_slpc_fwif.h>
 
 struct intel_guc_slpc {
+	/* Protects access to vma and SLPC actions */
+	struct mutex lock;
+	struct i915_vma *vma;
 };
 
 int intel_guc_slpc_init(struct intel_guc_slpc *slpc);
-- 
2.7.4

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[PATCH v12 07/17] drm/i915/guc/slpc: Send RESET event to restart/enable SLPC tasks

[Sagar Arun Kamble]

Host to GuC actions for SLPC receive additional data as output through
scratch registers currently. intel_guc_send_and_receive handles this.
We need to define SLPC specific Host to GuC send action (slpc_send) as
wrapper on top of it to process the SLPC status that is received in
SOFT_SCRATCH(1).

Send host2guc SLPC reset event to GuC post GuC load for enabling SLPC.
Post this, i915 can ascertain if SLPC has started running successfully
through shared data. This check is done by waiting for maximum 5ms.
SLPC reset event also needs to be sent when parameters in shared data
are updated.

v1: Extract host2guc_slpc to handle slpc status code and style changes.
    (Paulo). Removed WARN_ON for checking msb of gtt address of shared
     gem obj. (Chris). host2guc_action to i915_guc_action change.(Sagar)
    Updating SLPC enabled status. (Sagar)

v2: Commit message update. (David)

v3: Rebase.

v4: Added DRM_INFO message when SLPC is enabled.

v5: Updated patch as host2guc_slpc is moved to earlier patch. SLPC
    activation status message put after checking the state from shared
    data during intel_init_gt_powersave.

v6: Added definition of host2guc_slpc and clflush the shared data only
    for required size. Setting state to NOT_RUNNING before sending RESET
    event. Output data for SLPC actions is to be retrieved during
    intel_guc_send with lock protection so created wrapper
    __intel_guc_send that outputs GuC output data if needed. Clearing
    pm_rps_events on confirming SLPC RUNNING status so that even if
    host touches any of the PM registers by mistake it should not have
    any effect. (Sagar)

v7: Added save/restore_default_rps as Uncore sanitize will clear the
    RP_CONTROL setup by BIOS. s/i915_ggtt_offset/guc_ggtt_offset.

v8: Added support for handling TDR based SLPC reset. Added functions
    host2guc_slpc_tdr_reset, intel_slpc_reset_prepare and
    intel_slpc_tdr_reset to handle TDR based SLPC reset.

v9: Moved TDR support to later patch. Removed intel_slpc_get_status
    and waiting for maximum of 5ms for SLPC state to turn RUNNING instead
    of hiding the latency across uc_init_hw and init_gt_powersave.
    s/if..else/switch..case in intel_guc_slpc_get_state_str. Removed SLPC
    sanitization from init_gt_powersave. (Michal Wajdeczko)

v10: Rebase.

v11: Rebase. Created slpc_send func as wrapper on guc_send_and_receive.

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
Cc: Jeff McGee <jeff.mcgee@intel.com>
---
 drivers/gpu/drm/i915/intel_guc_slpc.c | 239 ++++++++++++++++++++++++++++++++++
 1 file changed, 239 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_guc_slpc.c b/drivers/gpu/drm/i915/intel_guc_slpc.c
index 974a3c0..bc2c717 100644
--- a/drivers/gpu/drm/i915/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/intel_guc_slpc.c
@@ -163,6 +163,211 @@ static void slpc_shared_data_init(struct intel_guc_slpc *slpc)
 	kunmap_atomic(data);
 }
 
+static const char *slpc_status_stringify(int status)
+{
+	const char *str = NULL;
+
+	switch(status) {
+	case SLPC_STATUS_OK:
+		str = "Ok";
+		break;
+	case SLPC_STATUS_ERROR:
+		str = "Error";
+		break;
+	case SLPC_STATUS_ILLEGAL_COMMAND:
+		str = "Illegal command";
+		break;
+	case SLPC_STATUS_INVALID_ARGS:
+		str = "Invalid args";
+		break;
+	case SLPC_STATUS_INVALID_PARAMS:
+		str = "Invalid params";
+		break;
+	case SLPC_STATUS_INVALID_DATA:
+		str = "Invalid data";
+		break;
+	case SLPC_STATUS_OUT_OF_RANGE:
+		str = "Out of range";
+		break;
+	case SLPC_STATUS_NOT_SUPPORTED:
+		str = "Not supported";
+		break;
+	case SLPC_STATUS_NOT_IMPLEMENTED:
+		str = "Not implemented";
+		break;
+	case SLPC_STATUS_NO_DATA:
+		str = "No data";
+		break;
+	case SLPC_STATUS_EVENT_NOT_REGISTERED:
+		str = "Event not registered";
+		break;
+	case SLPC_STATUS_REGISTER_LOCKED:
+		str = "Register locked";
+		break;
+	case SLPC_STATUS_TEMPORARILY_UNAVAILABLE:
+		str = "Temporarily unavailable";
+		break;
+	case SLPC_STATUS_VALUE_ALREADY_SET:
+		str = "Value already set";
+		break;
+	case SLPC_STATUS_VALUE_ALREADY_UNSET:
+		str = "Value already unset";
+		break;
+	case SLPC_STATUS_VALUE_NOT_CHANGED:
+		str = "Value not changed";
+		break;
+	case SLPC_STATUS_MEMIO_ERROR:
+		str = "MMIO error";
+		break;
+	case SLPC_STATUS_EVENT_QUEUED_REQ_DPC:
+		str = "Event queued, DPC requested";
+		break;
+	case SLPC_STATUS_EVENT_QUEUED_NOREQ_DPC:
+		str = "Event queued, DPC not requested";
+		break;
+	case SLPC_STATUS_NO_EVENT_QUEUED:
+		str = "Event not queued";
+		break;
+	case SLPC_STATUS_OUT_OF_SPACE:
+		str = "Out of space";
+		break;
+	case SLPC_STATUS_TIMEOUT:
+		str = "Timeout";
+		break;
+	case SLPC_STATUS_NO_LOCK:
+		str = "No lock";
+		break;
+	}
+
+	return str;
+}
+
+static void slpc_send(struct intel_guc_slpc *slpc,
+		      struct slpc_event_input *input, u32 in_len)
+{
+	struct intel_guc *guc = slpc_to_guc(slpc);
+	struct slpc_event_output output;
+	u32 out_len = 1;
+	u32 *action;
+	int ret;
+
+	action = (u32 *)input;
+	action[0] = INTEL_GUC_ACTION_SLPC_REQUEST;
+
+	ret = intel_guc_send_and_receive(guc, action, in_len,
+					 (u32 *)&output.header, out_len);
+
+	/*
+	 * Currently output data from Host to GuC SLPC actions is populated
+	 * in scratch registers SOFT_SCRATCH(1) to SOFT_SCRATCH(14) based
+	 * on event. Currently only SLPC action status in GuC is meaningful
+	 * as Host can query only overridden parameters and that are fetched
+	 * from Host-GuC SLPC shared data. Other parameters can be read through
+	 * output data but that is available only for debug GuC firmwares.
+	 */
+	if (!ret) {
+		ret = output.header.status;
+		if (ret) {
+			GEM_BUG_ON(ret >= SLPC_STATUS_MAX);
+			DRM_ERROR("event 0x%x status %s\n",
+				  ((output.header.value & 0xFF00) >> 8),
+				  slpc_status_stringify(ret));
+		}
+	}
+}
+
+static void host2guc_slpc_reset(struct intel_guc_slpc *slpc)
+{
+	struct intel_guc *guc = slpc_to_guc(slpc);
+	u32 shared_data_gtt_offset = intel_guc_ggtt_offset(guc, slpc->vma);
+	struct slpc_event_input data = {0};
+
+	data.header.value = SLPC_EVENT(SLPC_EVENT_RESET, 2);
+	data.args[0] = shared_data_gtt_offset;
+	data.args[1] = 0;
+
+	slpc_send(slpc, &data, 4);
+}
+
+static void host2guc_slpc_query_task_state(struct intel_guc_slpc *slpc)
+{
+	struct intel_guc *guc = slpc_to_guc(slpc);
+	u32 shared_data_gtt_offset = intel_guc_ggtt_offset(guc, slpc->vma);
+	struct slpc_event_input data = {0};
+
+	data.header.value = SLPC_EVENT(SLPC_EVENT_QUERY_TASK_STATE, 2);
+	data.args[0] = shared_data_gtt_offset;
+	data.args[1] = 0;
+
+	slpc_send(slpc, &data, 4);
+}
+
+static void slpc_read_shared_data(struct intel_guc_slpc *slpc,
+				  struct slpc_shared_data *data)
+{
+	struct page *page;
+	void *pv = NULL;
+
+	host2guc_slpc_query_task_state(slpc);
+
+	page = i915_vma_first_page(slpc->vma);
+	pv = kmap_atomic(page);
+
+	drm_clflush_virt_range(pv, sizeof(struct slpc_shared_data));
+	memcpy(data, pv, sizeof(struct slpc_shared_data));
+
+	kunmap_atomic(pv);
+}
+
+static const char *slpc_state_stringify(enum slpc_global_state state)
+{
+	const char *str = NULL;
+
+	switch (state) {
+	case SLPC_GLOBAL_STATE_NOT_RUNNING:
+		str = "not running";
+		break;
+	case SLPC_GLOBAL_STATE_INITIALIZING:
+		str = "initializing";
+		break;
+	case SLPC_GLOBAL_STATE_RESETTING:
+		str = "resetting";
+		break;
+	case SLPC_GLOBAL_STATE_RUNNING:
+		str = "running";
+		break;
+	case SLPC_GLOBAL_STATE_SHUTTING_DOWN:
+		str = "shutting down";
+		break;
+	case SLPC_GLOBAL_STATE_ERROR:
+		str = "error";
+		break;
+	default:
+		str = "unknown";
+		break;
+	}
+
+	return str;
+}
+
+static const char *slpc_get_state(struct intel_guc_slpc *slpc)
+{
+	struct slpc_shared_data data;
+
+	slpc_read_shared_data(slpc, &data);
+
+	return slpc_state_stringify(data.global_state);
+}
+
+static bool slpc_running(struct intel_guc_slpc *slpc)
+{
+	struct slpc_shared_data data;
+
+	slpc_read_shared_data(slpc, &data);
+
+	return (data.global_state == SLPC_GLOBAL_STATE_RUNNING);
+}
+
 /**
  * intel_guc_slpc_init() - Initialize the SLPC shared data structure.
  * @slpc: pointer to intel_guc_slpc.
@@ -204,8 +409,42 @@ int intel_guc_slpc_init(struct intel_guc_slpc *slpc)
 	return 0;
 }
 
+/**
+ * intel_guc_slpc_enable() - Start SLPC.
+ * @slpc: pointer to intel_guc_slpc.
+ *
+ * This function will start GuC SLPC by sending Host to GuC action.
+ * SLPC shared data has to be initialized prior to this by
+ * intel_guc_slpc_init().
+ *
+ * Return: 0 on success, non-zero error code on failure.
+ */
 int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
 {
+	struct slpc_shared_data *data;
+	struct page *page;
+
+	mutex_lock(&slpc->lock);
+
+	page = i915_vma_first_page(slpc->vma);
+	data = kmap_atomic(page);
+	data->global_state = SLPC_GLOBAL_STATE_NOT_RUNNING;
+	kunmap_atomic(data);
+
+	host2guc_slpc_reset(slpc);
+
+	/* Check whether SLPC is running */
+	if (wait_for(slpc_running(slpc), 5)) {
+		DRM_ERROR("SLPC not enabled! State = %s\n",
+			  slpc_get_state(slpc));
+		mutex_unlock(&slpc->lock);
+		return -EIO;
+	}
+
+	DRM_INFO("SLPC state: %s\n", slpc_get_state(slpc));
+
+	mutex_unlock(&slpc->lock);
+
 	return 0;
 }
 
-- 
2.7.4

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[PATCH v12 08/17] drm/i915/guc/slpc: Send SHUTDOWN event to stop SLPC tasks

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Send SLPC shutdown event during uc_fini_hw or prior to enabling SLPC
done while communicating updated parameters in shared data.

v1: Return void instead of ignored error code (Paulo). Removed WARN_ON
    for checking msb of gtt address of shared gem obj. (Chris)
    Added SLPC state update during disable, suspend and reset. Changed
    semantics of reset. It is supposed to just disable. (Sagar)

v2-v4: Rebase.

v5: Updated the input data structure. (Sagar)

v6: Rebase.

v7: s/i915_ggtt_offset/guc_ggtt_offset.

v8: Updated the status check post disabling to wait for 20us. (Sagar)

v9: Updated the status check wait time to 5ms for safe margin as it is
    handled similar to reset by SLPC. s/slpc_disabled/slpc_stopped

v10: Rebase.

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
Cc: Jeff McGee <jeff.mcgee@intel.com>
---
 drivers/gpu/drm/i915/intel_guc_slpc.c | 38 +++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_uc.c       |  6 +++---
 2 files changed, 41 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_slpc.c b/drivers/gpu/drm/i915/intel_guc_slpc.c
index bc2c717..7f75d218 100644
--- a/drivers/gpu/drm/i915/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/intel_guc_slpc.c
@@ -368,6 +368,28 @@ static bool slpc_running(struct intel_guc_slpc *slpc)
 	return (data.global_state == SLPC_GLOBAL_STATE_RUNNING);
 }
 
+static void host2guc_slpc_shutdown(struct intel_guc_slpc *slpc)
+{
+	struct intel_guc *guc = slpc_to_guc(slpc);
+	u32 shared_data_gtt_offset = intel_guc_ggtt_offset(guc, slpc->vma);
+	struct slpc_event_input data = {0};
+
+	data.header.value = SLPC_EVENT(SLPC_EVENT_SHUTDOWN, 2);
+	data.args[0] = shared_data_gtt_offset;
+	data.args[1] = 0;
+
+	slpc_send(slpc, &data, 4);
+}
+
+static bool slpc_stopped(struct intel_guc_slpc *slpc)
+{
+	struct slpc_shared_data data;
+
+	slpc_read_shared_data(slpc, &data);
+
+	return (data.global_state == SLPC_GLOBAL_STATE_NOT_RUNNING);
+}
+
 /**
  * intel_guc_slpc_init() - Initialize the SLPC shared data structure.
  * @slpc: pointer to intel_guc_slpc.
@@ -448,8 +470,24 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
 	return 0;
 }
 
+/**
+ * intel_guc_slpc_disable() - Stop SLPC tasks.
+ * @slpc: pointer to intel_guc_slpc.
+ *
+ * This function will stop GuC SLPC tasks by sending Host to GuC action.
+ */
 void intel_guc_slpc_disable(struct intel_guc_slpc *slpc)
 {
+	mutex_lock(&slpc->lock);
+
+	host2guc_slpc_shutdown(slpc);
+
+	/* Ensure SLPC is not running */
+	if (wait_for(slpc_stopped(slpc), 5))
+		DRM_ERROR("SLPC not disabled! State = %s\n",
+			  slpc_get_state(slpc));
+
+	mutex_unlock(&slpc->lock);
 }
 
 /**
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 5bf33c8..ece6687 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -359,6 +359,9 @@ void intel_uc_sanitize(struct drm_i915_private *i915)
 
 	GEM_BUG_ON(!HAS_GUC(i915));
 
+	if (USES_GUC_SLPC(dev_priv))
+		intel_guc_slpc_disable(&guc->slpc);
+
 	guc_disable_communication(guc);
 
 	intel_huc_sanitize(huc);
@@ -484,9 +487,6 @@ void intel_uc_fini_hw(struct drm_i915_private *dev_priv)
 	if (USES_GUC_SUBMISSION(dev_priv))
 		intel_guc_submission_disable(guc);
 
-	if (USES_GUC_SLPC(dev_priv))
-		intel_guc_slpc_disable(&guc->slpc);
-
 	guc_disable_communication(guc);
 }
 
-- 
2.7.4

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[PATCH v12 09/17] drm/i915/guc/slpc: Reset SLPC on engine reset with flag TDR_OCCURRED

[Sagar Arun Kamble]

On engine reset, SLPC needs to be notified for it to clear metrics/stats.
This is done by sending GUC_SLPC_EVENT_RESET with a flag
GUC_SLPC_RESET_FLAG_TDR_OCCURRED.

v2: Full GPU reset in i915 triggers reload of GuC and SLPC reset happens
    along that path. Hence only handling engine reset.

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
Cc: Jeff McGee <jeff.mcgee@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c       |  3 +++
 drivers/gpu/drm/i915/intel_guc_slpc.c | 36 +++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_guc_slpc.h |  1 +
 drivers/gpu/drm/i915/intel_uc.c       |  5 +++++
 drivers/gpu/drm/i915/intel_uc.h       |  1 +
 5 files changed, 46 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index cc7dd85..726391c 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3020,6 +3020,9 @@ void i915_handle_error(struct drm_i915_private *dev_priv,
 			wake_up_bit(&dev_priv->gpu_error.flags,
 				    I915_RESET_ENGINE + engine->id);
 		}
+
+		if (!engine_mask)
+			intel_uc_handle_engine_reset(dev_priv);
 	}
 
 	if (!engine_mask)
diff --git a/drivers/gpu/drm/i915/intel_guc_slpc.c b/drivers/gpu/drm/i915/intel_guc_slpc.c
index 7f75d218..bdafbaa 100644
--- a/drivers/gpu/drm/i915/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/intel_guc_slpc.c
@@ -390,6 +390,20 @@ static bool slpc_stopped(struct intel_guc_slpc *slpc)
 	return (data.global_state == SLPC_GLOBAL_STATE_NOT_RUNNING);
 }
 
+static void host2guc_slpc_tdr_reset(struct intel_guc_slpc *slpc)
+{
+	struct intel_guc *guc = slpc_to_guc(slpc);
+	u32 shared_data_gtt_offset = intel_guc_ggtt_offset(guc, slpc->vma);
+	struct slpc_event_input data = {0};
+
+	data.header.value = SLPC_EVENT(SLPC_EVENT_RESET, 3);
+	data.args[0] = shared_data_gtt_offset;
+	data.args[1] = 0;
+	data.args[2] = SLPC_RESET_FLAG_TDR_OCCURRED;
+
+	slpc_send(slpc, &data, 5);
+}
+
 /**
  * intel_guc_slpc_init() - Initialize the SLPC shared data structure.
  * @slpc: pointer to intel_guc_slpc.
@@ -471,6 +485,28 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
 }
 
 /**
+ * intel_guc_slpc_handle_engine_reset() - Notify SLPC about engine reset.
+ * @slpc: pointer to intel_guc_slpc.
+ *
+ * On engine reset, SLPC needs to be notified for it to clear metrics/stats.
+ * This function notifies by invoking SLPC_EVENT_RESET with a flag
+ * SLPC_RESET_FLAG_TDR_OCCURRED.
+ */
+void intel_guc_slpc_handle_engine_reset(struct intel_guc_slpc *slpc)
+{
+	mutex_lock(&slpc->lock);
+
+	host2guc_slpc_tdr_reset(slpc);
+
+	/* Check whether SLPC is running */
+	if (wait_for(slpc_running(slpc), 5))
+		DRM_ERROR("SLPC not enabled! State = %s\n",
+			  slpc_get_state(slpc));
+
+	mutex_unlock(&slpc->lock);
+}
+
+/**
  * intel_guc_slpc_disable() - Stop SLPC tasks.
  * @slpc: pointer to intel_guc_slpc.
  *
diff --git a/drivers/gpu/drm/i915/intel_guc_slpc.h b/drivers/gpu/drm/i915/intel_guc_slpc.h
index 87dac07..75f0b5d 100644
--- a/drivers/gpu/drm/i915/intel_guc_slpc.h
+++ b/drivers/gpu/drm/i915/intel_guc_slpc.h
@@ -16,6 +16,7 @@ struct intel_guc_slpc {
 
 int intel_guc_slpc_init(struct intel_guc_slpc *slpc);
 int intel_guc_slpc_enable(struct intel_guc_slpc *slpc);
+void intel_guc_slpc_handle_engine_reset(struct intel_guc_slpc *slpc);
 void intel_guc_slpc_disable(struct intel_guc_slpc *slpc);
 void intel_guc_slpc_fini(struct intel_guc_slpc *slpc);
 
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index ece6687..c050444 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -475,6 +475,11 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
 	return ret;
 }
 
+void intel_uc_handle_engine_reset(struct drm_i915_private *dev_priv)
+{
+	intel_guc_slpc_handle_engine_reset(&dev_priv->guc.slpc);
+}
+
 void intel_uc_fini_hw(struct drm_i915_private *dev_priv)
 {
 	struct intel_guc *guc = &dev_priv->guc;
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index 76139d3..1d67ad3 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -35,6 +35,7 @@ int intel_uc_init_misc(struct drm_i915_private *dev_priv);
 void intel_uc_fini_misc(struct drm_i915_private *dev_priv);
 void intel_uc_sanitize(struct drm_i915_private *dev_priv);
 int intel_uc_init_hw(struct drm_i915_private *dev_priv);
+void intel_uc_handle_engine_reset(struct drm_i915_private *dev_priv);
 void intel_uc_fini_hw(struct drm_i915_private *dev_priv);
 int intel_uc_init(struct drm_i915_private *dev_priv);
 void intel_uc_fini(struct drm_i915_private *dev_priv);
-- 
2.7.4

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[PATCH v12 10/17] drm/i915/guc/slpc: Add parameter set/unset/get, task control/status functions

[Sagar Arun Kamble]

SLPC behavior can be changed through set of parameters. These parameters
can be updated and queried from i915 though Host to GuC SLPC events. This
patch adds parameter update events for setting/unsetting/getting params.
Setting parameter leads to overridding of default parameter value. Unset
leads to restoring of default value by communicating with GuC SLPC through
parameter updates in the shared data.
i915 can only query/get parameters that it overrides, so getting parameter
value is done by only reading from the shared data.

SLPC has various tasks, GTPERF, BALANCER and DCC. These can be controlled
through pair of GuC SLPC parameters. Enable/disable of these tasks require
combined update to both parameters hence new actions are added to control
and query the status of tasks.

v1: Use host2guc_slpc. Update slcp_param_id enum values for SLPC 2015.2.4
    Return void instead of ignored error code (Paulo)

v2: Checkpatch update.

v3: Rebase.

v4: Updated with GuC firmware v9.

v5: Updated input structure to host2guc_slpc. Added functions to update
    only parameters in the SLPC shared memory. This will allow to setup
    shared data with all parameters and send single event to SLPC take
    them into effect. Commit message update. (Sagar)

v6: Rearranged helpers to use them in slpc_shared_data_init. Added defn.
    of SLPC_KMD_MAX_PARAM.

v7: Added definition of host2guc_slpc with rearrangement of patches. Added
    task control/status functions.

v8: Rebase w.r.t s/intel_guc_send/intel_guc_send_mmio.

v9: Created intel_guc_slpc_send_mmio with SLPC specific H2G action send
    function. Rebase. Defined slpc_statuslist and using the same in
    intel_guc_slpc_send_mmio. (Michal Wajdeczko)

v10: Rebase. Added kernel documentation to the task control functions.

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
Cc: Jeff McGee <jeff.mcgee@intel.com>
---
 drivers/gpu/drm/i915/intel_guc_slpc.c | 173 ++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_guc_slpc.h |   5 +
 2 files changed, 178 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_guc_slpc.c b/drivers/gpu/drm/i915/intel_guc_slpc.c
index bdafbaa..011e442 100644
--- a/drivers/gpu/drm/i915/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/intel_guc_slpc.c
@@ -404,6 +404,179 @@ static void host2guc_slpc_tdr_reset(struct intel_guc_slpc *slpc)
 	slpc_send(slpc, &data, 5);
 }
 
+static void host2guc_slpc_set_param(struct intel_guc_slpc *slpc,
+				    u32 id, u32 value)
+{
+	struct slpc_event_input data = {0};
+
+	data.header.value = SLPC_EVENT(SLPC_EVENT_PARAMETER_SET, 2);
+	data.args[0] = id;
+	data.args[1] = value;
+
+	slpc_send(slpc, &data, 4);
+}
+
+static void host2guc_slpc_unset_param(struct intel_guc_slpc *slpc,
+				      u32 id)
+{
+	struct slpc_event_input data = {0};
+
+	data.header.value = SLPC_EVENT(SLPC_EVENT_PARAMETER_UNSET, 1);
+	data.args[0] = id;
+
+	slpc_send(slpc, &data, 3);
+}
+
+static void slpc_set_param(struct intel_guc_slpc *slpc, u32 id, u32 value)
+{
+	struct slpc_shared_data *data = NULL;
+	struct page *page;
+
+	GEM_BUG_ON(id >= SLPC_MAX_PARAM);
+	GEM_BUG_ON(!slpc->vma);
+
+	lockdep_assert_held(&slpc->lock);
+
+	page = i915_vma_first_page(slpc->vma);
+	data = kmap_atomic(page);
+	slpc_mem_set_param(data, id, value);
+	kunmap_atomic(data);
+
+	host2guc_slpc_set_param(slpc, id, value);
+}
+
+static void slpc_unset_param(struct intel_guc_slpc *slpc, u32 id)
+{
+	struct slpc_shared_data *data = NULL;
+	struct page *page;
+
+	GEM_BUG_ON(id >= SLPC_MAX_PARAM);
+	GEM_BUG_ON(!slpc->vma);
+
+	lockdep_assert_held(&slpc->lock);
+
+	page = i915_vma_first_page(slpc->vma);
+	data = kmap_atomic(page);
+	slpc_mem_unset_param(data, id);
+	kunmap_atomic(data);
+
+	host2guc_slpc_unset_param(slpc, id);
+}
+
+static void slpc_get_param(struct intel_guc_slpc *slpc, u32 id,
+			   int *overriding, u32 *value)
+{
+	struct slpc_shared_data *data = NULL;
+	struct page *page;
+	u32 bits;
+
+	GEM_BUG_ON(id >= SLPC_MAX_PARAM);
+	GEM_BUG_ON(!slpc->vma);
+
+	lockdep_assert_held(&slpc->lock);
+
+	page = i915_vma_first_page(slpc->vma);
+	data = kmap_atomic(page);
+	if (overriding) {
+		bits = data->override_params_set_bits[id >> 5];
+		*overriding = (0 != (bits & (1 << (id % 32))));
+	}
+	if (value)
+		*value = data->override_params_values[id];
+
+	kunmap_atomic(data);
+}
+
+/**
+ * intel_guc_slpc_task_control() - Update status of SLPC task.
+ * @slpc: pointer to intel_guc_slpc.
+ *
+ * This function will update status of task in SLPC shared data.
+ * Then it invokes SLPC Host to GuC action to communicate the
+ * required task status.
+ *
+ * Return: 0 on success, non-zero error code on failure.
+ */
+int intel_guc_slpc_task_control(struct intel_guc_slpc *slpc, u64 val,
+				u32 enable_id, u32 disable_id)
+{
+	int ret = 0;
+
+	GEM_BUG_ON(!slpc->vma);
+
+	lockdep_assert_held(&slpc->lock);
+
+	if (val == SLPC_PARAM_TASK_DEFAULT) {
+		/* set default */
+		slpc_unset_param(slpc, enable_id);
+		slpc_unset_param(slpc, disable_id);
+	} else if (val == SLPC_PARAM_TASK_ENABLED) {
+		/* set enable */
+		slpc_set_param(slpc, enable_id, 1);
+		slpc_unset_param(slpc, disable_id);
+	} else if (val == SLPC_PARAM_TASK_DISABLED) {
+		/* set disable */
+		slpc_set_param(slpc, disable_id, 1);
+		slpc_unset_param(slpc, enable_id);
+	} else {
+		ret = -EINVAL;
+	}
+
+	host2guc_slpc_reset(slpc);
+
+	return ret;
+}
+
+/**
+ * intel_guc_slpc_task_status() - gets the status of SLPC task.
+ * @slpc: pointer to intel_guc_slpc.
+ *
+ * This function will read status of task from SLPC shared data.
+ * Task could be in either "enabled", "disabled", "default" or
+ * "unknown" state.
+ *
+ * Return: 0 on success, non-zero error code on failure.
+ */
+int intel_guc_slpc_task_status(struct intel_guc_slpc *slpc, u64 *val,
+			       u32 enable_id, u32 disable_id)
+{
+	int override_enable, override_disable;
+	u32 value_enable, value_disable;
+	int ret = 0;
+
+	GEM_BUG_ON(!slpc->vma);
+
+	lockdep_assert_held(&slpc->lock);
+
+	if (val) {
+		slpc_get_param(slpc, enable_id,
+			       &override_enable, &value_enable);
+		slpc_get_param(slpc, disable_id,
+			       &override_disable, &value_disable);
+
+		/*
+		 * Set the output value:
+		 * 0: default
+		 * 1: enabled
+		 * 2: disabled
+		 * 3: unknown (should not happen)
+		 */
+		if (override_disable && value_disable == 1)
+			*val = SLPC_PARAM_TASK_DISABLED;
+		else if (override_enable && value_enable == 1)
+			*val = SLPC_PARAM_TASK_ENABLED;
+		else if (!override_enable && !override_disable)
+			*val = SLPC_PARAM_TASK_DEFAULT;
+		else
+			*val = SLPC_PARAM_TASK_UNKNOWN;
+
+	} else {
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
 /**
  * intel_guc_slpc_init() - Initialize the SLPC shared data structure.
  * @slpc: pointer to intel_guc_slpc.
diff --git a/drivers/gpu/drm/i915/intel_guc_slpc.h b/drivers/gpu/drm/i915/intel_guc_slpc.h
index 75f0b5d..87b504d 100644
--- a/drivers/gpu/drm/i915/intel_guc_slpc.h
+++ b/drivers/gpu/drm/i915/intel_guc_slpc.h
@@ -14,6 +14,11 @@ struct intel_guc_slpc {
 	struct i915_vma *vma;
 };
 
+int intel_guc_slpc_task_control(struct intel_guc_slpc *slpc, u64 val,
+				u32 enable_id, u32 disable_id);
+int intel_guc_slpc_task_status(struct intel_guc_slpc *slpc, u64 *val,
+			       u32 enable_id, u32 disable_id);
+
 int intel_guc_slpc_init(struct intel_guc_slpc *slpc);
 int intel_guc_slpc_enable(struct intel_guc_slpc *slpc);
 void intel_guc_slpc_handle_engine_reset(struct intel_guc_slpc *slpc);
-- 
2.7.4

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[PATCH v12 11/17] drm/i915/guc/slpc: Add support for sysfs min/max frequency control

[Sagar Arun Kamble]

Update sysfs functions to set SLPC parameters when setting max/min user
frequency limits.

v1: Update for SLPC 2015.2.4 (params for both slice and unslice). Replace
    HAS_SLPC with intel_slpc_active() (Paulo)

v2-v4: Rebase.

v5: Removed typecasting the frequency values to u32. (Chris). Changed
    intel_slpc_active to guc.slpc.enabled. Carved out SLPC helpers to set
    min and max frequencies.

v6: Rebase. Doing explicit SLPC reset on setting frequency to start sane
    and covered with RPM get/put. Caching SLPC limits post enabling first.

v7: Rebase due to change in the dev_priv->pm.rps structure.

v8: Updated returns from gt_min_freq_mhz_store and gt_max_freq_mhz_store
    and i915_min_freq_set and i915_max_freq_set.

v9: Rebase. Debugfs interfaces will be removed hence only updated sysfs.

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
Cc: Jeff McGee <jeff.mcgee@intel.com>
---
 drivers/gpu/drm/i915/i915_sysfs.c     | 52 +++++++++++++++++----
 drivers/gpu/drm/i915/intel_guc_slpc.c | 86 ++++++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_guc_slpc.h |  6 +++
 3 files changed, 133 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index c3083fa..d1b4793 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -343,10 +343,20 @@ static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev,
 static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
 {
 	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
+	struct intel_guc_slpc *slpc = &dev_priv->guc.slpc;
+	u32 freq;
 
-	return snprintf(buf, PAGE_SIZE, "%d\n",
-			intel_gpu_freq(dev_priv,
-				       dev_priv->gt_pm.rps.max_freq_softlimit));
+	if (USES_GUC_SLPC(dev_priv)) {
+		mutex_lock(&slpc->lock);
+		freq = dev_priv->guc.slpc.max_unslice_freq;
+		mutex_unlock(&slpc->lock);
+	} else {
+		mutex_lock(&dev_priv->pcu_lock);
+		freq = dev_priv->gt_pm.rps.max_freq_softlimit;
+		mutex_lock(&dev_priv->pcu_lock);
+	}
+
+	return snprintf(buf, PAGE_SIZE, "%d\n", intel_gpu_freq(dev_priv, freq));
 }
 
 static ssize_t gt_max_freq_mhz_store(struct device *kdev,
@@ -362,12 +372,17 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,
 	if (ret)
 		return ret;
 
+	val = intel_freq_opcode(dev_priv, val);
+
+	if (USES_GUC_SLPC(dev_priv)) {
+		ret = intel_guc_slpc_max_freq_set(&dev_priv->guc.slpc, val);
+		goto out;
+	}
+
 	intel_runtime_pm_get(dev_priv);
 
 	mutex_lock(&dev_priv->pcu_lock);
 
-	val = intel_freq_opcode(dev_priv, val);
-
 	if (val < rps->min_freq ||
 	    val > rps->max_freq ||
 	    val < rps->min_freq_softlimit) {
@@ -395,16 +410,27 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,
 
 	intel_runtime_pm_put(dev_priv);
 
+out:
 	return ret ?: count;
 }
 
 static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
 {
 	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
+	struct intel_guc_slpc *slpc = &dev_priv->guc.slpc;
+	u32 freq;
 
-	return snprintf(buf, PAGE_SIZE, "%d\n",
-			intel_gpu_freq(dev_priv,
-				       dev_priv->gt_pm.rps.min_freq_softlimit));
+	if (USES_GUC_SLPC(dev_priv)) {
+		mutex_lock(&slpc->lock);
+		freq = dev_priv->guc.slpc.min_unslice_freq;
+		mutex_unlock(&slpc->lock);
+	} else {
+		mutex_lock(&dev_priv->pcu_lock);
+		freq = dev_priv->gt_pm.rps.min_freq_softlimit;
+		mutex_lock(&dev_priv->pcu_lock);
+	}
+
+	return snprintf(buf, PAGE_SIZE, "%d\n", intel_gpu_freq(dev_priv, freq));
 }
 
 static ssize_t gt_min_freq_mhz_store(struct device *kdev,
@@ -420,12 +446,17 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
 	if (ret)
 		return ret;
 
+	val = intel_freq_opcode(dev_priv, val);
+
+	if (USES_GUC_SLPC(dev_priv)) {
+		ret = intel_guc_slpc_min_freq_set(&dev_priv->guc.slpc, val);
+		goto out;
+	}
+
 	intel_runtime_pm_get(dev_priv);
 
 	mutex_lock(&dev_priv->pcu_lock);
 
-	val = intel_freq_opcode(dev_priv, val);
-
 	if (val < rps->min_freq ||
 	    val > rps->max_freq ||
 	    val > rps->max_freq_softlimit) {
@@ -449,6 +480,7 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
 
 	intel_runtime_pm_put(dev_priv);
 
+out:
 	return ret ?: count;
 }
 
diff --git a/drivers/gpu/drm/i915/intel_guc_slpc.c b/drivers/gpu/drm/i915/intel_guc_slpc.c
index 011e442..34a5963 100644
--- a/drivers/gpu/drm/i915/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/intel_guc_slpc.c
@@ -630,7 +630,7 @@ int intel_guc_slpc_init(struct intel_guc_slpc *slpc)
  */
 int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
 {
-	struct slpc_shared_data *data;
+	struct slpc_shared_data *data, output;
 	struct page *page;
 
 	mutex_lock(&slpc->lock);
@@ -652,7 +652,91 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
 
 	DRM_INFO("SLPC state: %s\n", slpc_get_state(slpc));
 
+	slpc_read_shared_data(slpc, &output);
+	slpc->max_unslice_freq = output.task_state_data.max_unslice_freq *
+				 GEN9_FREQ_SCALER;
+	slpc->min_unslice_freq = output.task_state_data.min_unslice_freq *
+				 GEN9_FREQ_SCALER;
+
+	mutex_unlock(&slpc->lock);
+
+	return 0;
+}
+
+/**
+ * intel_guc_slpc_max_freq_set() - Set max frequency limit for SLPC.
+ * @slpc: pointer to intel_guc_slpc.
+ * @val: encoded frequency
+ *
+ * This function will invoke GuC SLPC action to update the max frequency
+ * limit.
+ *
+ * Return: 0 on success, non-zero error code on failure.
+ */
+int intel_guc_slpc_max_freq_set(struct intel_guc_slpc *slpc, u32 val)
+{
+	struct intel_guc *guc = slpc_to_guc(slpc);
+	struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
+	if (val < dev_priv->gt_pm.rps.min_freq ||
+	    val > dev_priv->gt_pm.rps.max_freq ||
+	    val < slpc->min_unslice_freq)
+		return -EINVAL;
+
+	intel_runtime_pm_get(dev_priv);
+	mutex_lock(&slpc->lock);
+
+	slpc_set_param(slpc,
+		       SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
+		       intel_gpu_freq(dev_priv, val));
+	slpc_set_param(slpc,
+		       SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ,
+		       intel_gpu_freq(dev_priv, val));
+
+	host2guc_slpc_reset(slpc);
+	slpc->max_unslice_freq = val;
+
+	mutex_unlock(&slpc->lock);
+	intel_runtime_pm_put(dev_priv);
+
+	return 0;
+}
+
+/**
+ * intel_guc_slpc_min_freq_set() - Set min frequency limit for SLPC.
+ * @slpc: pointer to intel_guc_slpc.
+ * @val: encoded frequency
+ *
+ * This function will invoke GuC SLPC action to update the min frequency
+ * limit.
+ *
+ * Return: 0 on success, non-zero error code on failure.
+ */
+int intel_guc_slpc_min_freq_set(struct intel_guc_slpc *slpc, u32 val)
+{
+	struct intel_guc *guc = slpc_to_guc(slpc);
+	struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
+	if (val < dev_priv->gt_pm.rps.min_freq ||
+	    val > dev_priv->gt_pm.rps.max_freq ||
+	    val > slpc->max_unslice_freq)
+		return -EINVAL;
+
+	intel_runtime_pm_get(dev_priv);
+	mutex_lock(&slpc->lock);
+
+	slpc_set_param(slpc,
+		       SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
+		       intel_gpu_freq(dev_priv, val));
+	slpc_set_param(slpc,
+		       SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ,
+		       intel_gpu_freq(dev_priv, val));
+
+	host2guc_slpc_reset(slpc);
+	slpc->min_unslice_freq = val;
+
 	mutex_unlock(&slpc->lock);
+	intel_runtime_pm_put(dev_priv);
 
 	return 0;
 }
diff --git a/drivers/gpu/drm/i915/intel_guc_slpc.h b/drivers/gpu/drm/i915/intel_guc_slpc.h
index 87b504d..51189b3 100644
--- a/drivers/gpu/drm/i915/intel_guc_slpc.h
+++ b/drivers/gpu/drm/i915/intel_guc_slpc.h
@@ -12,6 +12,10 @@ struct intel_guc_slpc {
 	/* Protects access to vma and SLPC actions */
 	struct mutex lock;
 	struct i915_vma *vma;
+
+	/* i915 cached SLPC frequency limits */
+	u32 min_unslice_freq;
+	u32 max_unslice_freq;
 };
 
 int intel_guc_slpc_task_control(struct intel_guc_slpc *slpc, u64 val,
@@ -21,6 +25,8 @@ int intel_guc_slpc_task_status(struct intel_guc_slpc *slpc, u64 *val,
 
 int intel_guc_slpc_init(struct intel_guc_slpc *slpc);
 int intel_guc_slpc_enable(struct intel_guc_slpc *slpc);
+int intel_guc_slpc_max_freq_set(struct intel_guc_slpc *slpc, u32 val);
+int intel_guc_slpc_min_freq_set(struct intel_guc_slpc *slpc, u32 val);
 void intel_guc_slpc_handle_engine_reset(struct intel_guc_slpc *slpc);
 void intel_guc_slpc_disable(struct intel_guc_slpc *slpc);
 void intel_guc_slpc_fini(struct intel_guc_slpc *slpc);
-- 
2.7.4

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[PATCH v12 12/17] drm/i915/guc/slpc: Add enable/disable controls for SLPC tasks

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Adds debugfs hooks for enabling/disabling each SLPC task.

The enable/disable debugfs files are:
i915_guc_slpc_gtperf, i915_guc_slpc_balancer, and i915_guc_slpc_dcc.

Each of these can take the values: "default", "enabled", or "disabled"

v1: update for SLPC v2015.2.4
    dfps and turbo merged and renamed "gtperf"
    ibc split out and renamed "balancer"
    Avoid magic numbers (Jon Bloomfield)

v2-v3: Rebase.

v5: Moved slpc_enable_disable_set and slpc_enable_disable_get to
    intel_slpc.c. s/slpc_enable_disable_get/intel_slpc_task_status
    and s/slpc_enable_disable_set/intel_slpc_task_control. Prepared
    separate functions to update the task status only in the SLPC
    shared memory. Passing dev_priv as parameter.

v6: Rebase. s/slpc_param_show|write/slpc_task_param_show|write.
    Moved functions to intel_slpc.c. RPM Get/Put added before setting
    parameters and sending RESET event explicitly. (Sagar)

v7: Rebase.

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
Cc: Jeff McGee <jeff.mcgee@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 200 ++++++++++++++++++++++++++++++++++++
 1 file changed, 200 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index ff90577..d646a04 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2580,6 +2580,203 @@ static const struct file_operations i915_guc_log_relay_fops = {
 	.release = i915_guc_log_relay_release,
 };
 
+static const char *slpc_task_status_stringify(int state)
+{
+	const char *str = NULL;
+
+	switch (state) {
+	case SLPC_PARAM_TASK_DEFAULT:
+		str = "default\n";
+		break;
+
+	case SLPC_PARAM_TASK_ENABLED:
+		str = "enabled\n";
+		break;
+
+	case SLPC_PARAM_TASK_DISABLED:
+		str = "disabled\n";
+		break;
+
+	default:
+		str = "unknown\n";
+		break;
+	}
+
+	return str;
+}
+
+static int slpc_task_status_show(struct seq_file *m,
+				 u32 enable_id,
+				 u32 disable_id)
+{
+	struct drm_i915_private *dev_priv = m->private;
+	struct intel_guc_slpc *slpc = &dev_priv->guc.slpc;
+	const char *status = NULL;
+	u64 val;
+	int ret;
+
+	mutex_lock(&slpc->lock);
+	ret = intel_guc_slpc_task_status(slpc, &val, enable_id, disable_id);
+	mutex_unlock(&slpc->lock);
+
+	if (!ret)
+		status = slpc_task_status_stringify(val);
+
+	seq_printf(m, "%s", status);
+
+	return 0;
+}
+
+static int slpc_task_status_write(struct seq_file *m,
+				  const char __user *ubuf,
+				  size_t len,
+				  u32 enable_id,
+				  u32 disable_id)
+{
+	struct drm_i915_private *dev_priv = m->private;
+	struct intel_guc_slpc *slpc = &dev_priv->guc.slpc;
+	int ret = 0;
+	char status[10];
+	u64 val;
+
+	if (len >= sizeof(status))
+		ret = -EINVAL;
+	else if (copy_from_user(status, ubuf, len))
+		ret = -EFAULT;
+	else
+		status[len] = '\0';
+
+	if (ret)
+		return ret;
+
+	if (!strncmp(status, "default", 7))
+		val = SLPC_PARAM_TASK_DEFAULT;
+	else if (!strncmp(status, "enabled", 7))
+		val = SLPC_PARAM_TASK_ENABLED;
+	else if (!strncmp(status, "disabled", 8))
+		val = SLPC_PARAM_TASK_DISABLED;
+	else
+		return -EINVAL;
+
+	mutex_lock(&slpc->lock);
+	ret = intel_guc_slpc_task_control(slpc, val, enable_id, disable_id);
+	mutex_unlock(&slpc->lock);
+
+	return ret;
+}
+
+static int slpc_gtperf_show(struct seq_file *m, void *data)
+{
+	return slpc_task_status_show(m,
+				     SLPC_PARAM_TASK_ENABLE_GTPERF,
+				     SLPC_PARAM_TASK_DISABLE_GTPERF);
+}
+
+static int i915_guc_slpc_gtperf_open(struct inode *inode, struct file *file)
+{
+	struct drm_i915_private *dev_priv = inode->i_private;
+
+	return single_open(file, slpc_gtperf_show, dev_priv);
+}
+
+static ssize_t i915_guc_slpc_gtperf_write(struct file *file,
+					  const char __user *ubuf,
+					  size_t len,
+					  loff_t *offp)
+{
+	struct seq_file *m = file->private_data;
+	int ret = 0;
+
+	ret = slpc_task_status_write(m, ubuf, len,
+				     SLPC_PARAM_TASK_ENABLE_GTPERF,
+				     SLPC_PARAM_TASK_DISABLE_GTPERF);
+
+	return ret ?: len;
+}
+
+const struct file_operations i915_guc_slpc_gtperf_fops = {
+	.owner	 = THIS_MODULE,
+	.open	 = i915_guc_slpc_gtperf_open,
+	.release = single_release,
+	.read	 = seq_read,
+	.write	 = i915_guc_slpc_gtperf_write,
+	.llseek	 = seq_lseek
+};
+
+static int slpc_balancer_show(struct seq_file *m, void *data)
+{
+	return slpc_task_status_show(m,
+				     SLPC_PARAM_TASK_ENABLE_BALANCER,
+				     SLPC_PARAM_TASK_DISABLE_BALANCER);
+}
+
+static int i915_guc_slpc_balancer_open(struct inode *inode, struct file *file)
+{
+	struct drm_i915_private *dev_priv = inode->i_private;
+
+	return single_open(file, slpc_balancer_show, dev_priv);
+}
+
+static ssize_t i915_guc_slpc_balancer_write(struct file *file,
+					    const char __user *ubuf,
+					    size_t len,
+					    loff_t *offp)
+{
+	struct seq_file *m = file->private_data;
+	int ret = 0;
+
+	ret = slpc_task_status_write(m, ubuf, len,
+				     SLPC_PARAM_TASK_ENABLE_BALANCER,
+				     SLPC_PARAM_TASK_DISABLE_BALANCER);
+	return ret ?: len;
+}
+
+const struct file_operations i915_guc_slpc_balancer_fops = {
+	.owner	 = THIS_MODULE,
+	.open	 = i915_guc_slpc_balancer_open,
+	.release = single_release,
+	.read	 = seq_read,
+	.write	 = i915_guc_slpc_balancer_write,
+	.llseek	 = seq_lseek
+};
+
+static int slpc_dcc_show(struct seq_file *m, void *data)
+{
+	return slpc_task_status_show(m,
+				     SLPC_PARAM_TASK_ENABLE_DCC,
+				     SLPC_PARAM_TASK_DISABLE_DCC);
+}
+
+static int i915_guc_slpc_dcc_open(struct inode *inode, struct file *file)
+{
+	struct drm_i915_private *dev_priv = inode->i_private;
+
+	return single_open(file, slpc_dcc_show, dev_priv);
+}
+
+static ssize_t i915_guc_slpc_dcc_write(struct file *file,
+				       const char __user *ubuf,
+				       size_t len,
+				       loff_t *offp)
+{
+	struct seq_file *m = file->private_data;
+	int ret = 0;
+
+	ret = slpc_task_status_write(m, ubuf, len,
+				     SLPC_PARAM_TASK_ENABLE_DCC,
+				     SLPC_PARAM_TASK_DISABLE_DCC);
+	return ret ?: len;
+}
+
+const struct file_operations i915_guc_slpc_dcc_fops = {
+	.owner	 = THIS_MODULE,
+	.open	 = i915_guc_slpc_dcc_open,
+	.release = single_release,
+	.read	 = seq_read,
+	.write	 = i915_guc_slpc_dcc_write,
+	.llseek	 = seq_lseek
+};
+
 static const char *psr2_live_status(u32 val)
 {
 	static const char * const live_status[] = {
@@ -4810,6 +5007,9 @@ static const struct i915_debugfs_files {
 	{"i915_dp_test_active", &i915_displayport_test_active_fops},
 	{"i915_guc_log_level", &i915_guc_log_level_fops},
 	{"i915_guc_log_relay", &i915_guc_log_relay_fops},
+	{"i915_guc_slpc_gtperf", &i915_guc_slpc_gtperf_fops},
+	{"i915_guc_slpc_balancer", &i915_guc_slpc_balancer_fops},
+	{"i915_guc_slpc_dcc", &i915_guc_slpc_dcc_fops},
 	{"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops},
 	{"i915_ipc_status", &i915_ipc_status_fops},
 	{"i915_drrs_ctl", &i915_drrs_ctl_fops}
-- 
2.7.4

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[PATCH v12 13/17] drm/i915/debugfs: Create generic string tokenize function and update CRC control parsing

[Sagar Arun Kamble]

Input string parsing used in CRC control parameter parsing is generic and
can be reused for other debugfs interfaces. We plan to use this in the
next patch for SLPC debugfs control. Hence name it as buffer_tokenize
instead of tying to display_crc. Also fix the function desciption for CRC
control parsing that was misplaced at tokenize function.

v2: Moved buffer_tokenize to i915_debugfs.c (Michal Wajdeczko)

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Acked-by: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c   | 31 +++++++++++++++++++
 drivers/gpu/drm/i915/i915_drv.h       |  1 +
 drivers/gpu/drm/i915/intel_pipe_crc.c | 57 ++++++++---------------------------
 3 files changed, 45 insertions(+), 44 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index d646a04..5c1231f 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -5158,3 +5158,34 @@ int i915_debugfs_connector_add(struct drm_connector *connector)
 
 	return 0;
 }
+
+int buffer_tokenize(char *buf, char *words[], int max_words)
+{
+	int n_words = 0;
+
+	while (*buf) {
+		char *end;
+
+		/* skip leading white space */
+		buf = skip_spaces(buf);
+		if (!*buf)
+			break;	/* end of buffer */
+
+		/* find end of word */
+		for (end = buf; *end && !isspace(*end); end++)
+			;
+
+		if (n_words == max_words) {
+			DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
+					 max_words);
+			return -EINVAL;	/* ran out of words[] before bytes */
+		}
+
+		if (*end)
+			*end++ = '\0';
+		words[n_words++] = buf;
+		buf = end;
+	}
+
+	return n_words;
+}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d17e778..7473d34 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3326,6 +3326,7 @@ u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
 int i915_debugfs_register(struct drm_i915_private *dev_priv);
 int i915_debugfs_connector_add(struct drm_connector *connector);
 void intel_display_crc_init(struct drm_i915_private *dev_priv);
+int buffer_tokenize(char *buf, char *words[], int max_words);
 #else
 static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;}
 static inline int i915_debugfs_connector_add(struct drm_connector *connector)
diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c b/drivers/gpu/drm/i915/intel_pipe_crc.c
index 4f367c1..6519526 100644
--- a/drivers/gpu/drm/i915/intel_pipe_crc.c
+++ b/drivers/gpu/drm/i915/intel_pipe_crc.c
@@ -710,49 +710,6 @@ static int pipe_crc_set_source(struct drm_i915_private *dev_priv,
 	return ret;
 }
 
-/*
- * Parse pipe CRC command strings:
- *   command: wsp* object wsp+ name wsp+ source wsp*
- *   object: 'pipe'
- *   name: (A | B | C)
- *   source: (none | plane1 | plane2 | pf)
- *   wsp: (#0x20 | #0x9 | #0xA)+
- *
- * eg.:
- *  "pipe A plane1"  ->  Start CRC computations on plane1 of pipe A
- *  "pipe A none"    ->  Stop CRC
- */
-static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
-{
-	int n_words = 0;
-
-	while (*buf) {
-		char *end;
-
-		/* skip leading white space */
-		buf = skip_spaces(buf);
-		if (!*buf)
-			break;	/* end of buffer */
-
-		/* find end of word */
-		for (end = buf; *end && !isspace(*end); end++)
-			;
-
-		if (n_words == max_words) {
-			DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
-					 max_words);
-			return -EINVAL;	/* ran out of words[] before bytes */
-		}
-
-		if (*end)
-			*end++ = '\0';
-		words[n_words++] = buf;
-		buf = end;
-	}
-
-	return n_words;
-}
-
 enum intel_pipe_crc_object {
 	PIPE_CRC_OBJECT_PIPE,
 };
@@ -807,6 +764,18 @@ display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
 	return -EINVAL;
 }
 
+/*
+ * Parse pipe CRC command strings:
+ *   command: wsp* object wsp+ name wsp+ source wsp*
+ *   object: 'pipe'
+ *   name: (A | B | C)
+ *   source: (none | plane1 | plane2 | pf)
+ *   wsp: (#0x20 | #0x9 | #0xA)+
+ *
+ * eg.:
+ *  "pipe A plane1"  ->  Start CRC computations on plane1 of pipe A
+ *  "pipe A none"    ->  Stop CRC
+ */
 static int display_crc_ctl_parse(struct drm_i915_private *dev_priv,
 				 char *buf, size_t len)
 {
@@ -817,7 +786,7 @@ static int display_crc_ctl_parse(struct drm_i915_private *dev_priv,
 	enum intel_pipe_crc_object object;
 	enum intel_pipe_crc_source source;
 
-	n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
+	n_words = buffer_tokenize(buf, words, N_WORDS);
 	if (n_words != N_WORDS) {
 		DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
 				 N_WORDS);
-- 
2.7.4

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[PATCH v12 14/17] drm/i915/guc/slpc: Add debugfs support to read/write/revert the parameters

[Sagar Arun Kamble]

Add support to set/read parameters and unset the parameters which will
revert them to default SLPC internal values. Explicit SLPC reset is needed
on setting/unsetting some of the parameters.

This patch adds two debugfs interfaces:
1. i915_guc_slpc_params: List of all parameters that Host can configure.
   Currently listing id and description of each.
2. i915_guc_slpc_param_ctl: This allows to change the parameters.
   Syntax is:
   * Update parameter with id <id> with value <value>:
     echo "write <id> <value>" > i915_guc_slpc_param_ctl
   * Read parameter with id <id>
     echo "read <id>" > i915_guc_slpc_param_ctl
     cat i915_guc_slpc_param_ctl
   * Revert parameter with id <id> to default value
     echo "revert <id>" > i915_guc_slpc_param_ctl.

v2: Moved the SLPC interfaces to i915_debugfs.c. Added error handling to
the range of parameters and parsing. Making use of intel_guc_slpc_enabled
instead of accessing status variable. Optimized token parsing.
(Michal Wajdeczko) s/i915_slpc_paramlist/i915_guc_slpc_params and
s/i915_slpc_param_ctl/i915_guc_slpc_param_ctl

v3: Rebase.

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
Cc: Jeff McGee <jeff.mcgee@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c        | 156 +++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_guc_slpc.c      |  87 ++++++++++++++++
 drivers/gpu/drm/i915/intel_guc_slpc.h      |  18 ++++
 drivers/gpu/drm/i915/intel_guc_slpc_fwif.h |  23 +++++
 4 files changed, 284 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 5c1231f..f90ad52 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2777,6 +2777,160 @@ const struct file_operations i915_guc_slpc_dcc_fops = {
 	.llseek	 = seq_lseek
 };
 
+static int i915_guc_slpc_params_info(struct seq_file *m, void *data)
+{
+	struct drm_i915_private *dev_priv = node_to_i915(m->private);
+	struct drm_printer p = drm_seq_file_printer(m);
+
+	if (!USES_GUC_SLPC(dev_priv))
+		return -ENODEV;
+
+	intel_guc_slpc_params_print(&dev_priv->guc.slpc, &p);
+
+	return 0;
+}
+
+static int slpc_param_ctl_show(struct seq_file *m, void *data)
+{
+	struct drm_i915_private *dev_priv = m->private;
+	struct intel_guc_slpc *slpc = &dev_priv->guc.slpc;
+
+	if (!USES_GUC_SLPC(dev_priv))
+		return -ENODEV;
+
+	if (slpc->debug.param_id >= SLPC_MAX_PARAM)
+		return -EINVAL;
+
+	BUILD_BUG_ON(ARRAY_SIZE(slpc_params_desc) != SLPC_MAX_PARAM);
+
+	seq_printf(m, "%s=%u, override=%s\n",
+			slpc_params_desc[slpc->debug.param_id],
+			slpc->debug.param_value,
+			yesno(!!slpc->debug.param_override));
+
+	return 0;
+}
+
+static int slpc_param_ctl_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, slpc_param_ctl_show, inode->i_private);
+}
+
+/*
+ * Parse SLPC parameter control strings: (Similar to Pipe CRC handling)
+ *   command: wsp* op wsp+ param id wsp+ [value] wsp*
+ *   op: "read"/"write"/"revert"
+ *   param id: slpc_param_id
+ *   value: u32 value
+ *   wsp: (#0x20 | #0x9 | #0xA)+
+ *
+ * eg.:
+ *  "read 0"		-> read SLPC_PARAM_TASK_ENABLE_GTPERF
+ *  "write 7 500"	-> set SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ to 500MHz
+ *  "revert 7"		-> revert SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ to
+ *			   default value.
+ */
+static int slpc_param_ctl_parse(char *buf, size_t len, int *op,
+				u32 *id, u32 *value)
+{
+#define MAX_WORDS 3
+	int n_words;
+	char *words[MAX_WORDS];
+	ssize_t ret;
+
+	n_words = buffer_tokenize(buf, words, MAX_WORDS);
+	if (!(n_words == 3) && !(n_words == 2)) {
+		DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
+				 MAX_WORDS);
+		return -EINVAL;
+	}
+
+	if (!strcmp(words[0], "read"))
+		*op = READ_OP;
+	else if (!strcmp(words[0], "write"))
+		*op = WRITE_OP;
+	else if (!strcmp(words[0], "revert"))
+		*op = REVERT_OP;
+	else {
+		DRM_DEBUG_DRIVER("unknown operation\n");
+		return -EINVAL;
+	}
+
+	ret = kstrtou32(words[1], 0, id);
+	if (ret)
+		return ret;
+
+	if (n_words == 3) {
+		ret = kstrtou32(words[2], 0, value);
+		if (ret)
+			return ret;
+	}
+
+	return (n_words-1);
+}
+
+static ssize_t slpc_param_ctl_write(struct file *file, const char __user *ubuf,
+				     size_t len, loff_t *offp)
+{
+	struct seq_file *m = file->private_data;
+	struct drm_i915_private *dev_priv = m->private;
+	struct intel_guc_slpc *slpc = &dev_priv->guc.slpc;
+	char *tmpbuf;
+	u32 id, value;
+	int op, params;
+	int ret = 0;
+
+	if (len == 0)
+		return 0;
+
+	if (len > 40) {
+		DRM_DEBUG_DRIVER("expected <40 chars into slpc_param_ctl\n");
+		return -E2BIG;
+	}
+
+	tmpbuf = kmalloc(len + 1, GFP_KERNEL);
+	if (!tmpbuf)
+		return -ENOMEM;
+
+	if (copy_from_user(tmpbuf, ubuf, len)) {
+		ret = -EFAULT;
+		goto out;
+	}
+	tmpbuf[len] = '\0';
+
+	params = slpc_param_ctl_parse(tmpbuf, len, &op, &id, &value);
+
+	if (params < 0 || id >= SLPC_MAX_PARAM) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	intel_runtime_pm_get(dev_priv);
+	mutex_lock(&slpc->lock);
+
+	ret = intel_guc_slpc_param_control(slpc, params, op, id, value);
+
+	mutex_unlock(&slpc->lock);
+	intel_runtime_pm_put(dev_priv);
+
+out:
+	kfree(tmpbuf);
+	if (ret < 0)
+		return ret;
+
+	*offp += len;
+	return len;
+}
+
+const struct file_operations i915_guc_slpc_param_ctl_fops = {
+	.owner = THIS_MODULE,
+	.open = slpc_param_ctl_open,
+	.read = seq_read,
+	.llseek = seq_lseek,
+	.release = single_release,
+	.write = slpc_param_ctl_write
+};
+
 static const char *psr2_live_status(u32 val)
 {
 	static const char * const live_status[] = {
@@ -4942,6 +5096,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
 	{"i915_guc_log_dump", i915_guc_log_dump, 0},
 	{"i915_guc_load_err_log_dump", i915_guc_log_dump, 0, (void *)1},
 	{"i915_guc_stage_pool", i915_guc_stage_pool, 0},
+	{"i915_guc_slpc_params", i915_guc_slpc_params_info, 0},
 	{"i915_huc_load_status", i915_huc_load_status_info, 0},
 	{"i915_frequency_info", i915_frequency_info, 0},
 	{"i915_hangcheck_info", i915_hangcheck_info, 0},
@@ -5010,6 +5165,7 @@ static const struct i915_debugfs_files {
 	{"i915_guc_slpc_gtperf", &i915_guc_slpc_gtperf_fops},
 	{"i915_guc_slpc_balancer", &i915_guc_slpc_balancer_fops},
 	{"i915_guc_slpc_dcc", &i915_guc_slpc_dcc_fops},
+	{"i915_guc_slpc_param_ctl", &i915_guc_slpc_param_ctl_fops},
 	{"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops},
 	{"i915_ipc_status", &i915_ipc_status_fops},
 	{"i915_drrs_ctl", &i915_drrs_ctl_fops}
diff --git a/drivers/gpu/drm/i915/intel_guc_slpc.c b/drivers/gpu/drm/i915/intel_guc_slpc.c
index 34a5963..7bd5e3e 100644
--- a/drivers/gpu/drm/i915/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/intel_guc_slpc.c
@@ -578,6 +578,93 @@ int intel_guc_slpc_task_status(struct intel_guc_slpc *slpc, u64 *val,
 }
 
 /**
+ * intel_guc_slpc_params_print() - print parameters list.
+ * @slpc: pointer to intel_guc_slpc.
+ * @p: drm printer
+ *
+ * This function will print SLPC parameters id and their description.
+ *
+ */
+void intel_guc_slpc_params_print(struct intel_guc_slpc *slpc,
+				 struct drm_printer *p)
+{
+	int i;
+
+	BUILD_BUG_ON(ARRAY_SIZE(slpc_params_desc) != SLPC_MAX_PARAM);
+
+	drm_printf(p, "Param id\tParam description\n");
+	for (i = 0; i < ARRAY_SIZE(slpc_params_desc); i++)
+		drm_printf(p, "%8d\t%s\n", i, slpc_params_desc[i]);
+}
+
+/**
+ * intel_guc_slpc_param_control() - read/write/revert parameter.
+ * @slpc: pointer to intel_guc_slpc.
+ * @params: number of parameters
+ * @op: operation (read, write, revert)
+ * @id: parameter id
+ * @value: parameter value
+ *
+ * This function will create object to be shared with GuC SLPC and
+ * initialize it with required initial parameter values for various
+ * SLPC knobs such as min frequency limit, enabling/disabling of SLPC
+ * tasks etc.
+ *
+ * Return: 0 on success, non-zero error code on failure.
+ */
+int intel_guc_slpc_param_control(struct intel_guc_slpc *slpc,
+				 u32 params, u32 op, u32 id, u32 value)
+{
+	int ret = 0;
+
+	GEM_BUG_ON(!slpc->vma);
+
+	lockdep_assert_held(&slpc->lock);
+
+	if (op == READ_OP) {
+		if (params != 1) {
+			ret = -EINVAL;
+			goto out;
+		}
+		slpc_get_param(slpc, id,
+			       &slpc->debug.param_override,
+			       &slpc->debug.param_value);
+		slpc->debug.param_id = id;
+	} else if ((op == WRITE_OP) || (op == REVERT_OP)) {
+		if ((id >= SLPC_PARAM_TASK_ENABLE_GTPERF) &&
+		    (id <= SLPC_PARAM_TASK_DISABLE_DCC)) {
+			DRM_DEBUG_DRIVER("Tasks are not controlled by "
+					 "this interface\n");
+			ret = -EINVAL;
+			goto out;
+		}
+
+		/*
+		 * After updating parameters, RESET event has to be sent to GuC
+		 * SLPC for ensuring parameters take effect.
+		 */
+		if (op == WRITE_OP) {
+			if (params != 2) {
+				ret = -EINVAL;
+				goto out;
+			}
+			slpc_set_param(slpc, id, value);
+		} else {
+			if (params != 1) {
+				ret = -EINVAL;
+				goto out;
+			}
+			slpc_unset_param(slpc, id);
+		}
+		host2guc_slpc_reset(slpc);
+	}
+
+out:
+
+	return ret;
+}
+
+/**
  * intel_guc_slpc_init() - Initialize the SLPC shared data structure.
  * @slpc: pointer to intel_guc_slpc.
  *
diff --git a/drivers/gpu/drm/i915/intel_guc_slpc.h b/drivers/gpu/drm/i915/intel_guc_slpc.h
index 51189b3..693343e 100644
--- a/drivers/gpu/drm/i915/intel_guc_slpc.h
+++ b/drivers/gpu/drm/i915/intel_guc_slpc.h
@@ -8,6 +8,8 @@
 
 #include <intel_guc_slpc_fwif.h>
 
+struct drm_printer;
+
 struct intel_guc_slpc {
 	/* Protects access to vma and SLPC actions */
 	struct mutex lock;
@@ -16,12 +18,28 @@ struct intel_guc_slpc {
 	/* i915 cached SLPC frequency limits */
 	u32 min_unslice_freq;
 	u32 max_unslice_freq;
+
+	struct {
+		u32 param_id;
+		u32 param_value;
+		u32 param_override;
+	} debug;
+};
+
+enum {
+	READ_OP,
+	WRITE_OP,
+	REVERT_OP
 };
 
 int intel_guc_slpc_task_control(struct intel_guc_slpc *slpc, u64 val,
 				u32 enable_id, u32 disable_id);
 int intel_guc_slpc_task_status(struct intel_guc_slpc *slpc, u64 *val,
 			       u32 enable_id, u32 disable_id);
+void intel_guc_slpc_params_print(struct intel_guc_slpc *slpc,
+				 struct drm_printer *p);
+int intel_guc_slpc_param_control(struct intel_guc_slpc *slpc,
+				 u32 params, u32 op, u32 id, u32 value);
 
 int intel_guc_slpc_init(struct intel_guc_slpc *slpc);
 int intel_guc_slpc_enable(struct intel_guc_slpc *slpc);
diff --git a/drivers/gpu/drm/i915/intel_guc_slpc_fwif.h b/drivers/gpu/drm/i915/intel_guc_slpc_fwif.h
index 9400af4..65bbb03 100644
--- a/drivers/gpu/drm/i915/intel_guc_slpc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_slpc_fwif.h
@@ -71,6 +71,29 @@ enum slpc_param_id {
 	SLPC_KMD_MAX_PARAM = 32,
 };
 
+static const char * const slpc_params_desc[] = {
+	"Enable task GTPERF",
+	"Disable task GTPERF",
+	"Enable task BALANCER",
+	"Disable task BALANCER",
+	"Enable task DCC",
+	"Disable task DCC",
+	"Minimum GT frequency request for unslice",
+	"Maximum GT frequency request for unslice",
+	"Minimum GT frequency request for slice",
+	"Maximum GT frequency request for slice",
+	"If non-zero, will slow down frame-based apps to this frame-rate",
+	"Lock GT frequency request to RPe",
+	"Set to TRUE to enable slowing framerate",
+	"Prevent from changing the RC mode",
+	"Override fused value of unslice RP0",
+	"Override fused value of slice RP0",
+	"TRUE means enable Intelligent Bias Control",
+	"TRUE = enable eval mode when transitioning from idle to active.",
+	"FALSE = disable eval mode completely",
+	"Enable IBC when non-Gaming Mode is enabled"
+};
+
 enum slpc_global_state {
 	SLPC_GLOBAL_STATE_NOT_RUNNING = 0,
 	SLPC_GLOBAL_STATE_INITIALIZING = 1,
-- 
2.7.4

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[PATCH v12 15/17] drm/i915/guc/slpc: Add i915_guc_slpc_info to debugfs

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

i915_guc_slpc_info shows the contents of SLPC shared data parsed into text
format.

v1: Reformat slpc info (Radek). Squashed query task state info in slpc
    info, kunmap before seq_print (Paulo) Return void instead of ignored
    return value (Paulo)
    Avoid magic numbers and use local variables (Jon Bloomfield). Removed
    WARN_ON for checking msb of gtt address of shared gem obj. (Chris)
    Moved definition of power plan and power source to earlier patch in
    the series. drm/i915/slpc: Allocate/Release/Initialize SLPC shared
    data (Akash)

v2-v3: Rebase.

v4: Updated with GuC firmware v9.

v5: Updated host2guc_slpc_query_task_state with struct slpc_input_event
    structure. Removed unnecessary checks of vma from i915_slpc_info.
    Created helpers for reading the SLPC shared data and string form of
    SLPC state. (Sagar)

v6: s/i915_slpc_info/i915_guc_slpc_info. Prepared helpers platform_sku
    _to_string, power_plan_to_string and power_source_to_string.
    (Michal Wajdeczko)

v7: Moved all SLPC data printing changes to guc_slpc.c and making use of
    drm_printer.

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
Cc: Jeff McGee <jeff.mcgee@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c   |  10 ++
 drivers/gpu/drm/i915/intel_guc_slpc.c | 193 ++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_guc_slpc.h |   2 +
 3 files changed, 205 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index f90ad52..1a66507 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1053,6 +1053,15 @@ DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
 			NULL, i915_next_seqno_set,
 			"0x%llx\n");
 
+static int i915_guc_slpc_info(struct seq_file *m, void *unused)
+{
+	struct drm_i915_private *dev_priv = node_to_i915(m->private);
+	struct intel_guc_slpc *slpc = &dev_priv->guc.slpc;
+	struct drm_printer p = drm_seq_file_printer(m);
+
+	return intel_guc_slpc_info(slpc, &p);
+}
+
 static int i915_frequency_info(struct seq_file *m, void *unused)
 {
 	struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -5097,6 +5106,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
 	{"i915_guc_load_err_log_dump", i915_guc_log_dump, 0, (void *)1},
 	{"i915_guc_stage_pool", i915_guc_stage_pool, 0},
 	{"i915_guc_slpc_params", i915_guc_slpc_params_info, 0},
+	{"i915_guc_slpc_info", i915_guc_slpc_info, 0},
 	{"i915_huc_load_status", i915_huc_load_status_info, 0},
 	{"i915_frequency_info", i915_frequency_info, 0},
 	{"i915_hangcheck_info", i915_hangcheck_info, 0},
diff --git a/drivers/gpu/drm/i915/intel_guc_slpc.c b/drivers/gpu/drm/i915/intel_guc_slpc.c
index 7bd5e3e..94c6c19 100644
--- a/drivers/gpu/drm/i915/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/intel_guc_slpc.c
@@ -487,6 +487,199 @@ static void slpc_get_param(struct intel_guc_slpc *slpc, u32 id,
 	kunmap_atomic(data);
 }
 
+static const char *slpc_platform_sku_stringify(int platform_sku)
+{
+	const char *str = NULL;
+
+	switch (platform_sku) {
+	case SLPC_PLATFORM_SKU_UNDEFINED:
+		str = "undefined";
+		break;
+	case SLPC_PLATFORM_SKU_ULX:
+		str = "ULX";
+		break;
+	case SLPC_PLATFORM_SKU_ULT:
+		str = "ULT";
+		break;
+	case SLPC_PLATFORM_SKU_T:
+		str = "T";
+		break;
+	case SLPC_PLATFORM_SKU_MOBL:
+		str = "Mobile";
+		break;
+	case SLPC_PLATFORM_SKU_DT:
+		str = "DT";
+		break;
+	case SLPC_PLATFORM_SKU_UNKNOWN:
+	default:
+		str = "unknown";
+		break;
+	}
+
+	return str;
+}
+
+static const char *slpc_power_plan_stringify(int power_plan)
+{
+	const char *str = NULL;
+
+	switch (power_plan) {
+	case SLPC_POWER_PLAN_UNDEFINED:
+		str = "undefined";
+		break;
+	case SLPC_POWER_PLAN_BATTERY_SAVER:
+		str = "battery saver";
+		break;
+	case SLPC_POWER_PLAN_BALANCED:
+		str = "balanced";
+		break;
+	case SLPC_POWER_PLAN_PERFORMANCE:
+		str = "performance";
+		break;
+	case SLPC_POWER_PLAN_UNKNOWN:
+	default:
+		str = "unknown";
+		break;
+	}
+
+	return str;
+}
+
+static const char *slpc_power_source_stringify(int power_source)
+{
+	const char *str = NULL;
+
+	switch (power_source) {
+	case SLPC_POWER_SOURCE_UNDEFINED:
+		str = "undefined";
+		break;
+	case SLPC_POWER_SOURCE_AC:
+		str = "AC";
+		break;
+	case SLPC_POWER_SOURCE_DC:
+		str = "DC";
+		break;
+	case SLPC_POWER_SOURCE_UNKNOWN:
+	default:
+		str = "unknown";
+		break;
+	}
+
+	return str;
+}
+
+int intel_guc_slpc_info(struct intel_guc_slpc *slpc, struct drm_printer *p)
+{
+	struct intel_guc *guc = slpc_to_guc(slpc);
+	struct drm_i915_private *dev_priv = guc_to_i915(guc);
+	struct slpc_shared_data data;
+	struct slpc_platform_info *platform_info;
+	struct slpc_task_state_data *task_data;
+	int i, value;
+
+	if (!USES_GUC_SLPC(dev_priv))
+		return -ENODEV;
+
+	GEM_BUG_ON(!slpc->vma);
+
+	intel_runtime_pm_get(dev_priv);
+	mutex_lock(&slpc->lock);
+
+	slpc_read_shared_data(slpc, &data);
+
+	mutex_unlock(&slpc->lock);
+	intel_runtime_pm_put(dev_priv);
+
+	platform_info = &data.platform_info;
+
+	drm_printf(p, "shared data size: %d\n", data.shared_data_size);
+
+	value = data.global_state;
+	drm_printf(p, "global state: %d (", value);
+	drm_printf(p, "%s)\n", slpc_state_stringify(value));
+
+	value = platform_info->sku;
+	drm_printf(p, "sku: %d (%s)\n",
+		   value, slpc_platform_sku_stringify(value));
+	drm_printf(p, "slice count: %d\n", platform_info->slice_count);
+
+	value = SLPC_POWER_PLAN(platform_info->power_plan_source);
+	drm_printf(p, "power plan/source: 0x%x\n\tplan:\t%s",
+		   platform_info->power_plan_source,
+		   slpc_power_plan_stringify(value));
+
+	value = SLPC_POWER_SOURCE(platform_info->power_plan_source);
+	drm_printf(p, "\n\tsource:\t%s\n",
+		   slpc_power_source_stringify(value));
+
+	drm_printf(p,
+		   "IA frequency (MHz):\n\tP0: %d\n\tP1: %d\n\t"
+		   "Pe: %d\n\tPn: %d\n",
+		   platform_info->p0_freq * 50,
+		   platform_info->p1_freq * 50,
+		   platform_info->pe_freq * 50,
+		   platform_info->pn_freq * 50);
+
+	task_data = &data.task_state_data;
+	drm_printf(p, "task state data: 0x%08x 0x%08x\n",
+		   task_data->bitfield1, task_data->bitfield2);
+
+	drm_printf(p, "\tgtperf task active: %s\n",
+		   yesno(task_data->gtperf_task_active));
+	drm_printf(p, "\tgtperf stall possible: %s\n",
+		   yesno(task_data->gtperf_stall_possible));
+	drm_printf(p, "\tgtperf gaming mode: %s\n",
+		   yesno(task_data->gtperf_gaming_mode));
+	drm_printf(p, "\tgtperf target fps: %d\n",
+		   task_data->gtperf_target_fps);
+
+	drm_printf(p, "\tdcc task active: %s\n",
+		   yesno(task_data->dcc_task_active));
+	drm_printf(p, "\tin dcc: %s\n",
+		   yesno(task_data->in_dcc));
+	drm_printf(p, "\tin dct: %s\n",
+		   yesno(task_data->in_dct));
+	drm_printf(p, "\tfreq switch active: %s\n",
+		   yesno(task_data->freq_switch_active));
+
+	drm_printf(p, "\tibc enabled: %s\n",
+		   yesno(task_data->ibc_enabled));
+	drm_printf(p, "\tibc active: %s\n",
+		   yesno(task_data->ibc_active));
+	drm_printf(p, "\tpg1 enabled: %s\n",
+		   yesno(task_data->pg1_enabled));
+	drm_printf(p, "\tpg1 active: %s\n",
+		   yesno(task_data->pg1_active));
+
+	drm_printf(p, "\tunslice max freq: %dMHz\n",
+		   intel_gpu_freq(dev_priv,
+			task_data->max_unslice_freq * GEN9_FREQ_SCALER));
+	drm_printf(p, "\tunslice min freq: %dMHz\n",
+		   intel_gpu_freq(dev_priv,
+			task_data->min_unslice_freq * GEN9_FREQ_SCALER));
+	drm_printf(p, "\tslice max freq: %dMHz\n",
+		   intel_gpu_freq(dev_priv,
+			task_data->max_slice_freq * GEN9_FREQ_SCALER));
+	drm_printf(p, "\tslice min freq: %dMHz\n",
+		   intel_gpu_freq(dev_priv,
+			task_data->min_slice_freq * GEN9_FREQ_SCALER));
+
+	drm_printf(p, "override parameter bitfield\n");
+	for (i = 0; i < SLPC_OVERRIDE_BITFIELD_SIZE; i++)
+		drm_printf(p, "%d: 0x%08x\n", i,
+			   data.override_params_set_bits[i]);
+
+	drm_printf(p, "override parameters (only non-zero shown)\n");
+	for (i = 0; i < SLPC_MAX_OVERRIDE_PARAMETERS; i++) {
+		value = data.override_params_values[i];
+		if (value)
+			drm_printf(p, "%d: 0x%8x\n", i, value);
+	}
+
+	return 0;
+}
+
+
 /**
  * intel_guc_slpc_task_control() - Update status of SLPC task.
  * @slpc: pointer to intel_guc_slpc.
diff --git a/drivers/gpu/drm/i915/intel_guc_slpc.h b/drivers/gpu/drm/i915/intel_guc_slpc.h
index 693343e..edb0dec 100644
--- a/drivers/gpu/drm/i915/intel_guc_slpc.h
+++ b/drivers/gpu/drm/i915/intel_guc_slpc.h
@@ -41,6 +41,8 @@ void intel_guc_slpc_params_print(struct intel_guc_slpc *slpc,
 int intel_guc_slpc_param_control(struct intel_guc_slpc *slpc,
 				 u32 params, u32 op, u32 id, u32 value);
 
+int intel_guc_slpc_info(struct intel_guc_slpc *slpc, struct drm_printer *p);
+
 int intel_guc_slpc_init(struct intel_guc_slpc *slpc);
 int intel_guc_slpc_enable(struct intel_guc_slpc *slpc);
 int intel_guc_slpc_max_freq_set(struct intel_guc_slpc *slpc, u32 val);
-- 
2.7.4

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[PATCH v12 16/17] drm/i915/guc/slpc: Add SLPC banner to RPS debugfs interfaces

[Sagar Arun Kamble]

When SLPC is controlling frequency requests, RPS state related to
autotuning is no longer valid. Make user aware through banner
upfront. Value read from register RPNSWREQ likely has the frequency
requested last by GuC SLPC.

v1: Replace HAS_SLPC with intel_slpc_active (Paulo)
    Avoid magic numbers (Nick)
    Use a function for repeated code (Jon)

v2: Add "SLPC Active" to i915_frequency_info output and
    don't update cur_freq as it is driver internal request. (Chris)

v3: Removing sysfs interface gt_req_freq_mhz out of this patch
    for proper division of functionality. (Sagar)

v4: idle_freq, boost_freq are also not used with SLPC.

v5: Added SLPC banner to i915_rps_boost_info and keep printing
    driver internal values. (Chris)

v6: Commit message update.

v7: Rebase.

v8: Rebase.

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
Cc: Jeff McGee <jeff.mcgee@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 1a66507..5d2ac24 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1068,6 +1068,9 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
 	struct intel_rps *rps = &dev_priv->gt_pm.rps;
 	int ret = 0;
 
+	if (USES_GUC_SLPC(dev_priv))
+		seq_puts(m, "SLPC Active\n");
+
 	intel_runtime_pm_get(dev_priv);
 
 	if (IS_GEN5(dev_priv)) {
@@ -2209,6 +2212,9 @@ static int i915_rps_boost_info(struct seq_file *m, void *data)
 	struct intel_rps *rps = &dev_priv->gt_pm.rps;
 	struct drm_file *file;
 
+	if (USES_GUC_SLPC(dev_priv))
+		seq_puts(m, "SLPC Active\n");
+
 	seq_printf(m, "RPS enabled? %d\n", rps->enabled);
 	seq_printf(m, "GPU busy? %s [%d requests]\n",
 		   yesno(dev_priv->gt.awake), dev_priv->gt.active_requests);
-- 
2.7.4

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[PATCH v12 17/17] HAX: drm/i915/guc: Enable GuC

[Sagar Arun Kamble]

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_params.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index 2484925..dd2de06 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -48,7 +48,7 @@ struct drm_printer;
 	param(int, disable_power_well, -1) \
 	param(int, enable_ips, 1) \
 	param(int, invert_brightness, 0) \
-	param(int, enable_guc, 0) \
+	param(int, enable_guc, -1) \
 	param(int, guc_log_level, -1) \
 	param(char *, guc_firmware_path, NULL) \
 	param(char *, huc_firmware_path, NULL) \
-- 
2.7.4

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✗ Fi.CI.CHECKPATCH: warning for Add support for GuC-based SLPC (rev12)

[Patchwork]

== Series Details ==

Series: Add support for GuC-based SLPC (rev12)
URL   : https://patchwork.freedesktop.org/series/2691/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
d53e35c3815d drm/i915/guc/slpc: Add SLPC control to enable_guc modparam
6cf8c81b2bca drm/i915/guc/slpc: Disable host RPS
bb01d5961927 drm/i915/guc/slpc: Lay out SLPC init/enable/disable/fini helpers
-:106: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#106: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 126 lines checked
bd7f17539b74 drm/i915/guc/slpc: Enable SLPC in GuC load control params
1ed1936a7f0d drm/i915/guc/slpc: Add SLPC communication interfaces
-:61: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#61: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 219 lines checked
b4db20e94cee drm/i915/guc/slpc: Allocate/initialize/release SLPC shared data
-:64: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects?
#64: FILE: drivers/gpu/drm/i915/i915_drv.h:2419:
+#define IS_ULX_SKU(dev_priv)	(IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv))

-:65: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects?
#65: FILE: drivers/gpu/drm/i915/i915_drv.h:2420:
+#define IS_ULT_SKU(dev_priv)	(IS_SKL_ULT(dev_priv) || \
+				 IS_KBL_ULT(dev_priv) || \
+				 IS_CFL_ULT(dev_priv))

total: 0 errors, 0 warnings, 2 checks, 240 lines checked
b470c3d03b1c drm/i915/guc/slpc: Send RESET event to restart/enable SLPC tasks
-:80: ERROR:SPACING: space required before the open parenthesis '('
#80: FILE: drivers/gpu/drm/i915/intel_guc_slpc.c:170:
+	switch(status) {

total: 1 errors, 0 warnings, 0 checks, 253 lines checked
423af87658f2 drm/i915/guc/slpc: Send SHUTDOWN event to stop SLPC tasks
6b80339da56f drm/i915/guc/slpc: Reset SLPC on engine reset with flag TDR_OCCURRED
182447860555 drm/i915/guc/slpc: Add parameter set/unset/get, task control/status functions
8a14dde3f5d4 drm/i915/guc/slpc: Add support for sysfs min/max frequency control
b1b7f3a4a9a0 drm/i915/guc/slpc: Add enable/disable controls for SLPC tasks
1683b3cafee8 drm/i915/debugfs: Create generic string tokenize function and update CRC control parsing
9f4c9bd0a832 drm/i915/guc/slpc: Add debugfs support to read/write/revert the parameters
-:75: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#75: FILE: drivers/gpu/drm/i915/i915_debugfs.c:2807:
+	seq_printf(m, "%s=%u, override=%s\n",
+			slpc_params_desc[slpc->debug.param_id],

-:116: CHECK:BRACES: braces {} should be used on all arms of this statement
#116: FILE: drivers/gpu/drm/i915/i915_debugfs.c:2848:
+	if (!strcmp(words[0], "read"))
[...]
+	else if (!strcmp(words[0], "write"))
[...]
+	else if (!strcmp(words[0], "revert"))
[...]
+	else {
[...]

-:122: CHECK:BRACES: Unbalanced braces around else statement
#122: FILE: drivers/gpu/drm/i915/i915_debugfs.c:2854:
+	else {

-:137: CHECK:SPACING: spaces preferred around that '-' (ctx:VxV)
#137: FILE: drivers/gpu/drm/i915/i915_debugfs.c:2869:
+	return (n_words-1);
 	               ^

-:141: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#141: FILE: drivers/gpu/drm/i915/i915_debugfs.c:2873:
+static ssize_t slpc_param_ctl_write(struct file *file, const char __user *ubuf,
+				     size_t len, loff_t *offp)

-:282: CHECK:UNNECESSARY_PARENTHESES: Unnecessary parentheses around 'id >= SLPC_PARAM_TASK_ENABLE_GTPERF'
#282: FILE: drivers/gpu/drm/i915/intel_guc_slpc.c:634:
+		if ((id >= SLPC_PARAM_TASK_ENABLE_GTPERF) &&
+		    (id <= SLPC_PARAM_TASK_DISABLE_DCC)) {

-:282: CHECK:UNNECESSARY_PARENTHESES: Unnecessary parentheses around 'id <= SLPC_PARAM_TASK_DISABLE_DCC'
#282: FILE: drivers/gpu/drm/i915/intel_guc_slpc.c:634:
+		if ((id >= SLPC_PARAM_TASK_ENABLE_GTPERF) &&
+		    (id <= SLPC_PARAM_TASK_DISABLE_DCC)) {

total: 0 errors, 0 warnings, 7 checks, 332 lines checked
18faa445aae6 drm/i915/guc/slpc: Add i915_guc_slpc_info to debugfs
-:245: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#245: FILE: drivers/gpu/drm/i915/intel_guc_slpc.c:656:
+		   intel_gpu_freq(dev_priv,
+			task_data->max_unslice_freq * GEN9_FREQ_SCALER));

-:248: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#248: FILE: drivers/gpu/drm/i915/intel_guc_slpc.c:659:
+		   intel_gpu_freq(dev_priv,
+			task_data->min_unslice_freq * GEN9_FREQ_SCALER));

-:251: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#251: FILE: drivers/gpu/drm/i915/intel_guc_slpc.c:662:
+		   intel_gpu_freq(dev_priv,
+			task_data->max_slice_freq * GEN9_FREQ_SCALER));

-:254: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#254: FILE: drivers/gpu/drm/i915/intel_guc_slpc.c:665:
+		   intel_gpu_freq(dev_priv,
+			task_data->min_slice_freq * GEN9_FREQ_SCALER));

-:271: CHECK:LINE_SPACING: Please don't use multiple blank lines
#271: FILE: drivers/gpu/drm/i915/intel_guc_slpc.c:682:
+
+

total: 0 errors, 0 warnings, 5 checks, 229 lines checked
0029128b8efc drm/i915/guc/slpc: Add SLPC banner to RPS debugfs interfaces
73cfdac309a0 HAX: drm/i915/guc: Enable GuC

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✗ Fi.CI.SPARSE: warning for Add support for GuC-based SLPC (rev12)

[Patchwork]

== Series Details ==

Series: Add support for GuC-based SLPC (rev12)
URL   : https://patchwork.freedesktop.org/series/2691/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Commit: drm/i915/guc/slpc: Add SLPC control to enable_guc modparam
Okay!

Commit: drm/i915/guc/slpc: Disable host RPS
Okay!

Commit: drm/i915/guc/slpc: Lay out SLPC init/enable/disable/fini helpers
Okay!

Commit: drm/i915/guc/slpc: Enable SLPC in GuC load control params
Okay!

Commit: drm/i915/guc/slpc: Add SLPC communication interfaces
Okay!

Commit: drm/i915/guc/slpc: Allocate/initialize/release SLPC shared data
Okay!

Commit: drm/i915/guc/slpc: Send RESET event to restart/enable SLPC tasks
Okay!

Commit: drm/i915/guc/slpc: Send SHUTDOWN event to stop SLPC tasks
Okay!

Commit: drm/i915/guc/slpc: Reset SLPC on engine reset with flag TDR_OCCURRED
Okay!

Commit: drm/i915/guc/slpc: Add parameter set/unset/get, task control/status functions
Okay!

Commit: drm/i915/guc/slpc: Add support for sysfs min/max frequency control
Okay!

Commit: drm/i915/guc/slpc: Add enable/disable controls for SLPC tasks
-
+drivers/gpu/drm/i915/i915_debugfs.c:2697:30: warning: symbol 'i915_guc_slpc_gtperf_fops' was not declared. Should it be static?
+drivers/gpu/drm/i915/i915_debugfs.c:2734:30: warning: symbol 'i915_guc_slpc_balancer_fops' was not declared. Should it be static?
+drivers/gpu/drm/i915/i915_debugfs.c:2771:30: warning: symbol 'i915_guc_slpc_dcc_fops' was not declared. Should it be static?

Commit: drm/i915/debugfs: Create generic string tokenize function and update CRC control parsing
Okay!

Commit: drm/i915/guc/slpc: Add debugfs support to read/write/revert the parameters
+drivers/gpu/drm/i915/i915_debugfs.c:2925:30: warning: symbol 'i915_guc_slpc_param_ctl_fops' was not declared. Should it be static?

Commit: drm/i915/guc/slpc: Add i915_guc_slpc_info to debugfs
Okay!

Commit: drm/i915/guc/slpc: Add SLPC banner to RPS debugfs interfaces
Okay!

Commit: HAX: drm/i915/guc: Enable GuC
Okay!

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✗ Fi.CI.BAT: failure for Add support for GuC-based SLPC (rev12)

[Patchwork]

== Series Details ==

Series: Add support for GuC-based SLPC (rev12)
URL   : https://patchwork.freedesktop.org/series/2691/
State : failure

== Summary ==

Series 2691v12 Add support for GuC-based SLPC
https://patchwork.freedesktop.org/api/1.0/series/2691/revisions/12/mbox/

Warning: Kernel 32bit buildtest failed
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8543/build_32bit.log

---- Possible new issues:

Test debugfs_test:
        Subgroup read_all_entries:
                pass       -> DMESG-FAIL (fi-bdw-5557u)
                pass       -> DMESG-FAIL (fi-bdw-gvtdvm)
                pass       -> DMESG-FAIL (fi-blb-e6850)
                pass       -> DMESG-FAIL (fi-bsw-n3050)
                pass       -> DMESG-FAIL (fi-bwr-2160)
                pass       -> DMESG-FAIL (fi-byt-j1900)
                pass       -> DMESG-FAIL (fi-byt-n2820)
                pass       -> DMESG-FAIL (fi-cnl-y3)
                pass       -> DMESG-FAIL (fi-gdg-551)
                pass       -> DMESG-FAIL (fi-hsw-4770)
                pass       -> DMESG-FAIL (fi-ilk-650)
                pass       -> DMESG-FAIL (fi-ivb-3520m)
                pass       -> DMESG-FAIL (fi-ivb-3770)
                pass       -> DMESG-FAIL (fi-pnv-d510)
                pass       -> DMESG-FAIL (fi-skl-guc)
                pass       -> DMESG-FAIL (fi-snb-2600)
Test drv_hangman:
        Subgroup error-state-basic:
                pass       -> DMESG-FAIL (fi-bdw-5557u)
                pass       -> DMESG-FAIL (fi-bdw-gvtdvm)
                pass       -> INCOMPLETE (fi-bsw-n3050)
                pass       -> DMESG-FAIL (fi-cnl-y3)
                pass       -> DMESG-FAIL (fi-glk-1)
                pass       -> DMESG-FAIL (fi-skl-guc)
Test drv_module_reload:
        Subgroup basic-reload:
                pass       -> INCOMPLETE (fi-blb-e6850)
                pass       -> INCOMPLETE (fi-bwr-2160)
                pass       -> INCOMPLETE (fi-elk-e7500)
                pass       -> INCOMPLETE (fi-gdg-551)
                pass       -> INCOMPLETE (fi-ilk-650)
                pass       -> INCOMPLETE (fi-pnv-d510)
Test gem_basic:
        Subgroup create-close:
                pass       -> INCOMPLETE (fi-glk-1)
Test gem_busy:
        Subgroup basic-hang-default:
                pass       -> INCOMPLETE (fi-bdw-5557u)
                pass       -> INCOMPLETE (fi-bdw-gvtdvm)
                pass       -> INCOMPLETE (fi-cnl-y3)
Test pm_rps:
        Subgroup basic-api:
                pass       -> INCOMPLETE (fi-byt-j1900)
                pass       -> INCOMPLETE (fi-byt-n2820)
                pass       -> INCOMPLETE (fi-hsw-4770)
                pass       -> INCOMPLETE (fi-ivb-3520m)
                pass       -> INCOMPLETE (fi-ivb-3770)
                pass       -> FAIL       (fi-skl-6770hq)
                pass       -> INCOMPLETE (fi-snb-2520m)
                pass       -> INCOMPLETE (fi-snb-2600)

---- Known issues:

Test debugfs_test:
        Subgroup read_all_entries:
                pass       -> DMESG-FAIL (fi-elk-e7500) fdo#103989 +1
                pass       -> DMESG-FAIL (fi-glk-1) fdo#105421
                pass       -> DMESG-FAIL (fi-snb-2520m) fdo#103713
Test gem_busy:
        Subgroup basic-hang-default:
                pass       -> INCOMPLETE (fi-skl-guc) fdo#104108 +1

fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
fdo#105421 https://bugs.freedesktop.org/show_bug.cgi?id=105421
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108

fi-bdw-5557u     total:11   pass:8    dwarn:0   dfail:2   fail:0   skip:0  
fi-bdw-gvtdvm    total:11   pass:8    dwarn:0   dfail:2   fail:0   skip:0  
fi-blb-e6850     total:282  pass:216  dwarn:1   dfail:1   fail:0   skip:63 
fi-bsw-n3050     total:6    pass:4    dwarn:0   dfail:1   fail:0   skip:0  
fi-bwr-2160      total:282  pass:176  dwarn:0   dfail:1   fail:0   skip:104
fi-bxt-dsi       total:285  pass:255  dwarn:0   dfail:0   fail:0   skip:30  time:518s
fi-bxt-j4205     total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  time:515s
fi-byt-j1900     total:250  pass:214  dwarn:0   dfail:1   fail:0   skip:34 
fi-byt-n2820     total:250  pass:210  dwarn:0   dfail:1   fail:0   skip:38 
fi-cfl-8700k     total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  time:413s
fi-cfl-s3        total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  time:565s
fi-cfl-u         total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  time:515s
fi-cnl-y3        total:11   pass:8    dwarn:0   dfail:2   fail:0   skip:0  
fi-elk-e7500     total:282  pass:222  dwarn:0   dfail:1   fail:0   skip:58 
fi-gdg-551       total:282  pass:172  dwarn:0   dfail:1   fail:1   skip:107
fi-glk-1         total:8    pass:5    dwarn:0   dfail:2   fail:0   skip:0  
fi-hsw-4770      total:250  pass:222  dwarn:0   dfail:1   fail:0   skip:26 
fi-ilk-650       total:282  pass:221  dwarn:0   dfail:1   fail:0   skip:59 
fi-ivb-3520m     total:250  pass:221  dwarn:0   dfail:1   fail:0   skip:27 
fi-ivb-3770      total:250  pass:216  dwarn:0   dfail:1   fail:0   skip:32 
fi-kbl-7500u     total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  time:484s
fi-kbl-7567u     total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  time:469s
fi-kbl-r         total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  time:513s
WARNING: Long output truncated

9829fcd7ae99d5955bb76a8fb8060e63339d7c9d drm-tip: 2018y-03m-29d-19h-56m-48s UTC integration manifest
73cfdac309a0 HAX: drm/i915/guc: Enable GuC
0029128b8efc drm/i915/guc/slpc: Add SLPC banner to RPS debugfs interfaces
18faa445aae6 drm/i915/guc/slpc: Add i915_guc_slpc_info to debugfs
9f4c9bd0a832 drm/i915/guc/slpc: Add debugfs support to read/write/revert the parameters
1683b3cafee8 drm/i915/debugfs: Create generic string tokenize function and update CRC control parsing
b1b7f3a4a9a0 drm/i915/guc/slpc: Add enable/disable controls for SLPC tasks
8a14dde3f5d4 drm/i915/guc/slpc: Add support for sysfs min/max frequency control
182447860555 drm/i915/guc/slpc: Add parameter set/unset/get, task control/status functions
6b80339da56f drm/i915/guc/slpc: Reset SLPC on engine reset with flag TDR_OCCURRED
423af87658f2 drm/i915/guc/slpc: Send SHUTDOWN event to stop SLPC tasks
b470c3d03b1c drm/i915/guc/slpc: Send RESET event to restart/enable SLPC tasks
b4db20e94cee drm/i915/guc/slpc: Allocate/initialize/release SLPC shared data
1ed1936a7f0d drm/i915/guc/slpc: Add SLPC communication interfaces
bd7f17539b74 drm/i915/guc/slpc: Enable SLPC in GuC load control params
bb01d5961927 drm/i915/guc/slpc: Lay out SLPC init/enable/disable/fini helpers
6cf8c81b2bca drm/i915/guc/slpc: Disable host RPS
d53e35c3815d drm/i915/guc/slpc: Add SLPC control to enable_guc modparam

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8543/issues.html
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Re: [PATCH v12 01/17] drm/i915/guc/slpc: Add SLPC control to enable_guc modparam

[Michal Wajdeczko]

On Fri, 30 Mar 2018 10:31:46 +0200, Sagar Arun Kamble  
<sagar.a.kamble@intel.com> wrote:

> From: Tom O'Rourke <Tom.O'Rourke@intel.com>
>
> GuC is currently being used for submission and HuC authentication.
> Choices can be configured through enable_guc modparam. GuC SLPC is GT
> Power and Performance management feature in GuC. Add another option to
> enable_guc modparam to control SLPC.
>
> v1: Add early call to sanitize enable_guc_slpc in intel_guc_ucode_init
>     Remove sanitize enable_guc_slpc call before firmware version check
>     is performed. (ChrisW)
>     Version check is added in next patch and that will be done as part
>     of slpc_enable_sanitize function in the next patch. (Sagar) Updated
>     slpc option sanitize function call for platforms without GuC support.
>     This was caught by CI BAT.
>
> v2: Changed parameter to dev_priv for HAS_SLPC macro. (David)
>     Code indentation based on checkpatch.
>
> v3: Rebase.
>
> v4: Moved sanitization of SLPC option post GuC load.
>
> v5: Removed function intel_slpc_enabled. Planning to rely only on kernel
>     parameter. Moved sanitization prior to GuC load to use the parameter
>     during SLPC state setup during to GuC load. (Sagar)
>
> v6: Commit message update. Rebase.
>
> v7: Moved SLPC option sanitization to intel_uc_sanitize_options.
>
> v8: Clearing SLPC option on GuC load failure. Change moved from later
>     patch. (Sagar)
>
> v9: s/enable_slpc/enable_guc_slpc. Rebase w.r.t modparam change.
>
> v10: Rebase. Separate modparam is not needed now that we maintain all
>      options in single param enable_guc.
>
> Suggested-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
> Cc: Jeff McGee <jeff.mcgee@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_params.c |  5 +++--
>  drivers/gpu/drm/i915/i915_params.h |  1 +
>  drivers/gpu/drm/i915/intel_uc.c    | 23 +++++++++++++++++++----
>  drivers/gpu/drm/i915/intel_uc.h    |  6 ++++++
>  4 files changed, 29 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_params.c  
> b/drivers/gpu/drm/i915/i915_params.c
> index 08108ce..40b799b 100644
> --- a/drivers/gpu/drm/i915/i915_params.c
> +++ b/drivers/gpu/drm/i915/i915_params.c
> @@ -150,9 +150,10 @@ i915_param_named_unsafe(edp_vswing, int, 0400,
>  	"2=default swing(400mV))");
> i915_param_named_unsafe(enable_guc, int, 0400,
> -	"Enable GuC load for GuC submission and/or HuC load. "
> +	"Enable GuC load for GuC submission and/or HuC load and/or GuC SLPC. "
>  	"Required functionality can be selected using bitmask values. "
> -	"(-1=auto, 0=disable [default], 1=GuC submission, 2=HuC load)");
> +	"(-1=auto, 0=disable [default], 1=GuC submission, 2=HuC load, "
> +	"4=GuC SLPC)");

Maybe to avoid later surprise, we should explicitly say that:

+	"4=GuC SLPC [requires GuC submission])");

> i915_param_named(guc_log_level, int, 0400,
>  	"GuC firmware logging level. Requires GuC to be loaded. "
> diff --git a/drivers/gpu/drm/i915/i915_params.h  
> b/drivers/gpu/drm/i915/i915_params.h
> index c963603..2484925 100644
> --- a/drivers/gpu/drm/i915/i915_params.h
> +++ b/drivers/gpu/drm/i915/i915_params.h
> @@ -32,6 +32,7 @@ struct drm_printer;
> #define ENABLE_GUC_SUBMISSION		BIT(0)
>  #define ENABLE_GUC_LOAD_HUC		BIT(1)
> +#define ENABLE_GUC_SLPC			BIT(2)
> #define I915_PARAMS_FOR_EACH(param) \
>  	param(char *, vbt_firmware, NULL) \
> diff --git a/drivers/gpu/drm/i915/intel_uc.c  
> b/drivers/gpu/drm/i915/intel_uc.c
> index 1cffaf7..0e4a97f 100644
> --- a/drivers/gpu/drm/i915/intel_uc.c
> +++ b/drivers/gpu/drm/i915/intel_uc.c
> @@ -56,9 +56,15 @@ static int __get_platform_enable_guc(struct  
> drm_i915_private *dev_priv)
>  	struct intel_uc_fw *huc_fw = &dev_priv->huc.fw;
>  	int enable_guc = 0;
> -	/* Default is to enable GuC/HuC if we know their firmwares */
> -	if (intel_uc_fw_is_selected(guc_fw))
> +	/*
> +	 * Default is to enable GuC submission/SLPC/HuC if we know their
> +	 * firmwares
> +	 */
> +	if (intel_uc_fw_is_selected(guc_fw)) {
>  		enable_guc |= ENABLE_GUC_SUBMISSION;
> +		enable_guc |= ENABLE_GUC_SLPC;
> +	}
> +
>  	if (intel_uc_fw_is_selected(huc_fw))
>  		enable_guc |= ENABLE_GUC_LOAD_HUC;
> @@ -110,10 +116,11 @@ static void sanitize_options_early(struct  
> drm_i915_private *dev_priv)
>  	if (i915_modparams.enable_guc < 0)
>  		i915_modparams.enable_guc = __get_platform_enable_guc(dev_priv);
> -	DRM_DEBUG_DRIVER("enable_guc=%d (submission:%s huc:%s)\n",
> +	DRM_DEBUG_DRIVER("enable_guc=%d (submission:%s huc:%s slpc:%s)\n",
>  			 i915_modparams.enable_guc,
>  			 yesno(intel_uc_is_using_guc_submission()),
> -			 yesno(intel_uc_is_using_huc()));
> +			 yesno(intel_uc_is_using_huc()),
> +			 yesno(intel_uc_is_using_guc_slpc()));
> 	/* Verify GuC firmware availability */
>  	if (intel_uc_is_using_guc() && !intel_uc_fw_is_selected(guc_fw)) {
> @@ -123,6 +130,14 @@ static void sanitize_options_early(struct  
> drm_i915_private *dev_priv)
>  					      "no GuC firmware");
>  	}
> +	/* Verify GuC submission and SLPC dependency */
> +	if (intel_uc_is_using_guc_slpc() &&
> +	    !intel_uc_is_using_guc_submission()) {
> +		DRM_WARN("Incompatible option detected: %s=%d, "
> +			 "GuC SLPC enabled without enabling GuC submission!\n",
> +			 "enable_guc", i915_modparams.enable_guc);

If this is unsupported variant, then maybe we should clear slpc bit:

	i915_modparams.enable_guc &= ~ENABLE_GUC_SLPC;

> +	}
> +
>  	/* Verify HuC firmware availability */
>  	if (intel_uc_is_using_huc() && !intel_uc_fw_is_selected(huc_fw)) {
>  		DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
> diff --git a/drivers/gpu/drm/i915/intel_uc.h  
> b/drivers/gpu/drm/i915/intel_uc.h
> index 25d73ad..76139d3 100644
> --- a/drivers/gpu/drm/i915/intel_uc.h
> +++ b/drivers/gpu/drm/i915/intel_uc.h
> @@ -59,4 +59,10 @@ static inline bool intel_uc_is_using_huc(void)
>  	return i915_modparams.enable_guc & ENABLE_GUC_LOAD_HUC;
>  }
> +static inline bool intel_uc_is_using_guc_slpc(void)
> +{
> +	GEM_BUG_ON(i915_modparams.enable_guc < 0);
> +	return i915_modparams.enable_guc & ENABLE_GUC_SLPC;
> +}
> +
>  #endif

In intel_uc_init_hw() we print summary, so maybe add there:

	dev_info(dev_priv->drm.dev, "GuC SLPC %s\n",
		 enableddisabled(USES_GUC_SLPC(dev_priv)));

Then we can move USES_GUC_SLPC() definition from patch 2 to 1.

With all that,

Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
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Re: [PATCH v12 05/17] drm/i915/guc/slpc: Add SLPC communication interfaces

[Michal Wajdeczko]

On Fri, 30 Mar 2018 10:31:50 +0200, Sagar Arun Kamble  
<sagar.a.kamble@intel.com> wrote:

> Communication with SLPC is via Host to GuC interrupt through shared data
> and parameters. This patch defines the structure of shared data,
> parameters, data structure to be passed as input and received as output
> from SLPC. This patch also defines the events to be sent as input and
> status values output by GuC on processing SLPC events.
> SLPC shared data has details of SKU type, Slice count, IA Perf MSR  
> values,
> SLPC state, Power source/plan, SLPC tasks status. Parameters allow
> overriding task control, frequency range etc.
>
> v1: fix whitespace (Sagar)
>
> v2-v3: Rebase.
>
> v4: Updated with GuC firmware v9.
>
> v5: Added definition of input and output data structures for SLPC
>     events. Updated commit message.
>
> v6: Removed definition of host2guc_slpc. Will be added in the next
>     patch that uses it. Commit subject update. Rebase.
>
> v7: Added definition of SLPC_RESET_FLAG_TDR_OCCURRED to be sent
>     throgh SLPC reset in case of engine reset. Moved all Host/SLPC
>     interfaces from later patches to this patch. Commit message update.
>
> v8: Updated value of SLPC_RESET_FLAG_TDR_OCCURRED.
>
> v9: Removed struct slpc_param, slpc_paramlist and corresponding defines.
>     Will be added in later patches where they are used.
>
> v10: Rebase. Prepared separate header for SLPC firmware interface.
>
> Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
> Cc: Jeff McGee <jeff.mcgee@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_guc_slpc.h      |   2 +
>  drivers/gpu/drm/i915/intel_guc_slpc_fwif.h | 211  
> +++++++++++++++++++++++++++++
>  2 files changed, 213 insertions(+)
>  create mode 100644 drivers/gpu/drm/i915/intel_guc_slpc_fwif.h
>
> diff --git a/drivers/gpu/drm/i915/intel_guc_slpc.h  
> b/drivers/gpu/drm/i915/intel_guc_slpc.h
> index 66c76fe..81250c0 100644
> --- a/drivers/gpu/drm/i915/intel_guc_slpc.h
> +++ b/drivers/gpu/drm/i915/intel_guc_slpc.h
> @@ -6,6 +6,8 @@
>  #ifndef _INTEL_GUC_SLPC_H_
>  #define _INTEL_GUC_SLPC_H_
> +#include <intel_guc_slpc_fwif.h>

Please use "" instead of <>

> +
>  struct intel_guc_slpc {
>  };
> diff --git a/drivers/gpu/drm/i915/intel_guc_slpc_fwif.h  
> b/drivers/gpu/drm/i915/intel_guc_slpc_fwif.h
> new file mode 100644
> index 0000000..9400af4
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/intel_guc_slpc_fwif.h
> @@ -0,0 +1,211 @@
> +/*
> + * SPDX-License-Identifier: MIT
> + *
> + * Copyright © 2015-2018 Intel Corporation
> + */
> +#ifndef _INTEL_GUC_SLPC_FWIF_H_
> +#define _INTEL_GUC_SLPC_FWIF_H_
> +
> +#include <linux/types.h>
> +
> +enum slpc_status {

s/slpc_status/intel_guc_slpc_status

> +	SLPC_STATUS_OK = 0,
> +	SLPC_STATUS_ERROR = 1,
> +	SLPC_STATUS_ILLEGAL_COMMAND = 2,
> +	SLPC_STATUS_INVALID_ARGS = 3,
> +	SLPC_STATUS_INVALID_PARAMS = 4,
> +	SLPC_STATUS_INVALID_DATA = 5,
> +	SLPC_STATUS_OUT_OF_RANGE = 6,
> +	SLPC_STATUS_NOT_SUPPORTED = 7,
> +	SLPC_STATUS_NOT_IMPLEMENTED = 8,
> +	SLPC_STATUS_NO_DATA = 9,
> +	SLPC_STATUS_EVENT_NOT_REGISTERED = 10,
> +	SLPC_STATUS_REGISTER_LOCKED = 11,
> +	SLPC_STATUS_TEMPORARILY_UNAVAILABLE = 12,
> +	SLPC_STATUS_VALUE_ALREADY_SET = 13,
> +	SLPC_STATUS_VALUE_ALREADY_UNSET = 14,
> +	SLPC_STATUS_VALUE_NOT_CHANGED = 15,
> +	SLPC_STATUS_MEMIO_ERROR = 16,
> +	SLPC_STATUS_EVENT_QUEUED_REQ_DPC = 17,
> +	SLPC_STATUS_EVENT_QUEUED_NOREQ_DPC = 18,
> +	SLPC_STATUS_NO_EVENT_QUEUED = 19,
> +	SLPC_STATUS_OUT_OF_SPACE = 20,
> +	SLPC_STATUS_TIMEOUT = 21,
> +	SLPC_STATUS_NO_LOCK = 22,
> +	SLPC_STATUS_MAX

s/SLPC_STATUS/INTEL_GUC_SLPC_STATUS

> +};
> +
> +enum slpc_event_id {

s/slpc_event_id/intel_guc_slpc_event

> +	SLPC_EVENT_RESET = 0,
> +	SLPC_EVENT_SHUTDOWN = 1,
> +	SLPC_EVENT_PLATFORM_INFO_CHANGE = 2,
> +	SLPC_EVENT_DISPLAY_MODE_CHANGE = 3,
> +	SLPC_EVENT_FLIP_COMPLETE = 4,
> +	SLPC_EVENT_QUERY_TASK_STATE = 5,
> +	SLPC_EVENT_PARAMETER_SET = 6,
> +	SLPC_EVENT_PARAMETER_UNSET = 7,

s/SLPC_EVENT/INTEL_GUC_SLPC_EVENT

> +};
> +
> +enum slpc_param_id {

s/slpc_param_id/intel_guc_slpc_param

> +	SLPC_PARAM_TASK_ENABLE_GTPERF = 0,
> +	SLPC_PARAM_TASK_DISABLE_GTPERF = 1,
> +	SLPC_PARAM_TASK_ENABLE_BALANCER = 2,
> +	SLPC_PARAM_TASK_DISABLE_BALANCER = 3,
> +	SLPC_PARAM_TASK_ENABLE_DCC = 4,
> +	SLPC_PARAM_TASK_DISABLE_DCC = 5,
> +	SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ = 6,
> +	SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ = 7,
> +	SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ = 8,
> +	SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ = 9,
> +	SLPC_PARAM_GTPERF_THRESHOLD_MAX_FPS = 10,
> +	SLPC_PARAM_GLOBAL_DISABLE_GT_FREQ_MANAGEMENT = 11,
> +	SLPC_PARAM_GTPERF_ENABLE_FRAMERATE_STALLING = 12,
> +	SLPC_PARAM_GLOBAL_DISABLE_RC6_MODE_CHANGE = 13,
> +	SLPC_PARAM_GLOBAL_OC_UNSLICE_FREQ_MHZ = 14,
> +	SLPC_PARAM_GLOBAL_OC_SLICE_FREQ_MHZ = 15,
> +	SLPC_PARAM_GLOBAL_ENABLE_IA_GT_BALANCING = 16,
> +	SLPC_PARAM_GLOBAL_ENABLE_ADAPTIVE_BURST_TURBO = 17,
> +	SLPC_PARAM_GLOBAL_ENABLE_EVAL_MODE = 18,
> +	SLPC_PARAM_GLOBAL_ENABLE_BALANCER_IN_NON_GAMING_MODE = 19,

s/SLPC_PARAM/INTEL_GUC_SLPC_PARAM

> +	SLPC_MAX_PARAM,
> +	SLPC_KMD_MAX_PARAM = 32,

hmm, do we really need these two ? please drop

or maybe these are related to SLPC_MAX_OVERRIDE_PARAMETERS ?

> +};
> +
> +enum slpc_global_state {

s/slpc_global_state/intel_guc_slpc_state

> +	SLPC_GLOBAL_STATE_NOT_RUNNING = 0,
> +	SLPC_GLOBAL_STATE_INITIALIZING = 1,
> +	SLPC_GLOBAL_STATE_RESETTING = 2,
> +	SLPC_GLOBAL_STATE_RUNNING = 3,
> +	SLPC_GLOBAL_STATE_SHUTTING_DOWN = 4,
> +	SLPC_GLOBAL_STATE_ERROR = 5

s/SLPC_GLOBAL_STATE/INTEL_GUC_SLPC_STATE

> +};
> +
> +enum slpc_platform_sku {
> +	SLPC_PLATFORM_SKU_UNDEFINED = 0,
> +	SLPC_PLATFORM_SKU_ULX = 1,
> +	SLPC_PLATFORM_SKU_ULT = 2,
> +	SLPC_PLATFORM_SKU_T = 3,
> +	SLPC_PLATFORM_SKU_MOBL = 4,
> +	SLPC_PLATFORM_SKU_DT = 5,
> +	SLPC_PLATFORM_SKU_UNKNOWN = 6,

hmm, this should be already known to GuC/SLPC.
and if still needed, can it be made non-SLPC specific?

> +};
> +
> +enum slpc_power_source {

s/slpc_power_source/intel_power_source

> +	SLPC_POWER_SOURCE_UNDEFINED = 0,
> +	SLPC_POWER_SOURCE_AC = 1,
> +	SLPC_POWER_SOURCE_DC = 2,
> +	SLPC_POWER_SOURCE_UNKNOWN = 3,

s/SLPC_POWER_SOURCE/INTEL_POWER_SOURCE

> +};
> +
> +enum slpc_power_plan {
> +	SLPC_POWER_PLAN_UNDEFINED = 0,
> +	SLPC_POWER_PLAN_BATTERY_SAVER = 1,
> +	SLPC_POWER_PLAN_BALANCED = 2,
> +	SLPC_POWER_PLAN_PERFORMANCE = 3,
> +	SLPC_POWER_PLAN_UNKNOWN = 4,
> +};
> +
> +struct slpc_platform_info {

s/slpc_platform_info/intel_guc_slpc_platform

> +	u8 sku;
> +	u8 slice_count;
> +	u8 reserved;
> +	u8 power_plan_source;

 from macros below, it looks that this is bitfield and
in other struct bitfields are defined explicitly...

what about defining related MASK/SHIFT and MAKE/TO macros here?

> +	u8 p0_freq;
> +	u8 p1_freq;
> +	u8 pe_freq;
> +	u8 pn_freq;
> +	u32 reserved1;
> +	u32 reserved2;
> +} __packed;
> +
> +struct slpc_task_state_data {
> +	union {
> +		u32 bitfield1;
> +		struct {
> +			u32 gtperf_task_active:1;
> +			u32 gtperf_stall_possible:1;
> +			u32 gtperf_gaming_mode:1;
> +			u32 gtperf_target_fps:8;
> +			u32 dcc_task_active:1;
> +			u32 in_dcc:1;
> +			u32 in_dct:1;
> +			u32 freq_switch_active:1;
> +			u32 ibc_enabled:1;
> +			u32 ibc_active:1;
> +			u32 pg1_enabled:1;
> +			u32 pg1_active:1;
> +			u32 reserved:13;

All register bits and most of shared data are defined as
macros, maybe we can do the same for SLPC ?

#define INTEL_GUC_SLPC_TASK_GTPERF_ACTIVE	(1 << 0)
#define INTEL_GUC_SLPC_TASK_GTPERF_STALL	(1 << 1)
...

> +		};
> +	};
> +	union {
> +		u32 bitfield2;
> +		struct {
> +			u32 max_unslice_freq:8;
> +			u32 min_unslice_freq:8;
> +			u32 max_slice_freq:8;
> +			u32 min_slice_freq:8;
> +		};
> +	};
> +} __packed;
> +
> +#define SLPC_MAX_OVERRIDE_PARAMETERS 192
> +#define SLPC_OVERRIDE_BITFIELD_SIZE \
> +		((SLPC_MAX_OVERRIDE_PARAMETERS + 31) / 32)

are there "NON-OVERRIDE" parameters?

> +
> +struct slpc_shared_data {

s/slpc_shared_data/intel_guc_slpc_shared_data
or
s/slpc_shared_data/intel_guc_slpc_data

> +	u32 reserved;

hmm, starting with reserved is odd ;)

> +	u32 shared_data_size;

s/shared_data_size/size

> +	u32 global_state;
> +	struct slpc_platform_info platform_info;
> +	struct slpc_task_state_data task_state_data;
> +	u32 override_params_set_bits[SLPC_OVERRIDE_BITFIELD_SIZE];
> +	u32 override_params_values[SLPC_MAX_OVERRIDE_PARAMETERS];

above two can be promoted to separate struct:

struct intel_guc_slpc_params {
	u32 valid[INTEL_GUC_SLPC_PARAMS_BITFIELD_SIZE];
	u32 values[INTEL_GUC_SLPC_MAX_PARAMS];
};

> +} __packed;
> +
> +enum slpc_reset_flags {

s/slpc_reset_flags/intel_guc_slpc_reset_flags

> +	SLPC_RESET_FLAG_TDR_OCCURRED = (1 << 0)

s/SLPC_RESET_FLAG/INTEL_GUC_SLPC_RESET_FLAG
and to minimize later diffs add trailing ","

> +};
> +
> +#define SLPC_EVENT_MAX_INPUT_ARGS  7
> +#define SLPC_EVENT_MAX_OUTPUT_ARGS 1
> +
> +union slpc_event_input_header {
> +	u32 value;
> +	struct {
> +		u32 num_args:8;
> +		u32 event_id:8;
> +	};

I'm not sure that this struct deserves separate definition

> +};
> +
> +struct slpc_event_input {
> +	u32 h2g_action_id;

what h2g action is this ?
if this event is sent over CTB then probably num_args is
redundant as total CTB message len is already stored in
CT header...

> +	union slpc_event_input_header header;
> +	u32 args[SLPC_EVENT_MAX_INPUT_ARGS];
> +} __packed;
> +
> +union slpc_event_output_header {
> +	u32 value;
> +	struct {
> +		u32 num_args:8;
> +		u32 event_id:8;
> +		u32 status:16;
> +	};
> +};
> +
> +struct slpc_event_output {
> +	u32 reserved;

is this needed ?

> +	union slpc_event_output_header header;

hmm, "header" should be first ;)

> +	u32 args[SLPC_EVENT_MAX_OUTPUT_ARGS];
> +} __packed;
> +
> +#define SLPC_EVENT(id, argc)		 ((u32)(id) << 8 | (argc))
> +#define SLPC_POWER_PLAN_SOURCE(plan, source) ((plan) | ((source) << 6))
> +#define SLPC_POWER_PLAN(plan_source)	 ((plan_source) & 0x3F)
> +#define SLPC_POWER_SOURCE(plan_source)	 ((plan_source) >> 6)

maybe:

	INTEL_GUC_SLPC_MAKE_EVENT
	INTEL_GUC_SLPC_MAKE_POWER_INFO
	INTEL_GUC_SLPC_POWER_INFO_TO_PLAN
	INTEL_GUC_SLPC_POWER_INFO_TO_SOURCE

and use SHIFT/MASK macros

> +
> +#define SLPC_PARAM_TASK_DEFAULT  0
> +#define SLPC_PARAM_TASK_ENABLED  1
> +#define SLPC_PARAM_TASK_DISABLED 2
> +#define SLPC_PARAM_TASK_UNKNOWN  3

in other places you are using enums, why #defines here?

> +
> +#endif
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Re: [PATCH v12 01/17] drm/i915/guc/slpc: Add SLPC control to enable_guc modparam

[Sagar Arun Kamble]

Thanks for the review. Will update with all suggestions in the next rev.

On 3/30/2018 6:07 PM, Michal Wajdeczko wrote:
> On Fri, 30 Mar 2018 10:31:46 +0200, Sagar Arun Kamble 
> <sagar.a.kamble@intel.com> wrote:
>
>> From: Tom O'Rourke <Tom.O'Rourke@intel.com>
>>
>> GuC is currently being used for submission and HuC authentication.
>> Choices can be configured through enable_guc modparam. GuC SLPC is GT
>> Power and Performance management feature in GuC. Add another option to
>> enable_guc modparam to control SLPC.
>>
>> v1: Add early call to sanitize enable_guc_slpc in intel_guc_ucode_init
>>     Remove sanitize enable_guc_slpc call before firmware version check
>>     is performed. (ChrisW)
>>     Version check is added in next patch and that will be done as part
>>     of slpc_enable_sanitize function in the next patch. (Sagar) Updated
>>     slpc option sanitize function call for platforms without GuC 
>> support.
>>     This was caught by CI BAT.
>>
>> v2: Changed parameter to dev_priv for HAS_SLPC macro. (David)
>>     Code indentation based on checkpatch.
>>
>> v3: Rebase.
>>
>> v4: Moved sanitization of SLPC option post GuC load.
>>
>> v5: Removed function intel_slpc_enabled. Planning to rely only on kernel
>>     parameter. Moved sanitization prior to GuC load to use the parameter
>>     during SLPC state setup during to GuC load. (Sagar)
>>
>> v6: Commit message update. Rebase.
>>
>> v7: Moved SLPC option sanitization to intel_uc_sanitize_options.
>>
>> v8: Clearing SLPC option on GuC load failure. Change moved from later
>>     patch. (Sagar)
>>
>> v9: s/enable_slpc/enable_guc_slpc. Rebase w.r.t modparam change.
>>
>> v10: Rebase. Separate modparam is not needed now that we maintain all
>>      options in single param enable_guc.
>>
>> Suggested-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
>> Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
>> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>> Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
>> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
>> Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
>> Cc: Jeff McGee <jeff.mcgee@intel.com>
>> ---
>>  drivers/gpu/drm/i915/i915_params.c |  5 +++--
>>  drivers/gpu/drm/i915/i915_params.h |  1 +
>>  drivers/gpu/drm/i915/intel_uc.c    | 23 +++++++++++++++++++----
>>  drivers/gpu/drm/i915/intel_uc.h    |  6 ++++++
>>  4 files changed, 29 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_params.c 
>> b/drivers/gpu/drm/i915/i915_params.c
>> index 08108ce..40b799b 100644
>> --- a/drivers/gpu/drm/i915/i915_params.c
>> +++ b/drivers/gpu/drm/i915/i915_params.c
>> @@ -150,9 +150,10 @@ i915_param_named_unsafe(edp_vswing, int, 0400,
>>      "2=default swing(400mV))");
>> i915_param_named_unsafe(enable_guc, int, 0400,
>> -    "Enable GuC load for GuC submission and/or HuC load. "
>> +    "Enable GuC load for GuC submission and/or HuC load and/or GuC 
>> SLPC. "
>>      "Required functionality can be selected using bitmask values. "
>> -    "(-1=auto, 0=disable [default], 1=GuC submission, 2=HuC load)");
>> +    "(-1=auto, 0=disable [default], 1=GuC submission, 2=HuC load, "
>> +    "4=GuC SLPC)");
>
> Maybe to avoid later surprise, we should explicitly say that:
>
> +    "4=GuC SLPC [requires GuC submission])");
>
>> i915_param_named(guc_log_level, int, 0400,
>>      "GuC firmware logging level. Requires GuC to be loaded. "
>> diff --git a/drivers/gpu/drm/i915/i915_params.h 
>> b/drivers/gpu/drm/i915/i915_params.h
>> index c963603..2484925 100644
>> --- a/drivers/gpu/drm/i915/i915_params.h
>> +++ b/drivers/gpu/drm/i915/i915_params.h
>> @@ -32,6 +32,7 @@ struct drm_printer;
>> #define ENABLE_GUC_SUBMISSION        BIT(0)
>>  #define ENABLE_GUC_LOAD_HUC        BIT(1)
>> +#define ENABLE_GUC_SLPC            BIT(2)
>> #define I915_PARAMS_FOR_EACH(param) \
>>      param(char *, vbt_firmware, NULL) \
>> diff --git a/drivers/gpu/drm/i915/intel_uc.c 
>> b/drivers/gpu/drm/i915/intel_uc.c
>> index 1cffaf7..0e4a97f 100644
>> --- a/drivers/gpu/drm/i915/intel_uc.c
>> +++ b/drivers/gpu/drm/i915/intel_uc.c
>> @@ -56,9 +56,15 @@ static int __get_platform_enable_guc(struct 
>> drm_i915_private *dev_priv)
>>      struct intel_uc_fw *huc_fw = &dev_priv->huc.fw;
>>      int enable_guc = 0;
>> -    /* Default is to enable GuC/HuC if we know their firmwares */
>> -    if (intel_uc_fw_is_selected(guc_fw))
>> +    /*
>> +     * Default is to enable GuC submission/SLPC/HuC if we know their
>> +     * firmwares
>> +     */
>> +    if (intel_uc_fw_is_selected(guc_fw)) {
>>          enable_guc |= ENABLE_GUC_SUBMISSION;
>> +        enable_guc |= ENABLE_GUC_SLPC;
>> +    }
>> +
>>      if (intel_uc_fw_is_selected(huc_fw))
>>          enable_guc |= ENABLE_GUC_LOAD_HUC;
>> @@ -110,10 +116,11 @@ static void sanitize_options_early(struct 
>> drm_i915_private *dev_priv)
>>      if (i915_modparams.enable_guc < 0)
>>          i915_modparams.enable_guc = 
>> __get_platform_enable_guc(dev_priv);
>> -    DRM_DEBUG_DRIVER("enable_guc=%d (submission:%s huc:%s)\n",
>> +    DRM_DEBUG_DRIVER("enable_guc=%d (submission:%s huc:%s slpc:%s)\n",
>>               i915_modparams.enable_guc,
>>               yesno(intel_uc_is_using_guc_submission()),
>> -             yesno(intel_uc_is_using_huc()));
>> +             yesno(intel_uc_is_using_huc()),
>> +             yesno(intel_uc_is_using_guc_slpc()));
>>     /* Verify GuC firmware availability */
>>      if (intel_uc_is_using_guc() && !intel_uc_fw_is_selected(guc_fw)) {
>> @@ -123,6 +130,14 @@ static void sanitize_options_early(struct 
>> drm_i915_private *dev_priv)
>>                            "no GuC firmware");
>>      }
>> +    /* Verify GuC submission and SLPC dependency */
>> +    if (intel_uc_is_using_guc_slpc() &&
>> +        !intel_uc_is_using_guc_submission()) {
>> +        DRM_WARN("Incompatible option detected: %s=%d, "
>> +             "GuC SLPC enabled without enabling GuC submission!\n",
>> +             "enable_guc", i915_modparams.enable_guc);
>
> If this is unsupported variant, then maybe we should clear slpc bit:
>
>     i915_modparams.enable_guc &= ~ENABLE_GUC_SLPC;
>
>> +    }
>> +
>>      /* Verify HuC firmware availability */
>>      if (intel_uc_is_using_huc() && !intel_uc_fw_is_selected(huc_fw)) {
>>          DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
>> diff --git a/drivers/gpu/drm/i915/intel_uc.h 
>> b/drivers/gpu/drm/i915/intel_uc.h
>> index 25d73ad..76139d3 100644
>> --- a/drivers/gpu/drm/i915/intel_uc.h
>> +++ b/drivers/gpu/drm/i915/intel_uc.h
>> @@ -59,4 +59,10 @@ static inline bool intel_uc_is_using_huc(void)
>>      return i915_modparams.enable_guc & ENABLE_GUC_LOAD_HUC;
>>  }
>> +static inline bool intel_uc_is_using_guc_slpc(void)
>> +{
>> +    GEM_BUG_ON(i915_modparams.enable_guc < 0);
>> +    return i915_modparams.enable_guc & ENABLE_GUC_SLPC;
>> +}
>> +
>>  #endif
>
> In intel_uc_init_hw() we print summary, so maybe add there:
>
>     dev_info(dev_priv->drm.dev, "GuC SLPC %s\n",
>          enableddisabled(USES_GUC_SLPC(dev_priv)));
>
> Then we can move USES_GUC_SLPC() definition from patch 2 to 1.
>
> With all that,
>
> Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com>

-- 
Thanks,
Sagar

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Re: [PATCH v12 05/17] drm/i915/guc/slpc: Add SLPC communication interfaces

[Sagar Arun Kamble]

On 3/30/2018 7:07 PM, Michal Wajdeczko wrote:
> On Fri, 30 Mar 2018 10:31:50 +0200, Sagar Arun Kamble 
> <sagar.a.kamble@intel.com> wrote:
<snip>
>> diff --git a/drivers/gpu/drm/i915/intel_guc_slpc.h 
>> b/drivers/gpu/drm/i915/intel_guc_slpc.h
>> index 66c76fe..81250c0 100644
>> --- a/drivers/gpu/drm/i915/intel_guc_slpc.h
>> +++ b/drivers/gpu/drm/i915/intel_guc_slpc.h
>> @@ -6,6 +6,8 @@
>>  #ifndef _INTEL_GUC_SLPC_H_
>>  #define _INTEL_GUC_SLPC_H_
>> +#include <intel_guc_slpc_fwif.h>
>
> Please use "" instead of <>
Yes. will hopefully not forget this next time :)
>
>> +
>>  struct intel_guc_slpc {
>>  };
>> diff --git a/drivers/gpu/drm/i915/intel_guc_slpc_fwif.h 
>> b/drivers/gpu/drm/i915/intel_guc_slpc_fwif.h
>> new file mode 100644
>> index 0000000..9400af4
>> --- /dev/null
>> +++ b/drivers/gpu/drm/i915/intel_guc_slpc_fwif.h
>> @@ -0,0 +1,211 @@
>> +/*
>> + * SPDX-License-Identifier: MIT
>> + *
>> + * Copyright © 2015-2018 Intel Corporation
>> + */
>> +#ifndef _INTEL_GUC_SLPC_FWIF_H_
>> +#define _INTEL_GUC_SLPC_FWIF_H_
>> +
>> +#include <linux/types.h>
>> +
>> +enum slpc_status {
>
> s/slpc_status/intel_guc_slpc_status
>
I have done this because of following reasons:
1. GuC SLPC interface file shared by firmware team names enums/structs 
as SLPM_* or SLPM_KMD_*. i understand that this isn't strict requirement. :)
2. INTEL_GUC_STATUS|EVENT|PARAM_* becomes more than 80 chars for some values
3. I wanted intel_guc_slpc_fwif.h to be included only in 
intel_guc_slpc.c from where we can export functions as intel_guc_slpc_*
     static functions in intel_guc_slpc.c are named as slpc_*.
    In my series, point 3 above is not done but that was intent. There 
is access to SLPC enums from debugfs.c. Would consolidate all in 
intel_guc_slpc.c and export.

Does this plan look good?
>> +    SLPC_STATUS_OK = 0,
>> +    SLPC_STATUS_ERROR = 1,
>> +    SLPC_STATUS_ILLEGAL_COMMAND = 2,
>> +    SLPC_STATUS_INVALID_ARGS = 3,
>> +    SLPC_STATUS_INVALID_PARAMS = 4,
>> +    SLPC_STATUS_INVALID_DATA = 5,
>> +    SLPC_STATUS_OUT_OF_RANGE = 6,
>> +    SLPC_STATUS_NOT_SUPPORTED = 7,
>> +    SLPC_STATUS_NOT_IMPLEMENTED = 8,
>> +    SLPC_STATUS_NO_DATA = 9,
>> +    SLPC_STATUS_EVENT_NOT_REGISTERED = 10,
>> +    SLPC_STATUS_REGISTER_LOCKED = 11,
>> +    SLPC_STATUS_TEMPORARILY_UNAVAILABLE = 12,
>> +    SLPC_STATUS_VALUE_ALREADY_SET = 13,
>> +    SLPC_STATUS_VALUE_ALREADY_UNSET = 14,
>> +    SLPC_STATUS_VALUE_NOT_CHANGED = 15,
>> +    SLPC_STATUS_MEMIO_ERROR = 16,
>> +    SLPC_STATUS_EVENT_QUEUED_REQ_DPC = 17,
>> +    SLPC_STATUS_EVENT_QUEUED_NOREQ_DPC = 18,
>> +    SLPC_STATUS_NO_EVENT_QUEUED = 19,
>> +    SLPC_STATUS_OUT_OF_SPACE = 20,
>> +    SLPC_STATUS_TIMEOUT = 21,
>> +    SLPC_STATUS_NO_LOCK = 22,
>> +    SLPC_STATUS_MAX
>
> s/SLPC_STATUS/INTEL_GUC_SLPC_STATUS
>
>> +};
>> +
>> +enum slpc_event_id {
>
> s/slpc_event_id/intel_guc_slpc_event
>
>> +    SLPC_EVENT_RESET = 0,
>> +    SLPC_EVENT_SHUTDOWN = 1,
>> +    SLPC_EVENT_PLATFORM_INFO_CHANGE = 2,
>> +    SLPC_EVENT_DISPLAY_MODE_CHANGE = 3,
>> +    SLPC_EVENT_FLIP_COMPLETE = 4,
>> +    SLPC_EVENT_QUERY_TASK_STATE = 5,
>> +    SLPC_EVENT_PARAMETER_SET = 6,
>> +    SLPC_EVENT_PARAMETER_UNSET = 7,
>
> s/SLPC_EVENT/INTEL_GUC_SLPC_EVENT
>
>> +};
>> +
>> +enum slpc_param_id {
>
> s/slpc_param_id/intel_guc_slpc_param
>
>> +    SLPC_PARAM_TASK_ENABLE_GTPERF = 0,
>> +    SLPC_PARAM_TASK_DISABLE_GTPERF = 1,
>> +    SLPC_PARAM_TASK_ENABLE_BALANCER = 2,
>> +    SLPC_PARAM_TASK_DISABLE_BALANCER = 3,
>> +    SLPC_PARAM_TASK_ENABLE_DCC = 4,
>> +    SLPC_PARAM_TASK_DISABLE_DCC = 5,
>> +    SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ = 6,
>> +    SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ = 7,
>> +    SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ = 8,
>> +    SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ = 9,
>> +    SLPC_PARAM_GTPERF_THRESHOLD_MAX_FPS = 10,
>> +    SLPC_PARAM_GLOBAL_DISABLE_GT_FREQ_MANAGEMENT = 11,
>> +    SLPC_PARAM_GTPERF_ENABLE_FRAMERATE_STALLING = 12,
>> +    SLPC_PARAM_GLOBAL_DISABLE_RC6_MODE_CHANGE = 13,
>> +    SLPC_PARAM_GLOBAL_OC_UNSLICE_FREQ_MHZ = 14,
>> +    SLPC_PARAM_GLOBAL_OC_SLICE_FREQ_MHZ = 15,
>> +    SLPC_PARAM_GLOBAL_ENABLE_IA_GT_BALANCING = 16,
>> +    SLPC_PARAM_GLOBAL_ENABLE_ADAPTIVE_BURST_TURBO = 17,
>> +    SLPC_PARAM_GLOBAL_ENABLE_EVAL_MODE = 18,
>> +    SLPC_PARAM_GLOBAL_ENABLE_BALANCER_IN_NON_GAMING_MODE = 19,
>
> s/SLPC_PARAM/INTEL_GUC_SLPC_PARAM
>
>> +    SLPC_MAX_PARAM,
>> +    SLPC_KMD_MAX_PARAM = 32,
>
> hmm, do we really need these two ? please drop
>
> or maybe these are related to SLPC_MAX_OVERRIDE_PARAMETERS ?
Ok. Will drop SLPC_KMD_MAX_PARAM.
There are total 192 params (MAX_OVERRIDE_PARAMS) out of which 32 
(KMD_MAX_PARAM) params can be exposed
to KMD, but currently only params till MAX_PARAM < 32 are exported.
>
>> +};
>> +
>> +enum slpc_global_state {
>
> s/slpc_global_state/intel_guc_slpc_state
>
>> +    SLPC_GLOBAL_STATE_NOT_RUNNING = 0,
>> +    SLPC_GLOBAL_STATE_INITIALIZING = 1,
>> +    SLPC_GLOBAL_STATE_RESETTING = 2,
>> +    SLPC_GLOBAL_STATE_RUNNING = 3,
>> +    SLPC_GLOBAL_STATE_SHUTTING_DOWN = 4,
>> +    SLPC_GLOBAL_STATE_ERROR = 5
>
> s/SLPC_GLOBAL_STATE/INTEL_GUC_SLPC_STATE
>
>> +};
>> +
>> +enum slpc_platform_sku {
>> +    SLPC_PLATFORM_SKU_UNDEFINED = 0,
>> +    SLPC_PLATFORM_SKU_ULX = 1,
>> +    SLPC_PLATFORM_SKU_ULT = 2,
>> +    SLPC_PLATFORM_SKU_T = 3,
>> +    SLPC_PLATFORM_SKU_MOBL = 4,
>> +    SLPC_PLATFORM_SKU_DT = 5,
>> +    SLPC_PLATFORM_SKU_UNKNOWN = 6,
>
> hmm, this should be already known to GuC/SLPC.
> and if still needed, can it be made non-SLPC specific?
>
In current firmwares this is not possible but certainly can be changed 
in newer firmwares.
Will suggest this to Bob, Daisy.
Will keep it SLPC specific for now as only SLPC uses it.
>> +};
>> +
>> +enum slpc_power_source {
>
> s/slpc_power_source/intel_power_source
>
>> +    SLPC_POWER_SOURCE_UNDEFINED = 0,
>> +    SLPC_POWER_SOURCE_AC = 1,
>> +    SLPC_POWER_SOURCE_DC = 2,
>> +    SLPC_POWER_SOURCE_UNKNOWN = 3,
>
> s/SLPC_POWER_SOURCE/INTEL_POWER_SOURCE
>
>> +};
>> +
>> +enum slpc_power_plan {
>> +    SLPC_POWER_PLAN_UNDEFINED = 0,
>> +    SLPC_POWER_PLAN_BATTERY_SAVER = 1,
>> +    SLPC_POWER_PLAN_BALANCED = 2,
>> +    SLPC_POWER_PLAN_PERFORMANCE = 3,
>> +    SLPC_POWER_PLAN_UNKNOWN = 4,
>> +};
>> +
>> +struct slpc_platform_info {
>
> s/slpc_platform_info/intel_guc_slpc_platform
>
>> +    u8 sku;
>> +    u8 slice_count;
>> +    u8 reserved;
>> +    u8 power_plan_source;
>
> from macros below, it looks that this is bitfield and
> in other struct bitfields are defined explicitly...
>
> what about defining related MASK/SHIFT and MAKE/TO macros here?
>
Yes. Can add those.
>> +    u8 p0_freq;
>> +    u8 p1_freq;
>> +    u8 pe_freq;
>> +    u8 pn_freq;
>> +    u32 reserved1;
>> +    u32 reserved2;
>> +} __packed;
>> +
>> +struct slpc_task_state_data {
>> +    union {
>> +        u32 bitfield1;
>> +        struct {
>> +            u32 gtperf_task_active:1;
>> +            u32 gtperf_stall_possible:1;
>> +            u32 gtperf_gaming_mode:1;
>> +            u32 gtperf_target_fps:8;
>> +            u32 dcc_task_active:1;
>> +            u32 in_dcc:1;
>> +            u32 in_dct:1;
>> +            u32 freq_switch_active:1;
>> +            u32 ibc_enabled:1;
>> +            u32 ibc_active:1;
>> +            u32 pg1_enabled:1;
>> +            u32 pg1_active:1;
>> +            u32 reserved:13;
>
> All register bits and most of shared data are defined as
> macros, maybe we can do the same for SLPC ?
>
> #define INTEL_GUC_SLPC_TASK_GTPERF_ACTIVE    (1 << 0)
> #define INTEL_GUC_SLPC_TASK_GTPERF_STALL    (1 << 1)
> ...
>
>> +        };
>> +    };
>> +    union {
>> +        u32 bitfield2;
>> +        struct {
>> +            u32 max_unslice_freq:8;
>> +            u32 min_unslice_freq:8;
>> +            u32 max_slice_freq:8;
>> +            u32 min_slice_freq:8;
>> +        };
>> +    };
>> +} __packed;
>> +
>> +#define SLPC_MAX_OVERRIDE_PARAMETERS 192
>> +#define SLPC_OVERRIDE_BITFIELD_SIZE \
>> +        ((SLPC_MAX_OVERRIDE_PARAMETERS + 31) / 32)
>
> are there "NON-OVERRIDE" parameters?
>
Yes. Non-accessible ones (>MAX_PARAM)
>> +
>> +struct slpc_shared_data {
>
> s/slpc_shared_data/intel_guc_slpc_shared_data
> or
> s/slpc_shared_data/intel_guc_slpc_data
>
>> +    u32 reserved;
>
> hmm, starting with reserved is odd ;)
Yes.
>
>> +    u32 shared_data_size;
>
> s/shared_data_size/size
>
Will do this.
>> +    u32 global_state;
>> +    struct slpc_platform_info platform_info;
>> +    struct slpc_task_state_data task_state_data;
>> +    u32 override_params_set_bits[SLPC_OVERRIDE_BITFIELD_SIZE];
>> +    u32 override_params_values[SLPC_MAX_OVERRIDE_PARAMETERS];
>
> above two can be promoted to separate struct:
>
> struct intel_guc_slpc_params {
>     u32 valid[INTEL_GUC_SLPC_PARAMS_BITFIELD_SIZE];
>     u32 values[INTEL_GUC_SLPC_MAX_PARAMS];
> };
>
Sure.
>> +} __packed;
>> +
>> +enum slpc_reset_flags {
>
> s/slpc_reset_flags/intel_guc_slpc_reset_flags
>
>> +    SLPC_RESET_FLAG_TDR_OCCURRED = (1 << 0)
>
> s/SLPC_RESET_FLAG/INTEL_GUC_SLPC_RESET_FLAG
> and to minimize later diffs add trailing ","
>
>> +};
>> +
>> +#define SLPC_EVENT_MAX_INPUT_ARGS  7
>> +#define SLPC_EVENT_MAX_OUTPUT_ARGS 1
>> +
>> +union slpc_event_input_header {
>> +    u32 value;
>> +    struct {
>> +        u32 num_args:8;
>> +        u32 event_id:8;
>> +    };
>
> I'm not sure that this struct deserves separate definition
>
>> +};
>> +
>> +struct slpc_event_input {
>> +    u32 h2g_action_id;
>
> what h2g action is this ?
Seems to be not used by even by GuC SLPC. another change for interface 
update.
> if this event is sent over CTB then probably num_args is
> redundant as total CTB message len is already stored in
> CT header...
>
Agree.
>> +    union slpc_event_input_header header;
>> +    u32 args[SLPC_EVENT_MAX_INPUT_ARGS];
>> +} __packed;
>> +
>> +union slpc_event_output_header {
>> +    u32 value;
>> +    struct {
>> +        u32 num_args:8;
>> +        u32 event_id:8;
>> +        u32 status:16;
>> +    };
>> +};
>> +
>> +struct slpc_event_output {
>> +    u32 reserved;
>
> is this needed ?
>
Can skip. What I have done is take entire SLPC interface file from 
firmware source and just rename things.
Agree that such things should not be exported if they are not going to 
be used. Will share with Bob/Daisy.
>> +    union slpc_event_output_header header;
>
> hmm, "header" should be first ;)
>
>> +    u32 args[SLPC_EVENT_MAX_OUTPUT_ARGS];
>> +} __packed;
>> +
>> +#define SLPC_EVENT(id, argc)         ((u32)(id) << 8 | (argc))
>> +#define SLPC_POWER_PLAN_SOURCE(plan, source) ((plan) | ((source) << 6))
>> +#define SLPC_POWER_PLAN(plan_source)     ((plan_source) & 0x3F)
>> +#define SLPC_POWER_SOURCE(plan_source)     ((plan_source) >> 6)
>
> maybe:
>
>     INTEL_GUC_SLPC_MAKE_EVENT
>     INTEL_GUC_SLPC_MAKE_POWER_INFO
>     INTEL_GUC_SLPC_POWER_INFO_TO_PLAN
>     INTEL_GUC_SLPC_POWER_INFO_TO_SOURCE
>
> and use SHIFT/MASK macros
>
Yes but need your thoughts on INTEL_GUC prefix.
>> +
>> +#define SLPC_PARAM_TASK_DEFAULT  0
>> +#define SLPC_PARAM_TASK_ENABLED  1
>> +#define SLPC_PARAM_TASK_DISABLED 2
>> +#define SLPC_PARAM_TASK_UNKNOWN  3
>
> in other places you are using enums, why #defines here?
>
Will unify.

Thanks for the review
>> +
>> +#endif

-- 
Thanks,
Sagar

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Re: [PATCH v12 03/17] drm/i915/guc/slpc: Lay out SLPC init/enable/disable/fini helpers

[Michal Wajdeczko]

On Fri, 30 Mar 2018 10:31:48 +0200, Sagar Arun Kamble  
<sagar.a.kamble@intel.com> wrote:

> SLPC operates based on parameters setup in shared data between i915 and
> GuC SLPC. This is to be created/initialized in intel_guc_slpc_init. From
> there onwards i915 can control the SLPC operations by enabling, disabling
> complete SLPC or changing SLPC parameters. During cleanup, SLPC shared
> data has to be freed.
>
> v1: Return void instead of ignored error code. Replace HAS_SLPC() use  
> with
>     intel_slpc_enabled()/ intel_slpc_active() (Paulo)
>     Enable/disable RC6 in SLPC flows (Sagar)
>     Fix for renaming gen9_disable_rps to gen9_disable_rc6 in
>     "drm/i915/bxt: Explicitly clear the Turbo control register"
>     Defer RC6 and SLPC enabling to intel_gen6_powersave_work. (Sagar)
>     Performance drop with SLPC was happening as ring frequency table was
>     not programmed when SLPC was enabled. This patch programs ring
>     frequency table with SLPC. Initial reset of SLPC is based on kernel
>     parameter as planning to add slpc state in intel_slpc_active. Cleanup
>     is also based on kernel parameter as SLPC gets disabled in
>     disable/suspend.(Sagar)
>
> v2: Usage of INTEL_GEN instead of INTEL_INFO->gen (David)
>     Checkpatch update.
>
> v3: Rebase
>
> v4: Removed reset functions to comply with *_gt_powersave routines.
>     (Sagar)
>
> v5: Removed intel_slpc_active. Relying on slpc.active for control flows
>     that are based on SLPC active status in GuC. State setup/cleanup  
> needed
>     for SLPC is handled using kernel parameter i915.enable_slpc. Moved  
> SLPC
>     init and enabling to GuC enable path as SLPC in GuC can start doing  
> the
>     setup post GuC init. Commit message update. (Sagar)
>
> v6: Rearranged function definitions.
>
> v7: Makefile rearrangement. Reducing usage of i915.enable_slpc and  
> relying
>     mostly on rps.rps_enabled to bypass Host RPS flows. Commit message
>     update.
>
> v8: Changed parameters for SLPC functions to struct intel_slpc*.
>
> v9: Reinstated intel_slpc_active and intel_slpc_enabled as they are more
>     meaningful.
>
> v10: Rebase changes due to creation of intel_guc.h. Updates in
>      intel_guc_cleanup w.r.t slpc cleanup.
>
> v11: s/intel_slpc/intel_guc_slpc. Adjusted place for slpc struct inside
>      guc struct. (Michal Wajdeczko)
>      Updated comment about intel_slpc_enable as we plan to not defer the
>      SLPC status check on enabling later and will have to wait for SLPC
>      status as part of intel_slpc_enable itself.
>      Prepared guc_slpc_initialized and guc_slpc_enabled to track state
>      of SLPC initialization and enabling.
>
> v12: s/guc_slpc_cleanup/guc_slpc_fini. Updated SLPC flows w.r.t uC flows.
>
> Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
> Cc: Jeff McGee <jeff.mcgee@intel.com>
> ---
>  drivers/gpu/drm/i915/Makefile         |  1 +
>  drivers/gpu/drm/i915/intel_guc.h      |  2 ++
>  drivers/gpu/drm/i915/intel_guc_slpc.c | 25 +++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_guc_slpc.h | 17 +++++++++++++++++
>  drivers/gpu/drm/i915/intel_uc.c       | 30  
> +++++++++++++++++++++++++++++-
>  5 files changed, 74 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/gpu/drm/i915/intel_guc_slpc.c
>  create mode 100644 drivers/gpu/drm/i915/intel_guc_slpc.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile  
> b/drivers/gpu/drm/i915/Makefile
> index 0c79c19..499cb89 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -90,6 +90,7 @@ i915-y += intel_uc.o \
>  	  intel_guc_ct.o \
>  	  intel_guc_fw.o \
>  	  intel_guc_log.o \
> +	  intel_guc_slpc.o \
>  	  intel_guc_submission.o \
>  	  intel_huc.o \
>  	  intel_huc_fw.o
> diff --git a/drivers/gpu/drm/i915/intel_guc.h  
> b/drivers/gpu/drm/i915/intel_guc.h
> index f1265e1..2d2451a 100644
> --- a/drivers/gpu/drm/i915/intel_guc.h
> +++ b/drivers/gpu/drm/i915/intel_guc.h
> @@ -31,6 +31,7 @@
>  #include "intel_guc_ct.h"
>  #include "intel_guc_log.h"
>  #include "intel_guc_reg.h"
> +#include "intel_guc_slpc.h"
>  #include "intel_uc_fw.h"
>  #include "i915_vma.h"
> @@ -48,6 +49,7 @@ struct intel_guc {
>  	struct intel_uc_fw fw;
>  	struct intel_guc_log log;
>  	struct intel_guc_ct ct;
> +	struct intel_guc_slpc slpc;
> 	/* Offset where Non-WOPCM memory starts. */
>  	u32 ggtt_pin_bias;
> diff --git a/drivers/gpu/drm/i915/intel_guc_slpc.c  
> b/drivers/gpu/drm/i915/intel_guc_slpc.c
> new file mode 100644
> index 0000000..63f100c
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/intel_guc_slpc.c
> @@ -0,0 +1,25 @@
> +/*
> + * SPDX-License-Identifier: MIT
> + *
> + * Copyright © 2015-2018 Intel Corporation
> + */
> +
> +#include "intel_guc_slpc.h"
> +
> +int intel_guc_slpc_init(struct intel_guc_slpc *slpc)
> +{
> +	return 0;
> +}
> +
> +int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
> +{
> +	return 0;
> +}
> +
> +void intel_guc_slpc_disable(struct intel_guc_slpc *slpc)
> +{
> +}
> +
> +void intel_guc_slpc_fini(struct intel_guc_slpc *slpc)
> +{
> +}
> diff --git a/drivers/gpu/drm/i915/intel_guc_slpc.h  
> b/drivers/gpu/drm/i915/intel_guc_slpc.h
> new file mode 100644
> index 0000000..66c76fe
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/intel_guc_slpc.h
> @@ -0,0 +1,17 @@
> +/*
> + * SPDX-License-Identifier: MIT
> + *
> + * Copyright © 2015-2018 Intel Corporation
> + */
> +#ifndef _INTEL_GUC_SLPC_H_
> +#define _INTEL_GUC_SLPC_H_
> +
> +struct intel_guc_slpc {
> +};
> +
> +int intel_guc_slpc_init(struct intel_guc_slpc *slpc);
> +int intel_guc_slpc_enable(struct intel_guc_slpc *slpc);
> +void intel_guc_slpc_disable(struct intel_guc_slpc *slpc);
> +void intel_guc_slpc_fini(struct intel_guc_slpc *slpc);
> +
> +#endif
> diff --git a/drivers/gpu/drm/i915/intel_uc.c  
> b/drivers/gpu/drm/i915/intel_uc.c
> index 0e4a97f..5bf33c8 100644
> --- a/drivers/gpu/drm/i915/intel_uc.c
> +++ b/drivers/gpu/drm/i915/intel_uc.c
> @@ -319,6 +319,15 @@ int intel_uc_init(struct drm_i915_private *dev_priv)
>  		}
>  	}
> +	if (USES_GUC_SLPC(dev_priv)) {
> +		ret = intel_guc_slpc_init(&guc->slpc);
> +		if (ret) {
> +			intel_guc_submission_fini(guc);
> +			intel_guc_fini(guc);
> +			return ret;

I think we prefer to use "goto" single cleanup section at the end of  
function.

> +		}
> +	}
> +
>  	return 0;
>  }
> @@ -331,6 +340,9 @@ void intel_uc_fini(struct drm_i915_private *dev_priv)
> 	GEM_BUG_ON(!HAS_GUC(dev_priv));
> +	if (USES_GUC_SLPC(dev_priv))
> +		intel_guc_slpc_fini(&guc->slpc);
> +
>  	if (USES_GUC_SUBMISSION(dev_priv))
>  		intel_guc_submission_fini(guc);
> @@ -413,10 +425,21 @@ int intel_uc_init_hw(struct drm_i915_private  
> *dev_priv)
>  			goto err_communication;
>  	}
> +	/*
> +	 * SLPC is enabled by setting up the shared data structure and
> +	 * sending reset event to GuC SLPC. Initial data is setup in
> +	 * intel_guc_slpc_init. Here we send the reset event.
> +	 */

This comment should be part of intel_guc_slpc_enable fun description.

Hmm, but wait, this patch defines only placeholders for slpc* functions,
so maybe you should revisit that idea and provide real implementation here.

> +	if (USES_GUC_SLPC(dev_priv)) {
> +		ret = intel_guc_slpc_enable(&guc->slpc);
> +		if (ret)
> +			goto err_communication;
> +	}
> +
>  	if (USES_GUC_SUBMISSION(dev_priv)) {
>  		ret = intel_guc_submission_enable(guc);
>  		if (ret)
> -			goto err_communication;
> +			goto err_slpc;
>  	}
> 	dev_info(dev_priv->drm.dev, "GuC firmware version %u.%u\n",
> @@ -431,6 +454,8 @@ int intel_uc_init_hw(struct drm_i915_private  
> *dev_priv)
>  	/*
>  	 * We've failed to load the firmware :(
>  	 */
> +err_slpc:
> +	intel_guc_slpc_disable(&guc->slpc);
>  err_communication:
>  	guc_disable_communication(guc);
>  err_log_capture:
> @@ -459,6 +484,9 @@ void intel_uc_fini_hw(struct drm_i915_private  
> *dev_priv)
>  	if (USES_GUC_SUBMISSION(dev_priv))
>  		intel_guc_submission_disable(guc);
> +	if (USES_GUC_SLPC(dev_priv))
> +		intel_guc_slpc_disable(&guc->slpc);
> +
>  	guc_disable_communication(guc);
>  }
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Re: [PATCH v12 06/17] drm/i915/guc/slpc: Allocate/initialize/release SLPC shared data

[Michal Wajdeczko]

On Fri, 30 Mar 2018 10:31:51 +0200, Sagar Arun Kamble  
<sagar.a.kamble@intel.com> wrote:

> Populate SLPC shared data with required default values for slice count,
> power source/plan, IA perf MSRs.
>
> v1: Update for SLPC interface version 2015.2.4. intel_slpc_active()
>     returns 1 if slpc initialized (Paulo)
>     change default host_os to "Windows"
>     Spelling fixes (Sagar and Nick Hoath). Added WARN for checking if
>     upper 32bits of GTT offset of shared object are zero. (Chris)
>     Updated commit message and moved POWER_PLAN and POWER_SOURCE defn.
>     from later patch. (Akash)
>     Add struct_mutex locking while allocating/releasing slpc shared
>     object. This was caught by CI BAT. Adding SLPC state variable to
>     determine if it is active as it not just dependent on shared data
>     setup. Rebase with guc_allocate_vma related changes.
>
> v2: WARN_ON for platform_sku validity and space changes.(David)
>     Checkpatch update.
>
> v3: Fixing WARNING in igt@drv_module_reload_basic found in trybot BAT
>     with SLPC Enabled.
>
> v4: Updated support for GuC v9.  
> s/slice_total/hweight8(slice_mask)/(Dave).
>
> v5: SLPC vma map changes and removed explicit type conversions.(Chris).
>     s/freq_unslice_max|min/unslice__max|min_freq.
>
> v6: Commit message update. s/msr_value/val for reuse later.
>
> v7: Set default values for tasks and min frequency parameters. Moved init
>     with allocation of data so that post GuC load earlier params persist.
>
> v8: Added check for SLPC status during cleanup of shared data. SLPC
>     disabling is asynchronous and should complete within 10us.
>
> v9: Enabling Balancer task in SLPC.
>
> v10: Rebase.
>
> v11: Rebase. Added lock specific to SLPC.
>
> Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
> Cc: Jeff McGee <jeff.mcgee@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h       |   5 +
>  drivers/gpu/drm/i915/intel_guc_slpc.c | 204  
> ++++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_guc_slpc.h |   3 +
>  3 files changed, 212 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h  
> b/drivers/gpu/drm/i915/i915_drv.h
> index 5176801..d17e778 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2416,6 +2416,11 @@ intel_info(const struct drm_i915_private  
> *dev_priv)
> #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
> +#define IS_ULX_SKU(dev_priv)	(IS_SKL_ULX(dev_priv) ||  
> IS_KBL_ULX(dev_priv))
> +#define IS_ULT_SKU(dev_priv)	(IS_SKL_ULT(dev_priv) || \
> +				 IS_KBL_ULT(dev_priv) || \
> +				 IS_CFL_ULT(dev_priv))
> +
>  #define SKL_REVID_A0		0x0
>  #define SKL_REVID_B0		0x1
>  #define SKL_REVID_C0		0x2
> diff --git a/drivers/gpu/drm/i915/intel_guc_slpc.c  
> b/drivers/gpu/drm/i915/intel_guc_slpc.c
> index 63f100c..974a3c0 100644
> --- a/drivers/gpu/drm/i915/intel_guc_slpc.c
> +++ b/drivers/gpu/drm/i915/intel_guc_slpc.c
> @@ -4,10 +4,203 @@
>   * Copyright © 2015-2018 Intel Corporation
>   */
> +#include <asm/msr-index.h>
> +
> +#include "i915_drv.h"
>  #include "intel_guc_slpc.h"
> +static inline struct intel_guc *slpc_to_guc(struct intel_guc_slpc *slpc)
> +{
> +	return container_of(slpc, struct intel_guc, slpc);
> +}
> +
> +static unsigned int slpc_get_platform_sku(struct drm_i915_private  
> *dev_priv)

If you want to use 'slpc_' prefix for your functions, then always pass
struct intel_guc_slpc *slpc as first param

> +{
> +	enum slpc_platform_sku platform_sku;
> +
> +	if (IS_ULX_SKU(dev_priv))
> +		platform_sku = SLPC_PLATFORM_SKU_ULX;
> +	else if (IS_ULT_SKU(dev_priv))
> +		platform_sku = SLPC_PLATFORM_SKU_ULT;
> +	else
> +		platform_sku = SLPC_PLATFORM_SKU_DT;

Do we really need to pass this to SLPC/GuC?

> +
> +	WARN_ON(platform_sku > 0xFF);

Maybe just define this function to return u16 ?

> +
> +	return platform_sku;
> +}
> +
> +static unsigned int slpc_get_slice_count(struct drm_i915_private  
> *dev_priv)

Is this really slpc specific function ?
Maybe this can be added as inline from intel_device_info.h ?

> +{
> +	unsigned int slice_count = 1;
> +
> +	if (IS_SKYLAKE(dev_priv))
> +		slice_count = hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask);
> +
> +	return slice_count;
> +}
> +
> +static void slpc_mem_set_param(struct slpc_shared_data *data,
> +			       u32 id,
> +			       u32 value)
> +{
> +	data->override_params_set_bits[id >> 5] |= (1 << (id % 32));
> +	data->override_params_values[id] = value;
> +}
> +
> +static void slpc_mem_unset_param(struct slpc_shared_data *data,
> +				 u32 id)
> +{
> +	data->override_params_set_bits[id >> 5] &= (~(1 << (id % 32)));
> +	data->override_params_values[id] = 0;
> +}
> +
> +static int slpc_mem_task_control(struct slpc_shared_data *data,
> +				 u64 val, u32 enable_id, u32 disable_id)
> +{
> +	int ret = 0;
> +
> +	if (val == SLPC_PARAM_TASK_DEFAULT) {
> +		/* set default */
> +		slpc_mem_unset_param(data, enable_id);
> +		slpc_mem_unset_param(data, disable_id);
> +	} else if (val == SLPC_PARAM_TASK_ENABLED) {
> +		/* set enable */
> +		slpc_mem_set_param(data, enable_id, 1);
> +		slpc_mem_unset_param(data, disable_id);
> +	} else if (val == SLPC_PARAM_TASK_DISABLED) {
> +		/* set disable */
> +		slpc_mem_set_param(data, disable_id, 1);
> +		slpc_mem_unset_param(data, enable_id);
> +	} else {
> +		ret = -EINVAL;
> +	}
> +
> +	return ret;
> +}
> +
> +static void slpc_shared_data_init(struct intel_guc_slpc *slpc)
> +{
> +	struct intel_guc *guc = slpc_to_guc(slpc);
> +	struct drm_i915_private *dev_priv = guc_to_i915(guc);
> +	struct slpc_platform_info *platform_info;
> +	struct slpc_shared_data *data;
> +	struct page *page;
> +	u64 val;
> +
> +	lockdep_assert_held(&slpc->lock);
> +
> +	page = i915_vma_first_page(slpc->vma);
> +	data = kmap_atomic(page);
> +	platform_info = &data->platform_info;
> +
> +	memset(data, 0, sizeof(struct slpc_shared_data));
> +
> +	data->shared_data_size = sizeof(struct slpc_shared_data);
> +	data->global_state = SLPC_GLOBAL_STATE_NOT_RUNNING;
> +	platform_info->sku = slpc_get_platform_sku(dev_priv);
> +	platform_info->slice_count = slpc_get_slice_count(dev_priv);
> +	platform_info->power_plan_source =
> +			SLPC_POWER_PLAN_SOURCE(SLPC_POWER_PLAN_BALANCED,
> +					       SLPC_POWER_SOURCE_AC);
> +
> +	rdmsrl(MSR_TURBO_RATIO_LIMIT, val);
> +	platform_info->p0_freq = val;
> +	rdmsrl(MSR_PLATFORM_INFO, val);
> +	platform_info->p1_freq = val >> 8;
> +	platform_info->pe_freq = val >> 40;
> +	platform_info->pn_freq = val >> 48;
> +
> +	/* Enable only GTPERF task, Disable others */
> +	val = SLPC_PARAM_TASK_ENABLED;
> +	slpc_mem_task_control(data, val,
> +			      SLPC_PARAM_TASK_ENABLE_GTPERF,
> +			      SLPC_PARAM_TASK_DISABLE_GTPERF);
> +
> +	slpc_mem_task_control(data, val,
> +			      SLPC_PARAM_TASK_ENABLE_BALANCER,
> +			      SLPC_PARAM_TASK_DISABLE_BALANCER);
> +
> +	val = SLPC_PARAM_TASK_DISABLED;
> +	slpc_mem_task_control(data, val,
> +			      SLPC_PARAM_TASK_ENABLE_DCC,
> +			      SLPC_PARAM_TASK_DISABLE_DCC);
> +
> +	slpc_mem_set_param(data,
> +			   SLPC_PARAM_GTPERF_THRESHOLD_MAX_FPS,
> +			   0);
> +
> +	slpc_mem_set_param(data,
> +			   SLPC_PARAM_GTPERF_ENABLE_FRAMERATE_STALLING,
> +			   0);
> +
> +	slpc_mem_set_param(data,
> +			   SLPC_PARAM_GLOBAL_ENABLE_IA_GT_BALANCING,
> +			   1);
> +
> +	slpc_mem_set_param(data,
> +			   SLPC_PARAM_GLOBAL_ENABLE_ADAPTIVE_BURST_TURBO,
> +			   0);
> +
> +	slpc_mem_set_param(data,
> +			   SLPC_PARAM_GLOBAL_ENABLE_EVAL_MODE,
> +			   0);
> +
> +	slpc_mem_set_param(data,
> +			   SLPC_PARAM_GLOBAL_ENABLE_BALANCER_IN_NON_GAMING_MODE,
> +			   1);
> +
> +	slpc_mem_set_param(data,
> +			   SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
> +			   intel_gpu_freq(dev_priv,
> +					  dev_priv->gt_pm.rps.efficient_freq));
> +
> +	slpc_mem_set_param(data,
> +			   SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ,
> +			   intel_gpu_freq(dev_priv,
> +					  dev_priv->gt_pm.rps.efficient_freq));
> +
> +	kunmap_atomic(data);
> +}
> +
> +/**
> + * intel_guc_slpc_init() - Initialize the SLPC shared data structure.
> + * @slpc: pointer to intel_guc_slpc.
> + *
> + * This function will create object to be shared with GuC SLPC and
> + * initialize it with required initial parameter values for various
> + * SLPC knobs such as min frequency limit, enabling/disabling of SLPC
> + * tasks etc.
> + *
> + * Return: 0 on success, non-zero error code on failure.
> + */
> +
>  int intel_guc_slpc_init(struct intel_guc_slpc *slpc)
>  {
> +	struct intel_guc *guc = slpc_to_guc(slpc);
> +	u32 size = PAGE_ALIGN(sizeof(struct slpc_shared_data));
> +	struct i915_vma *vma;
> +
> +	mutex_init(&slpc->lock);
> +
> +	mutex_lock(&slpc->lock);

Do we need this lock here ?

> +
> +	vma = slpc->vma;
> +	if (!vma) {
> +		/* Allocate shared data structure */
> +		vma = intel_guc_allocate_vma(guc, size);
> +		if (IS_ERR(vma)) {
> +			DRM_ERROR("Shared data allocation failed\n");
> +			mutex_unlock(&slpc->lock);
> +			return PTR_ERR(vma);
> +		}
> +		slpc->vma = vma;
> +	}
> +
> +	slpc_shared_data_init(slpc);
> +
> +	mutex_unlock(&slpc->lock);
> +
>  	return 0;
>  }
> @@ -20,6 +213,17 @@ void intel_guc_slpc_disable(struct intel_guc_slpc  
> *slpc)
>  {
>  }
> +/**
> + * intel_guc_slpc_fini() - Release the SLPC shared data structure.
> + * @slpc: pointer to intel_guc_slpc.
> + *
> + * This function will release the shared data. SLPC needs to be disabled
> + * prior to this.
> + */
>  void intel_guc_slpc_fini(struct intel_guc_slpc *slpc)
>  {
> +	/* Release shared data structure */
> +	mutex_lock(&slpc->lock);
> +	i915_vma_unpin_and_release(&slpc->vma);
> +	mutex_unlock(&slpc->lock);
>  }
> diff --git a/drivers/gpu/drm/i915/intel_guc_slpc.h  
> b/drivers/gpu/drm/i915/intel_guc_slpc.h
> index 81250c0..87dac07 100644
> --- a/drivers/gpu/drm/i915/intel_guc_slpc.h
> +++ b/drivers/gpu/drm/i915/intel_guc_slpc.h
> @@ -9,6 +9,9 @@
>  #include <intel_guc_slpc_fwif.h>
> struct intel_guc_slpc {
> +	/* Protects access to vma and SLPC actions */
> +	struct mutex lock;
> +	struct i915_vma *vma;
>  };
> int intel_guc_slpc_init(struct intel_guc_slpc *slpc);
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Re: [PATCH v12 07/17] drm/i915/guc/slpc: Send RESET event to restart/enable SLPC tasks

[Michal Wajdeczko]

On Fri, 30 Mar 2018 10:31:52 +0200, Sagar Arun Kamble  
<sagar.a.kamble@intel.com> wrote:

> Host to GuC actions for SLPC receive additional data as output through
> scratch registers currently. intel_guc_send_and_receive handles this.
> We need to define SLPC specific Host to GuC send action (slpc_send) as
> wrapper on top of it to process the SLPC status that is received in
> SOFT_SCRATCH(1).
>
> Send host2guc SLPC reset event to GuC post GuC load for enabling SLPC.
> Post this, i915 can ascertain if SLPC has started running successfully
> through shared data. This check is done by waiting for maximum 5ms.
> SLPC reset event also needs to be sent when parameters in shared data
> are updated.
>
> v1: Extract host2guc_slpc to handle slpc status code and style changes.
>     (Paulo). Removed WARN_ON for checking msb of gtt address of shared
>      gem obj. (Chris). host2guc_action to i915_guc_action change.(Sagar)
>     Updating SLPC enabled status. (Sagar)
>
> v2: Commit message update. (David)
>
> v3: Rebase.
>
> v4: Added DRM_INFO message when SLPC is enabled.
>
> v5: Updated patch as host2guc_slpc is moved to earlier patch. SLPC
>     activation status message put after checking the state from shared
>     data during intel_init_gt_powersave.
>
> v6: Added definition of host2guc_slpc and clflush the shared data only
>     for required size. Setting state to NOT_RUNNING before sending RESET
>     event. Output data for SLPC actions is to be retrieved during
>     intel_guc_send with lock protection so created wrapper
>     __intel_guc_send that outputs GuC output data if needed. Clearing
>     pm_rps_events on confirming SLPC RUNNING status so that even if
>     host touches any of the PM registers by mistake it should not have
>     any effect. (Sagar)
>
> v7: Added save/restore_default_rps as Uncore sanitize will clear the
>     RP_CONTROL setup by BIOS. s/i915_ggtt_offset/guc_ggtt_offset.
>
> v8: Added support for handling TDR based SLPC reset. Added functions
>     host2guc_slpc_tdr_reset, intel_slpc_reset_prepare and
>     intel_slpc_tdr_reset to handle TDR based SLPC reset.
>
> v9: Moved TDR support to later patch. Removed intel_slpc_get_status
>     and waiting for maximum of 5ms for SLPC state to turn RUNNING instead
>     of hiding the latency across uc_init_hw and init_gt_powersave.
>     s/if..else/switch..case in intel_guc_slpc_get_state_str. Removed SLPC
>     sanitization from init_gt_powersave. (Michal Wajdeczko)
>
> v10: Rebase.
>
> v11: Rebase. Created slpc_send func as wrapper on guc_send_and_receive.
>
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
> Cc: Jeff McGee <jeff.mcgee@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_guc_slpc.c | 239  
> ++++++++++++++++++++++++++++++++++
>  1 file changed, 239 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_guc_slpc.c  
> b/drivers/gpu/drm/i915/intel_guc_slpc.c
> index 974a3c0..bc2c717 100644
> --- a/drivers/gpu/drm/i915/intel_guc_slpc.c
> +++ b/drivers/gpu/drm/i915/intel_guc_slpc.c
> @@ -163,6 +163,211 @@ static void slpc_shared_data_init(struct  
> intel_guc_slpc *slpc)
>  	kunmap_atomic(data);
>  }
> +static const char *slpc_status_stringify(int status)

I guess this should be defined as:

static const char *slpc_status_stringify(enum slpc_status status)
or
static const char *stringify_slpc_status(enum slpc_status status)

but I'm wondering if we really need to be that user friendly,
as all these errors are unlikely and will be interpreted by the
professionals that can match error value with the enum name in code;)

> +{
> +	const char *str = NULL;
> +
> +	switch(status) {
> +	case SLPC_STATUS_OK:
> +		str = "Ok";
> +		break;
> +	case SLPC_STATUS_ERROR:
> +		str = "Error";
> +		break;
> +	case SLPC_STATUS_ILLEGAL_COMMAND:
> +		str = "Illegal command";
> +		break;
> +	case SLPC_STATUS_INVALID_ARGS:
> +		str = "Invalid args";
> +		break;
> +	case SLPC_STATUS_INVALID_PARAMS:
> +		str = "Invalid params";
> +		break;
> +	case SLPC_STATUS_INVALID_DATA:
> +		str = "Invalid data";
> +		break;
> +	case SLPC_STATUS_OUT_OF_RANGE:
> +		str = "Out of range";
> +		break;
> +	case SLPC_STATUS_NOT_SUPPORTED:
> +		str = "Not supported";
> +		break;
> +	case SLPC_STATUS_NOT_IMPLEMENTED:
> +		str = "Not implemented";
> +		break;
> +	case SLPC_STATUS_NO_DATA:
> +		str = "No data";
> +		break;
> +	case SLPC_STATUS_EVENT_NOT_REGISTERED:
> +		str = "Event not registered";
> +		break;
> +	case SLPC_STATUS_REGISTER_LOCKED:
> +		str = "Register locked";
> +		break;
> +	case SLPC_STATUS_TEMPORARILY_UNAVAILABLE:
> +		str = "Temporarily unavailable";
> +		break;
> +	case SLPC_STATUS_VALUE_ALREADY_SET:
> +		str = "Value already set";
> +		break;
> +	case SLPC_STATUS_VALUE_ALREADY_UNSET:
> +		str = "Value already unset";
> +		break;
> +	case SLPC_STATUS_VALUE_NOT_CHANGED:
> +		str = "Value not changed";
> +		break;
> +	case SLPC_STATUS_MEMIO_ERROR:
> +		str = "MMIO error";
> +		break;
> +	case SLPC_STATUS_EVENT_QUEUED_REQ_DPC:
> +		str = "Event queued, DPC requested";
> +		break;
> +	case SLPC_STATUS_EVENT_QUEUED_NOREQ_DPC:
> +		str = "Event queued, DPC not requested";
> +		break;
> +	case SLPC_STATUS_NO_EVENT_QUEUED:
> +		str = "Event not queued";
> +		break;
> +	case SLPC_STATUS_OUT_OF_SPACE:
> +		str = "Out of space";
> +		break;
> +	case SLPC_STATUS_TIMEOUT:
> +		str = "Timeout";
> +		break;
> +	case SLPC_STATUS_NO_LOCK:
> +		str = "No lock";
> +		break;
> +	}
> +
> +	return str;
> +}
> +
> +static void slpc_send(struct intel_guc_slpc *slpc,
> +		      struct slpc_event_input *input, u32 in_len)
> +{
> +	struct intel_guc *guc = slpc_to_guc(slpc);
> +	struct slpc_event_output output;
> +	u32 out_len = 1;
> +	u32 *action;
> +	int ret;
> +
> +	action = (u32 *)input;

maybe better to be explicit and use:

	action = input->h2g_action_id;

> +	action[0] = INTEL_GUC_ACTION_SLPC_REQUEST;
> +
> +	ret = intel_guc_send_and_receive(guc, action, in_len,
> +					 (u32 *)&output.header, out_len);
> +
> +	/*
> +	 * Currently output data from Host to GuC SLPC actions is populated
> +	 * in scratch registers SOFT_SCRATCH(1) to SOFT_SCRATCH(14) based

hmm, this comment will be wrong if we use CT as communication method

> +	 * on event. Currently only SLPC action status in GuC is meaningful
> +	 * as Host can query only overridden parameters and that are fetched
> +	 * from Host-GuC SLPC shared data. Other parameters can be read through
> +	 * output data but that is available only for debug GuC firmwares.
> +	 */
> +	if (!ret) {
> +		ret = output.header.status;
> +		if (ret) {
> +			GEM_BUG_ON(ret >= SLPC_STATUS_MAX);
> +			DRM_ERROR("event 0x%x status %s\n",
> +				  ((output.header.value & 0xFF00) >> 8),
> +				  slpc_status_stringify(ret));
> +		}
> +	}
> +}
> +
> +static void host2guc_slpc_reset(struct intel_guc_slpc *slpc)
> +{
> +	struct intel_guc *guc = slpc_to_guc(slpc);
> +	u32 shared_data_gtt_offset = intel_guc_ggtt_offset(guc, slpc->vma);
> +	struct slpc_event_input data = {0};
> +
> +	data.header.value = SLPC_EVENT(SLPC_EVENT_RESET, 2);

maybe s/SLPC_EVENT/MAKE_SLPC_EVENT_HEADER ?

> +	data.args[0] = shared_data_gtt_offset;
> +	data.args[1] = 0;
> +
> +	slpc_send(slpc, &data, 4);

you don't need to pass 4 explicitly, instead let slpc_send() use:

	input->num_args

> +}
> +
> +static void host2guc_slpc_query_task_state(struct intel_guc_slpc *slpc)
> +{
> +	struct intel_guc *guc = slpc_to_guc(slpc);
> +	u32 shared_data_gtt_offset = intel_guc_ggtt_offset(guc, slpc->vma);
> +	struct slpc_event_input data = {0};
> +
> +	data.header.value = SLPC_EVENT(SLPC_EVENT_QUERY_TASK_STATE, 2);
> +	data.args[0] = shared_data_gtt_offset;

no need for local var, use:

	data.args[0] = intel_guc_ggtt_offset(guc, slpc->vma);

> +	data.args[1] = 0;
> +
> +	slpc_send(slpc, &data, 4);
> +}
> +
> +static void slpc_read_shared_data(struct intel_guc_slpc *slpc,
> +				  struct slpc_shared_data *data)
> +{
> +	struct page *page;
> +	void *pv = NULL;
> +
> +	host2guc_slpc_query_task_state(slpc);
> +
> +	page = i915_vma_first_page(slpc->vma);
> +	pv = kmap_atomic(page);

maybe it would be better to kmap once and keep pv as part of slpc?

> +
> +	drm_clflush_virt_range(pv, sizeof(struct slpc_shared_data));
> +	memcpy(data, pv, sizeof(struct slpc_shared_data));
> +
> +	kunmap_atomic(pv);
> +}
> +
> +static const char *slpc_state_stringify(enum slpc_global_state state)
> +{
> +	const char *str = NULL;
> +
> +	switch (state) {
> +	case SLPC_GLOBAL_STATE_NOT_RUNNING:
> +		str = "not running";
> +		break;
> +	case SLPC_GLOBAL_STATE_INITIALIZING:
> +		str = "initializing";
> +		break;
> +	case SLPC_GLOBAL_STATE_RESETTING:
> +		str = "resetting";
> +		break;
> +	case SLPC_GLOBAL_STATE_RUNNING:
> +		str = "running";
> +		break;
> +	case SLPC_GLOBAL_STATE_SHUTTING_DOWN:
> +		str = "shutting down";
> +		break;
> +	case SLPC_GLOBAL_STATE_ERROR:
> +		str = "error";
> +		break;
> +	default:
> +		str = "unknown";
> +		break;
> +	}
> +
> +	return str;
> +}
> +
> +static const char *slpc_get_state(struct intel_guc_slpc *slpc)

to be more flexible, I would rather define this helper as:

static enum slpc_global_state slpc_get_state(struct intel_guc_slpc *slpc)

to let the caller decide later if he want value or string

> +{
> +	struct slpc_shared_data data;
> +
> +	slpc_read_shared_data(slpc, &data);
> +
> +	return slpc_state_stringify(data.global_state);
> +}
> +
> +static bool slpc_running(struct intel_guc_slpc *slpc)
> +{
> +	struct slpc_shared_data data;
> +
> +	slpc_read_shared_data(slpc, &data);
> +
> +	return (data.global_state == SLPC_GLOBAL_STATE_RUNNING);
> +}
> +
>  /**
>   * intel_guc_slpc_init() - Initialize the SLPC shared data structure.
>   * @slpc: pointer to intel_guc_slpc.
> @@ -204,8 +409,42 @@ int intel_guc_slpc_init(struct intel_guc_slpc *slpc)
>  	return 0;
>  }
> +/**
> + * intel_guc_slpc_enable() - Start SLPC.
> + * @slpc: pointer to intel_guc_slpc.
> + *
> + * This function will start GuC SLPC by sending Host to GuC action.
> + * SLPC shared data has to be initialized prior to this by
> + * intel_guc_slpc_init().
> + *
> + * Return: 0 on success, non-zero error code on failure.
> + */
>  int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
>  {
> +	struct slpc_shared_data *data;
> +	struct page *page;
> +
> +	mutex_lock(&slpc->lock);
> +
> +	page = i915_vma_first_page(slpc->vma);
> +	data = kmap_atomic(page);
> +	data->global_state = SLPC_GLOBAL_STATE_NOT_RUNNING;
> +	kunmap_atomic(data);
> +
> +	host2guc_slpc_reset(slpc);

please add error check

> +
> +	/* Check whether SLPC is running */
> +	if (wait_for(slpc_running(slpc), 5)) {

hmm, it looks that reading shared data will be done many times
in this function ... why we can't add H2G SLPC command that will
return with status that will match 'global' status, not just ack?

> +		DRM_ERROR("SLPC not enabled! State = %s\n",
> +			  slpc_get_state(slpc));
> +		mutex_unlock(&slpc->lock);
> +		return -EIO;
> +	}
> +
> +	DRM_INFO("SLPC state: %s\n", slpc_get_state(slpc));
> +
> +	mutex_unlock(&slpc->lock);
> +
>  	return 0;
>  }
>

/michal
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Re: [PATCH v12 08/17] drm/i915/guc/slpc: Send SHUTDOWN event to stop SLPC tasks

[Michal Wajdeczko]

On Fri, 30 Mar 2018 10:31:53 +0200, Sagar Arun Kamble  
<sagar.a.kamble@intel.com> wrote:

> From: Tom O'Rourke <Tom.O'Rourke@intel.com>
>
> Send SLPC shutdown event during uc_fini_hw or prior to enabling SLPC
> done while communicating updated parameters in shared data.
>
> v1: Return void instead of ignored error code (Paulo). Removed WARN_ON
>     for checking msb of gtt address of shared gem obj. (Chris)
>     Added SLPC state update during disable, suspend and reset. Changed
>     semantics of reset. It is supposed to just disable. (Sagar)
>
> v2-v4: Rebase.
>
> v5: Updated the input data structure. (Sagar)
>
> v6: Rebase.
>
> v7: s/i915_ggtt_offset/guc_ggtt_offset.
>
> v8: Updated the status check post disabling to wait for 20us. (Sagar)
>
> v9: Updated the status check wait time to 5ms for safe margin as it is
>     handled similar to reset by SLPC. s/slpc_disabled/slpc_stopped
>
> v10: Rebase.
>
> Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
> Cc: Jeff McGee <jeff.mcgee@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_guc_slpc.c | 38  
> +++++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_uc.c       |  6 +++---
>  2 files changed, 41 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_guc_slpc.c  
> b/drivers/gpu/drm/i915/intel_guc_slpc.c
> index bc2c717..7f75d218 100644
> --- a/drivers/gpu/drm/i915/intel_guc_slpc.c
> +++ b/drivers/gpu/drm/i915/intel_guc_slpc.c
> @@ -368,6 +368,28 @@ static bool slpc_running(struct intel_guc_slpc  
> *slpc)
>  	return (data.global_state == SLPC_GLOBAL_STATE_RUNNING);
>  }
> +static void host2guc_slpc_shutdown(struct intel_guc_slpc *slpc)
> +{
> +	struct intel_guc *guc = slpc_to_guc(slpc);
> +	u32 shared_data_gtt_offset = intel_guc_ggtt_offset(guc, slpc->vma);
> +	struct slpc_event_input data = {0};
> +
> +	data.header.value = SLPC_EVENT(SLPC_EVENT_SHUTDOWN, 2);
> +	data.args[0] = shared_data_gtt_offset;

	data.args[0] = intel_guc_ggtt_offset(guc, slpc->vma);

> +	data.args[1] = 0;

hmm, this '0' means something ? or it is MBZ ?
but since events num_args is flexible, maybe we can drop it ?

> +
> +	slpc_send(slpc, &data, 4);
> +}
> +
> +static bool slpc_stopped(struct intel_guc_slpc *slpc)
> +{
> +	struct slpc_shared_data data;
> +
> +	slpc_read_shared_data(slpc, &data);
> +
> +	return (data.global_state == SLPC_GLOBAL_STATE_NOT_RUNNING);
> +}
> +
>  /**
>   * intel_guc_slpc_init() - Initialize the SLPC shared data structure.
>   * @slpc: pointer to intel_guc_slpc.
> @@ -448,8 +470,24 @@ int intel_guc_slpc_enable(struct intel_guc_slpc  
> *slpc)
>  	return 0;
>  }
> +/**
> + * intel_guc_slpc_disable() - Stop SLPC tasks.
> + * @slpc: pointer to intel_guc_slpc.
> + *
> + * This function will stop GuC SLPC tasks by sending Host to GuC action.
> + */
>  void intel_guc_slpc_disable(struct intel_guc_slpc *slpc)
>  {
> +	mutex_lock(&slpc->lock);
> +
> +	host2guc_slpc_shutdown(slpc);
> +
> +	/* Ensure SLPC is not running */
> +	if (wait_for(slpc_stopped(slpc), 5))
> +		DRM_ERROR("SLPC not disabled! State = %s\n",
> +			  slpc_get_state(slpc));
> +
> +	mutex_unlock(&slpc->lock);
>  }
> /**
> diff --git a/drivers/gpu/drm/i915/intel_uc.c  
> b/drivers/gpu/drm/i915/intel_uc.c
> index 5bf33c8..ece6687 100644
> --- a/drivers/gpu/drm/i915/intel_uc.c
> +++ b/drivers/gpu/drm/i915/intel_uc.c
> @@ -359,6 +359,9 @@ void intel_uc_sanitize(struct drm_i915_private *i915)
> 	GEM_BUG_ON(!HAS_GUC(i915));
> +	if (USES_GUC_SLPC(dev_priv))
> +		intel_guc_slpc_disable(&guc->slpc);
> +
>  	guc_disable_communication(guc);
> 	intel_huc_sanitize(huc);
> @@ -484,9 +487,6 @@ void intel_uc_fini_hw(struct drm_i915_private  
> *dev_priv)
>  	if (USES_GUC_SUBMISSION(dev_priv))
>  		intel_guc_submission_disable(guc);
> -	if (USES_GUC_SLPC(dev_priv))
> -		intel_guc_slpc_disable(&guc->slpc);
> -

Can we avoid such code movement within one series ?

>  	guc_disable_communication(guc);
>  }
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Re: [PATCH v12 10/17] drm/i915/guc/slpc: Add parameter set/unset/get, task control/status functions

[Michal Wajdeczko]

On Fri, 30 Mar 2018 10:31:55 +0200, Sagar Arun Kamble  
<sagar.a.kamble@intel.com> wrote:

> SLPC behavior can be changed through set of parameters. These parameters
> can be updated and queried from i915 though Host to GuC SLPC events. This
> patch adds parameter update events for setting/unsetting/getting params.
> Setting parameter leads to overridding of default parameter value. Unset
> leads to restoring of default value by communicating with GuC SLPC  
> through
> parameter updates in the shared data.
> i915 can only query/get parameters that it overrides, so getting  
> parameter
> value is done by only reading from the shared data.
>
> SLPC has various tasks, GTPERF, BALANCER and DCC. These can be controlled
> through pair of GuC SLPC parameters. Enable/disable of these tasks  
> require
> combined update to both parameters hence new actions are added to control
> and query the status of tasks.
>
> v1: Use host2guc_slpc. Update slcp_param_id enum values for SLPC 2015.2.4
>     Return void instead of ignored error code (Paulo)
>
> v2: Checkpatch update.
>
> v3: Rebase.
>
> v4: Updated with GuC firmware v9.
>
> v5: Updated input structure to host2guc_slpc. Added functions to update
>     only parameters in the SLPC shared memory. This will allow to setup
>     shared data with all parameters and send single event to SLPC take
>     them into effect. Commit message update. (Sagar)
>
> v6: Rearranged helpers to use them in slpc_shared_data_init. Added defn.
>     of SLPC_KMD_MAX_PARAM.
>
> v7: Added definition of host2guc_slpc with rearrangement of patches.  
> Added
>     task control/status functions.
>
> v8: Rebase w.r.t s/intel_guc_send/intel_guc_send_mmio.
>
> v9: Created intel_guc_slpc_send_mmio with SLPC specific H2G action send
>     function. Rebase. Defined slpc_statuslist and using the same in
>     intel_guc_slpc_send_mmio. (Michal Wajdeczko)
>
> v10: Rebase. Added kernel documentation to the task control functions.
>
> Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
> Cc: Jeff McGee <jeff.mcgee@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_guc_slpc.c | 173  
> ++++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_guc_slpc.h |   5 +
>  2 files changed, 178 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_guc_slpc.c  
> b/drivers/gpu/drm/i915/intel_guc_slpc.c
> index bdafbaa..011e442 100644
> --- a/drivers/gpu/drm/i915/intel_guc_slpc.c
> +++ b/drivers/gpu/drm/i915/intel_guc_slpc.c
> @@ -404,6 +404,179 @@ static void host2guc_slpc_tdr_reset(struct  
> intel_guc_slpc *slpc)
>  	slpc_send(slpc, &data, 5);
>  }
> +static void host2guc_slpc_set_param(struct intel_guc_slpc *slpc,
> +				    u32 id, u32 value)

s/host2guc_slpc_set_param/slpc_send_set_param

and in general (not sure if already discussed this):
s/host2guc_slpc_/slpc_send_


> +{
> +	struct slpc_event_input data = {0};
> +
> +	data.header.value = SLPC_EVENT(SLPC_EVENT_PARAMETER_SET, 2);
> +	data.args[0] = id;
> +	data.args[1] = value;
> +
> +	slpc_send(slpc, &data, 4);
> +}
> +
> +static void host2guc_slpc_unset_param(struct intel_guc_slpc *slpc,
> +				      u32 id)
> +{
> +	struct slpc_event_input data = {0};
> +
> +	data.header.value = SLPC_EVENT(SLPC_EVENT_PARAMETER_UNSET, 1);
> +	data.args[0] = id;
> +
> +	slpc_send(slpc, &data, 3);
> +}
> +
> +static void slpc_set_param(struct intel_guc_slpc *slpc, u32 id, u32  
> value)
> +{
> +	struct slpc_shared_data *data = NULL;
> +	struct page *page;
> +
> +	GEM_BUG_ON(id >= SLPC_MAX_PARAM);
> +	GEM_BUG_ON(!slpc->vma);
> +
> +	lockdep_assert_held(&slpc->lock);
> +
> +	page = i915_vma_first_page(slpc->vma);
> +	data = kmap_atomic(page);
> +	slpc_mem_set_param(data, id, value);

hmm, why we have to pass param value by two mechanisms?
what if 'send' fails or slpc rejects that value?

> +	kunmap_atomic(data);
> +
> +	host2guc_slpc_set_param(slpc, id, value);
> +}
> +
> +static void slpc_unset_param(struct intel_guc_slpc *slpc, u32 id)
> +{
> +	struct slpc_shared_data *data = NULL;
> +	struct page *page;
> +
> +	GEM_BUG_ON(id >= SLPC_MAX_PARAM);
> +	GEM_BUG_ON(!slpc->vma);
> +
> +	lockdep_assert_held(&slpc->lock);
> +
> +	page = i915_vma_first_page(slpc->vma);
> +	data = kmap_atomic(page);
> +	slpc_mem_unset_param(data, id);
> +	kunmap_atomic(data);
> +
> +	host2guc_slpc_unset_param(slpc, id);
> +}
> +
> +static void slpc_get_param(struct intel_guc_slpc *slpc, u32 id,
> +			   int *overriding, u32 *value)
> +{
> +	struct slpc_shared_data *data = NULL;
> +	struct page *page;
> +	u32 bits;
> +
> +	GEM_BUG_ON(id >= SLPC_MAX_PARAM);
> +	GEM_BUG_ON(!slpc->vma);
> +
> +	lockdep_assert_held(&slpc->lock);
> +
> +	page = i915_vma_first_page(slpc->vma);
> +	data = kmap_atomic(page);
> +	if (overriding) {
> +		bits = data->override_params_set_bits[id >> 5];
> +		*overriding = (0 != (bits & (1 << (id % 32))));
> +	}
> +	if (value)
> +		*value = data->override_params_values[id];
> +
> +	kunmap_atomic(data);
> +}
> +
> +/**
> + * intel_guc_slpc_task_control() - Update status of SLPC task.
> + * @slpc: pointer to intel_guc_slpc.
> + *
> + * This function will update status of task in SLPC shared data.
> + * Then it invokes SLPC Host to GuC action to communicate the
> + * required task status.
> + *
> + * Return: 0 on success, non-zero error code on failure.
> + */
> +int intel_guc_slpc_task_control(struct intel_guc_slpc *slpc, u64 val,
> +				u32 enable_id, u32 disable_id)
> +{
> +	int ret = 0;
> +
> +	GEM_BUG_ON(!slpc->vma);
> +
> +	lockdep_assert_held(&slpc->lock);
> +
> +	if (val == SLPC_PARAM_TASK_DEFAULT) {
> +		/* set default */

please drop these comments

> +		slpc_unset_param(slpc, enable_id);
> +		slpc_unset_param(slpc, disable_id);
> +	} else if (val == SLPC_PARAM_TASK_ENABLED) {
> +		/* set enable */
> +		slpc_set_param(slpc, enable_id, 1);
> +		slpc_unset_param(slpc, disable_id);
> +	} else if (val == SLPC_PARAM_TASK_DISABLED) {
> +		/* set disable */
> +		slpc_set_param(slpc, disable_id, 1);
> +		slpc_unset_param(slpc, enable_id);
> +	} else {
> +		ret = -EINVAL;
> +	}
> +
> +	host2guc_slpc_reset(slpc);
> +
> +	return ret;
> +}
> +
> +/**
> + * intel_guc_slpc_task_status() - gets the status of SLPC task.
> + * @slpc: pointer to intel_guc_slpc.
> + *
> + * This function will read status of task from SLPC shared data.
> + * Task could be in either "enabled", "disabled", "default" or
> + * "unknown" state.
> + *
> + * Return: 0 on success, non-zero error code on failure.
> + */
> +int intel_guc_slpc_task_status(struct intel_guc_slpc *slpc, u64 *val,
> +			       u32 enable_id, u32 disable_id)
> +{
> +	int override_enable, override_disable;
> +	u32 value_enable, value_disable;
> +	int ret = 0;
> +
> +	GEM_BUG_ON(!slpc->vma);

iirc, bkm is that we should not check against null ptr

> +
> +	lockdep_assert_held(&slpc->lock);
> +
> +	if (val) {
> +		slpc_get_param(slpc, enable_id,
> +			       &override_enable, &value_enable);
> +		slpc_get_param(slpc, disable_id,
> +			       &override_disable, &value_disable);
> +
> +		/*
> +		 * Set the output value:
> +		 * 0: default
> +		 * 1: enabled
> +		 * 2: disabled
> +		 * 3: unknown (should not happen)
> +		 */
> +		if (override_disable && value_disable == 1)
> +			*val = SLPC_PARAM_TASK_DISABLED;
> +		else if (override_enable && value_enable == 1)
> +			*val = SLPC_PARAM_TASK_ENABLED;
> +		else if (!override_enable && !override_disable)
> +			*val = SLPC_PARAM_TASK_DEFAULT;
> +		else
> +			*val = SLPC_PARAM_TASK_UNKNOWN;
> +
> +	} else {
> +		ret = -EINVAL;
> +	}
> +
> +	return ret;
> +}
> +
>  /**
>   * intel_guc_slpc_init() - Initialize the SLPC shared data structure.
>   * @slpc: pointer to intel_guc_slpc.
> diff --git a/drivers/gpu/drm/i915/intel_guc_slpc.h  
> b/drivers/gpu/drm/i915/intel_guc_slpc.h
> index 75f0b5d..87b504d 100644
> --- a/drivers/gpu/drm/i915/intel_guc_slpc.h
> +++ b/drivers/gpu/drm/i915/intel_guc_slpc.h
> @@ -14,6 +14,11 @@ struct intel_guc_slpc {
>  	struct i915_vma *vma;
>  };
> +int intel_guc_slpc_task_control(struct intel_guc_slpc *slpc, u64 val,
> +				u32 enable_id, u32 disable_id);
> +int intel_guc_slpc_task_status(struct intel_guc_slpc *slpc, u64 *val,
> +			       u32 enable_id, u32 disable_id);
> +
>  int intel_guc_slpc_init(struct intel_guc_slpc *slpc);
>  int intel_guc_slpc_enable(struct intel_guc_slpc *slpc);
>  void intel_guc_slpc_handle_engine_reset(struct intel_guc_slpc *slpc);
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Re: [PATCH v12 12/17] drm/i915/guc/slpc: Add enable/disable controls for SLPC tasks

[Michal Wajdeczko]

On Fri, 30 Mar 2018 10:31:57 +0200, Sagar Arun Kamble  
<sagar.a.kamble@intel.com> wrote:

> From: Tom O'Rourke <Tom.O'Rourke@intel.com>
>
> Adds debugfs hooks for enabling/disabling each SLPC task.
>
> The enable/disable debugfs files are:
> i915_guc_slpc_gtperf, i915_guc_slpc_balancer, and i915_guc_slpc_dcc.
>
> Each of these can take the values: "default", "enabled", or "disabled"
>
> v1: update for SLPC v2015.2.4
>     dfps and turbo merged and renamed "gtperf"
>     ibc split out and renamed "balancer"
>     Avoid magic numbers (Jon Bloomfield)
>
> v2-v3: Rebase.
>
> v5: Moved slpc_enable_disable_set and slpc_enable_disable_get to
>     intel_slpc.c. s/slpc_enable_disable_get/intel_slpc_task_status
>     and s/slpc_enable_disable_set/intel_slpc_task_control. Prepared
>     separate functions to update the task status only in the SLPC
>     shared memory. Passing dev_priv as parameter.
>
> v6: Rebase. s/slpc_param_show|write/slpc_task_param_show|write.
>     Moved functions to intel_slpc.c. RPM Get/Put added before setting
>     parameters and sending RESET event explicitly. (Sagar)
>
> v7: Rebase.
>
> Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
> Cc: Jeff McGee <jeff.mcgee@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 200  
> ++++++++++++++++++++++++++++++++++++
>  1 file changed, 200 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c  
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index ff90577..d646a04 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2580,6 +2580,203 @@ static const struct file_operations  
> i915_guc_log_relay_fops = {
>  	.release = i915_guc_log_relay_release,
>  };
> +static const char *slpc_task_status_stringify(int state)
> +{
> +	const char *str = NULL;
> +
> +	switch (state) {
> +	case SLPC_PARAM_TASK_DEFAULT:
> +		str = "default\n";

no \n please

> +		break;
> +
> +	case SLPC_PARAM_TASK_ENABLED:
> +		str = "enabled\n";
> +		break;
> +
> +	case SLPC_PARAM_TASK_DISABLED:
> +		str = "disabled\n";
> +		break;
> +
> +	default:
> +		str = "unknown\n";
> +		break;
> +	}
> +

btw, stringify_* functions can be as simple as:

switch(state)
{
case A:
	return "A";
case B:
	return "B";
default:
	return "<invalid>";
}

> +	return str;
> +}
> +
> +static int slpc_task_status_show(struct seq_file *m,
> +				 u32 enable_id,
> +				 u32 disable_id)
> +{
> +	struct drm_i915_private *dev_priv = m->private;
> +	struct intel_guc_slpc *slpc = &dev_priv->guc.slpc;
> +	const char *status = NULL;
> +	u64 val;
> +	int ret;
> +
> +	mutex_lock(&slpc->lock);
> +	ret = intel_guc_slpc_task_status(slpc, &val, enable_id, disable_id);

s/intel_guc_slpc_task_status/intel_guc_slpc_get_task_status

> +	mutex_unlock(&slpc->lock);
> +
> +	if (!ret)
> +		status = slpc_task_status_stringify(val);

hmm, I'm not sure if status "null" is something that user want to see
if we hit non zero 'ret'

> +
> +	seq_printf(m, "%s", status);

hmm, as val is returned by guc fw, what if its value will not
match predefined 0..3 ? showing just "unknown" without actual
bad value may be insufficient

> +
> +	return 0;
> +}
> +
> +static int slpc_task_status_write(struct seq_file *m,
> +				  const char __user *ubuf,
> +				  size_t len,
> +				  u32 enable_id,
> +				  u32 disable_id)
> +{
> +	struct drm_i915_private *dev_priv = m->private;
> +	struct intel_guc_slpc *slpc = &dev_priv->guc.slpc;
> +	int ret = 0;
> +	char status[10];
> +	u64 val;
> +
> +	if (len >= sizeof(status))
> +		ret = -EINVAL;
> +	else if (copy_from_user(status, ubuf, len))
> +		ret = -EFAULT;
> +	else
> +		status[len] = '\0';
> +
> +	if (ret)
> +		return ret;
> +
> +	if (!strncmp(status, "default", 7))
> +		val = SLPC_PARAM_TASK_DEFAULT;
> +	else if (!strncmp(status, "enabled", 7))
> +		val = SLPC_PARAM_TASK_ENABLED;
> +	else if (!strncmp(status, "disabled", 8))
> +		val = SLPC_PARAM_TASK_DISABLED;
> +	else
> +		return -EINVAL;
> +
> +	mutex_lock(&slpc->lock);
> +	ret = intel_guc_slpc_task_control(slpc, val, enable_id, disable_id);
> +	mutex_unlock(&slpc->lock);
> +
> +	return ret;
> +}
> +
> +static int slpc_gtperf_show(struct seq_file *m, void *data)
> +{
> +	return slpc_task_status_show(m,
> +				     SLPC_PARAM_TASK_ENABLE_GTPERF,
> +				     SLPC_PARAM_TASK_DISABLE_GTPERF);
> +}
> +
> +static int i915_guc_slpc_gtperf_open(struct inode *inode, struct file  
> *file)
> +{
> +	struct drm_i915_private *dev_priv = inode->i_private;
> +
> +	return single_open(file, slpc_gtperf_show, dev_priv);
> +}
> +
> +static ssize_t i915_guc_slpc_gtperf_write(struct file *file,
> +					  const char __user *ubuf,
> +					  size_t len,
> +					  loff_t *offp)
> +{
> +	struct seq_file *m = file->private_data;
> +	int ret = 0;
> +
> +	ret = slpc_task_status_write(m, ubuf, len,
> +				     SLPC_PARAM_TASK_ENABLE_GTPERF,
> +				     SLPC_PARAM_TASK_DISABLE_GTPERF);
> +
> +	return ret ?: len;
> +}
> +
> +const struct file_operations i915_guc_slpc_gtperf_fops = {
> +	.owner	 = THIS_MODULE,
> +	.open	 = i915_guc_slpc_gtperf_open,
> +	.release = single_release,
> +	.read	 = seq_read,
> +	.write	 = i915_guc_slpc_gtperf_write,
> +	.llseek	 = seq_lseek
> +};
> +
> +static int slpc_balancer_show(struct seq_file *m, void *data)
> +{
> +	return slpc_task_status_show(m,
> +				     SLPC_PARAM_TASK_ENABLE_BALANCER,
> +				     SLPC_PARAM_TASK_DISABLE_BALANCER);
> +}
> +
> +static int i915_guc_slpc_balancer_open(struct inode *inode, struct file  
> *file)
> +{
> +	struct drm_i915_private *dev_priv = inode->i_private;
> +
> +	return single_open(file, slpc_balancer_show, dev_priv);
> +}
> +
> +static ssize_t i915_guc_slpc_balancer_write(struct file *file,
> +					    const char __user *ubuf,
> +					    size_t len,
> +					    loff_t *offp)
> +{
> +	struct seq_file *m = file->private_data;
> +	int ret = 0;
> +
> +	ret = slpc_task_status_write(m, ubuf, len,
> +				     SLPC_PARAM_TASK_ENABLE_BALANCER,
> +				     SLPC_PARAM_TASK_DISABLE_BALANCER);
> +	return ret ?: len;
> +}
> +
> +const struct file_operations i915_guc_slpc_balancer_fops = {
> +	.owner	 = THIS_MODULE,
> +	.open	 = i915_guc_slpc_balancer_open,
> +	.release = single_release,
> +	.read	 = seq_read,
> +	.write	 = i915_guc_slpc_balancer_write,
> +	.llseek	 = seq_lseek
> +};
> +
> +static int slpc_dcc_show(struct seq_file *m, void *data)
> +{
> +	return slpc_task_status_show(m,
> +				     SLPC_PARAM_TASK_ENABLE_DCC,
> +				     SLPC_PARAM_TASK_DISABLE_DCC);
> +}
> +
> +static int i915_guc_slpc_dcc_open(struct inode *inode, struct file  
> *file)
> +{
> +	struct drm_i915_private *dev_priv = inode->i_private;
> +
> +	return single_open(file, slpc_dcc_show, dev_priv);
> +}
> +
> +static ssize_t i915_guc_slpc_dcc_write(struct file *file,
> +				       const char __user *ubuf,
> +				       size_t len,
> +				       loff_t *offp)
> +{
> +	struct seq_file *m = file->private_data;
> +	int ret = 0;
> +
> +	ret = slpc_task_status_write(m, ubuf, len,
> +				     SLPC_PARAM_TASK_ENABLE_DCC,
> +				     SLPC_PARAM_TASK_DISABLE_DCC);
> +	return ret ?: len;
> +}
> +
> +const struct file_operations i915_guc_slpc_dcc_fops = {
> +	.owner	 = THIS_MODULE,
> +	.open	 = i915_guc_slpc_dcc_open,
> +	.release = single_release,
> +	.read	 = seq_read,
> +	.write	 = i915_guc_slpc_dcc_write,
> +	.llseek	 = seq_lseek
> +};
> +

it would be good if you move all above code to intel_guc_slpc.c
to keep all slpc related stuff in one file

/michal

>  static const char *psr2_live_status(u32 val)
>  {
>  	static const char * const live_status[] = {
> @@ -4810,6 +5007,9 @@ static const struct i915_debugfs_files {
>  	{"i915_dp_test_active", &i915_displayport_test_active_fops},
>  	{"i915_guc_log_level", &i915_guc_log_level_fops},
>  	{"i915_guc_log_relay", &i915_guc_log_relay_fops},
> +	{"i915_guc_slpc_gtperf", &i915_guc_slpc_gtperf_fops},
> +	{"i915_guc_slpc_balancer", &i915_guc_slpc_balancer_fops},
> +	{"i915_guc_slpc_dcc", &i915_guc_slpc_dcc_fops},
>  	{"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops},
>  	{"i915_ipc_status", &i915_ipc_status_fops},
>  	{"i915_drrs_ctl", &i915_drrs_ctl_fops}
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Re: [PATCH v12 14/17] drm/i915/guc/slpc: Add debugfs support to read/write/revert the parameters

[Michal Wajdeczko]

On Fri, 30 Mar 2018 10:31:59 +0200, Sagar Arun Kamble  
<sagar.a.kamble@intel.com> wrote:

> Add support to set/read parameters and unset the parameters which will
> revert them to default SLPC internal values. Explicit SLPC reset is  
> needed
> on setting/unsetting some of the parameters.
>
> This patch adds two debugfs interfaces:
> 1. i915_guc_slpc_params: List of all parameters that Host can configure.
>    Currently listing id and description of each.
> 2. i915_guc_slpc_param_ctl: This allows to change the parameters.
>    Syntax is:
>    * Update parameter with id <id> with value <value>:
>      echo "write <id> <value>" > i915_guc_slpc_param_ctl
>    * Read parameter with id <id>
>      echo "read <id>" > i915_guc_slpc_param_ctl
>      cat i915_guc_slpc_param_ctl
>    * Revert parameter with id <id> to default value
>      echo "revert <id>" > i915_guc_slpc_param_ctl.
>
> v2: Moved the SLPC interfaces to i915_debugfs.c. Added error handling to
> the range of parameters and parsing. Making use of intel_guc_slpc_enabled
> instead of accessing status variable. Optimized token parsing.
> (Michal Wajdeczko) s/i915_slpc_paramlist/i915_guc_slpc_params and
> s/i915_slpc_param_ctl/i915_guc_slpc_param_ctl
>
> v3: Rebase.
>
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
> Cc: Jeff McGee <jeff.mcgee@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c        | 156  
> +++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_guc_slpc.c      |  87 ++++++++++++++++
>  drivers/gpu/drm/i915/intel_guc_slpc.h      |  18 ++++
>  drivers/gpu/drm/i915/intel_guc_slpc_fwif.h |  23 +++++
>  4 files changed, 284 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c  
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 5c1231f..f90ad52 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2777,6 +2777,160 @@ const struct file_operations  
> i915_guc_slpc_dcc_fops = {
>  	.llseek	 = seq_lseek
>  };
> +static int i915_guc_slpc_params_info(struct seq_file *m, void *data)
> +{
> +	struct drm_i915_private *dev_priv = node_to_i915(m->private);
> +	struct drm_printer p = drm_seq_file_printer(m);
> +
> +	if (!USES_GUC_SLPC(dev_priv))
> +		return -ENODEV;
> +
> +	intel_guc_slpc_params_print(&dev_priv->guc.slpc, &p);
> +
> +	return 0;
> +}
> +
> +static int slpc_param_ctl_show(struct seq_file *m, void *data)
> +{
> +	struct drm_i915_private *dev_priv = m->private;
> +	struct intel_guc_slpc *slpc = &dev_priv->guc.slpc;
> +
> +	if (!USES_GUC_SLPC(dev_priv))
> +		return -ENODEV;
> +
> +	if (slpc->debug.param_id >= SLPC_MAX_PARAM)
> +		return -EINVAL;
> +
> +	BUILD_BUG_ON(ARRAY_SIZE(slpc_params_desc) != SLPC_MAX_PARAM);
> +
> +	seq_printf(m, "%s=%u, override=%s\n",
> +			slpc_params_desc[slpc->debug.param_id],
> +			slpc->debug.param_value,
> +			yesno(!!slpc->debug.param_override));
> +
> +	return 0;
> +}
> +
> +static int slpc_param_ctl_open(struct inode *inode, struct file *file)
> +{
> +	return single_open(file, slpc_param_ctl_show, inode->i_private);
> +}
> +
> +/*
> + * Parse SLPC parameter control strings: (Similar to Pipe CRC handling)
> + *   command: wsp* op wsp+ param id wsp+ [value] wsp*
> + *   op: "read"/"write"/"revert"
> + *   param id: slpc_param_id
> + *   value: u32 value
> + *   wsp: (#0x20 | #0x9 | #0xA)+
> + *
> + * eg.:
> + *  "read 0"		-> read SLPC_PARAM_TASK_ENABLE_GTPERF
> + *  "write 7 500"	-> set SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ to  
> 500MHz
> + *  "revert 7"		-> revert SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ to
> + *			   default value.
> + */
> +static int slpc_param_ctl_parse(char *buf, size_t len, int *op,
> +				u32 *id, u32 *value)
> +{
> +#define MAX_WORDS 3
> +	int n_words;
> +	char *words[MAX_WORDS];
> +	ssize_t ret;
> +
> +	n_words = buffer_tokenize(buf, words, MAX_WORDS);
> +	if (!(n_words == 3) && !(n_words == 2)) {
> +		DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
> +				 MAX_WORDS);
> +		return -EINVAL;
> +	}
> +
> +	if (!strcmp(words[0], "read"))
> +		*op = READ_OP;
> +	else if (!strcmp(words[0], "write"))
> +		*op = WRITE_OP;
> +	else if (!strcmp(words[0], "revert"))
> +		*op = REVERT_OP;
> +	else {
> +		DRM_DEBUG_DRIVER("unknown operation\n");
> +		return -EINVAL;
> +	}
> +
> +	ret = kstrtou32(words[1], 0, id);
> +	if (ret)
> +		return ret;
> +
> +	if (n_words == 3) {
> +		ret = kstrtou32(words[2], 0, value);
> +		if (ret)
> +			return ret;
> +	}
> +
> +	return (n_words-1);
> +}
> +
> +static ssize_t slpc_param_ctl_write(struct file *file, const char  
> __user *ubuf,
> +				     size_t len, loff_t *offp)
> +{
> +	struct seq_file *m = file->private_data;
> +	struct drm_i915_private *dev_priv = m->private;
> +	struct intel_guc_slpc *slpc = &dev_priv->guc.slpc;
> +	char *tmpbuf;
> +	u32 id, value;
> +	int op, params;
> +	int ret = 0;
> +
> +	if (len == 0)
> +		return 0;
> +
> +	if (len > 40) {
> +		DRM_DEBUG_DRIVER("expected <40 chars into slpc_param_ctl\n");
> +		return -E2BIG;
> +	}
> +
> +	tmpbuf = kmalloc(len + 1, GFP_KERNEL);
> +	if (!tmpbuf)
> +		return -ENOMEM;
> +
> +	if (copy_from_user(tmpbuf, ubuf, len)) {
> +		ret = -EFAULT;
> +		goto out;
> +	}
> +	tmpbuf[len] = '\0';
> +
> +	params = slpc_param_ctl_parse(tmpbuf, len, &op, &id, &value);
> +
> +	if (params < 0 || id >= SLPC_MAX_PARAM) {
> +		ret = -EINVAL;
> +		goto out;
> +	}
> +
> +	intel_runtime_pm_get(dev_priv);
> +	mutex_lock(&slpc->lock);
> +
> +	ret = intel_guc_slpc_param_control(slpc, params, op, id, value);
> +
> +	mutex_unlock(&slpc->lock);
> +	intel_runtime_pm_put(dev_priv);
> +
> +out:
> +	kfree(tmpbuf);
> +	if (ret < 0)
> +		return ret;
> +
> +	*offp += len;
> +	return len;
> +}
> +
> +const struct file_operations i915_guc_slpc_param_ctl_fops = {
> +	.owner = THIS_MODULE,
> +	.open = slpc_param_ctl_open,
> +	.read = seq_read,
> +	.llseek = seq_lseek,
> +	.release = single_release,
> +	.write = slpc_param_ctl_write
> +};
> +

it would be great if you try to move even more of the above
code to intel_guc_slpc.c

>  static const char *psr2_live_status(u32 val)
>  {
>  	static const char * const live_status[] = {
> @@ -4942,6 +5096,7 @@ static const struct drm_info_list  
> i915_debugfs_list[] = {
>  	{"i915_guc_log_dump", i915_guc_log_dump, 0},
>  	{"i915_guc_load_err_log_dump", i915_guc_log_dump, 0, (void *)1},
>  	{"i915_guc_stage_pool", i915_guc_stage_pool, 0},
> +	{"i915_guc_slpc_params", i915_guc_slpc_params_info, 0},
>  	{"i915_huc_load_status", i915_huc_load_status_info, 0},
>  	{"i915_frequency_info", i915_frequency_info, 0},
>  	{"i915_hangcheck_info", i915_hangcheck_info, 0},
> @@ -5010,6 +5165,7 @@ static const struct i915_debugfs_files {
>  	{"i915_guc_slpc_gtperf", &i915_guc_slpc_gtperf_fops},
>  	{"i915_guc_slpc_balancer", &i915_guc_slpc_balancer_fops},
>  	{"i915_guc_slpc_dcc", &i915_guc_slpc_dcc_fops},
> +	{"i915_guc_slpc_param_ctl", &i915_guc_slpc_param_ctl_fops},
>  	{"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops},
>  	{"i915_ipc_status", &i915_ipc_status_fops},
>  	{"i915_drrs_ctl", &i915_drrs_ctl_fops}
> diff --git a/drivers/gpu/drm/i915/intel_guc_slpc.c  
> b/drivers/gpu/drm/i915/intel_guc_slpc.c
> index 34a5963..7bd5e3e 100644
> --- a/drivers/gpu/drm/i915/intel_guc_slpc.c
> +++ b/drivers/gpu/drm/i915/intel_guc_slpc.c
> @@ -578,6 +578,93 @@ int intel_guc_slpc_task_status(struct  
> intel_guc_slpc *slpc, u64 *val,
>  }
> /**
> + * intel_guc_slpc_params_print() - print parameters list.
> + * @slpc: pointer to intel_guc_slpc.
> + * @p: drm printer
> + *
> + * This function will print SLPC parameters id and their description.
> + *
> + */
> +void intel_guc_slpc_params_print(struct intel_guc_slpc *slpc,
> +				 struct drm_printer *p)
> +{
> +	int i;
> +
> +	BUILD_BUG_ON(ARRAY_SIZE(slpc_params_desc) != SLPC_MAX_PARAM);
> +
> +	drm_printf(p, "Param id\tParam description\n");
> +	for (i = 0; i < ARRAY_SIZE(slpc_params_desc); i++)
> +		drm_printf(p, "%8d\t%s\n", i, slpc_params_desc[i]);
> +}
> +
> +/**
> + * intel_guc_slpc_param_control() - read/write/revert parameter.
> + * @slpc: pointer to intel_guc_slpc.
> + * @params: number of parameters
> + * @op: operation (read, write, revert)
> + * @id: parameter id
> + * @value: parameter value
> + *
> + * This function will create object to be shared with GuC SLPC and
> + * initialize it with required initial parameter values for various
> + * SLPC knobs such as min frequency limit, enabling/disabling of SLPC
> + * tasks etc.
> + *
> + * Return: 0 on success, non-zero error code on failure.
> + */
> +int intel_guc_slpc_param_control(struct intel_guc_slpc *slpc,
> +				 u32 params, u32 op, u32 id, u32 value)
> +{
> +	int ret = 0;
> +
> +	GEM_BUG_ON(!slpc->vma);
> +
> +	lockdep_assert_held(&slpc->lock);
> +
> +	if (op == READ_OP) {
> +		if (params != 1) {
> +			ret = -EINVAL;
> +			goto out;
> +		}
> +		slpc_get_param(slpc, id,
> +			       &slpc->debug.param_override,
> +			       &slpc->debug.param_value);
> +		slpc->debug.param_id = id;
> +	} else if ((op == WRITE_OP) || (op == REVERT_OP)) {
> +		if ((id >= SLPC_PARAM_TASK_ENABLE_GTPERF) &&
> +		    (id <= SLPC_PARAM_TASK_DISABLE_DCC)) {
> +			DRM_DEBUG_DRIVER("Tasks are not controlled by "
> +					 "this interface\n");
> +			ret = -EINVAL;
> +			goto out;
> +		}
> +
> +		/*
> +		 * After updating parameters, RESET event has to be sent to GuC
> +		 * SLPC for ensuring parameters take effect.
> +		 */
> +		if (op == WRITE_OP) {
> +			if (params != 2) {
> +				ret = -EINVAL;
> +				goto out;
> +			}
> +			slpc_set_param(slpc, id, value);
> +		} else {
> +			if (params != 1) {
> +				ret = -EINVAL;
> +				goto out;
> +			}
> +			slpc_unset_param(slpc, id);
> +		}
> +		host2guc_slpc_reset(slpc);
> +	}
> +
> +out:
> +
> +	return ret;
> +}
> +
> +/**
>   * intel_guc_slpc_init() - Initialize the SLPC shared data structure.
>   * @slpc: pointer to intel_guc_slpc.
>   *
> diff --git a/drivers/gpu/drm/i915/intel_guc_slpc.h  
> b/drivers/gpu/drm/i915/intel_guc_slpc.h
> index 51189b3..693343e 100644
> --- a/drivers/gpu/drm/i915/intel_guc_slpc.h
> +++ b/drivers/gpu/drm/i915/intel_guc_slpc.h
> @@ -8,6 +8,8 @@
> #include <intel_guc_slpc_fwif.h>
> +struct drm_printer;
> +
>  struct intel_guc_slpc {
>  	/* Protects access to vma and SLPC actions */
>  	struct mutex lock;
> @@ -16,12 +18,28 @@ struct intel_guc_slpc {
>  	/* i915 cached SLPC frequency limits */
>  	u32 min_unslice_freq;
>  	u32 max_unslice_freq;
> +
> +	struct {
> +		u32 param_id;
> +		u32 param_value;
> +		u32 param_override;
> +	} debug;
> +};
> +
> +enum {
> +	READ_OP,
> +	WRITE_OP,
> +	REVERT_OP

maybe these enums should be prefixed with something slpc specific:

	[INTEL_]SLPC_PARAM_OP_ ?

>  };
> int intel_guc_slpc_task_control(struct intel_guc_slpc *slpc, u64 val,
>  				u32 enable_id, u32 disable_id);
>  int intel_guc_slpc_task_status(struct intel_guc_slpc *slpc, u64 *val,
>  			       u32 enable_id, u32 disable_id);
> +void intel_guc_slpc_params_print(struct intel_guc_slpc *slpc,
> +				 struct drm_printer *p);
> +int intel_guc_slpc_param_control(struct intel_guc_slpc *slpc,
> +				 u32 params, u32 op, u32 id, u32 value);
> int intel_guc_slpc_init(struct intel_guc_slpc *slpc);
>  int intel_guc_slpc_enable(struct intel_guc_slpc *slpc);
> diff --git a/drivers/gpu/drm/i915/intel_guc_slpc_fwif.h  
> b/drivers/gpu/drm/i915/intel_guc_slpc_fwif.h
> index 9400af4..65bbb03 100644
> --- a/drivers/gpu/drm/i915/intel_guc_slpc_fwif.h
> +++ b/drivers/gpu/drm/i915/intel_guc_slpc_fwif.h
> @@ -71,6 +71,29 @@ enum slpc_param_id {
>  	SLPC_KMD_MAX_PARAM = 32,
>  };
> +static const char * const slpc_params_desc[] = {

please, no arrays in .h

> +	"Enable task GTPERF",
> +	"Disable task GTPERF",
> +	"Enable task BALANCER",
> +	"Disable task BALANCER",
> +	"Enable task DCC",
> +	"Disable task DCC",
> +	"Minimum GT frequency request for unslice",
> +	"Maximum GT frequency request for unslice",
> +	"Minimum GT frequency request for slice",
> +	"Maximum GT frequency request for slice",
> +	"If non-zero, will slow down frame-based apps to this frame-rate",
> +	"Lock GT frequency request to RPe",
> +	"Set to TRUE to enable slowing framerate",
> +	"Prevent from changing the RC mode",
> +	"Override fused value of unslice RP0",
> +	"Override fused value of slice RP0",
> +	"TRUE means enable Intelligent Bias Control",
> +	"TRUE = enable eval mode when transitioning from idle to active.",
> +	"FALSE = disable eval mode completely",
> +	"Enable IBC when non-Gaming Mode is enabled"

to be safe:

[SLPC_PARAM_TASK_ENABLE_GTPERF] = "Enable task GTPERF",
[SLPC_PARAM_TASK_DISABLE_GTPERF] = "Disable task GTPERF",
...


> +};
> +
>  enum slpc_global_state {
>  	SLPC_GLOBAL_STATE_NOT_RUNNING = 0,
>  	SLPC_GLOBAL_STATE_INITIALIZING = 1,
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Re: [PATCH v12 16/17] drm/i915/guc/slpc: Add SLPC banner to RPS debugfs interfaces

[Michal Wajdeczko]

On Fri, 30 Mar 2018 10:32:01 +0200, Sagar Arun Kamble  
<sagar.a.kamble@intel.com> wrote:

> When SLPC is controlling frequency requests, RPS state related to
> autotuning is no longer valid. Make user aware through banner
> upfront. Value read from register RPNSWREQ likely has the frequency
> requested last by GuC SLPC.
>
> v1: Replace HAS_SLPC with intel_slpc_active (Paulo)
>     Avoid magic numbers (Nick)
>     Use a function for repeated code (Jon)
>
> v2: Add "SLPC Active" to i915_frequency_info output and
>     don't update cur_freq as it is driver internal request. (Chris)
>
> v3: Removing sysfs interface gt_req_freq_mhz out of this patch
>     for proper division of functionality. (Sagar)
>
> v4: idle_freq, boost_freq are also not used with SLPC.
>
> v5: Added SLPC banner to i915_rps_boost_info and keep printing
>     driver internal values. (Chris)
>
> v6: Commit message update.
>
> v7: Rebase.
>
> v8: Rebase.
>
> Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
> Cc: Jeff McGee <jeff.mcgee@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c  
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 1a66507..5d2ac24 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1068,6 +1068,9 @@ static int i915_frequency_info(struct seq_file *m,  
> void *unused)
>  	struct intel_rps *rps = &dev_priv->gt_pm.rps;
>  	int ret = 0;
> +	if (USES_GUC_SLPC(dev_priv))
> +		seq_puts(m, "SLPC Active\n");
> +
>  	intel_runtime_pm_get(dev_priv);
> 	if (IS_GEN5(dev_priv)) {
> @@ -2209,6 +2212,9 @@ static int i915_rps_boost_info(struct seq_file *m,  
> void *data)
>  	struct intel_rps *rps = &dev_priv->gt_pm.rps;
>  	struct drm_file *file;
> +	if (USES_GUC_SLPC(dev_priv))
> +		seq_puts(m, "SLPC Active\n");

[bikeshed] maybe to match below pattern:

	seq_puts(m, "SLPC active? %s\n", yesno(true));
or
	seq_puts(m, "SLPC active? %s\n", yesno((USES_GUC_SLPC(dev_priv)));

> +
>  	seq_printf(m, "RPS enabled? %d\n", rps->enabled);
>  	seq_printf(m, "GPU busy? %s [%d requests]\n",
>  		   yesno(dev_priv->gt.awake), dev_priv->gt.active_requests);
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