* [PATCH 0/3] clk: uniphier: add support for PCIe, SATA and ethernet
@ 2018-03-30 9:44 ` Kunihiko Hayashi
0 siblings, 0 replies; 23+ messages in thread
From: Kunihiko Hayashi @ 2018-03-30 9:44 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Masahiro Yamada, linux-clk
Cc: linux-arm-kernel, linux-kernel, Kunihiko Hayashi
Add clock lines for PCI-express and SATA controllers implemented on
UniPhier SoCs, and additional clock lines for ethernet controller on Pro4.
Kunihiko Hayashi (3):
clk: uniphier: add PCIe clock control support
clk: uniphier: add SATA clock control support
clk: uniphier: add additional ethernet clock lines for Pro4
drivers/clk/uniphier/clk-uniphier-sys.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
--
2.7.4
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 0/3] clk: uniphier: add support for PCIe, SATA and ethernet
@ 2018-03-30 9:44 ` Kunihiko Hayashi
0 siblings, 0 replies; 23+ messages in thread
From: Kunihiko Hayashi @ 2018-03-30 9:44 UTC (permalink / raw)
To: linux-arm-kernel
Add clock lines for PCI-express and SATA controllers implemented on
UniPhier SoCs, and additional clock lines for ethernet controller on Pro4.
Kunihiko Hayashi (3):
clk: uniphier: add PCIe clock control support
clk: uniphier: add SATA clock control support
clk: uniphier: add additional ethernet clock lines for Pro4
drivers/clk/uniphier/clk-uniphier-sys.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
--
2.7.4
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 1/3] clk: uniphier: add PCIe clock control support
2018-03-30 9:44 ` Kunihiko Hayashi
@ 2018-03-30 9:44 ` Kunihiko Hayashi
-1 siblings, 0 replies; 23+ messages in thread
From: Kunihiko Hayashi @ 2018-03-30 9:44 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Masahiro Yamada, linux-clk
Cc: linux-arm-kernel, linux-kernel, Kunihiko Hayashi
Add clock control for PCIe controller on UniPhier SoCs. This adds
support for Pro5, LD20 and PXs3.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
drivers/clk/uniphier/clk-uniphier-sys.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c
index fa7f2f3..d539c82 100644
--- a/drivers/clk/uniphier/clk-uniphier-sys.c
+++ b/drivers/clk/uniphier/clk-uniphier-sys.c
@@ -141,6 +141,7 @@ const struct uniphier_clk_data uniphier_pro5_sys_clk_data[] = {
UNIPHIER_PRO4_SYS_CLK_GIO(12), /* PCIe, USB3 */
UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),
UNIPHIER_PRO4_SYS_CLK_USB3(15, 1),
+ UNIPHIER_CLK_GATE("pcie", 24, NULL, 0x2108, 2),
UNIPHIER_PRO5_SYS_CLK_AIO(40),
{ /* sentinel */ }
};
@@ -216,6 +217,7 @@ const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {
UNIPHIER_CLK_GATE("usb30", 14, NULL, 0x210c, 14),
UNIPHIER_CLK_GATE("usb30-phy0", 16, NULL, 0x210c, 12),
UNIPHIER_CLK_GATE("usb30-phy1", 17, NULL, 0x210c, 13),
+ UNIPHIER_CLK_GATE("pcie", 24, NULL, 0x210c, 4),
UNIPHIER_LD11_SYS_CLK_AIO(40),
UNIPHIER_LD11_SYS_CLK_EVEA(41),
UNIPHIER_LD11_SYS_CLK_EXIV(42),
@@ -254,6 +256,7 @@ const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = {
UNIPHIER_CLK_GATE("usb30-phy2", 18, NULL, 0x210c, 20),
UNIPHIER_CLK_GATE("usb31-phy0", 20, NULL, 0x210c, 17),
UNIPHIER_CLK_GATE("usb31-phy1", 21, NULL, 0x210c, 19),
+ UNIPHIER_CLK_GATE("pcie", 24, NULL, 0x210c, 3),
/* CPU gears */
UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8),
UNIPHIER_CLK_DIV4("spll", 2, 3, 4, 8),
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 1/3] clk: uniphier: add PCIe clock control support
@ 2018-03-30 9:44 ` Kunihiko Hayashi
0 siblings, 0 replies; 23+ messages in thread
From: Kunihiko Hayashi @ 2018-03-30 9:44 UTC (permalink / raw)
To: linux-arm-kernel
Add clock control for PCIe controller on UniPhier SoCs. This adds
support for Pro5, LD20 and PXs3.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
drivers/clk/uniphier/clk-uniphier-sys.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c
index fa7f2f3..d539c82 100644
--- a/drivers/clk/uniphier/clk-uniphier-sys.c
+++ b/drivers/clk/uniphier/clk-uniphier-sys.c
@@ -141,6 +141,7 @@ const struct uniphier_clk_data uniphier_pro5_sys_clk_data[] = {
UNIPHIER_PRO4_SYS_CLK_GIO(12), /* PCIe, USB3 */
UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),
UNIPHIER_PRO4_SYS_CLK_USB3(15, 1),
+ UNIPHIER_CLK_GATE("pcie", 24, NULL, 0x2108, 2),
UNIPHIER_PRO5_SYS_CLK_AIO(40),
{ /* sentinel */ }
};
@@ -216,6 +217,7 @@ const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {
UNIPHIER_CLK_GATE("usb30", 14, NULL, 0x210c, 14),
UNIPHIER_CLK_GATE("usb30-phy0", 16, NULL, 0x210c, 12),
UNIPHIER_CLK_GATE("usb30-phy1", 17, NULL, 0x210c, 13),
+ UNIPHIER_CLK_GATE("pcie", 24, NULL, 0x210c, 4),
UNIPHIER_LD11_SYS_CLK_AIO(40),
UNIPHIER_LD11_SYS_CLK_EVEA(41),
UNIPHIER_LD11_SYS_CLK_EXIV(42),
@@ -254,6 +256,7 @@ const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = {
UNIPHIER_CLK_GATE("usb30-phy2", 18, NULL, 0x210c, 20),
UNIPHIER_CLK_GATE("usb31-phy0", 20, NULL, 0x210c, 17),
UNIPHIER_CLK_GATE("usb31-phy1", 21, NULL, 0x210c, 19),
+ UNIPHIER_CLK_GATE("pcie", 24, NULL, 0x210c, 3),
/* CPU gears */
UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8),
UNIPHIER_CLK_DIV4("spll", 2, 3, 4, 8),
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 2/3] clk: uniphier: add SATA clock control support
2018-03-30 9:44 ` Kunihiko Hayashi
@ 2018-03-30 9:44 ` Kunihiko Hayashi
-1 siblings, 0 replies; 23+ messages in thread
From: Kunihiko Hayashi @ 2018-03-30 9:44 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Masahiro Yamada, linux-clk
Cc: linux-arm-kernel, linux-kernel, Kunihiko Hayashi
Add clock control for SATA controller on UniPhier SoCs. This adds
support for PXs2, LD20 and PXs3.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
drivers/clk/uniphier/clk-uniphier-sys.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c
index d539c82..7d66dfb 100644
--- a/drivers/clk/uniphier/clk-uniphier-sys.c
+++ b/drivers/clk/uniphier/clk-uniphier-sys.c
@@ -112,6 +112,8 @@ const struct uniphier_clk_data uniphier_pro4_sys_clk_data[] = {
UNIPHIER_PRO4_SYS_CLK_GIO(12), /* Ether, SATA, USB3 */
UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),
UNIPHIER_PRO4_SYS_CLK_USB3(15, 1),
+ UNIPHIER_CLK_GATE("sata0", 28, NULL, 0x2104, 18),
+ UNIPHIER_CLK_GATE("sata1", 29, NULL, 0x2104, 19),
UNIPHIER_PRO4_SYS_CLK_AIO(40),
{ /* sentinel */ }
};
@@ -160,6 +162,7 @@ const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = {
/* The document mentions 0x2104 bit 18, but not functional */
UNIPHIER_CLK_GATE("usb30-phy", 16, NULL, 0x2104, 19),
UNIPHIER_CLK_GATE("usb31-phy", 20, NULL, 0x2104, 20),
+ UNIPHIER_CLK_GATE("sata0", 28, NULL, 0x2104, 22),
UNIPHIER_PRO5_SYS_CLK_AIO(40),
{ /* sentinel */ }
};
@@ -257,6 +260,9 @@ const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = {
UNIPHIER_CLK_GATE("usb31-phy0", 20, NULL, 0x210c, 17),
UNIPHIER_CLK_GATE("usb31-phy1", 21, NULL, 0x210c, 19),
UNIPHIER_CLK_GATE("pcie", 24, NULL, 0x210c, 3),
+ UNIPHIER_CLK_GATE("sata0", 28, NULL, 0x210c, 7),
+ UNIPHIER_CLK_GATE("sata1", 29, NULL, 0x210c, 8),
+ UNIPHIER_CLK_GATE("sata-phy", 30, NULL, 0x210c, 21),
/* CPU gears */
UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8),
UNIPHIER_CLK_DIV4("spll", 2, 3, 4, 8),
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 2/3] clk: uniphier: add SATA clock control support
@ 2018-03-30 9:44 ` Kunihiko Hayashi
0 siblings, 0 replies; 23+ messages in thread
From: Kunihiko Hayashi @ 2018-03-30 9:44 UTC (permalink / raw)
To: linux-arm-kernel
Add clock control for SATA controller on UniPhier SoCs. This adds
support for PXs2, LD20 and PXs3.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
drivers/clk/uniphier/clk-uniphier-sys.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c
index d539c82..7d66dfb 100644
--- a/drivers/clk/uniphier/clk-uniphier-sys.c
+++ b/drivers/clk/uniphier/clk-uniphier-sys.c
@@ -112,6 +112,8 @@ const struct uniphier_clk_data uniphier_pro4_sys_clk_data[] = {
UNIPHIER_PRO4_SYS_CLK_GIO(12), /* Ether, SATA, USB3 */
UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),
UNIPHIER_PRO4_SYS_CLK_USB3(15, 1),
+ UNIPHIER_CLK_GATE("sata0", 28, NULL, 0x2104, 18),
+ UNIPHIER_CLK_GATE("sata1", 29, NULL, 0x2104, 19),
UNIPHIER_PRO4_SYS_CLK_AIO(40),
{ /* sentinel */ }
};
@@ -160,6 +162,7 @@ const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = {
/* The document mentions 0x2104 bit 18, but not functional */
UNIPHIER_CLK_GATE("usb30-phy", 16, NULL, 0x2104, 19),
UNIPHIER_CLK_GATE("usb31-phy", 20, NULL, 0x2104, 20),
+ UNIPHIER_CLK_GATE("sata0", 28, NULL, 0x2104, 22),
UNIPHIER_PRO5_SYS_CLK_AIO(40),
{ /* sentinel */ }
};
@@ -257,6 +260,9 @@ const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = {
UNIPHIER_CLK_GATE("usb31-phy0", 20, NULL, 0x210c, 17),
UNIPHIER_CLK_GATE("usb31-phy1", 21, NULL, 0x210c, 19),
UNIPHIER_CLK_GATE("pcie", 24, NULL, 0x210c, 3),
+ UNIPHIER_CLK_GATE("sata0", 28, NULL, 0x210c, 7),
+ UNIPHIER_CLK_GATE("sata1", 29, NULL, 0x210c, 8),
+ UNIPHIER_CLK_GATE("sata-phy", 30, NULL, 0x210c, 21),
/* CPU gears */
UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8),
UNIPHIER_CLK_DIV4("spll", 2, 3, 4, 8),
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 3/3] clk: uniphier: add additional ethernet clock lines for Pro4
2018-03-30 9:44 ` Kunihiko Hayashi
@ 2018-03-30 9:44 ` Kunihiko Hayashi
-1 siblings, 0 replies; 23+ messages in thread
From: Kunihiko Hayashi @ 2018-03-30 9:44 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Masahiro Yamada, linux-clk
Cc: linux-arm-kernel, linux-kernel, Kunihiko Hayashi
Pro4 SoC has clock lines for Giga-bit feature and ethernet phy,
and these are mandatory to activate the ethernet controller. This adds
support for the clock lines.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
drivers/clk/uniphier/clk-uniphier-sys.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c
index 7d66dfb..ebc78ab2 100644
--- a/drivers/clk/uniphier/clk-uniphier-sys.c
+++ b/drivers/clk/uniphier/clk-uniphier-sys.c
@@ -102,13 +102,16 @@ const struct uniphier_clk_data uniphier_pro4_sys_clk_data[] = {
UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25), /* 288 MHz */
UNIPHIER_CLK_FACTOR("a2pll", -1, "upll", 256, 125), /* 589.824 MHz */
UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25), /* 270 MHz */
+ UNIPHIER_CLK_FACTOR("gpll", -1, "ref", 10, 1), /* 250 MHz */
UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 8),
UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 32),
UNIPHIER_LD4_SYS_CLK_NAND(2),
UNIPHIER_LD4_SYS_CLK_SD,
UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),
UNIPHIER_PRO4_SYS_CLK_ETHER(6),
+ UNIPHIER_CLK_GATE("ether-gb", 7, "gpll", 0x2104, 5),
UNIPHIER_LD4_SYS_CLK_STDMAC(8), /* HSC, MIO, RLE */
+ UNIPHIER_CLK_GATE("ether-phy", 10, "ref", 0x2260, 0),
UNIPHIER_PRO4_SYS_CLK_GIO(12), /* Ether, SATA, USB3 */
UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),
UNIPHIER_PRO4_SYS_CLK_USB3(15, 1),
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 3/3] clk: uniphier: add additional ethernet clock lines for Pro4
@ 2018-03-30 9:44 ` Kunihiko Hayashi
0 siblings, 0 replies; 23+ messages in thread
From: Kunihiko Hayashi @ 2018-03-30 9:44 UTC (permalink / raw)
To: linux-arm-kernel
Pro4 SoC has clock lines for Giga-bit feature and ethernet phy,
and these are mandatory to activate the ethernet controller. This adds
support for the clock lines.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
drivers/clk/uniphier/clk-uniphier-sys.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c
index 7d66dfb..ebc78ab2 100644
--- a/drivers/clk/uniphier/clk-uniphier-sys.c
+++ b/drivers/clk/uniphier/clk-uniphier-sys.c
@@ -102,13 +102,16 @@ const struct uniphier_clk_data uniphier_pro4_sys_clk_data[] = {
UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25), /* 288 MHz */
UNIPHIER_CLK_FACTOR("a2pll", -1, "upll", 256, 125), /* 589.824 MHz */
UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25), /* 270 MHz */
+ UNIPHIER_CLK_FACTOR("gpll", -1, "ref", 10, 1), /* 250 MHz */
UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 8),
UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 32),
UNIPHIER_LD4_SYS_CLK_NAND(2),
UNIPHIER_LD4_SYS_CLK_SD,
UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),
UNIPHIER_PRO4_SYS_CLK_ETHER(6),
+ UNIPHIER_CLK_GATE("ether-gb", 7, "gpll", 0x2104, 5),
UNIPHIER_LD4_SYS_CLK_STDMAC(8), /* HSC, MIO, RLE */
+ UNIPHIER_CLK_GATE("ether-phy", 10, "ref", 0x2260, 0),
UNIPHIER_PRO4_SYS_CLK_GIO(12), /* Ether, SATA, USB3 */
UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),
UNIPHIER_PRO4_SYS_CLK_USB3(15, 1),
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH 1/3] clk: uniphier: add PCIe clock control support
2018-03-30 9:44 ` Kunihiko Hayashi
@ 2018-04-02 3:40 ` Masahiro Yamada
-1 siblings, 0 replies; 23+ messages in thread
From: Masahiro Yamada @ 2018-04-02 3:40 UTC (permalink / raw)
To: Kunihiko Hayashi
Cc: Michael Turquette, Stephen Boyd, linux-clk, linux-arm-kernel,
Linux Kernel Mailing List
2018-03-30 18:44 GMT+09:00 Kunihiko Hayashi <hayashi.kunihiko@socionext.com>:
> Add clock control for PCIe controller on UniPhier SoCs. This adds
> support for Pro5, LD20 and PXs3.
>
> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
> ---
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
--
Best Regards
Masahiro Yamada
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 1/3] clk: uniphier: add PCIe clock control support
@ 2018-04-02 3:40 ` Masahiro Yamada
0 siblings, 0 replies; 23+ messages in thread
From: Masahiro Yamada @ 2018-04-02 3:40 UTC (permalink / raw)
To: linux-arm-kernel
2018-03-30 18:44 GMT+09:00 Kunihiko Hayashi <hayashi.kunihiko@socionext.com>:
> Add clock control for PCIe controller on UniPhier SoCs. This adds
> support for Pro5, LD20 and PXs3.
>
> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
> ---
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
--
Best Regards
Masahiro Yamada
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 2/3] clk: uniphier: add SATA clock control support
2018-03-30 9:44 ` Kunihiko Hayashi
@ 2018-04-02 3:40 ` Masahiro Yamada
-1 siblings, 0 replies; 23+ messages in thread
From: Masahiro Yamada @ 2018-04-02 3:40 UTC (permalink / raw)
To: Kunihiko Hayashi
Cc: Michael Turquette, Stephen Boyd, linux-clk, linux-arm-kernel,
Linux Kernel Mailing List
2018-03-30 18:44 GMT+09:00 Kunihiko Hayashi <hayashi.kunihiko@socionext.com>:
> Add clock control for SATA controller on UniPhier SoCs. This adds
> support for PXs2, LD20 and PXs3.
>
> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
> ---
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
--
Best Regards
Masahiro Yamada
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 2/3] clk: uniphier: add SATA clock control support
@ 2018-04-02 3:40 ` Masahiro Yamada
0 siblings, 0 replies; 23+ messages in thread
From: Masahiro Yamada @ 2018-04-02 3:40 UTC (permalink / raw)
To: linux-arm-kernel
2018-03-30 18:44 GMT+09:00 Kunihiko Hayashi <hayashi.kunihiko@socionext.com>:
> Add clock control for SATA controller on UniPhier SoCs. This adds
> support for PXs2, LD20 and PXs3.
>
> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
> ---
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
--
Best Regards
Masahiro Yamada
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 3/3] clk: uniphier: add additional ethernet clock lines for Pro4
2018-03-30 9:44 ` Kunihiko Hayashi
@ 2018-04-02 3:41 ` Masahiro Yamada
-1 siblings, 0 replies; 23+ messages in thread
From: Masahiro Yamada @ 2018-04-02 3:41 UTC (permalink / raw)
To: Kunihiko Hayashi
Cc: Michael Turquette, Stephen Boyd, linux-clk, linux-arm-kernel,
Linux Kernel Mailing List
2018-03-30 18:44 GMT+09:00 Kunihiko Hayashi <hayashi.kunihiko@socionext.com>:
> Pro4 SoC has clock lines for Giga-bit feature and ethernet phy,
> and these are mandatory to activate the ethernet controller. This adds
> support for the clock lines.
>
> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
> ---
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
--
Best Regards
Masahiro Yamada
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 3/3] clk: uniphier: add additional ethernet clock lines for Pro4
@ 2018-04-02 3:41 ` Masahiro Yamada
0 siblings, 0 replies; 23+ messages in thread
From: Masahiro Yamada @ 2018-04-02 3:41 UTC (permalink / raw)
To: linux-arm-kernel
2018-03-30 18:44 GMT+09:00 Kunihiko Hayashi <hayashi.kunihiko@socionext.com>:
> Pro4 SoC has clock lines for Giga-bit feature and ethernet phy,
> and these are mandatory to activate the ethernet controller. This adds
> support for the clock lines.
>
> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
> ---
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
--
Best Regards
Masahiro Yamada
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 1/3] clk: uniphier: add PCIe clock control support
2018-03-30 9:44 ` Kunihiko Hayashi
(?)
@ 2018-04-05 22:05 ` Stephen Boyd
-1 siblings, 0 replies; 23+ messages in thread
From: Stephen Boyd @ 2018-04-05 22:05 UTC (permalink / raw)
To: Kunihiko Hayashi, Masahiro Yamada, Michael Turquette, linux-clk
Cc: linux-arm-kernel, linux-kernel, Kunihiko Hayashi
Quoting Kunihiko Hayashi (2018-03-30 02:44:12)
> Add clock control for PCIe controller on UniPhier SoCs. This adds
> support for Pro5, LD20 and PXs3.
>
> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 1/3] clk: uniphier: add PCIe clock control support
@ 2018-04-05 22:05 ` Stephen Boyd
0 siblings, 0 replies; 23+ messages in thread
From: Stephen Boyd @ 2018-04-05 22:05 UTC (permalink / raw)
To: Kunihiko Hayashi, Masahiro Yamada, Michael Turquette, linux-clk
Cc: linux-arm-kernel, linux-kernel, Kunihiko Hayashi
Quoting Kunihiko Hayashi (2018-03-30 02:44:12)
> Add clock control for PCIe controller on UniPhier SoCs. This adds
> support for Pro5, LD20 and PXs3.
> =
> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 1/3] clk: uniphier: add PCIe clock control support
@ 2018-04-05 22:05 ` Stephen Boyd
0 siblings, 0 replies; 23+ messages in thread
From: Stephen Boyd @ 2018-04-05 22:05 UTC (permalink / raw)
To: linux-arm-kernel
Quoting Kunihiko Hayashi (2018-03-30 02:44:12)
> Add clock control for PCIe controller on UniPhier SoCs. This adds
> support for Pro5, LD20 and PXs3.
>
> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 2/3] clk: uniphier: add SATA clock control support
2018-03-30 9:44 ` Kunihiko Hayashi
(?)
@ 2018-04-05 22:05 ` Stephen Boyd
-1 siblings, 0 replies; 23+ messages in thread
From: Stephen Boyd @ 2018-04-05 22:05 UTC (permalink / raw)
To: Kunihiko Hayashi, Masahiro Yamada, Michael Turquette, linux-clk
Cc: linux-arm-kernel, linux-kernel, Kunihiko Hayashi
Quoting Kunihiko Hayashi (2018-03-30 02:44:13)
> Add clock control for SATA controller on UniPhier SoCs. This adds
> support for PXs2, LD20 and PXs3.
>
> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 2/3] clk: uniphier: add SATA clock control support
@ 2018-04-05 22:05 ` Stephen Boyd
0 siblings, 0 replies; 23+ messages in thread
From: Stephen Boyd @ 2018-04-05 22:05 UTC (permalink / raw)
To: Kunihiko Hayashi, Masahiro Yamada, Michael Turquette, linux-clk
Cc: linux-arm-kernel, linux-kernel, Kunihiko Hayashi
Quoting Kunihiko Hayashi (2018-03-30 02:44:13)
> Add clock control for SATA controller on UniPhier SoCs. This adds
> support for PXs2, LD20 and PXs3.
> =
> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 2/3] clk: uniphier: add SATA clock control support
@ 2018-04-05 22:05 ` Stephen Boyd
0 siblings, 0 replies; 23+ messages in thread
From: Stephen Boyd @ 2018-04-05 22:05 UTC (permalink / raw)
To: linux-arm-kernel
Quoting Kunihiko Hayashi (2018-03-30 02:44:13)
> Add clock control for SATA controller on UniPhier SoCs. This adds
> support for PXs2, LD20 and PXs3.
>
> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 3/3] clk: uniphier: add additional ethernet clock lines for Pro4
2018-03-30 9:44 ` Kunihiko Hayashi
(?)
@ 2018-04-05 22:05 ` Stephen Boyd
-1 siblings, 0 replies; 23+ messages in thread
From: Stephen Boyd @ 2018-04-05 22:05 UTC (permalink / raw)
To: Kunihiko Hayashi, Masahiro Yamada, Michael Turquette, linux-clk
Cc: linux-arm-kernel, linux-kernel, Kunihiko Hayashi
Quoting Kunihiko Hayashi (2018-03-30 02:44:14)
> Pro4 SoC has clock lines for Giga-bit feature and ethernet phy,
> and these are mandatory to activate the ethernet controller. This adds
> support for the clock lines.
>
> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 3/3] clk: uniphier: add additional ethernet clock lines for Pro4
@ 2018-04-05 22:05 ` Stephen Boyd
0 siblings, 0 replies; 23+ messages in thread
From: Stephen Boyd @ 2018-04-05 22:05 UTC (permalink / raw)
To: Kunihiko Hayashi, Masahiro Yamada, Michael Turquette, linux-clk
Cc: linux-arm-kernel, linux-kernel, Kunihiko Hayashi
Quoting Kunihiko Hayashi (2018-03-30 02:44:14)
> Pro4 SoC has clock lines for Giga-bit feature and ethernet phy,
> and these are mandatory to activate the ethernet controller. This adds
> support for the clock lines.
> =
> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 3/3] clk: uniphier: add additional ethernet clock lines for Pro4
@ 2018-04-05 22:05 ` Stephen Boyd
0 siblings, 0 replies; 23+ messages in thread
From: Stephen Boyd @ 2018-04-05 22:05 UTC (permalink / raw)
To: linux-arm-kernel
Quoting Kunihiko Hayashi (2018-03-30 02:44:14)
> Pro4 SoC has clock lines for Giga-bit feature and ethernet phy,
> and these are mandatory to activate the ethernet controller. This adds
> support for the clock lines.
>
> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 23+ messages in thread
end of thread, other threads:[~2018-04-05 22:05 UTC | newest]
Thread overview: 23+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-03-30 9:44 [PATCH 0/3] clk: uniphier: add support for PCIe, SATA and ethernet Kunihiko Hayashi
2018-03-30 9:44 ` Kunihiko Hayashi
2018-03-30 9:44 ` [PATCH 1/3] clk: uniphier: add PCIe clock control support Kunihiko Hayashi
2018-03-30 9:44 ` Kunihiko Hayashi
2018-04-02 3:40 ` Masahiro Yamada
2018-04-02 3:40 ` Masahiro Yamada
2018-04-05 22:05 ` Stephen Boyd
2018-04-05 22:05 ` Stephen Boyd
2018-04-05 22:05 ` Stephen Boyd
2018-03-30 9:44 ` [PATCH 2/3] clk: uniphier: add SATA " Kunihiko Hayashi
2018-03-30 9:44 ` Kunihiko Hayashi
2018-04-02 3:40 ` Masahiro Yamada
2018-04-02 3:40 ` Masahiro Yamada
2018-04-05 22:05 ` Stephen Boyd
2018-04-05 22:05 ` Stephen Boyd
2018-04-05 22:05 ` Stephen Boyd
2018-03-30 9:44 ` [PATCH 3/3] clk: uniphier: add additional ethernet clock lines for Pro4 Kunihiko Hayashi
2018-03-30 9:44 ` Kunihiko Hayashi
2018-04-02 3:41 ` Masahiro Yamada
2018-04-02 3:41 ` Masahiro Yamada
2018-04-05 22:05 ` Stephen Boyd
2018-04-05 22:05 ` Stephen Boyd
2018-04-05 22:05 ` Stephen Boyd
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