[PATCH 1/3] Revert "drm/amd/powerply: fix power reading on Fiji"

[PATCH 1/3] Revert "drm/amd/powerply: fix power reading on Fiji"

[Rex Zhu]

we don't have limit of [50ms, 4sec] sampling period.
only confused the average power and max power.
so don't need to increase delay time.

This reverts commit 462d8dcc9fec0d89f1ff6a1f93f1d4f670878c71.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index aaa9f5b..40f2f87 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -3368,8 +3368,7 @@ static int smu7_get_gpu_power(struct pp_hwmgr *hwmgr,
 			"Failed to start pm status log!",
 			return -1);
 
-	/* Sampling period from 50ms to 4sec */
-	msleep_interruptible(200);
+	msleep_interruptible(20);
 
 	PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
 			PPSMC_MSG_PmStatusLogSample),
-- 
1.9.1

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[PATCH 2/3] drm/amd/pp: Refine get_gpu_power for VI

[Rex Zhu]

1. On polaris10/11/12, Sending smu message PPSMC_MSG_GetCurrPkgPwr to
   read currentpkgpwr directly.
2. On Fiji/tonga/bonaire/hawwii, no PPSMC_MSG_GetCurrPkgPwr support.
   Send PPSMC_MSG_PmStatusLogStart to let smu write currentpkgpwr
   to ixSMU_PM_STATUS_94. this is asynchronous. need to delay no less
   than 1ms.
3. Clean ixSMU_PM_STATUS_94 immediately when send PPSMC_MSG_PmStatusLogStart
   to avoid read old value.
4. delay 10 ms instand of 20 ms. so the result will more similar to
   the output of PPSMC_MSG_GetCurrPkgPwr.
5. remove max power/vddc/vddci output to keep consistent with vega.
6. for vddc/vddci power, we can calculate the average value per
   [10ms, 4s] in other interface if needed.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 45 +++++++++++-------------
 1 file changed, 21 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 40f2f87..c0ce672 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -3363,30 +3363,27 @@ static int smu7_get_pp_table_entry(struct pp_hwmgr *hwmgr,
 static int smu7_get_gpu_power(struct pp_hwmgr *hwmgr,
 		struct pp_gpu_power *query)
 {
-	PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
-			PPSMC_MSG_PmStatusLogStart),
-			"Failed to start pm status log!",
-			return -1);
-
-	msleep_interruptible(20);
-
-	PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
-			PPSMC_MSG_PmStatusLogSample),
-			"Failed to sample pm status log!",
-			return -1);
-
-	query->vddc_power = cgs_read_ind_register(hwmgr->device,
-			CGS_IND_REG__SMC,
-			ixSMU_PM_STATUS_40);
-	query->vddci_power = cgs_read_ind_register(hwmgr->device,
-			CGS_IND_REG__SMC,
-			ixSMU_PM_STATUS_49);
-	query->max_gpu_power = cgs_read_ind_register(hwmgr->device,
-			CGS_IND_REG__SMC,
-			ixSMU_PM_STATUS_94);
-	query->average_gpu_power = cgs_read_ind_register(hwmgr->device,
-			CGS_IND_REG__SMC,
-			ixSMU_PM_STATUS_95);
+	if (!query)
+		return -EINVAL;
+
+	memset(query, 0, sizeof *query);
+
+	if (hwmgr->chip_id >= CHIP_POLARIS10) {
+		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrPkgPwr);
+		query->average_gpu_power = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
+	} else {
+		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogStart);
+		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
+					ixSMU_PM_STATUS_94, 0);
+
+		msleep_interruptible(10);
+
+		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogSample);
+
+		query->average_gpu_power = cgs_read_ind_register(hwmgr->device,
+							CGS_IND_REG__SMC,
+							ixSMU_PM_STATUS_94);
+	}
 
 	return 0;
 }
-- 
1.9.1

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[PATCH 3/3] drm/amd/pp: Remove dead struct pp_gpu_power

[Rex Zhu]

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c            |  7 ++-----
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c             | 22 +++++++---------------
 drivers/gpu/drm/amd/include/kgd_pp_interface.h     |  7 -------
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c   | 14 ++++----------
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 17 +++++++----------
 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 13 ++++---------
 6 files changed, 24 insertions(+), 56 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 487d39e..1e59818 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -701,9 +701,6 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
 		}
 	}
 	case AMDGPU_INFO_SENSOR: {
-		struct pp_gpu_power query = {0};
-		int query_size = sizeof(query);
-
 		if (!adev->pm.dpm_enabled)
 			return -ENOENT;
 
@@ -746,10 +743,10 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
 			/* get average GPU power */
 			if (amdgpu_dpm_read_sensor(adev,
 						   AMDGPU_PP_SENSOR_GPU_POWER,
-						   (void *)&query, &query_size)) {
+						   (void *)&ui32, &ui32_size)) {
 				return -EINVAL;
 			}
-			ui32 = query.average_gpu_power >> 8;
+			ui32 >>= 8;
 			break;
 		case AMDGPU_INFO_SENSOR_VDDNB:
 			/* get VDDNB in millivolts */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index e5f60fc..744f105 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -1020,8 +1020,8 @@ static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev,
 {
 	struct amdgpu_device *adev = dev_get_drvdata(dev);
 	struct drm_device *ddev = adev->ddev;
-	struct pp_gpu_power query = {0};
-	int r, size = sizeof(query);
+	u32 query = 0;
+	int r, size = sizeof(u32);
 	unsigned uw;
 
 	/* Can't get power when the card is off */
@@ -1041,7 +1041,7 @@ static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev,
 		return r;
 
 	/* convert to microwatts */
-	uw = (query.average_gpu_power >> 8) * 1000000;
+	uw = (query >> 8) * 1000000 + (query & 0xff) * 1000;
 
 	return snprintf(buf, PAGE_SIZE, "%u\n", uw);
 }
@@ -1752,7 +1752,7 @@ void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
 {
 	uint32_t value;
-	struct pp_gpu_power query = {0};
+	uint32_t query = 0;
 	int size;
 
 	/* sanity check PP is enabled */
@@ -1775,17 +1775,9 @@ static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *a
 		seq_printf(m, "\t%u mV (VDDGFX)\n", value);
 	if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size))
 		seq_printf(m, "\t%u mV (VDDNB)\n", value);
-	size = sizeof(query);
-	if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, (void *)&query, &size)) {
-		seq_printf(m, "\t%u.%u W (VDDC)\n", query.vddc_power >> 8,
-				query.vddc_power & 0xff);
-		seq_printf(m, "\t%u.%u W (VDDCI)\n", query.vddci_power >> 8,
-				query.vddci_power & 0xff);
-		seq_printf(m, "\t%u.%u W (max GPU)\n", query.max_gpu_power >> 8,
-				query.max_gpu_power & 0xff);
-		seq_printf(m, "\t%u.%u W (average GPU)\n", query.average_gpu_power >> 8,
-				query.average_gpu_power & 0xff);
-	}
+	size = sizeof(uint32_t);
+	if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, (void *)&query, &size))
+		seq_printf(m, "\t%u.%u W (average GPU)\n", query >> 8, query & 0xff);
 	size = sizeof(value);
 	seq_printf(m, "\n");
 
diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index 5c840c0..1bec907 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -149,13 +149,6 @@ struct pp_states_info {
 	uint32_t states[16];
 };
 
-struct pp_gpu_power {
-	uint32_t vddc_power;
-	uint32_t vddci_power;
-	uint32_t max_gpu_power;
-	uint32_t average_gpu_power;
-};
-
 #define PP_GROUP_MASK        0xF0000000
 #define PP_GROUP_SHIFT       28
 
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index c0ce672..81a50cf 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -3360,17 +3360,14 @@ static int smu7_get_pp_table_entry(struct pp_hwmgr *hwmgr,
 	return 0;
 }
 
-static int smu7_get_gpu_power(struct pp_hwmgr *hwmgr,
-		struct pp_gpu_power *query)
+static int smu7_get_gpu_power(struct pp_hwmgr *hwmgr, u32 *query)
 {
 	if (!query)
 		return -EINVAL;
 
-	memset(query, 0, sizeof *query);
-
 	if (hwmgr->chip_id >= CHIP_POLARIS10) {
 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrPkgPwr);
-		query->average_gpu_power = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
+		*query = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
 	} else {
 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogStart);
 		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
@@ -3380,7 +3377,7 @@ static int smu7_get_gpu_power(struct pp_hwmgr *hwmgr,
 
 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogSample);
 
-		query->average_gpu_power = cgs_read_ind_register(hwmgr->device,
+		*query = cgs_read_ind_register(hwmgr->device,
 							CGS_IND_REG__SMC,
 							ixSMU_PM_STATUS_94);
 	}
@@ -3436,10 +3433,7 @@ static int smu7_read_sensor(struct pp_hwmgr *hwmgr, int idx,
 		*size = 4;
 		return 0;
 	case AMDGPU_PP_SENSOR_GPU_POWER:
-		if (*size < sizeof(struct pp_gpu_power))
-			return -EINVAL;
-		*size = sizeof(struct pp_gpu_power);
-		return smu7_get_gpu_power(hwmgr, (struct pp_gpu_power *)value);
+		return smu7_get_gpu_power(hwmgr, (uint32_t *)value);
 	case AMDGPU_PP_SENSOR_VDDGFX:
 		if ((data->vr_config & 0xff) == 0x2)
 			val_vid = PHM_READ_INDIRECT_FIELD(hwmgr->device,
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index ba29942..c2cf89f 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -3791,16 +3791,18 @@ static uint32_t vega10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
 }
 
 static int vega10_get_gpu_power(struct pp_hwmgr *hwmgr,
-		struct pp_gpu_power *query)
+		uint32_t *query)
 {
 	uint32_t value;
 
+	if (!query)
+		return -EINVAL;
+
 	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrPkgPwr);
 	value = smum_get_argument(hwmgr);
 
-	/* power value is an integer */
-	memset(query, 0, sizeof *query);
-	query->average_gpu_power = value << 8;
+	/* SMC returning actual watts, keep consistent with legacy asics, low 8 bit as 8 fractional bits */
+	*query = value << 8;
 
 	return 0;
 }
@@ -3854,12 +3856,7 @@ static int vega10_read_sensor(struct pp_hwmgr *hwmgr, int idx,
 		*size = 4;
 		break;
 	case AMDGPU_PP_SENSOR_GPU_POWER:
-		if (*size < sizeof(struct pp_gpu_power))
-			ret = -EINVAL;
-		else {
-			*size = sizeof(struct pp_gpu_power);
-			ret = vega10_get_gpu_power(hwmgr, (struct pp_gpu_power *)value);
-		}
+		ret = vega10_get_gpu_power(hwmgr, (uint32_t *)value);
 		break;
 	case AMDGPU_PP_SENSOR_VDDGFX:
 		reg = soc15_get_register_offset(SMUIO_HWID, 0,
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
index 6a85238..2bd3fd7 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
@@ -1064,8 +1064,7 @@ static uint32_t vega12_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
 	return (mem_clk * 100);
 }
 
-static int vega12_get_gpu_power(struct pp_hwmgr *hwmgr,
-		struct pp_gpu_power *query)
+static int vega12_get_gpu_power(struct pp_hwmgr *hwmgr, uint32_t *query)
 {
 #if 0
 	uint32_t value;
@@ -1077,7 +1076,7 @@ static int vega12_get_gpu_power(struct pp_hwmgr *hwmgr,
 
 	vega12_read_arg_from_smc(hwmgr, &value);
 	/* power value is an integer */
-	query->average_gpu_power = value << 8;
+	*query = value << 8;
 #endif
 	return 0;
 }
@@ -1186,12 +1185,8 @@ static int vega12_read_sensor(struct pp_hwmgr *hwmgr, int idx,
 		*size = 4;
 		break;
 	case AMDGPU_PP_SENSOR_GPU_POWER:
-		if (*size < sizeof(struct pp_gpu_power))
-			ret = -EINVAL;
-		else {
-			*size = sizeof(struct pp_gpu_power);
-			ret = vega12_get_gpu_power(hwmgr, (struct pp_gpu_power *)value);
-		}
+		ret = vega12_get_gpu_power(hwmgr, (uint32_t *)value);
+
 		break;
 	default:
 		ret = -EINVAL;
-- 
1.9.1

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Re: [PATCH 1/3] Revert "drm/amd/powerply: fix power reading on Fiji"

[Eric Huang]

Did you contact tools team about this? Since the smc messages 
PPSMC_MSG_PmStatusLogStart and PPSMC_MSG_PmStatusLogSample are 
exclusively used by tools, driver just shared it. And AGT gets different 
result as driver if you change it back to 20ms. To keep consistent 
result as AGT, please verify it through full test cases.

Regards,
Eric

On 2018-04-04 04:25 AM, Rex Zhu wrote:
> we don't have limit of [50ms, 4sec] sampling period.
> only confused the average power and max power.
> so don't need to increase delay time.
>
> This reverts commit 462d8dcc9fec0d89f1ff6a1f93f1d4f670878c71.
>
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
> ---
>   drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 3 +--
>   1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> index aaa9f5b..40f2f87 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> @@ -3368,8 +3368,7 @@ static int smu7_get_gpu_power(struct pp_hwmgr *hwmgr,
>   			"Failed to start pm status log!",
>   			return -1);
>   
> -	/* Sampling period from 50ms to 4sec */
> -	msleep_interruptible(200);
> +	msleep_interruptible(20);
>   
>   	PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
>   			PPSMC_MSG_PmStatusLogSample),

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Re: [PATCH 2/3] drm/amd/pp: Refine get_gpu_power for VI

[Eric Huang]

Sampling period is too short. The power reading value will be not 
aligned with AGT's. It will confuse user that why AMD provides two 
different power results.

Regards,
Eric

On 2018-04-04 04:25 AM, Rex Zhu wrote:
> 1. On polaris10/11/12, Sending smu message PPSMC_MSG_GetCurrPkgPwr to
>     read currentpkgpwr directly.
> 2. On Fiji/tonga/bonaire/hawwii, no PPSMC_MSG_GetCurrPkgPwr support.
>     Send PPSMC_MSG_PmStatusLogStart to let smu write currentpkgpwr
>     to ixSMU_PM_STATUS_94. this is asynchronous. need to delay no less
>     than 1ms.
> 3. Clean ixSMU_PM_STATUS_94 immediately when send PPSMC_MSG_PmStatusLogStart
>     to avoid read old value.
> 4. delay 10 ms instand of 20 ms. so the result will more similar to
>     the output of PPSMC_MSG_GetCurrPkgPwr.
> 5. remove max power/vddc/vddci output to keep consistent with vega.
> 6. for vddc/vddci power, we can calculate the average value per
>     [10ms, 4s] in other interface if needed.
>
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
> ---
>   drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 45 +++++++++++-------------
>   1 file changed, 21 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> index 40f2f87..c0ce672 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> @@ -3363,30 +3363,27 @@ static int smu7_get_pp_table_entry(struct pp_hwmgr *hwmgr,
>   static int smu7_get_gpu_power(struct pp_hwmgr *hwmgr,
>   		struct pp_gpu_power *query)
>   {
> -	PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
> -			PPSMC_MSG_PmStatusLogStart),
> -			"Failed to start pm status log!",
> -			return -1);
> -
> -	msleep_interruptible(20);
> -
> -	PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
> -			PPSMC_MSG_PmStatusLogSample),
> -			"Failed to sample pm status log!",
> -			return -1);
> -
> -	query->vddc_power = cgs_read_ind_register(hwmgr->device,
> -			CGS_IND_REG__SMC,
> -			ixSMU_PM_STATUS_40);
> -	query->vddci_power = cgs_read_ind_register(hwmgr->device,
> -			CGS_IND_REG__SMC,
> -			ixSMU_PM_STATUS_49);
> -	query->max_gpu_power = cgs_read_ind_register(hwmgr->device,
> -			CGS_IND_REG__SMC,
> -			ixSMU_PM_STATUS_94);
> -	query->average_gpu_power = cgs_read_ind_register(hwmgr->device,
> -			CGS_IND_REG__SMC,
> -			ixSMU_PM_STATUS_95);
> +	if (!query)
> +		return -EINVAL;
> +
> +	memset(query, 0, sizeof *query);
> +
> +	if (hwmgr->chip_id >= CHIP_POLARIS10) {
> +		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrPkgPwr);
> +		query->average_gpu_power = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
> +	} else {
> +		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogStart);
> +		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
> +					ixSMU_PM_STATUS_94, 0);
> +
> +		msleep_interruptible(10);
> +
> +		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogSample);
> +
> +		query->average_gpu_power = cgs_read_ind_register(hwmgr->device,
> +							CGS_IND_REG__SMC,
> +							ixSMU_PM_STATUS_94);
> +	}
>   
>   	return 0;
>   }

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Re: [PATCH 2/3] drm/amd/pp: Refine get_gpu_power for VI

[Zhu, Rex]

[-- Attachment #1.1: Type: text/plain, Size: 5060 bytes --]

If user send message PPSMC_MSG_GetCurrPkgPwr, firmware will return the pkgpwr immediately as current power value.

as no PPSMC_MSG_GetCurrPkgPwr support, so send message  let firmware write pkgpwr  to ixSMU_PM_STATUS_94,

and driver delay 10ms to read ixSMU_PM_STATUS_94.


I don't think there is any problem. otherwise, there is same issue on polaris/vega.


I clean ixSMU_PM_STATUS_94 before let smu write it.

The delay time is enough unless we got 0 from ixSMU_PM_STATUS_94 .



Best Regards

Rex


________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of Eric Huang <jinhuieric.huang-5C7GfCeVMHo@public.gmane.org>
Sent: Wednesday, April 4, 2018 11:36 PM
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: Re: [PATCH 2/3] drm/amd/pp: Refine get_gpu_power for VI

Sampling period is too short. The power reading value will be not
aligned with AGT's. It will confuse user that why AMD provides two
different power results.

Regards,
Eric

On 2018-04-04 04:25 AM, Rex Zhu wrote:
> 1. On polaris10/11/12, Sending smu message PPSMC_MSG_GetCurrPkgPwr to
>     read currentpkgpwr directly.
> 2. On Fiji/tonga/bonaire/hawwii, no PPSMC_MSG_GetCurrPkgPwr support.
>     Send PPSMC_MSG_PmStatusLogStart to let smu write currentpkgpwr
>     to ixSMU_PM_STATUS_94. this is asynchronous. need to delay no less
>     than 1ms.
> 3. Clean ixSMU_PM_STATUS_94 immediately when send PPSMC_MSG_PmStatusLogStart
>     to avoid read old value.
> 4. delay 10 ms instand of 20 ms. so the result will more similar to
>     the output of PPSMC_MSG_GetCurrPkgPwr.
> 5. remove max power/vddc/vddci output to keep consistent with vega.
> 6. for vddc/vddci power, we can calculate the average value per
>     [10ms, 4s] in other interface if needed.
>
> Signed-off-by: Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
> ---
>   drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 45 +++++++++++-------------
>   1 file changed, 21 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> index 40f2f87..c0ce672 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> @@ -3363,30 +3363,27 @@ static int smu7_get_pp_table_entry(struct pp_hwmgr *hwmgr,
>   static int smu7_get_gpu_power(struct pp_hwmgr *hwmgr,
>                struct pp_gpu_power *query)
>   {
> -     PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
> -                     PPSMC_MSG_PmStatusLogStart),
> -                     "Failed to start pm status log!",
> -                     return -1);
> -
> -     msleep_interruptible(20);
> -
> -     PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
> -                     PPSMC_MSG_PmStatusLogSample),
> -                     "Failed to sample pm status log!",
> -                     return -1);
> -
> -     query->vddc_power = cgs_read_ind_register(hwmgr->device,
> -                     CGS_IND_REG__SMC,
> -                     ixSMU_PM_STATUS_40);
> -     query->vddci_power = cgs_read_ind_register(hwmgr->device,
> -                     CGS_IND_REG__SMC,
> -                     ixSMU_PM_STATUS_49);
> -     query->max_gpu_power = cgs_read_ind_register(hwmgr->device,
> -                     CGS_IND_REG__SMC,
> -                     ixSMU_PM_STATUS_94);
> -     query->average_gpu_power = cgs_read_ind_register(hwmgr->device,
> -                     CGS_IND_REG__SMC,
> -                     ixSMU_PM_STATUS_95);
> +     if (!query)
> +             return -EINVAL;
> +
> +     memset(query, 0, sizeof *query);
> +
> +     if (hwmgr->chip_id >= CHIP_POLARIS10) {
> +             smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrPkgPwr);
> +             query->average_gpu_power = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
> +     } else {
> +             smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogStart);
> +             cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
> +                                     ixSMU_PM_STATUS_94, 0);
> +
> +             msleep_interruptible(10);
> +
> +             smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogSample);
> +
> +             query->average_gpu_power = cgs_read_ind_register(hwmgr->device,
> +                                                     CGS_IND_REG__SMC,
> +                                                     ixSMU_PM_STATUS_94);
> +     }
>
>        return 0;
>   }

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Re: [PATCH 2/3] drm/amd/pp: Refine get_gpu_power for VI

[Eric Huang]

[-- Attachment #1.1: Type: text/plain, Size: 5631 bytes --]

So you didn't compare the result with AGT, but I did. The reality is not 
like your speculation.


Regards,

Eric


On 2018-04-04 11:50 AM, Zhu, Rex wrote:
>
> If user send message PPSMC_MSG_GetCurrPkgPwr, firmware will return the 
> pkgpwr immediately as current power value.
>
> as no PPSMC_MSG_GetCurrPkgPwr support, so send message  let firmware 
> write pkgpwr  to ixSMU_PM_STATUS_94,
>
> and driver delay 10ms to read ixSMU_PM_STATUS_94.
>
>
> I don't think there is any problem. otherwise, there is same issue on 
> polaris/vega.
>
>
> I clean ixSMU_PM_STATUS_94 before let smu write it.
>
> The delay time is enough unless we got 0 from ixSMU_PM_STATUS_94 .
>
>
>
> Best Regards
>
> Rex
>
>
>
> ------------------------------------------------------------------------
> *From:* amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of 
> Eric Huang <jinhuieric.huang-5C7GfCeVMHo@public.gmane.org>
> *Sent:* Wednesday, April 4, 2018 11:36 PM
> *To:* amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> *Subject:* Re: [PATCH 2/3] drm/amd/pp: Refine get_gpu_power for VI
> Sampling period is too short. The power reading value will be not
> aligned with AGT's. It will confuse user that why AMD provides two
> different power results.
>
> Regards,
> Eric
>
> On 2018-04-04 04:25 AM, Rex Zhu wrote:
> > 1. On polaris10/11/12, Sending smu message PPSMC_MSG_GetCurrPkgPwr to
> >     read currentpkgpwr directly.
> > 2. On Fiji/tonga/bonaire/hawwii, no PPSMC_MSG_GetCurrPkgPwr support.
> >     Send PPSMC_MSG_PmStatusLogStart to let smu write currentpkgpwr
> >     to ixSMU_PM_STATUS_94. this is asynchronous. need to delay no less
> >     than 1ms.
> > 3. Clean ixSMU_PM_STATUS_94 immediately when send 
> PPSMC_MSG_PmStatusLogStart
> >     to avoid read old value.
> > 4. delay 10 ms instand of 20 ms. so the result will more similar to
> >     the output of PPSMC_MSG_GetCurrPkgPwr.
> > 5. remove max power/vddc/vddci output to keep consistent with vega.
> > 6. for vddc/vddci power, we can calculate the average value per
> >     [10ms, 4s] in other interface if needed.
> >
> > Signed-off-by: Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
> > ---
> > drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 45 
> +++++++++++-------------
> >   1 file changed, 21 insertions(+), 24 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> > index 40f2f87..c0ce672 100644
> > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> > @@ -3363,30 +3363,27 @@ static int smu7_get_pp_table_entry(struct 
> pp_hwmgr *hwmgr,
> >   static int smu7_get_gpu_power(struct pp_hwmgr *hwmgr,
> >                struct pp_gpu_power *query)
> >   {
> > - PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
> > - PPSMC_MSG_PmStatusLogStart),
> > -                     "Failed to start pm status log!",
> > -                     return -1);
> > -
> > -     msleep_interruptible(20);
> > -
> > - PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
> > - PPSMC_MSG_PmStatusLogSample),
> > -                     "Failed to sample pm status log!",
> > -                     return -1);
> > -
> > -     query->vddc_power = cgs_read_ind_register(hwmgr->device,
> > -                     CGS_IND_REG__SMC,
> > -                     ixSMU_PM_STATUS_40);
> > -     query->vddci_power = cgs_read_ind_register(hwmgr->device,
> > -                     CGS_IND_REG__SMC,
> > -                     ixSMU_PM_STATUS_49);
> > -     query->max_gpu_power = cgs_read_ind_register(hwmgr->device,
> > -                     CGS_IND_REG__SMC,
> > -                     ixSMU_PM_STATUS_94);
> > -     query->average_gpu_power = cgs_read_ind_register(hwmgr->device,
> > -                     CGS_IND_REG__SMC,
> > -                     ixSMU_PM_STATUS_95);
> > +     if (!query)
> > +             return -EINVAL;
> > +
> > +     memset(query, 0, sizeof *query);
> > +
> > +     if (hwmgr->chip_id >= CHIP_POLARIS10) {
> > +             smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrPkgPwr);
> > +             query->average_gpu_power = 
> cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
> > +     } else {
> > +             smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogStart);
> > + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
> > + ixSMU_PM_STATUS_94, 0);
> > +
> > +             msleep_interruptible(10);
> > +
> > +             smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogSample);
> > +
> > +             query->average_gpu_power = 
> cgs_read_ind_register(hwmgr->device,
> > + CGS_IND_REG__SMC,
> > + ixSMU_PM_STATUS_94);
> > +     }
> >
> >        return 0;
> >   }
>
> _______________________________________________
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>
>
>


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Re: [PATCH 2/3] drm/amd/pp: Refine get_gpu_power for VI

[Zhu, Rex]

[-- Attachment #1.1: Type: text/plain, Size: 5845 bytes --]

with this patch, there should be no difference between AGT and sysfs.



Best Regards

Rex

________________________________
From: Huang, JinHuiEric
Sent: Thursday, April 5, 2018 12:00 AM
To: Zhu, Rex; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: Re: [PATCH 2/3] drm/amd/pp: Refine get_gpu_power for VI


So you didn't compare the result with AGT, but I did. The reality is not like your speculation.


Regards,

Eric

On 2018-04-04 11:50 AM, Zhu, Rex wrote:

If user send message PPSMC_MSG_GetCurrPkgPwr, firmware will return the pkgpwr immediately as current power value.

as no PPSMC_MSG_GetCurrPkgPwr support, so send message  let firmware write pkgpwr  to ixSMU_PM_STATUS_94,

and driver delay 10ms to read ixSMU_PM_STATUS_94.


I don't think there is any problem. otherwise, there is same issue on polaris/vega.


I clean ixSMU_PM_STATUS_94 before let smu write it.

The delay time is enough unless we got 0 from ixSMU_PM_STATUS_94 .



Best Regards

Rex


________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org><mailto:amd-gfx-bounces@lists.freedesktop.org> on behalf of Eric Huang <jinhuieric.huang-5C7GfCeVMHo@public.gmane.org><mailto:jinhuieric.huang-5C7GfCeVMHo@public.gmane.org>
Sent: Wednesday, April 4, 2018 11:36 PM
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
Subject: Re: [PATCH 2/3] drm/amd/pp: Refine get_gpu_power for VI

Sampling period is too short. The power reading value will be not
aligned with AGT's. It will confuse user that why AMD provides two
different power results.

Regards,
Eric

On 2018-04-04 04:25 AM, Rex Zhu wrote:
> 1. On polaris10/11/12, Sending smu message PPSMC_MSG_GetCurrPkgPwr to
>     read currentpkgpwr directly.
> 2. On Fiji/tonga/bonaire/hawwii, no PPSMC_MSG_GetCurrPkgPwr support.
>     Send PPSMC_MSG_PmStatusLogStart to let smu write currentpkgpwr
>     to ixSMU_PM_STATUS_94. this is asynchronous. need to delay no less
>     than 1ms.
> 3. Clean ixSMU_PM_STATUS_94 immediately when send PPSMC_MSG_PmStatusLogStart
>     to avoid read old value.
> 4. delay 10 ms instand of 20 ms. so the result will more similar to
>     the output of PPSMC_MSG_GetCurrPkgPwr.
> 5. remove max power/vddc/vddci output to keep consistent with vega.
> 6. for vddc/vddci power, we can calculate the average value per
>     [10ms, 4s] in other interface if needed.
>
> Signed-off-by: Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org><mailto:Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
> ---
>   drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 45 +++++++++++-------------
>   1 file changed, 21 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> index 40f2f87..c0ce672 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> @@ -3363,30 +3363,27 @@ static int smu7_get_pp_table_entry(struct pp_hwmgr *hwmgr,
>   static int smu7_get_gpu_power(struct pp_hwmgr *hwmgr,
>                struct pp_gpu_power *query)
>   {
> -     PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
> -                     PPSMC_MSG_PmStatusLogStart),
> -                     "Failed to start pm status log!",
> -                     return -1);
> -
> -     msleep_interruptible(20);
> -
> -     PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
> -                     PPSMC_MSG_PmStatusLogSample),
> -                     "Failed to sample pm status log!",
> -                     return -1);
> -
> -     query->vddc_power = cgs_read_ind_register(hwmgr->device,
> -                     CGS_IND_REG__SMC,
> -                     ixSMU_PM_STATUS_40);
> -     query->vddci_power = cgs_read_ind_register(hwmgr->device,
> -                     CGS_IND_REG__SMC,
> -                     ixSMU_PM_STATUS_49);
> -     query->max_gpu_power = cgs_read_ind_register(hwmgr->device,
> -                     CGS_IND_REG__SMC,
> -                     ixSMU_PM_STATUS_94);
> -     query->average_gpu_power = cgs_read_ind_register(hwmgr->device,
> -                     CGS_IND_REG__SMC,
> -                     ixSMU_PM_STATUS_95);
> +     if (!query)
> +             return -EINVAL;
> +
> +     memset(query, 0, sizeof *query);
> +
> +     if (hwmgr->chip_id >= CHIP_POLARIS10) {
> +             smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrPkgPwr);
> +             query->average_gpu_power = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
> +     } else {
> +             smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogStart);
> +             cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
> +                                     ixSMU_PM_STATUS_94, 0);
> +
> +             msleep_interruptible(10);
> +
> +             smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogSample);
> +
> +             query->average_gpu_power = cgs_read_ind_register(hwmgr->device,
> +                                                     CGS_IND_REG__SMC,
> +                                                     ixSMU_PM_STATUS_94);
> +     }
>
>        return 0;
>   }

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Re: [PATCH 1/3] Revert "drm/amd/powerply: fix power reading on Fiji"

[Eric Huang]

If it is verified by SMU team, I am OK with it.

Regards,
Eric

On 2018-04-11 01:19 PM, Alex Deucher wrote:
> On Wed, Apr 11, 2018 at 2:31 AM, Rex Zhu <Rex.Zhu@amd.com> wrote:
>> we don't have limit of [50ms, 4sec] sampling period.
>> smu calculate average gpu power in real time.
>> we can read average gpu power through smu message or
>> read special register.
>>
>> This reverts commit 462d8dcc9fec0d89f1ff6a1f93f1d4f670878c71.
>>
>> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
> If Eric is ok with this,
>
> Acked-by: Alex Deucher <alexander.deucher@amd.com>
>
>> ---
>>   drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 3 +--
>>   1 file changed, 1 insertion(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
>> index 21c021b..388184e 100644
>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
>> @@ -3364,8 +3364,7 @@ static int smu7_get_gpu_power(struct pp_hwmgr *hwmgr,
>>                          "Failed to start pm status log!",
>>                          return -1);
>>
>> -       /* Sampling period from 50ms to 4sec */
>> -       msleep_interruptible(200);
>> +       msleep_interruptible(20);
>>
>>          PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
>>                          PPSMC_MSG_PmStatusLogSample),
>> --
>> 1.9.1
>>
>> _______________________________________________
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>> amd-gfx@lists.freedesktop.org
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> _______________________________________________
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Re: [PATCH 1/3] Revert "drm/amd/powerply: fix power reading on Fiji"

[Alex Deucher]

On Wed, Apr 11, 2018 at 2:31 AM, Rex Zhu <Rex.Zhu@amd.com> wrote:
> we don't have limit of [50ms, 4sec] sampling period.
> smu calculate average gpu power in real time.
> we can read average gpu power through smu message or
> read special register.
>
> This reverts commit 462d8dcc9fec0d89f1ff6a1f93f1d4f670878c71.
>
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>

If Eric is ok with this,

Acked-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> index 21c021b..388184e 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> @@ -3364,8 +3364,7 @@ static int smu7_get_gpu_power(struct pp_hwmgr *hwmgr,
>                         "Failed to start pm status log!",
>                         return -1);
>
> -       /* Sampling period from 50ms to 4sec */
> -       msleep_interruptible(200);
> +       msleep_interruptible(20);
>
>         PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
>                         PPSMC_MSG_PmStatusLogSample),
> --
> 1.9.1
>
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[PATCH 1/3] Revert "drm/amd/powerply: fix power reading on Fiji"

[Rex Zhu]

we don't have limit of [50ms, 4sec] sampling period.
smu calculate average gpu power in real time.
we can read average gpu power through smu message or
read special register.

This reverts commit 462d8dcc9fec0d89f1ff6a1f93f1d4f670878c71.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 21c021b..388184e 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -3364,8 +3364,7 @@ static int smu7_get_gpu_power(struct pp_hwmgr *hwmgr,
 			"Failed to start pm status log!",
 			return -1);
 
-	/* Sampling period from 50ms to 4sec */
-	msleep_interruptible(200);
+	msleep_interruptible(20);
 
 	PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
 			PPSMC_MSG_PmStatusLogSample),
-- 
1.9.1

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