* [PATCH] drm/amd/powerplay: Get more than 8 level gfxclk states
@ 2018-04-04 8:33 Kenneth Feng
[not found] ` <1522830792-23141-1-git-send-email-kenneth.feng-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 4+ messages in thread
From: Kenneth Feng @ 2018-04-04 8:33 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Kenneth Feng
To apply on Vega12 for more than 8 gfx dpm levels
Change-Id: I0a0e1e044b35d27a28a3145b2de365d3be6132cd
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h
index bc98b1d..e81ded1 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h
@@ -33,7 +33,7 @@
#define WaterMarksExist 1
#define WaterMarksLoaded 2
-#define VG12_PSUEDO_NUM_GFXCLK_DPM_LEVELS 8
+#define VG12_PSUEDO_NUM_GFXCLK_DPM_LEVELS 16
#define VG12_PSUEDO_NUM_SOCCLK_DPM_LEVELS 8
#define VG12_PSUEDO_NUM_DCEFCLK_DPM_LEVELS 8
#define VG12_PSUEDO_NUM_UCLK_DPM_LEVELS 4
--
2.7.4
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^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH] drm/amd/powerplay: implement pp_dpm_sclk sysfs interface on Vega12
[not found] ` <1522830792-23141-1-git-send-email-kenneth.feng-5C7GfCeVMHo@public.gmane.org>
@ 2018-04-04 8:33 ` Kenneth Feng
[not found] ` <1522830792-23141-2-git-send-email-kenneth.feng-5C7GfCeVMHo@public.gmane.org>
2018-04-04 18:13 ` [PATCH] drm/amd/powerplay: Get more than 8 level gfxclk states Alex Deucher
1 sibling, 1 reply; 4+ messages in thread
From: Kenneth Feng @ 2018-04-04 8:33 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Kenneth Feng
Change-Id: Icd8f1a9bb9ef4bbd439f5eb5febd1d624b06bbd2
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 27 +++++++++++++++++-----
1 file changed, 21 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
index 6a85238..caeabda 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
@@ -1742,13 +1742,28 @@ static int vega12_force_clock_level(struct pp_hwmgr *hwmgr,
data->smc_state_table.gfx_boot_level = mask ? (ffs(mask) - 1) : 0;
data->smc_state_table.gfx_max_level = mask ? (fls(mask) - 1) : 0;
- PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr),
- "Failed to upload boot level to lowest!",
- return -EINVAL);
+ if (data->smc_state_table.gfx_boot_level !=
+ data->dpm_table.gfx_table.dpm_state.soft_min_level) {
+ PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetSoftMinByFreq,
+ PP_SCLK<<16 | data->dpm_table.gfx_table.dpm_levels[data->smc_state_table.gfx_boot_level].value) == 0,
+ "Failed to upload boot level to lowest!", return -EINVAL);
+ data->dpm_table.gfx_table.dpm_state.soft_min_level =
+ data->smc_state_table.gfx_boot_level;
+
+ }
+
+ if (data->smc_state_table.gfx_max_level !=
+ data->dpm_table.gfx_table.dpm_state.soft_max_level) {
+ PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetSoftMaxByFreq,
+ /* plus the vale by 1 to align the resolution */
+ PP_SCLK<<16 | (data->dpm_table.gfx_table.dpm_levels[data->smc_state_table.gfx_max_level].value + 1)) == 0,
+ "Failed to upload dpm max level to highest!", return -EINVAL);
+ data->dpm_table.gfx_table.dpm_state.soft_max_level =
+ data->smc_state_table.gfx_max_level;
+ }
- PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr),
- "Failed to upload dpm max level to highest!",
- return -EINVAL);
break;
case PP_MCLK:
--
2.7.4
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^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] drm/amd/powerplay: implement pp_dpm_sclk sysfs interface on Vega12
[not found] ` <1522830792-23141-2-git-send-email-kenneth.feng-5C7GfCeVMHo@public.gmane.org>
@ 2018-04-04 18:12 ` Alex Deucher
0 siblings, 0 replies; 4+ messages in thread
From: Alex Deucher @ 2018-04-04 18:12 UTC (permalink / raw)
To: Kenneth Feng; +Cc: amd-gfx list
On Wed, Apr 4, 2018 at 4:33 AM, Kenneth Feng <kenneth.feng@amd.com> wrote:
> Change-Id: Icd8f1a9bb9ef4bbd439f5eb5febd1d624b06bbd2
> Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Please include a proper patch description. E.g.,
Replace forced sclk stubs with a proper implementation.
With that added:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 27 +++++++++++++++++-----
> 1 file changed, 21 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> index 6a85238..caeabda 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> @@ -1742,13 +1742,28 @@ static int vega12_force_clock_level(struct pp_hwmgr *hwmgr,
> data->smc_state_table.gfx_boot_level = mask ? (ffs(mask) - 1) : 0;
> data->smc_state_table.gfx_max_level = mask ? (fls(mask) - 1) : 0;
>
> - PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr),
> - "Failed to upload boot level to lowest!",
> - return -EINVAL);
> + if (data->smc_state_table.gfx_boot_level !=
> + data->dpm_table.gfx_table.dpm_state.soft_min_level) {
> + PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetSoftMinByFreq,
> + PP_SCLK<<16 | data->dpm_table.gfx_table.dpm_levels[data->smc_state_table.gfx_boot_level].value) == 0,
> + "Failed to upload boot level to lowest!", return -EINVAL);
> + data->dpm_table.gfx_table.dpm_state.soft_min_level =
> + data->smc_state_table.gfx_boot_level;
> +
> + }
> +
> + if (data->smc_state_table.gfx_max_level !=
> + data->dpm_table.gfx_table.dpm_state.soft_max_level) {
> + PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetSoftMaxByFreq,
> + /* plus the vale by 1 to align the resolution */
> + PP_SCLK<<16 | (data->dpm_table.gfx_table.dpm_levels[data->smc_state_table.gfx_max_level].value + 1)) == 0,
> + "Failed to upload dpm max level to highest!", return -EINVAL);
> + data->dpm_table.gfx_table.dpm_state.soft_max_level =
> + data->smc_state_table.gfx_max_level;
> + }
>
> - PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr),
> - "Failed to upload dpm max level to highest!",
> - return -EINVAL);
> break;
>
> case PP_MCLK:
> --
> 2.7.4
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] drm/amd/powerplay: Get more than 8 level gfxclk states
[not found] ` <1522830792-23141-1-git-send-email-kenneth.feng-5C7GfCeVMHo@public.gmane.org>
2018-04-04 8:33 ` [PATCH] drm/amd/powerplay: implement pp_dpm_sclk sysfs interface on Vega12 Kenneth Feng
@ 2018-04-04 18:13 ` Alex Deucher
1 sibling, 0 replies; 4+ messages in thread
From: Alex Deucher @ 2018-04-04 18:13 UTC (permalink / raw)
To: Kenneth Feng; +Cc: amd-gfx list
On Wed, Apr 4, 2018 at 4:33 AM, Kenneth Feng <kenneth.feng@amd.com> wrote:
> To apply on Vega12 for more than 8 gfx dpm levels
>
> Change-Id: I0a0e1e044b35d27a28a3145b2de365d3be6132cd
> Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h
> index bc98b1d..e81ded1 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h
> @@ -33,7 +33,7 @@
> #define WaterMarksExist 1
> #define WaterMarksLoaded 2
>
> -#define VG12_PSUEDO_NUM_GFXCLK_DPM_LEVELS 8
> +#define VG12_PSUEDO_NUM_GFXCLK_DPM_LEVELS 16
> #define VG12_PSUEDO_NUM_SOCCLK_DPM_LEVELS 8
> #define VG12_PSUEDO_NUM_DCEFCLK_DPM_LEVELS 8
> #define VG12_PSUEDO_NUM_UCLK_DPM_LEVELS 4
> --
> 2.7.4
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 4+ messages in thread
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2018-04-04 8:33 [PATCH] drm/amd/powerplay: Get more than 8 level gfxclk states Kenneth Feng
[not found] ` <1522830792-23141-1-git-send-email-kenneth.feng-5C7GfCeVMHo@public.gmane.org>
2018-04-04 8:33 ` [PATCH] drm/amd/powerplay: implement pp_dpm_sclk sysfs interface on Vega12 Kenneth Feng
[not found] ` <1522830792-23141-2-git-send-email-kenneth.feng-5C7GfCeVMHo@public.gmane.org>
2018-04-04 18:12 ` Alex Deucher
2018-04-04 18:13 ` [PATCH] drm/amd/powerplay: Get more than 8 level gfxclk states Alex Deucher
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