* [PATCH v3 0/4] HDCP1.4 fixes
@ 2018-04-02 10:10 Ramalingam C
2018-04-02 10:10 ` [PATCH v3 1/4] drm/i915: Read HDCP R0 thrice in case of mismatch Ramalingam C
` (13 more replies)
0 siblings, 14 replies; 25+ messages in thread
From: Ramalingam C @ 2018-04-02 10:10 UTC (permalink / raw)
To: intel-gfx, dri-devel, seanpaul, ville.syrjala; +Cc: rodrigo.vivi
First two patches needed for below DP HDCP compliance tests
1A-06 and 1B-05
Third patch fixes the HDCP1.4 Key loadability check. where as fourth
one fixes the downstream device count read.
Fix for HDMI HDCP1.4 CTS tests: 1A-04 and 1A-07a are functional.
But the change from v2, as thinking to put through more regressive
testing before upstreaming.
Ramalingam C (4):
drm/i915: Read HDCP R0 thrice in case of mismatch
drm/i915: Read Vprime thrice incase of mismatch
drm/i915: Check hdcp key loadability
drm/i915: Fix reading downstream dev count
drivers/gpu/drm/i915/intel_hdcp.c | 182 +++++++++++++++++++++++++++-----------
include/drm/drm_hdcp.h | 2 +-
2 files changed, 130 insertions(+), 54 deletions(-)
--
2.7.4
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^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v3 1/4] drm/i915: Read HDCP R0 thrice in case of mismatch
2018-04-02 10:10 [PATCH v3 0/4] HDCP1.4 fixes Ramalingam C
@ 2018-04-02 10:10 ` Ramalingam C
2018-04-02 11:50 ` [PATCH v4 " Ramalingam C
2018-04-02 10:10 ` [PATCH v3 2/4] drm/i915: Read Vprime thrice incase " Ramalingam C
` (12 subsequent siblings)
13 siblings, 1 reply; 25+ messages in thread
From: Ramalingam C @ 2018-04-02 10:10 UTC (permalink / raw)
To: intel-gfx, dri-devel, seanpaul, ville.syrjala; +Cc: rodrigo.vivi
As per DP spec when R0 mismatch is detected, HDCP source supported
re-read the R0 atleast twice.
And For HDMI and DP minimum wait required for the R0 availability is
100mSec. So this patch changes the wait time to 100mSec but retries
twice with the time interval of 100mSec for each attempt.
This patch is needed for DP HDCP1.4 CTS Test: 1A-06.
v2:
No Change
v3:
Comment on R0 retry is moved closer to the code[Seanpaul]
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
---
drivers/gpu/drm/i915/intel_hdcp.c | 29 ++++++++++++++++++++---------
1 file changed, 20 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_hdcp.c b/drivers/gpu/drm/i915/intel_hdcp.c
index 14ca5d3057a7..838c8cd0f543 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -498,7 +498,7 @@ static int intel_hdcp_auth(struct intel_digital_port *intel_dig_port,
/*
* Wait for R0' to become available. The spec says 100ms from Aksv, but
* some monitors can take longer than this. We'll set the timeout at
- * 300ms just to be sure.
+- * 300ms just to be sure.
*
* On DP, there's an R0_READY bit available but no such bit
* exists on HDMI. Since the upper-bound is the same, we'll just do
@@ -506,15 +506,26 @@ static int intel_hdcp_auth(struct intel_digital_port *intel_dig_port,
*/
wait_remaining_ms_from_jiffies(r0_prime_gen_start, 300);
- ri.reg = 0;
- ret = shim->read_ri_prime(intel_dig_port, ri.shim);
- if (ret)
- return ret;
- I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg);
+ tries = 3;
- /* Wait for Ri prime match */
- if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
- (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
+ /*
+ * DP HDCP Spec mandates the two more reattempt to read R0, incase
+ * of R0 mismatch.
+ */
+ for (i = 0; i < tries; i++) {
+ ri.reg = 0;
+ ret = shim->read_ri_prime(intel_dig_port, ri.shim);
+ if (ret)
+ return ret;
+ I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg);
+
+ /* Wait for Ri prime match */
+ if (!wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
+ (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1))
+ break;
+ }
+
+ if (i == tries) {
DRM_ERROR("Timed out waiting for Ri prime match (%x)\n",
I915_READ(PORT_HDCP_STATUS(port)));
return -ETIMEDOUT;
--
2.7.4
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^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 2/4] drm/i915: Read Vprime thrice incase of mismatch
2018-04-02 10:10 [PATCH v3 0/4] HDCP1.4 fixes Ramalingam C
2018-04-02 10:10 ` [PATCH v3 1/4] drm/i915: Read HDCP R0 thrice in case of mismatch Ramalingam C
@ 2018-04-02 10:10 ` Ramalingam C
2018-04-02 13:50 ` Sean Paul
2018-04-02 10:10 ` [PATCH v3 3/4] drm/i915: Check hdcp key loadability Ramalingam C
` (11 subsequent siblings)
13 siblings, 1 reply; 25+ messages in thread
From: Ramalingam C @ 2018-04-02 10:10 UTC (permalink / raw)
To: intel-gfx, dri-devel, seanpaul, ville.syrjala; +Cc: rodrigo.vivi
In case of V prime mismatch, DP HDCP spec mandates the re-read of
Vprime atleast twice.
This patch needed for DP HDCP1.4 CTS Test: 1B-05.
v2:
Moved the V' validation into a function for retry. [Sean Paul]
v3:
Removed Inline keyword and DRM_DEBUG_KMS are used [Sean Paul]
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
---
drivers/gpu/drm/i915/intel_hdcp.c | 112 ++++++++++++++++++++++++--------------
1 file changed, 70 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_hdcp.c b/drivers/gpu/drm/i915/intel_hdcp.c
index 838c8cd0f543..e0bc03eee941 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -142,53 +142,17 @@ bool intel_hdcp_is_ksv_valid(u8 *ksv)
return true;
}
-/* Implements Part 2 of the HDCP authorization procedure */
static
-int intel_hdcp_auth_downstream(struct intel_digital_port *intel_dig_port,
- const struct intel_hdcp_shim *shim)
+int intel_hdcp_validate_v_prime(struct intel_digital_port *intel_dig_port,
+ const struct intel_hdcp_shim *shim,
+ u8 *ksv_fifo, u8 num_downstream, u8 *bstatus)
{
struct drm_i915_private *dev_priv;
u32 vprime, sha_text, sha_leftovers, rep_ctl;
- u8 bstatus[2], num_downstream, *ksv_fifo;
int ret, i, j, sha_idx;
dev_priv = intel_dig_port->base.base.dev->dev_private;
- ret = intel_hdcp_poll_ksv_fifo(intel_dig_port, shim);
- if (ret) {
- DRM_ERROR("KSV list failed to become ready (%d)\n", ret);
- return ret;
- }
-
- ret = shim->read_bstatus(intel_dig_port, bstatus);
- if (ret)
- return ret;
-
- if (DRM_HDCP_MAX_DEVICE_EXCEEDED(bstatus[0]) ||
- DRM_HDCP_MAX_CASCADE_EXCEEDED(bstatus[1])) {
- DRM_ERROR("Max Topology Limit Exceeded\n");
- return -EPERM;
- }
-
- /*
- * When repeater reports 0 device count, HDCP1.4 spec allows disabling
- * the HDCP encryption. That implies that repeater can't have its own
- * display. As there is no consumption of encrypted content in the
- * repeater with 0 downstream devices, we are failing the
- * authentication.
- */
- num_downstream = DRM_HDCP_NUM_DOWNSTREAM(bstatus[0]);
- if (num_downstream == 0)
- return -EINVAL;
-
- ksv_fifo = kzalloc(num_downstream * DRM_HDCP_KSV_LEN, GFP_KERNEL);
- if (!ksv_fifo)
- return -ENOMEM;
-
- ret = shim->read_ksv_fifo(intel_dig_port, num_downstream, ksv_fifo);
- if (ret)
- return ret;
-
/* Process V' values from the receiver */
for (i = 0; i < DRM_HDCP_V_PRIME_NUM_PARTS; i++) {
ret = shim->read_v_prime_part(intel_dig_port, i, &vprime);
@@ -353,7 +317,8 @@ int intel_hdcp_auth_downstream(struct intel_digital_port *intel_dig_port,
return ret;
sha_idx += sizeof(sha_text);
} else {
- DRM_ERROR("Invalid number of leftovers %d\n", sha_leftovers);
+ DRM_DEBUG_KMS("Invalid number of leftovers %d\n",
+ sha_leftovers);
return -EINVAL;
}
@@ -381,14 +346,77 @@ int intel_hdcp_auth_downstream(struct intel_digital_port *intel_dig_port,
if (intel_wait_for_register(dev_priv, HDCP_REP_CTL,
HDCP_SHA1_COMPLETE,
HDCP_SHA1_COMPLETE, 1)) {
- DRM_ERROR("Timed out waiting for SHA1 complete\n");
+ DRM_DEBUG_KMS("Timed out waiting for SHA1 complete\n");
return -ETIMEDOUT;
}
if (!(I915_READ(HDCP_REP_CTL) & HDCP_SHA1_V_MATCH)) {
- DRM_ERROR("SHA-1 mismatch, HDCP failed\n");
+ DRM_DEBUG_KMS("SHA-1 mismatch, HDCP failed\n");
return -ENXIO;
}
+ return 0;
+}
+
+/* Implements Part 2 of the HDCP authorization procedure */
+static
+int intel_hdcp_auth_downstream(struct intel_digital_port *intel_dig_port,
+ const struct intel_hdcp_shim *shim)
+{
+ u8 bstatus[2], num_downstream, *ksv_fifo;
+ int ret, i, tries = 3;
+
+ ret = intel_hdcp_poll_ksv_fifo(intel_dig_port, shim);
+ if (ret) {
+ DRM_ERROR("KSV list failed to become ready (%d)\n", ret);
+ return ret;
+ }
+
+ ret = shim->read_bstatus(intel_dig_port, bstatus);
+ if (ret)
+ return ret;
+
+ if (DRM_HDCP_MAX_DEVICE_EXCEEDED(bstatus[0]) ||
+ DRM_HDCP_MAX_CASCADE_EXCEEDED(bstatus[1])) {
+ DRM_ERROR("Max Topology Limit Exceeded\n");
+ return -EPERM;
+ }
+
+ /*
+ * When repeater reports 0 device count, HDCP1.4 spec allows disabling
+ * the HDCP encryption. That implies that repeater can't have its own
+ * display. As there is no consumption of encrypted content in the
+ * repeater with 0 downstream devices, we are failing the
+ * authentication.
+ */
+ num_downstream = DRM_HDCP_NUM_DOWNSTREAM(bstatus[0]);
+ if (num_downstream == 0)
+ return -EINVAL;
+
+ ksv_fifo = kzalloc(num_downstream * DRM_HDCP_KSV_LEN, GFP_KERNEL);
+ if (!ksv_fifo)
+ return -ENOMEM;
+
+ ret = shim->read_ksv_fifo(intel_dig_port, num_downstream, ksv_fifo);
+ if (ret)
+ return ret;
+
+ /*
+ * When V prime mismatches, DP Spec mandates re-read of
+ * V prime atleast twice.
+ */
+ for (i = 0; i < tries; i++) {
+ ret = intel_hdcp_validate_v_prime(intel_dig_port, shim,
+ ksv_fifo, num_downstream,
+ bstatus);
+ if (!ret)
+ break;
+ }
+
+ if (i == tries) {
+ DRM_ERROR("V Prime validation failed.(%d)\n", ret);
+ return ret;
+ }
+
DRM_DEBUG_KMS("HDCP is enabled (%d downstream devices)\n",
num_downstream);
return 0;
--
2.7.4
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 3/4] drm/i915: Check hdcp key loadability
2018-04-02 10:10 [PATCH v3 0/4] HDCP1.4 fixes Ramalingam C
2018-04-02 10:10 ` [PATCH v3 1/4] drm/i915: Read HDCP R0 thrice in case of mismatch Ramalingam C
2018-04-02 10:10 ` [PATCH v3 2/4] drm/i915: Read Vprime thrice incase " Ramalingam C
@ 2018-04-02 10:10 ` Ramalingam C
2018-04-02 10:10 ` [PATCH v3 4/4] drm/i915: Fix reading downstream dev count Ramalingam C
` (10 subsequent siblings)
13 siblings, 0 replies; 25+ messages in thread
From: Ramalingam C @ 2018-04-02 10:10 UTC (permalink / raw)
To: intel-gfx, dri-devel, seanpaul, ville.syrjala; +Cc: rodrigo.vivi
HDCP1.4 key can be loaded, only when Power well #1 is enabled and cdclk
is enabled. Using the I915 power well infrastruture, above requirement
is verified.
This patch enables the hdcp initialization for HSW, BDW, and BXT.
v2:
Choose the PW# based on the platform.
v3:
No Changes.
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
---
drivers/gpu/drm/i915/intel_hdcp.c | 41 +++++++++++++++++++++++++++++++++++++--
1 file changed, 39 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_hdcp.c b/drivers/gpu/drm/i915/intel_hdcp.c
index e0bc03eee941..94b7b5158169 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -37,6 +37,43 @@ static int intel_hdcp_poll_ksv_fifo(struct intel_digital_port *intel_dig_port,
return 0;
}
+static bool hdcp_key_loadable(struct drm_i915_private *dev_priv)
+{
+ struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ struct i915_power_well *power_well;
+ enum i915_power_well_id id;
+ bool enabled = false;
+
+ /*
+ * On HSW and BDW, Display HW loads the Key as soon as Display resumes.
+ * On all BXT+, SW can load the keys only when the PW#1 is turned on.
+ */
+ if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
+ id = HSW_DISP_PW_GLOBAL;
+ else
+ id = SKL_DISP_PW_1;
+
+ mutex_lock(&power_domains->lock);
+
+ /* PG1 (power well #1) needs to be enabled */
+ for_each_power_well(dev_priv, power_well) {
+ if (power_well->id == id) {
+ enabled = power_well->ops->is_enabled(dev_priv,
+ power_well);
+ break;
+ }
+ }
+ mutex_unlock(&power_domains->lock);
+
+ /*
+ * Another req for hdcp key loadability is enabled state of pll for
+ * cdclk. Without active crtc we wont land here. So we are assuming that
+ * cdclk is already on.
+ */
+
+ return enabled;
+}
+
static void intel_hdcp_clear_keys(struct drm_i915_private *dev_priv)
{
I915_WRITE(HDCP_KEY_CONF, HDCP_CLEAR_KEYS_TRIGGER);
@@ -619,8 +656,8 @@ static int _intel_hdcp_enable(struct intel_connector *connector)
DRM_DEBUG_KMS("[%s:%d] HDCP is being enabled...\n",
connector->base.name, connector->base.base.id);
- if (!(I915_READ(SKL_FUSE_STATUS) & SKL_FUSE_PG_DIST_STATUS(1))) {
- DRM_ERROR("PG1 is disabled, cannot load keys\n");
+ if (!hdcp_key_loadable(dev_priv)) {
+ DRM_ERROR("HDCP key Load is not possible\n");
return -ENXIO;
}
--
2.7.4
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^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 4/4] drm/i915: Fix reading downstream dev count
2018-04-02 10:10 [PATCH v3 0/4] HDCP1.4 fixes Ramalingam C
` (2 preceding siblings ...)
2018-04-02 10:10 ` [PATCH v3 3/4] drm/i915: Check hdcp key loadability Ramalingam C
@ 2018-04-02 10:10 ` Ramalingam C
2018-04-04 18:27 ` [PATCH v4] drm: Fix downstream dev count read Ramalingam C
2018-04-02 10:40 ` ✓ Fi.CI.BAT: success for HDCP1.4 fixes (rev4) Patchwork
` (9 subsequent siblings)
13 siblings, 1 reply; 25+ messages in thread
From: Ramalingam C @ 2018-04-02 10:10 UTC (permalink / raw)
To: intel-gfx, dri-devel, seanpaul, ville.syrjala; +Cc: rodrigo.vivi
In both HDMI and DP, device count is represented by 6:0 bits of a
register(BInfo/Bstatus)
So macro for bitmasking the device_count is fixed(0x3F->0x7F).
v3:
Retained the Rb-ed
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
cc: Sean Paul <seanpaul@chromium.org>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
---
include/drm/drm_hdcp.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h
index 562fa7df2637..98e63d870139 100644
--- a/include/drm/drm_hdcp.h
+++ b/include/drm/drm_hdcp.h
@@ -19,7 +19,7 @@
#define DRM_HDCP_RI_LEN 2
#define DRM_HDCP_V_PRIME_PART_LEN 4
#define DRM_HDCP_V_PRIME_NUM_PARTS 5
-#define DRM_HDCP_NUM_DOWNSTREAM(x) (x & 0x3f)
+#define DRM_HDCP_NUM_DOWNSTREAM(x) (x & 0x7f)
#define DRM_HDCP_MAX_CASCADE_EXCEEDED(x) (x & BIT(3))
#define DRM_HDCP_MAX_DEVICE_EXCEEDED(x) (x & BIT(7))
--
2.7.4
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^ permalink raw reply related [flat|nested] 25+ messages in thread
* ✓ Fi.CI.BAT: success for HDCP1.4 fixes (rev4)
2018-04-02 10:10 [PATCH v3 0/4] HDCP1.4 fixes Ramalingam C
` (3 preceding siblings ...)
2018-04-02 10:10 ` [PATCH v3 4/4] drm/i915: Fix reading downstream dev count Ramalingam C
@ 2018-04-02 10:40 ` Patchwork
2018-04-02 11:34 ` ✓ Fi.CI.IGT: " Patchwork
` (8 subsequent siblings)
13 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2018-04-02 10:40 UTC (permalink / raw)
To: Ramalingam C; +Cc: intel-gfx
== Series Details ==
Series: HDCP1.4 fixes (rev4)
URL : https://patchwork.freedesktop.org/series/38978/
State : success
== Summary ==
Series 38978v4 HDCP1.4 fixes
https://patchwork.freedesktop.org/api/1.0/series/38978/revisions/4/mbox/
fi-bdw-5557u total:285 pass:264 dwarn:0 dfail:0 fail:0 skip:21 time:434s
fi-bdw-gvtdvm total:285 pass:261 dwarn:0 dfail:0 fail:0 skip:24 time:441s
fi-blb-e6850 total:285 pass:220 dwarn:1 dfail:0 fail:0 skip:64 time:388s
fi-bsw-n3050 total:285 pass:239 dwarn:0 dfail:0 fail:0 skip:46 time:545s
fi-bwr-2160 total:285 pass:180 dwarn:0 dfail:0 fail:0 skip:105 time:296s
fi-bxt-dsi total:285 pass:255 dwarn:0 dfail:0 fail:0 skip:30 time:513s
fi-bxt-j4205 total:285 pass:256 dwarn:0 dfail:0 fail:0 skip:29 time:515s
fi-byt-j1900 total:285 pass:250 dwarn:0 dfail:0 fail:0 skip:35 time:523s
fi-byt-n2820 total:285 pass:246 dwarn:0 dfail:0 fail:0 skip:39 time:514s
fi-cfl-8700k total:285 pass:257 dwarn:0 dfail:0 fail:0 skip:28 time:410s
fi-cfl-s3 total:285 pass:259 dwarn:0 dfail:0 fail:0 skip:26 time:558s
fi-cfl-u total:285 pass:259 dwarn:0 dfail:0 fail:0 skip:26 time:510s
fi-cnl-y3 total:285 pass:259 dwarn:0 dfail:0 fail:0 skip:26 time:582s
fi-elk-e7500 total:285 pass:225 dwarn:1 dfail:0 fail:0 skip:59 time:430s
fi-gdg-551 total:285 pass:176 dwarn:0 dfail:0 fail:1 skip:108 time:316s
fi-glk-1 total:285 pass:257 dwarn:0 dfail:0 fail:0 skip:28 time:537s
fi-hsw-4770 total:285 pass:258 dwarn:0 dfail:0 fail:0 skip:27 time:404s
fi-ilk-650 total:285 pass:225 dwarn:0 dfail:0 fail:0 skip:60 time:422s
fi-ivb-3520m total:285 pass:256 dwarn:0 dfail:0 fail:0 skip:29 time:468s
fi-ivb-3770 total:285 pass:252 dwarn:0 dfail:0 fail:0 skip:33 time:426s
fi-kbl-7500u total:285 pass:260 dwarn:1 dfail:0 fail:0 skip:24 time:473s
fi-kbl-7567u total:285 pass:265 dwarn:0 dfail:0 fail:0 skip:20 time:464s
fi-kbl-r total:285 pass:258 dwarn:0 dfail:0 fail:0 skip:27 time:510s
fi-pnv-d510 total:285 pass:219 dwarn:1 dfail:0 fail:0 skip:65 time:659s
fi-skl-6260u total:285 pass:265 dwarn:0 dfail:0 fail:0 skip:20 time:443s
fi-skl-6600u total:285 pass:258 dwarn:0 dfail:0 fail:0 skip:27 time:530s
fi-skl-6700k2 total:285 pass:261 dwarn:0 dfail:0 fail:0 skip:24 time:503s
fi-skl-6770hq total:285 pass:265 dwarn:0 dfail:0 fail:0 skip:20 time:495s
fi-skl-guc total:285 pass:257 dwarn:0 dfail:0 fail:0 skip:28 time:426s
fi-skl-gvtdvm total:285 pass:262 dwarn:0 dfail:0 fail:0 skip:23 time:446s
fi-snb-2520m total:285 pass:245 dwarn:0 dfail:0 fail:0 skip:40 time:562s
fi-snb-2600 total:285 pass:245 dwarn:0 dfail:0 fail:0 skip:40 time:400s
Blacklisted hosts:
fi-cnl-psr total:285 pass:256 dwarn:3 dfail:0 fail:0 skip:26 time:520s
fi-glk-j4005 total:285 pass:256 dwarn:0 dfail:0 fail:0 skip:29 time:487s
c46052cde6a50c5459e00791ffc4d5aa1ec58a9e drm-tip: 2018y-03m-30d-18h-56m-26s UTC integration manifest
1a818c8dc867 drm/i915: Fix reading downstream dev count
d18c7aafdc2b drm/i915: Check hdcp key loadability
a80c7a7aa64c drm/i915: Read Vprime thrice incase of mismatch
0b223e11bf19 drm/i915: Read HDCP R0 thrice in case of mismatch
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8561/issues.html
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^ permalink raw reply [flat|nested] 25+ messages in thread
* ✓ Fi.CI.IGT: success for HDCP1.4 fixes (rev4)
2018-04-02 10:10 [PATCH v3 0/4] HDCP1.4 fixes Ramalingam C
` (4 preceding siblings ...)
2018-04-02 10:40 ` ✓ Fi.CI.BAT: success for HDCP1.4 fixes (rev4) Patchwork
@ 2018-04-02 11:34 ` Patchwork
2018-04-02 12:22 ` ✓ Fi.CI.BAT: success for HDCP1.4 fixes (rev5) Patchwork
` (7 subsequent siblings)
13 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2018-04-02 11:34 UTC (permalink / raw)
To: Ramalingam C; +Cc: intel-gfx
== Series Details ==
Series: HDCP1.4 fixes (rev4)
URL : https://patchwork.freedesktop.org/series/38978/
State : success
== Summary ==
---- Possible new issues:
Test kms_cursor_crc:
Subgroup cursor-64x64-suspend:
dmesg-warn -> PASS (shard-snb)
---- Known issues:
Test gem_softpin:
Subgroup noreloc-s3:
incomplete -> PASS (shard-hsw) fdo#103540
Test kms_flip:
Subgroup 2x-flip-vs-expired-vblank-interruptible:
pass -> FAIL (shard-hsw) fdo#102887
Subgroup 2x-plain-flip-fb-recreate:
pass -> FAIL (shard-hsw) fdo#100368
Subgroup modeset-vs-vblank-race-interruptible:
pass -> FAIL (shard-hsw) fdo#103060 +1
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-primscrn-shrfb-msflip-blt:
dmesg-fail -> PASS (shard-apl) fdo#104727
fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#104727 https://bugs.freedesktop.org/show_bug.cgi?id=104727
shard-apl total:3495 pass:1831 dwarn:1 dfail:0 fail:7 skip:1655 time:12874s
shard-hsw total:3495 pass:1779 dwarn:1 dfail:0 fail:5 skip:1709 time:11518s
shard-snb total:3495 pass:1374 dwarn:1 dfail:0 fail:3 skip:2117 time:7034s
Blacklisted hosts:
shard-kbl total:3477 pass:1937 dwarn:1 dfail:0 fail:10 skip:1528 time:9033s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8561/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v4 1/4] drm/i915: Read HDCP R0 thrice in case of mismatch
2018-04-02 10:10 ` [PATCH v3 1/4] drm/i915: Read HDCP R0 thrice in case of mismatch Ramalingam C
@ 2018-04-02 11:50 ` Ramalingam C
2018-04-02 13:49 ` Sean Paul
0 siblings, 1 reply; 25+ messages in thread
From: Ramalingam C @ 2018-04-02 11:50 UTC (permalink / raw)
To: intel-gfx, dri-devel, seanpaul, ville.syrjala
As per DP spec when R0 mismatch is detected, HDCP source supported
re-read the R0 atleast twice.
And For HDMI and DP minimum wait required for the R0 availability is
100mSec. So this patch changes the wait time to 100mSec but retries
twice with the time interval of 100mSec for each attempt.
This patch is needed for DP HDCP1.4 CTS Test: 1A-06.
v2:
No Change
v3:
Comment on R0 retry is moved closer to the code[Seanpaul]
v4:
Removing unwanted noise introduced in v3.
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
---
drivers/gpu/drm/i915/intel_hdcp.c | 27 +++++++++++++++++++--------
1 file changed, 19 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_hdcp.c b/drivers/gpu/drm/i915/intel_hdcp.c
index 14ca5d3057a7..f2cf2e3acd3c 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -506,15 +506,26 @@ static int intel_hdcp_auth(struct intel_digital_port *intel_dig_port,
*/
wait_remaining_ms_from_jiffies(r0_prime_gen_start, 300);
- ri.reg = 0;
- ret = shim->read_ri_prime(intel_dig_port, ri.shim);
- if (ret)
- return ret;
- I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg);
+ tries = 3;
- /* Wait for Ri prime match */
- if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
- (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
+ /*
+ * DP HDCP Spec mandates the two more reattempt to read R0, incase
+ * of R0 mismatch.
+ */
+ for (i = 0; i < tries; i++) {
+ ri.reg = 0;
+ ret = shim->read_ri_prime(intel_dig_port, ri.shim);
+ if (ret)
+ return ret;
+ I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg);
+
+ /* Wait for Ri prime match */
+ if (!wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
+ (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1))
+ break;
+ }
+
+ if (i == tries) {
DRM_ERROR("Timed out waiting for Ri prime match (%x)\n",
I915_READ(PORT_HDCP_STATUS(port)));
return -ETIMEDOUT;
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread
* ✓ Fi.CI.BAT: success for HDCP1.4 fixes (rev5)
2018-04-02 10:10 [PATCH v3 0/4] HDCP1.4 fixes Ramalingam C
` (5 preceding siblings ...)
2018-04-02 11:34 ` ✓ Fi.CI.IGT: " Patchwork
@ 2018-04-02 12:22 ` Patchwork
2018-04-02 13:06 ` ✗ Fi.CI.IGT: failure " Patchwork
` (6 subsequent siblings)
13 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2018-04-02 12:22 UTC (permalink / raw)
To: Ramalingam C; +Cc: intel-gfx
== Series Details ==
Series: HDCP1.4 fixes (rev5)
URL : https://patchwork.freedesktop.org/series/38978/
State : success
== Summary ==
Series 38978v5 HDCP1.4 fixes
https://patchwork.freedesktop.org/api/1.0/series/38978/revisions/5/mbox/
---- Known issues:
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass -> INCOMPLETE (fi-snb-2520m) fdo#103713
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fi-bdw-5557u total:285 pass:264 dwarn:0 dfail:0 fail:0 skip:21 time:433s
fi-bdw-gvtdvm total:285 pass:261 dwarn:0 dfail:0 fail:0 skip:24 time:452s
fi-blb-e6850 total:285 pass:220 dwarn:1 dfail:0 fail:0 skip:64 time:387s
fi-bsw-n3050 total:285 pass:239 dwarn:0 dfail:0 fail:0 skip:46 time:535s
fi-bwr-2160 total:285 pass:180 dwarn:0 dfail:0 fail:0 skip:105 time:295s
fi-bxt-dsi total:285 pass:255 dwarn:0 dfail:0 fail:0 skip:30 time:511s
fi-bxt-j4205 total:285 pass:256 dwarn:0 dfail:0 fail:0 skip:29 time:509s
fi-byt-j1900 total:285 pass:250 dwarn:0 dfail:0 fail:0 skip:35 time:518s
fi-byt-n2820 total:285 pass:246 dwarn:0 dfail:0 fail:0 skip:39 time:506s
fi-cfl-8700k total:285 pass:257 dwarn:0 dfail:0 fail:0 skip:28 time:406s
fi-cfl-s3 total:285 pass:259 dwarn:0 dfail:0 fail:0 skip:26 time:560s
fi-cfl-u total:285 pass:259 dwarn:0 dfail:0 fail:0 skip:26 time:512s
fi-cnl-y3 total:285 pass:259 dwarn:0 dfail:0 fail:0 skip:26 time:587s
fi-elk-e7500 total:285 pass:225 dwarn:1 dfail:0 fail:0 skip:59 time:422s
fi-gdg-551 total:285 pass:176 dwarn:0 dfail:0 fail:1 skip:108 time:317s
fi-glk-1 total:285 pass:257 dwarn:0 dfail:0 fail:0 skip:28 time:537s
fi-hsw-4770 total:285 pass:258 dwarn:0 dfail:0 fail:0 skip:27 time:404s
fi-ilk-650 total:285 pass:225 dwarn:0 dfail:0 fail:0 skip:60 time:420s
fi-ivb-3520m total:285 pass:256 dwarn:0 dfail:0 fail:0 skip:29 time:458s
fi-ivb-3770 total:285 pass:252 dwarn:0 dfail:0 fail:0 skip:33 time:429s
fi-kbl-7500u total:285 pass:260 dwarn:1 dfail:0 fail:0 skip:24 time:479s
fi-kbl-7567u total:285 pass:265 dwarn:0 dfail:0 fail:0 skip:20 time:465s
fi-kbl-r total:285 pass:258 dwarn:0 dfail:0 fail:0 skip:27 time:508s
fi-pnv-d510 total:285 pass:219 dwarn:1 dfail:0 fail:0 skip:65 time:657s
fi-skl-6260u total:285 pass:265 dwarn:0 dfail:0 fail:0 skip:20 time:443s
fi-skl-6600u total:285 pass:258 dwarn:0 dfail:0 fail:0 skip:27 time:530s
fi-skl-6700k2 total:285 pass:261 dwarn:0 dfail:0 fail:0 skip:24 time:502s
fi-skl-6770hq total:285 pass:265 dwarn:0 dfail:0 fail:0 skip:20 time:508s
fi-skl-guc total:285 pass:257 dwarn:0 dfail:0 fail:0 skip:28 time:434s
fi-skl-gvtdvm total:285 pass:262 dwarn:0 dfail:0 fail:0 skip:23 time:453s
fi-snb-2520m total:242 pass:208 dwarn:0 dfail:0 fail:0 skip:33
fi-snb-2600 total:285 pass:245 dwarn:0 dfail:0 fail:0 skip:40 time:399s
Blacklisted hosts:
fi-cnl-psr total:285 pass:256 dwarn:3 dfail:0 fail:0 skip:26 time:531s
fi-glk-j4005 total:285 pass:256 dwarn:0 dfail:0 fail:0 skip:29 time:486s
c46052cde6a50c5459e00791ffc4d5aa1ec58a9e drm-tip: 2018y-03m-30d-18h-56m-26s UTC integration manifest
c90312327145 drm/i915: Fix reading downstream dev count
376de82ef8ea drm/i915: Check hdcp key loadability
7f0a75907ccf drm/i915: Read Vprime thrice incase of mismatch
1386dd18899d drm/i915: Read HDCP R0 thrice in case of mismatch
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8562/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* ✗ Fi.CI.IGT: failure for HDCP1.4 fixes (rev5)
2018-04-02 10:10 [PATCH v3 0/4] HDCP1.4 fixes Ramalingam C
` (6 preceding siblings ...)
2018-04-02 12:22 ` ✓ Fi.CI.BAT: success for HDCP1.4 fixes (rev5) Patchwork
@ 2018-04-02 13:06 ` Patchwork
2018-04-03 17:35 ` ✓ Fi.CI.BAT: success " Patchwork
` (5 subsequent siblings)
13 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2018-04-02 13:06 UTC (permalink / raw)
To: Ramalingam C; +Cc: intel-gfx
== Series Details ==
Series: HDCP1.4 fixes (rev5)
URL : https://patchwork.freedesktop.org/series/38978/
State : failure
== Summary ==
---- Possible new issues:
Test drv_module_reload:
Subgroup basic-no-display:
pass -> INCOMPLETE (shard-snb)
Test kms_cursor_crc:
Subgroup cursor-64x64-suspend:
dmesg-warn -> PASS (shard-snb)
---- Known issues:
Test gem_softpin:
Subgroup noreloc-s3:
incomplete -> PASS (shard-hsw) fdo#103540
Test kms_flip:
Subgroup 2x-flip-vs-expired-vblank:
pass -> FAIL (shard-hsw) fdo#102887
Subgroup 2x-plain-flip-fb-recreate-interruptible:
pass -> FAIL (shard-hsw) fdo#100368 +1
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-primscrn-shrfb-msflip-blt:
dmesg-fail -> PASS (shard-apl) fdo#104727
Test kms_rotation_crc:
Subgroup primary-rotation-90:
pass -> FAIL (shard-apl) fdo#103925
fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#104727 https://bugs.freedesktop.org/show_bug.cgi?id=104727
fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925
shard-apl total:3495 pass:1830 dwarn:1 dfail:0 fail:8 skip:1655 time:12842s
shard-hsw total:3495 pass:1780 dwarn:1 dfail:0 fail:4 skip:1709 time:11477s
shard-snb total:3399 pass:1331 dwarn:1 dfail:0 fail:3 skip:2063 time:6920s
Blacklisted hosts:
shard-kbl total:3495 pass:1948 dwarn:12 dfail:1 fail:6 skip:1528 time:9208s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8562/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v4 1/4] drm/i915: Read HDCP R0 thrice in case of mismatch
2018-04-02 11:50 ` [PATCH v4 " Ramalingam C
@ 2018-04-02 13:49 ` Sean Paul
0 siblings, 0 replies; 25+ messages in thread
From: Sean Paul @ 2018-04-02 13:49 UTC (permalink / raw)
To: Ramalingam C; +Cc: intel-gfx, dri-devel
On Mon, Apr 02, 2018 at 05:20:22PM +0530, Ramalingam C wrote:
> As per DP spec when R0 mismatch is detected, HDCP source supported
> re-read the R0 atleast twice.
>
> And For HDMI and DP minimum wait required for the R0 availability is
> 100mSec. So this patch changes the wait time to 100mSec but retries
> twice with the time interval of 100mSec for each attempt.
>
> This patch is needed for DP HDCP1.4 CTS Test: 1A-06.
>
> v2:
> No Change
> v3:
> Comment on R0 retry is moved closer to the code[Seanpaul]
> v4:
> Removing unwanted noise introduced in v3.
>
> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
> ---
> drivers/gpu/drm/i915/intel_hdcp.c | 27 +++++++++++++++++++--------
> 1 file changed, 19 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_hdcp.c b/drivers/gpu/drm/i915/intel_hdcp.c
> index 14ca5d3057a7..f2cf2e3acd3c 100644
> --- a/drivers/gpu/drm/i915/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/intel_hdcp.c
> @@ -506,15 +506,26 @@ static int intel_hdcp_auth(struct intel_digital_port *intel_dig_port,
> */
> wait_remaining_ms_from_jiffies(r0_prime_gen_start, 300);
>
> - ri.reg = 0;
> - ret = shim->read_ri_prime(intel_dig_port, ri.shim);
> - if (ret)
> - return ret;
> - I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg);
> + tries = 3;
>
> - /* Wait for Ri prime match */
> - if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
> - (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
> + /*
> + * DP HDCP Spec mandates the two more reattempt to read R0, incase
> + * of R0 mismatch.
> + */
> + for (i = 0; i < tries; i++) {
> + ri.reg = 0;
> + ret = shim->read_ri_prime(intel_dig_port, ri.shim);
> + if (ret)
> + return ret;
> + I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg);
> +
> + /* Wait for Ri prime match */
> + if (!wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
> + (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1))
> + break;
> + }
> +
> + if (i == tries) {
> DRM_ERROR("Timed out waiting for Ri prime match (%x)\n",
> I915_READ(PORT_HDCP_STATUS(port)));
> return -ETIMEDOUT;
> --
> 2.7.4
>
--
Sean Paul, Software Engineer, Google / Chromium OS
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 2/4] drm/i915: Read Vprime thrice incase of mismatch
2018-04-02 10:10 ` [PATCH v3 2/4] drm/i915: Read Vprime thrice incase " Ramalingam C
@ 2018-04-02 13:50 ` Sean Paul
0 siblings, 0 replies; 25+ messages in thread
From: Sean Paul @ 2018-04-02 13:50 UTC (permalink / raw)
To: Ramalingam C; +Cc: intel-gfx, dri-devel, rodrigo.vivi
On Mon, Apr 02, 2018 at 03:40:32PM +0530, Ramalingam C wrote:
> In case of V prime mismatch, DP HDCP spec mandates the re-read of
> Vprime atleast twice.
>
> This patch needed for DP HDCP1.4 CTS Test: 1B-05.
>
> v2:
> Moved the V' validation into a function for retry. [Sean Paul]
> v3:
> Removed Inline keyword and DRM_DEBUG_KMS are used [Sean Paul]
>
> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
> ---
> drivers/gpu/drm/i915/intel_hdcp.c | 112 ++++++++++++++++++++++++--------------
> 1 file changed, 70 insertions(+), 42 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_hdcp.c b/drivers/gpu/drm/i915/intel_hdcp.c
> index 838c8cd0f543..e0bc03eee941 100644
> --- a/drivers/gpu/drm/i915/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/intel_hdcp.c
> @@ -142,53 +142,17 @@ bool intel_hdcp_is_ksv_valid(u8 *ksv)
> return true;
> }
>
> -/* Implements Part 2 of the HDCP authorization procedure */
> static
> -int intel_hdcp_auth_downstream(struct intel_digital_port *intel_dig_port,
> - const struct intel_hdcp_shim *shim)
> +int intel_hdcp_validate_v_prime(struct intel_digital_port *intel_dig_port,
> + const struct intel_hdcp_shim *shim,
> + u8 *ksv_fifo, u8 num_downstream, u8 *bstatus)
> {
> struct drm_i915_private *dev_priv;
> u32 vprime, sha_text, sha_leftovers, rep_ctl;
> - u8 bstatus[2], num_downstream, *ksv_fifo;
> int ret, i, j, sha_idx;
>
> dev_priv = intel_dig_port->base.base.dev->dev_private;
>
> - ret = intel_hdcp_poll_ksv_fifo(intel_dig_port, shim);
> - if (ret) {
> - DRM_ERROR("KSV list failed to become ready (%d)\n", ret);
> - return ret;
> - }
> -
> - ret = shim->read_bstatus(intel_dig_port, bstatus);
> - if (ret)
> - return ret;
> -
> - if (DRM_HDCP_MAX_DEVICE_EXCEEDED(bstatus[0]) ||
> - DRM_HDCP_MAX_CASCADE_EXCEEDED(bstatus[1])) {
> - DRM_ERROR("Max Topology Limit Exceeded\n");
> - return -EPERM;
> - }
> -
> - /*
> - * When repeater reports 0 device count, HDCP1.4 spec allows disabling
> - * the HDCP encryption. That implies that repeater can't have its own
> - * display. As there is no consumption of encrypted content in the
> - * repeater with 0 downstream devices, we are failing the
> - * authentication.
> - */
> - num_downstream = DRM_HDCP_NUM_DOWNSTREAM(bstatus[0]);
> - if (num_downstream == 0)
> - return -EINVAL;
> -
> - ksv_fifo = kzalloc(num_downstream * DRM_HDCP_KSV_LEN, GFP_KERNEL);
> - if (!ksv_fifo)
> - return -ENOMEM;
> -
> - ret = shim->read_ksv_fifo(intel_dig_port, num_downstream, ksv_fifo);
> - if (ret)
> - return ret;
> -
> /* Process V' values from the receiver */
> for (i = 0; i < DRM_HDCP_V_PRIME_NUM_PARTS; i++) {
> ret = shim->read_v_prime_part(intel_dig_port, i, &vprime);
> @@ -353,7 +317,8 @@ int intel_hdcp_auth_downstream(struct intel_digital_port *intel_dig_port,
> return ret;
> sha_idx += sizeof(sha_text);
> } else {
> - DRM_ERROR("Invalid number of leftovers %d\n", sha_leftovers);
> + DRM_DEBUG_KMS("Invalid number of leftovers %d\n",
> + sha_leftovers);
> return -EINVAL;
> }
>
> @@ -381,14 +346,77 @@ int intel_hdcp_auth_downstream(struct intel_digital_port *intel_dig_port,
> if (intel_wait_for_register(dev_priv, HDCP_REP_CTL,
> HDCP_SHA1_COMPLETE,
> HDCP_SHA1_COMPLETE, 1)) {
> - DRM_ERROR("Timed out waiting for SHA1 complete\n");
> + DRM_DEBUG_KMS("Timed out waiting for SHA1 complete\n");
> return -ETIMEDOUT;
> }
> if (!(I915_READ(HDCP_REP_CTL) & HDCP_SHA1_V_MATCH)) {
> - DRM_ERROR("SHA-1 mismatch, HDCP failed\n");
> + DRM_DEBUG_KMS("SHA-1 mismatch, HDCP failed\n");
> return -ENXIO;
> }
>
> + return 0;
> +}
> +
> +/* Implements Part 2 of the HDCP authorization procedure */
> +static
> +int intel_hdcp_auth_downstream(struct intel_digital_port *intel_dig_port,
> + const struct intel_hdcp_shim *shim)
> +{
> + u8 bstatus[2], num_downstream, *ksv_fifo;
> + int ret, i, tries = 3;
> +
> + ret = intel_hdcp_poll_ksv_fifo(intel_dig_port, shim);
> + if (ret) {
> + DRM_ERROR("KSV list failed to become ready (%d)\n", ret);
> + return ret;
> + }
> +
> + ret = shim->read_bstatus(intel_dig_port, bstatus);
> + if (ret)
> + return ret;
> +
> + if (DRM_HDCP_MAX_DEVICE_EXCEEDED(bstatus[0]) ||
> + DRM_HDCP_MAX_CASCADE_EXCEEDED(bstatus[1])) {
> + DRM_ERROR("Max Topology Limit Exceeded\n");
> + return -EPERM;
> + }
> +
> + /*
> + * When repeater reports 0 device count, HDCP1.4 spec allows disabling
> + * the HDCP encryption. That implies that repeater can't have its own
> + * display. As there is no consumption of encrypted content in the
> + * repeater with 0 downstream devices, we are failing the
> + * authentication.
> + */
> + num_downstream = DRM_HDCP_NUM_DOWNSTREAM(bstatus[0]);
> + if (num_downstream == 0)
> + return -EINVAL;
> +
> + ksv_fifo = kzalloc(num_downstream * DRM_HDCP_KSV_LEN, GFP_KERNEL);
> + if (!ksv_fifo)
> + return -ENOMEM;
> +
> + ret = shim->read_ksv_fifo(intel_dig_port, num_downstream, ksv_fifo);
> + if (ret)
> + return ret;
> +
> + /*
> + * When V prime mismatches, DP Spec mandates re-read of
> + * V prime atleast twice.
> + */
> + for (i = 0; i < tries; i++) {
> + ret = intel_hdcp_validate_v_prime(intel_dig_port, shim,
> + ksv_fifo, num_downstream,
> + bstatus);
> + if (!ret)
> + break;
> + }
> +
> + if (i == tries) {
> + DRM_ERROR("V Prime validation failed.(%d)\n", ret);
> + return ret;
> + }
> +
> DRM_DEBUG_KMS("HDCP is enabled (%d downstream devices)\n",
> num_downstream);
> return 0;
> --
> 2.7.4
>
--
Sean Paul, Software Engineer, Google / Chromium OS
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 25+ messages in thread
* ✓ Fi.CI.BAT: success for HDCP1.4 fixes (rev5)
2018-04-02 10:10 [PATCH v3 0/4] HDCP1.4 fixes Ramalingam C
` (7 preceding siblings ...)
2018-04-02 13:06 ` ✗ Fi.CI.IGT: failure " Patchwork
@ 2018-04-03 17:35 ` Patchwork
2018-04-03 19:09 ` ✓ Fi.CI.IGT: " Patchwork
` (4 subsequent siblings)
13 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2018-04-03 17:35 UTC (permalink / raw)
To: Ramalingam C; +Cc: intel-gfx
== Series Details ==
Series: HDCP1.4 fixes (rev5)
URL : https://patchwork.freedesktop.org/series/38978/
State : success
== Summary ==
Series 38978v5 HDCP1.4 fixes
https://patchwork.freedesktop.org/api/1.0/series/38978/revisions/5/mbox/
---- Known issues:
Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
fail -> PASS (fi-gdg-551) fdo#102575
Test kms_pipe_crc_basic:
Subgroup hang-read-crc-pipe-c:
fail -> PASS (fi-skl-6700k2) fdo#103191
fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fi-bdw-5557u total:285 pass:264 dwarn:0 dfail:0 fail:0 skip:21 time:431s
fi-bdw-gvtdvm total:285 pass:261 dwarn:0 dfail:0 fail:0 skip:24 time:444s
fi-blb-e6850 total:285 pass:220 dwarn:1 dfail:0 fail:0 skip:64 time:384s
fi-bsw-n3050 total:285 pass:239 dwarn:0 dfail:0 fail:0 skip:46 time:541s
fi-bwr-2160 total:285 pass:180 dwarn:0 dfail:0 fail:0 skip:105 time:298s
fi-bxt-dsi total:285 pass:255 dwarn:0 dfail:0 fail:0 skip:30 time:515s
fi-bxt-j4205 total:285 pass:256 dwarn:0 dfail:0 fail:0 skip:29 time:514s
fi-byt-j1900 total:285 pass:250 dwarn:0 dfail:0 fail:0 skip:35 time:521s
fi-byt-n2820 total:285 pass:246 dwarn:0 dfail:0 fail:0 skip:39 time:512s
fi-cfl-8700k total:285 pass:257 dwarn:0 dfail:0 fail:0 skip:28 time:408s
fi-cfl-s3 total:285 pass:259 dwarn:0 dfail:0 fail:0 skip:26 time:562s
fi-cfl-u total:285 pass:259 dwarn:0 dfail:0 fail:0 skip:26 time:513s
fi-cnl-y3 total:285 pass:259 dwarn:0 dfail:0 fail:0 skip:26 time:586s
fi-elk-e7500 total:285 pass:225 dwarn:1 dfail:0 fail:0 skip:59 time:421s
fi-gdg-551 total:285 pass:177 dwarn:0 dfail:0 fail:0 skip:108 time:316s
fi-glk-1 total:285 pass:257 dwarn:0 dfail:0 fail:0 skip:28 time:539s
fi-hsw-4770 total:285 pass:258 dwarn:0 dfail:0 fail:0 skip:27 time:405s
fi-ilk-650 total:285 pass:225 dwarn:0 dfail:0 fail:0 skip:60 time:426s
fi-ivb-3520m total:285 pass:256 dwarn:0 dfail:0 fail:0 skip:29 time:478s
fi-ivb-3770 total:285 pass:252 dwarn:0 dfail:0 fail:0 skip:33 time:433s
fi-kbl-7500u total:285 pass:260 dwarn:1 dfail:0 fail:0 skip:24 time:472s
fi-kbl-7567u total:285 pass:265 dwarn:0 dfail:0 fail:0 skip:20 time:464s
fi-kbl-r total:285 pass:258 dwarn:0 dfail:0 fail:0 skip:27 time:510s
fi-pnv-d510 total:285 pass:219 dwarn:1 dfail:0 fail:0 skip:65 time:665s
fi-skl-6260u total:285 pass:265 dwarn:0 dfail:0 fail:0 skip:20 time:442s
fi-skl-6600u total:285 pass:258 dwarn:0 dfail:0 fail:0 skip:27 time:538s
fi-skl-6700k2 total:285 pass:261 dwarn:0 dfail:0 fail:0 skip:24 time:499s
fi-skl-6770hq total:285 pass:265 dwarn:0 dfail:0 fail:0 skip:20 time:496s
fi-skl-guc total:285 pass:257 dwarn:0 dfail:0 fail:0 skip:28 time:430s
fi-skl-gvtdvm total:285 pass:262 dwarn:0 dfail:0 fail:0 skip:23 time:450s
fi-snb-2520m total:285 pass:245 dwarn:0 dfail:0 fail:0 skip:40 time:569s
fi-snb-2600 total:285 pass:245 dwarn:0 dfail:0 fail:0 skip:40 time:412s
Blacklisted hosts:
fi-cnl-psr total:285 pass:255 dwarn:3 dfail:0 fail:1 skip:26 time:517s
fi-glk-j4005 total:285 pass:256 dwarn:0 dfail:0 fail:0 skip:29 time:490s
29940f138482ff38047287ad288cea1fcf1f73b4 drm-tip: 2018y-04m-03d-13h-23m-36s UTC integration manifest
28f776e9d930 drm/i915: Fix reading downstream dev count
8259d0865458 drm/i915: Check hdcp key loadability
37d83a96d5ff drm/i915: Read Vprime thrice incase of mismatch
3db387dec7ec drm/i915: Read HDCP R0 thrice in case of mismatch
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8570/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* ✓ Fi.CI.IGT: success for HDCP1.4 fixes (rev5)
2018-04-02 10:10 [PATCH v3 0/4] HDCP1.4 fixes Ramalingam C
` (8 preceding siblings ...)
2018-04-03 17:35 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2018-04-03 19:09 ` Patchwork
2018-04-04 19:01 ` ✓ Fi.CI.BAT: success for HDCP1.4 fixes (rev6) Patchwork
` (3 subsequent siblings)
13 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2018-04-03 19:09 UTC (permalink / raw)
To: Ramalingam C; +Cc: intel-gfx
== Series Details ==
Series: HDCP1.4 fixes (rev5)
URL : https://patchwork.freedesktop.org/series/38978/
State : success
== Summary ==
---- Possible new issues:
Test kms_draw_crc:
Subgroup draw-method-xrgb8888-mmap-wc-untiled:
skip -> PASS (shard-snb)
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-indfb-draw-mmap-cpu:
skip -> PASS (shard-snb)
Subgroup fbc-1p-primscrn-spr-indfb-move:
skip -> PASS (shard-snb)
Subgroup fbc-stridechange:
fail -> PASS (shard-snb)
Subgroup fbcpsr-rgb565-draw-blt:
fail -> SKIP (shard-snb)
Subgroup psr-2p-scndscrn-pri-indfb-draw-render:
fail -> SKIP (shard-snb)
Subgroup psr-2p-scndscrn-spr-indfb-onoff:
fail -> SKIP (shard-snb)
Test kms_universal_plane:
Subgroup universal-plane-pipe-a-sanity:
fail -> PASS (shard-snb)
Test prime_vgem:
Subgroup basic-fence-flip:
skip -> PASS (shard-snb)
---- Known issues:
Test kms_flip:
Subgroup plain-flip-fb-recreate-interruptible:
fail -> PASS (shard-hsw) fdo#100368
Test kms_frontbuffer_tracking:
Subgroup fbcpsr-2p-primscrn-shrfb-pgflip-blt:
fail -> SKIP (shard-snb) fdo#103167 +1
Test kms_mmap_write_crc:
dmesg-warn -> PASS (shard-hsw) fdo#103286
Test kms_plane_multiple:
Subgroup atomic-pipe-a-tiling-x:
pass -> FAIL (shard-snb) fdo#103166
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103286 https://bugs.freedesktop.org/show_bug.cgi?id=103286
fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
shard-apl total:3498 pass:1834 dwarn:1 dfail:0 fail:7 skip:1655 time:12960s
shard-hsw total:3498 pass:1785 dwarn:1 dfail:0 fail:1 skip:1710 time:11534s
shard-snb total:3498 pass:1376 dwarn:1 dfail:0 fail:3 skip:2118 time:7086s
Blacklisted hosts:
shard-kbl total:3443 pass:1929 dwarn:1 dfail:1 fail:7 skip:1504 time:9124s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8570/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v4] drm: Fix downstream dev count read
2018-04-02 10:10 ` [PATCH v3 4/4] drm/i915: Fix reading downstream dev count Ramalingam C
@ 2018-04-04 18:27 ` Ramalingam C
2018-04-04 19:07 ` Rodrigo Vivi
2018-04-05 12:03 ` [PATCH v5] drm: Fix HDCP " Ramalingam C
0 siblings, 2 replies; 25+ messages in thread
From: Ramalingam C @ 2018-04-04 18:27 UTC (permalink / raw)
To: rodrigo.vivi, seanpaul, intel-gfx, dri-devel
In both HDMI and DP, device count is represented by 6:0 bits of a
register(BInfo/Bstatus)
So macro for bitmasking the device_count is fixed(0x3F->0x7F).
v3:
Retained the Rb-ed.
v4:
%s/drm\/i915/drm [rodrigo]
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
cc: Sean Paul <seanpaul@chromium.org>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
---
include/drm/drm_hdcp.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h
index 562fa7df2637..98e63d870139 100644
--- a/include/drm/drm_hdcp.h
+++ b/include/drm/drm_hdcp.h
@@ -19,7 +19,7 @@
#define DRM_HDCP_RI_LEN 2
#define DRM_HDCP_V_PRIME_PART_LEN 4
#define DRM_HDCP_V_PRIME_NUM_PARTS 5
-#define DRM_HDCP_NUM_DOWNSTREAM(x) (x & 0x3f)
+#define DRM_HDCP_NUM_DOWNSTREAM(x) (x & 0x7f)
#define DRM_HDCP_MAX_CASCADE_EXCEEDED(x) (x & BIT(3))
#define DRM_HDCP_MAX_DEVICE_EXCEEDED(x) (x & BIT(7))
--
2.7.4
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 25+ messages in thread
* ✓ Fi.CI.BAT: success for HDCP1.4 fixes (rev6)
2018-04-02 10:10 [PATCH v3 0/4] HDCP1.4 fixes Ramalingam C
` (9 preceding siblings ...)
2018-04-03 19:09 ` ✓ Fi.CI.IGT: " Patchwork
@ 2018-04-04 19:01 ` Patchwork
2018-04-04 21:15 ` ✓ Fi.CI.IGT: " Patchwork
` (2 subsequent siblings)
13 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2018-04-04 19:01 UTC (permalink / raw)
To: Ramalingam C; +Cc: intel-gfx
== Series Details ==
Series: HDCP1.4 fixes (rev6)
URL : https://patchwork.freedesktop.org/series/38978/
State : success
== Summary ==
Series 38978v6 HDCP1.4 fixes
https://patchwork.freedesktop.org/api/1.0/series/38978/revisions/6/mbox/
---- Known issues:
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass -> INCOMPLETE (fi-snb-2520m) fdo#103713
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fi-bdw-5557u total:285 pass:264 dwarn:0 dfail:0 fail:0 skip:21 time:430s
fi-bdw-gvtdvm total:285 pass:261 dwarn:0 dfail:0 fail:0 skip:24 time:442s
fi-blb-e6850 total:285 pass:220 dwarn:1 dfail:0 fail:0 skip:64 time:380s
fi-bsw-n3050 total:285 pass:239 dwarn:0 dfail:0 fail:0 skip:46 time:536s
fi-bwr-2160 total:285 pass:180 dwarn:0 dfail:0 fail:0 skip:105 time:298s
fi-bxt-dsi total:285 pass:255 dwarn:0 dfail:0 fail:0 skip:30 time:517s
fi-bxt-j4205 total:285 pass:256 dwarn:0 dfail:0 fail:0 skip:29 time:512s
fi-byt-j1900 total:285 pass:250 dwarn:0 dfail:0 fail:0 skip:35 time:520s
fi-byt-n2820 total:285 pass:246 dwarn:0 dfail:0 fail:0 skip:39 time:507s
fi-cfl-8700k total:285 pass:257 dwarn:0 dfail:0 fail:0 skip:28 time:408s
fi-cfl-s3 total:285 pass:259 dwarn:0 dfail:0 fail:0 skip:26 time:558s
fi-cfl-u total:285 pass:259 dwarn:0 dfail:0 fail:0 skip:26 time:508s
fi-cnl-y3 total:285 pass:259 dwarn:0 dfail:0 fail:0 skip:26 time:594s
fi-elk-e7500 total:285 pass:225 dwarn:1 dfail:0 fail:0 skip:59 time:424s
fi-gdg-551 total:285 pass:177 dwarn:0 dfail:0 fail:0 skip:108 time:319s
fi-glk-1 total:285 pass:257 dwarn:0 dfail:0 fail:0 skip:28 time:539s
fi-glk-j4005 total:285 pass:256 dwarn:0 dfail:0 fail:0 skip:29 time:490s
fi-hsw-4770 total:285 pass:258 dwarn:0 dfail:0 fail:0 skip:27 time:405s
fi-ilk-650 total:285 pass:225 dwarn:0 dfail:0 fail:0 skip:60 time:421s
fi-ivb-3520m total:285 pass:256 dwarn:0 dfail:0 fail:0 skip:29 time:469s
fi-ivb-3770 total:285 pass:252 dwarn:0 dfail:0 fail:0 skip:33 time:431s
fi-kbl-7500u total:285 pass:260 dwarn:1 dfail:0 fail:0 skip:24 time:469s
fi-kbl-7567u total:285 pass:265 dwarn:0 dfail:0 fail:0 skip:20 time:466s
fi-kbl-r total:285 pass:258 dwarn:0 dfail:0 fail:0 skip:27 time:511s
fi-skl-6260u total:285 pass:265 dwarn:0 dfail:0 fail:0 skip:20 time:438s
fi-skl-6600u total:285 pass:258 dwarn:0 dfail:0 fail:0 skip:27 time:536s
fi-skl-6700k2 total:285 pass:261 dwarn:0 dfail:0 fail:0 skip:24 time:508s
fi-skl-6770hq total:285 pass:265 dwarn:0 dfail:0 fail:0 skip:20 time:500s
fi-skl-guc total:285 pass:257 dwarn:0 dfail:0 fail:0 skip:28 time:431s
fi-skl-gvtdvm total:285 pass:262 dwarn:0 dfail:0 fail:0 skip:23 time:446s
fi-snb-2520m total:242 pass:208 dwarn:0 dfail:0 fail:0 skip:33
fi-snb-2600 total:285 pass:245 dwarn:0 dfail:0 fail:0 skip:40 time:400s
Blacklisted hosts:
fi-cnl-psr total:285 pass:256 dwarn:3 dfail:0 fail:0 skip:26 time:527s
8a51883453a91beb0492790d03cd2183eb923c38 drm-tip: 2018y-04m-04d-14h-43m-05s UTC integration manifest
be7559a88022 drm: Fix downstream dev count read
8fbba7c290e6 drm/i915: Check hdcp key loadability
cd233eb847df drm/i915: Read Vprime thrice incase of mismatch
34226dc9ea0d drm/i915: Read HDCP R0 thrice in case of mismatch
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8580/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v4] drm: Fix downstream dev count read
2018-04-04 18:27 ` [PATCH v4] drm: Fix downstream dev count read Ramalingam C
@ 2018-04-04 19:07 ` Rodrigo Vivi
2018-04-04 19:23 ` Sean Paul
2018-04-05 12:03 ` [PATCH v5] drm: Fix HDCP " Ramalingam C
1 sibling, 1 reply; 25+ messages in thread
From: Rodrigo Vivi @ 2018-04-04 19:07 UTC (permalink / raw)
To: Ramalingam C; +Cc: intel-gfx, dri-devel
On Wed, Apr 04, 2018 at 11:57:42PM +0530, Ramalingam C wrote:
> In both HDMI and DP, device count is represented by 6:0 bits of a
> register(BInfo/Bstatus)
>
> So macro for bitmasking the device_count is fixed(0x3F->0x7F).
>
> v3:
> Retained the Rb-ed.
> v4:
> %s/drm\/i915/drm [rodrigo]
>
Shouldn't this patch have a "Fixes:" ?
cc: stable?
I pushed first 3 patches on the series to dinq.
I believe this one here could be there with Dave's ack or
maybe on drm-misc-fixes?
> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> cc: Sean Paul <seanpaul@chromium.org>
> Reviewed-by: Sean Paul <seanpaul@chromium.org>
> ---
> include/drm/drm_hdcp.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h
> index 562fa7df2637..98e63d870139 100644
> --- a/include/drm/drm_hdcp.h
> +++ b/include/drm/drm_hdcp.h
> @@ -19,7 +19,7 @@
> #define DRM_HDCP_RI_LEN 2
> #define DRM_HDCP_V_PRIME_PART_LEN 4
> #define DRM_HDCP_V_PRIME_NUM_PARTS 5
> -#define DRM_HDCP_NUM_DOWNSTREAM(x) (x & 0x3f)
> +#define DRM_HDCP_NUM_DOWNSTREAM(x) (x & 0x7f)
> #define DRM_HDCP_MAX_CASCADE_EXCEEDED(x) (x & BIT(3))
> #define DRM_HDCP_MAX_DEVICE_EXCEEDED(x) (x & BIT(7))
>
> --
> 2.7.4
>
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v4] drm: Fix downstream dev count read
2018-04-04 19:07 ` Rodrigo Vivi
@ 2018-04-04 19:23 ` Sean Paul
2018-04-04 22:34 ` Ramalingam C
0 siblings, 1 reply; 25+ messages in thread
From: Sean Paul @ 2018-04-04 19:23 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx, dri-devel
On Wed, Apr 04, 2018 at 12:07:41PM -0700, Rodrigo Vivi wrote:
> On Wed, Apr 04, 2018 at 11:57:42PM +0530, Ramalingam C wrote:
> > In both HDMI and DP, device count is represented by 6:0 bits of a
> > register(BInfo/Bstatus)
> >
> > So macro for bitmasking the device_count is fixed(0x3F->0x7F).
> >
> > v3:
> > Retained the Rb-ed.
> > v4:
> > %s/drm\/i915/drm [rodrigo]
> >
>
> Shouldn't this patch have a "Fixes:" ?
Yes, I think that'd be good.
> cc: stable?
It couldn't hurt.
>
> I pushed first 3 patches on the series to dinq.
> I believe this one here could be there with Dave's ack or
> maybe on drm-misc-fixes?
Meh. The severity of this isn't too big, given that I doubt people care _too_
much about plugging in more than 64 HDCP-enabled devices. If you want to drop it
in -misc-next-fixes, I can send it out next week.
While we're asking for a respin, could we add HDCP somewhere in the subject?
Sean
>
> > Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> > cc: Sean Paul <seanpaul@chromium.org>
> > Reviewed-by: Sean Paul <seanpaul@chromium.org>
> > ---
> > include/drm/drm_hdcp.h | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h
> > index 562fa7df2637..98e63d870139 100644
> > --- a/include/drm/drm_hdcp.h
> > +++ b/include/drm/drm_hdcp.h
> > @@ -19,7 +19,7 @@
> > #define DRM_HDCP_RI_LEN 2
> > #define DRM_HDCP_V_PRIME_PART_LEN 4
> > #define DRM_HDCP_V_PRIME_NUM_PARTS 5
> > -#define DRM_HDCP_NUM_DOWNSTREAM(x) (x & 0x3f)
> > +#define DRM_HDCP_NUM_DOWNSTREAM(x) (x & 0x7f)
> > #define DRM_HDCP_MAX_CASCADE_EXCEEDED(x) (x & BIT(3))
> > #define DRM_HDCP_MAX_DEVICE_EXCEEDED(x) (x & BIT(7))
> >
> > --
> > 2.7.4
> >
--
Sean Paul, Software Engineer, Google / Chromium OS
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* ✓ Fi.CI.IGT: success for HDCP1.4 fixes (rev6)
2018-04-02 10:10 [PATCH v3 0/4] HDCP1.4 fixes Ramalingam C
` (10 preceding siblings ...)
2018-04-04 19:01 ` ✓ Fi.CI.BAT: success for HDCP1.4 fixes (rev6) Patchwork
@ 2018-04-04 21:15 ` Patchwork
2018-04-05 12:45 ` ✓ Fi.CI.BAT: success for HDCP1.4 fixes (rev7) Patchwork
2018-04-05 14:18 ` ✓ Fi.CI.IGT: " Patchwork
13 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2018-04-04 21:15 UTC (permalink / raw)
To: Ramalingam C; +Cc: intel-gfx
== Series Details ==
Series: HDCP1.4 fixes (rev6)
URL : https://patchwork.freedesktop.org/series/38978/
State : success
== Summary ==
---- Known issues:
Test drv_selftest:
Subgroup live_gtt:
incomplete -> PASS (shard-apl) fdo#103927
Test kms_flip:
Subgroup plain-flip-ts-check-interruptible:
pass -> FAIL (shard-hsw) fdo#100368
Test kms_sysfs_edid_timing:
pass -> WARN (shard-apl) fdo#100047
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047
shard-apl total:3498 pass:1834 dwarn:1 dfail:0 fail:7 skip:1655 time:12876s
shard-hsw total:3498 pass:1784 dwarn:1 dfail:0 fail:2 skip:1710 time:11490s
shard-snb total:3498 pass:1377 dwarn:1 dfail:0 fail:2 skip:2118 time:7095s
Blacklisted hosts:
shard-kbl total:3498 pass:1961 dwarn:1 dfail:0 fail:7 skip:1529 time:9232s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8580/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v4] drm: Fix downstream dev count read
2018-04-04 19:23 ` Sean Paul
@ 2018-04-04 22:34 ` Ramalingam C
2018-04-05 23:56 ` Rodrigo Vivi
0 siblings, 1 reply; 25+ messages in thread
From: Ramalingam C @ 2018-04-04 22:34 UTC (permalink / raw)
To: Sean Paul, Rodrigo Vivi; +Cc: intel-gfx, dri-devel
On Thursday 05 April 2018 12:53 AM, Sean Paul wrote:
> On Wed, Apr 04, 2018 at 12:07:41PM -0700, Rodrigo Vivi wrote:
>> On Wed, Apr 04, 2018 at 11:57:42PM +0530, Ramalingam C wrote:
>>> In both HDMI and DP, device count is represented by 6:0 bits of a
>>> register(BInfo/Bstatus)
>>>
>>> So macro for bitmasking the device_count is fixed(0x3F->0x7F).
>>>
>>> v3:
>>> Retained the Rb-ed.
>>> v4:
>>> %s/drm\/i915/drm [rodrigo]
>>>
>> Shouldn't this patch have a "Fixes:" ?
> Yes, I think that'd be good.
Will add
Fixes: 495eb7f877ab drm: Add some HDCP related #defines
>
>> cc: stable?
> It couldn't hurt.
Sorry what is needed here?
>
>> I pushed first 3 patches on the series to dinq.
>> I believe this one here could be there with Dave's ack or
>> maybe on drm-misc-fixes?
> Meh. The severity of this isn't too big, given that I doubt people care _too_
> much about plugging in more than 64 HDCP-enabled devices. If you want to drop it
> in -misc-next-fixes, I can send it out next week.
>
> While we're asking for a respin, could we add HDCP somewhere in the subject?
will change the sub to
drm: Fix HDCP downstream dev count read
--Ram
>
> Sean
>
>>> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
>>> cc: Sean Paul <seanpaul@chromium.org>
>>> Reviewed-by: Sean Paul <seanpaul@chromium.org>
>>> ---
>>> include/drm/drm_hdcp.h | 2 +-
>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h
>>> index 562fa7df2637..98e63d870139 100644
>>> --- a/include/drm/drm_hdcp.h
>>> +++ b/include/drm/drm_hdcp.h
>>> @@ -19,7 +19,7 @@
>>> #define DRM_HDCP_RI_LEN 2
>>> #define DRM_HDCP_V_PRIME_PART_LEN 4
>>> #define DRM_HDCP_V_PRIME_NUM_PARTS 5
>>> -#define DRM_HDCP_NUM_DOWNSTREAM(x) (x & 0x3f)
>>> +#define DRM_HDCP_NUM_DOWNSTREAM(x) (x & 0x7f)
>>> #define DRM_HDCP_MAX_CASCADE_EXCEEDED(x) (x & BIT(3))
>>> #define DRM_HDCP_MAX_DEVICE_EXCEEDED(x) (x & BIT(7))
>>>
>>> --
>>> 2.7.4
>>>
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^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v5] drm: Fix HDCP downstream dev count read
2018-04-04 18:27 ` [PATCH v4] drm: Fix downstream dev count read Ramalingam C
2018-04-04 19:07 ` Rodrigo Vivi
@ 2018-04-05 12:03 ` Ramalingam C
2018-04-16 16:11 ` Sean Paul
1 sibling, 1 reply; 25+ messages in thread
From: Ramalingam C @ 2018-04-05 12:03 UTC (permalink / raw)
To: rodrigo.vivi, seanpaul, intel-gfx, dri-devel
In both HDMI and DP, device count is represented by 6:0 bits of a
register(BInfo/Bstatus)
So macro for bitmasking the device_count is fixed(0x3F->0x7F).
v3:
Retained the Rb-ed.
v4:
%s/drm\/i915/drm [rodrigo]
v5:
Added "Fixes:" and HDCP keyword in subject [Rodrigo, Sean Paul]
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Fixes: 495eb7f877ab drm: Add some HDCP related #defines
cc: Sean Paul <seanpaul@chromium.org>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
---
include/drm/drm_hdcp.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h
index 562fa7df2637..98e63d870139 100644
--- a/include/drm/drm_hdcp.h
+++ b/include/drm/drm_hdcp.h
@@ -19,7 +19,7 @@
#define DRM_HDCP_RI_LEN 2
#define DRM_HDCP_V_PRIME_PART_LEN 4
#define DRM_HDCP_V_PRIME_NUM_PARTS 5
-#define DRM_HDCP_NUM_DOWNSTREAM(x) (x & 0x3f)
+#define DRM_HDCP_NUM_DOWNSTREAM(x) (x & 0x7f)
#define DRM_HDCP_MAX_CASCADE_EXCEEDED(x) (x & BIT(3))
#define DRM_HDCP_MAX_DEVICE_EXCEEDED(x) (x & BIT(7))
--
2.7.4
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^ permalink raw reply related [flat|nested] 25+ messages in thread
* ✓ Fi.CI.BAT: success for HDCP1.4 fixes (rev7)
2018-04-02 10:10 [PATCH v3 0/4] HDCP1.4 fixes Ramalingam C
` (11 preceding siblings ...)
2018-04-04 21:15 ` ✓ Fi.CI.IGT: " Patchwork
@ 2018-04-05 12:45 ` Patchwork
2018-04-05 14:18 ` ✓ Fi.CI.IGT: " Patchwork
13 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2018-04-05 12:45 UTC (permalink / raw)
To: Ramalingam C; +Cc: intel-gfx
== Series Details ==
Series: HDCP1.4 fixes (rev7)
URL : https://patchwork.freedesktop.org/series/38978/
State : success
== Summary ==
Series 38978v7 HDCP1.4 fixes
https://patchwork.freedesktop.org/api/1.0/series/38978/revisions/7/mbox/
---- Known issues:
Test debugfs_test:
Subgroup read_all_entries:
pass -> INCOMPLETE (fi-snb-2520m) fdo#103713
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-c:
dmesg-warn -> PASS (fi-glk-j4005) fdo#105644
Test prime_vgem:
Subgroup basic-fence-flip:
fail -> PASS (fi-ilk-650) fdo#104008
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#105644 https://bugs.freedesktop.org/show_bug.cgi?id=105644
fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008
fi-bdw-5557u total:285 pass:264 dwarn:0 dfail:0 fail:0 skip:21 time:429s
fi-bdw-gvtdvm total:285 pass:261 dwarn:0 dfail:0 fail:0 skip:24 time:441s
fi-blb-e6850 total:285 pass:220 dwarn:1 dfail:0 fail:0 skip:64 time:383s
fi-bsw-n3050 total:285 pass:239 dwarn:0 dfail:0 fail:0 skip:46 time:543s
fi-bwr-2160 total:285 pass:180 dwarn:0 dfail:0 fail:0 skip:105 time:297s
fi-bxt-dsi total:285 pass:255 dwarn:0 dfail:0 fail:0 skip:30 time:512s
fi-bxt-j4205 total:285 pass:256 dwarn:0 dfail:0 fail:0 skip:29 time:512s
fi-byt-j1900 total:285 pass:250 dwarn:0 dfail:0 fail:0 skip:35 time:520s
fi-byt-n2820 total:285 pass:246 dwarn:0 dfail:0 fail:0 skip:39 time:514s
fi-cfl-8700k total:285 pass:257 dwarn:0 dfail:0 fail:0 skip:28 time:414s
fi-cfl-s3 total:285 pass:259 dwarn:0 dfail:0 fail:0 skip:26 time:560s
fi-cfl-u total:285 pass:259 dwarn:0 dfail:0 fail:0 skip:26 time:510s
fi-cnl-y3 total:285 pass:259 dwarn:0 dfail:0 fail:0 skip:26 time:589s
fi-elk-e7500 total:285 pass:226 dwarn:0 dfail:0 fail:0 skip:59 time:419s
fi-gdg-551 total:285 pass:176 dwarn:0 dfail:0 fail:1 skip:108 time:316s
fi-glk-1 total:285 pass:257 dwarn:0 dfail:0 fail:0 skip:28 time:540s
fi-glk-j4005 total:285 pass:256 dwarn:0 dfail:0 fail:0 skip:29 time:484s
fi-hsw-4770 total:285 pass:258 dwarn:0 dfail:0 fail:0 skip:27 time:405s
fi-ilk-650 total:285 pass:225 dwarn:0 dfail:0 fail:0 skip:60 time:423s
fi-ivb-3520m total:285 pass:256 dwarn:0 dfail:0 fail:0 skip:29 time:464s
fi-ivb-3770 total:285 pass:252 dwarn:0 dfail:0 fail:0 skip:33 time:430s
fi-kbl-7500u total:285 pass:260 dwarn:1 dfail:0 fail:0 skip:24 time:472s
fi-kbl-7567u total:285 pass:265 dwarn:0 dfail:0 fail:0 skip:20 time:462s
fi-kbl-r total:285 pass:258 dwarn:0 dfail:0 fail:0 skip:27 time:513s
fi-pnv-d510 total:285 pass:220 dwarn:1 dfail:0 fail:0 skip:64 time:664s
fi-skl-6260u total:285 pass:265 dwarn:0 dfail:0 fail:0 skip:20 time:443s
fi-skl-6600u total:285 pass:258 dwarn:0 dfail:0 fail:0 skip:27 time:533s
fi-skl-6700k2 total:285 pass:261 dwarn:0 dfail:0 fail:0 skip:24 time:507s
fi-skl-6770hq total:285 pass:265 dwarn:0 dfail:0 fail:0 skip:20 time:499s
fi-skl-guc total:285 pass:257 dwarn:0 dfail:0 fail:0 skip:28 time:427s
fi-skl-gvtdvm total:285 pass:262 dwarn:0 dfail:0 fail:0 skip:23 time:445s
fi-snb-2520m total:3 pass:2 dwarn:0 dfail:0 fail:0 skip:0
fi-snb-2600 total:285 pass:245 dwarn:0 dfail:0 fail:0 skip:40 time:400s
Blacklisted hosts:
fi-cnl-psr total:285 pass:256 dwarn:3 dfail:0 fail:0 skip:26 time:520s
0eddede73765b01ec287cad00e23bee23c216a16 drm-tip: 2018y-04m-05d-09h-51m-03s UTC integration manifest
6fe98f643890 drm: Fix HDCP downstream dev count read
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8593/issues.html
_______________________________________________
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^ permalink raw reply [flat|nested] 25+ messages in thread
* ✓ Fi.CI.IGT: success for HDCP1.4 fixes (rev7)
2018-04-02 10:10 [PATCH v3 0/4] HDCP1.4 fixes Ramalingam C
` (12 preceding siblings ...)
2018-04-05 12:45 ` ✓ Fi.CI.BAT: success for HDCP1.4 fixes (rev7) Patchwork
@ 2018-04-05 14:18 ` Patchwork
13 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2018-04-05 14:18 UTC (permalink / raw)
To: Ramalingam C; +Cc: intel-gfx
== Series Details ==
Series: HDCP1.4 fixes (rev7)
URL : https://patchwork.freedesktop.org/series/38978/
State : success
== Summary ==
---- Possible new issues:
Test kms_cursor_legacy:
Subgroup cursor-vs-flip-toggle:
fail -> PASS (shard-hsw)
---- Known issues:
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-primscrn-pri-indfb-draw-render:
fail -> PASS (shard-snb) fdo#103167
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
shard-apl total:2680 pass:1835 dwarn:1 dfail:0 fail:7 skip:836 time:12694s
shard-hsw total:2680 pass:1786 dwarn:1 dfail:0 fail:1 skip:891 time:11383s
shard-snb total:2680 pass:1376 dwarn:1 dfail:0 fail:4 skip:1299 time:6941s
Blacklisted hosts:
shard-kbl total:2622 pass:1856 dwarn:51 dfail:1 fail:8 skip:705 time:8839s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8593/shards.html
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v4] drm: Fix downstream dev count read
2018-04-04 22:34 ` Ramalingam C
@ 2018-04-05 23:56 ` Rodrigo Vivi
0 siblings, 0 replies; 25+ messages in thread
From: Rodrigo Vivi @ 2018-04-05 23:56 UTC (permalink / raw)
To: Ramalingam C; +Cc: intel-gfx, dri-devel
On Thu, Apr 05, 2018 at 04:04:14AM +0530, Ramalingam C wrote:
>
>
> On Thursday 05 April 2018 12:53 AM, Sean Paul wrote:
> > On Wed, Apr 04, 2018 at 12:07:41PM -0700, Rodrigo Vivi wrote:
> > > On Wed, Apr 04, 2018 at 11:57:42PM +0530, Ramalingam C wrote:
> > > > In both HDMI and DP, device count is represented by 6:0 bits of a
> > > > register(BInfo/Bstatus)
> > > >
> > > > So macro for bitmasking the device_count is fixed(0x3F->0x7F).
> > > >
> > > > v3:
> > > > Retained the Rb-ed.
> > > > v4:
> > > > %s/drm\/i915/drm [rodrigo]
> > > >
> > > Shouldn't this patch have a "Fixes:" ?
> > Yes, I think that'd be good.
> Will add
> Fixes: 495eb7f877ab drm: Add some HDCP related #defines
> >
> > > cc: stable?
> > It couldn't hurt.
> Sorry what is needed here?
nothing actually...
$ dim fixes 495eb7f877ab3
Fixes: 495eb7f877ab ("drm: Add some HDCP related #defines")
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Ramalingam C <ramalingm.c@intel.com>
Cc: Sean Paul <seanpaul@chromium.org>
Cc: Gustavo Padovan <gustavo@padovan.org>
Cc: David Airlie <airlied@linux.ie>
Cc: dri-devel@lists.freedesktop.org
CC: Stable wasn't returned here so it is not needed.
> >
> > > I pushed first 3 patches on the series to dinq.
> > > I believe this one here could be there with Dave's ack or
> > > maybe on drm-misc-fixes?
> > Meh. The severity of this isn't too big, given that I doubt people care _too_
> > much about plugging in more than 64 HDCP-enabled devices. If you want to drop it
> > in -misc-next-fixes, I can send it out next week.
> >
> > While we're asking for a respin, could we add HDCP somewhere in the subject?
> will change the sub to
> drm: Fix HDCP downstream dev count read
>
> --Ram
> >
> > Sean
> >
> > > > Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> > > > cc: Sean Paul <seanpaul@chromium.org>
> > > > Reviewed-by: Sean Paul <seanpaul@chromium.org>
> > > > ---
> > > > include/drm/drm_hdcp.h | 2 +-
> > > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > > >
> > > > diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h
> > > > index 562fa7df2637..98e63d870139 100644
> > > > --- a/include/drm/drm_hdcp.h
> > > > +++ b/include/drm/drm_hdcp.h
> > > > @@ -19,7 +19,7 @@
> > > > #define DRM_HDCP_RI_LEN 2
> > > > #define DRM_HDCP_V_PRIME_PART_LEN 4
> > > > #define DRM_HDCP_V_PRIME_NUM_PARTS 5
> > > > -#define DRM_HDCP_NUM_DOWNSTREAM(x) (x & 0x3f)
> > > > +#define DRM_HDCP_NUM_DOWNSTREAM(x) (x & 0x7f)
> > > > #define DRM_HDCP_MAX_CASCADE_EXCEEDED(x) (x & BIT(3))
> > > > #define DRM_HDCP_MAX_DEVICE_EXCEEDED(x) (x & BIT(7))
> > > > --
> > > > 2.7.4
> > > >
>
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^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v5] drm: Fix HDCP downstream dev count read
2018-04-05 12:03 ` [PATCH v5] drm: Fix HDCP " Ramalingam C
@ 2018-04-16 16:11 ` Sean Paul
0 siblings, 0 replies; 25+ messages in thread
From: Sean Paul @ 2018-04-16 16:11 UTC (permalink / raw)
To: Ramalingam C; +Cc: Intel Graphics Development, dri-devel, Vivi, Rodrigo
On Thu, Apr 5, 2018 at 8:09 AM Ramalingam C <ramalingam.c@intel.com> wrote:
> In both HDMI and DP, device count is represented by 6:0 bits of a
> register(BInfo/Bstatus)
> So macro for bitmasking the device_count is fixed(0x3F->0x7F).
> v3:
> Retained the Rb-ed.
> v4:
> %s/drm\/i915/drm [rodrigo]
> v5:
> Added "Fixes:" and HDCP keyword in subject [Rodrigo, Sean Paul]
> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Thank you for your patch, I've pushed it to -misc-fixes
Sean
> Fixes: 495eb7f877ab drm: Add some HDCP related #defines
> cc: Sean Paul <seanpaul@chromium.org>
> Reviewed-by: Sean Paul <seanpaul@chromium.org>
> ---
> include/drm/drm_hdcp.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
> diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h
> index 562fa7df2637..98e63d870139 100644
> --- a/include/drm/drm_hdcp.h
> +++ b/include/drm/drm_hdcp.h
> @@ -19,7 +19,7 @@
> #define DRM_HDCP_RI_LEN 2
> #define DRM_HDCP_V_PRIME_PART_LEN 4
> #define DRM_HDCP_V_PRIME_NUM_PARTS 5
> -#define DRM_HDCP_NUM_DOWNSTREAM(x) (x & 0x3f)
> +#define DRM_HDCP_NUM_DOWNSTREAM(x) (x & 0x7f)
> #define DRM_HDCP_MAX_CASCADE_EXCEEDED(x) (x & BIT(3))
> #define DRM_HDCP_MAX_DEVICE_EXCEEDED(x) (x & BIT(7))
> --
> 2.7.4
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^ permalink raw reply [flat|nested] 25+ messages in thread
end of thread, other threads:[~2018-04-16 16:11 UTC | newest]
Thread overview: 25+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-04-02 10:10 [PATCH v3 0/4] HDCP1.4 fixes Ramalingam C
2018-04-02 10:10 ` [PATCH v3 1/4] drm/i915: Read HDCP R0 thrice in case of mismatch Ramalingam C
2018-04-02 11:50 ` [PATCH v4 " Ramalingam C
2018-04-02 13:49 ` Sean Paul
2018-04-02 10:10 ` [PATCH v3 2/4] drm/i915: Read Vprime thrice incase " Ramalingam C
2018-04-02 13:50 ` Sean Paul
2018-04-02 10:10 ` [PATCH v3 3/4] drm/i915: Check hdcp key loadability Ramalingam C
2018-04-02 10:10 ` [PATCH v3 4/4] drm/i915: Fix reading downstream dev count Ramalingam C
2018-04-04 18:27 ` [PATCH v4] drm: Fix downstream dev count read Ramalingam C
2018-04-04 19:07 ` Rodrigo Vivi
2018-04-04 19:23 ` Sean Paul
2018-04-04 22:34 ` Ramalingam C
2018-04-05 23:56 ` Rodrigo Vivi
2018-04-05 12:03 ` [PATCH v5] drm: Fix HDCP " Ramalingam C
2018-04-16 16:11 ` Sean Paul
2018-04-02 10:40 ` ✓ Fi.CI.BAT: success for HDCP1.4 fixes (rev4) Patchwork
2018-04-02 11:34 ` ✓ Fi.CI.IGT: " Patchwork
2018-04-02 12:22 ` ✓ Fi.CI.BAT: success for HDCP1.4 fixes (rev5) Patchwork
2018-04-02 13:06 ` ✗ Fi.CI.IGT: failure " Patchwork
2018-04-03 17:35 ` ✓ Fi.CI.BAT: success " Patchwork
2018-04-03 19:09 ` ✓ Fi.CI.IGT: " Patchwork
2018-04-04 19:01 ` ✓ Fi.CI.BAT: success for HDCP1.4 fixes (rev6) Patchwork
2018-04-04 21:15 ` ✓ Fi.CI.IGT: " Patchwork
2018-04-05 12:45 ` ✓ Fi.CI.BAT: success for HDCP1.4 fixes (rev7) Patchwork
2018-04-05 14:18 ` ✓ Fi.CI.IGT: " Patchwork
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