* [PATCH 1/7] drm/i915/icl: Add register definitions for Combo PHY vswing sequences.
2018-03-23 17:24 [PATCH CI 0/7] ICL reviewed mergeable patches Paulo Zanoni
@ 2018-03-23 17:24 ` Paulo Zanoni
2018-03-23 17:24 ` [PATCH 2/7] drm/i915/icl: Add Combo PHY DDI Buffer translation tables for Icelake Paulo Zanoni
` (8 subsequent siblings)
9 siblings, 0 replies; 17+ messages in thread
From: Paulo Zanoni @ 2018-03-23 17:24 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni, Rodrigo Vivi
From: Manasi Navare <manasi.d.navare@intel.com>
This patch defines register definitions required for ICL voltage
vswing programming for Combo PHY DDI Ports. It uses the same bit
definitions and macros as the CNL voltage swing sequences.
v8 (from Paulo):
* Rebase.
v7:
* Kill _MMIIO_PORT2_LN (Paulo)
v6:
* Replace some spaces with TAB (Paulo)
v5:
* Use _PORT instead of _PICK (Paulo)
* Remove DW7 defs for ICL, not used (Paulo)
v4:
* Rebase after _PICK was used instead of _PORT3
* Use _PICK for _MMIO_PORT2 since address of B is less
than address of A so cant use the math (Paulo)
v3:
* Make changes to the existing macro in a diff patch (Paulo)
v2:
* Add new defs fro ICL regs (Paulo)
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 44 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index da2f6c623ab2..0299e53f9c49 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1697,6 +1697,16 @@ enum i915_power_well_id {
_CNL_PORT_PCS_DW1_LN0_D, \
_CNL_PORT_PCS_DW1_LN0_AE, \
_CNL_PORT_PCS_DW1_LN0_F))
+#define _ICL_PORT_PCS_DW1_GRP_A 0x162604
+#define _ICL_PORT_PCS_DW1_GRP_B 0x6C604
+#define _ICL_PORT_PCS_DW1_LN0_A 0x162804
+#define _ICL_PORT_PCS_DW1_LN0_B 0x6C804
+#define ICL_PORT_PCS_DW1_GRP(port) _MMIO_PORT(port,\
+ _ICL_PORT_PCS_DW1_GRP_A, \
+ _ICL_PORT_PCS_DW1_GRP_B)
+#define ICL_PORT_PCS_DW1_LN0(port) _MMIO_PORT(port, \
+ _ICL_PORT_PCS_DW1_LN0_A, \
+ _ICL_PORT_PCS_DW1_LN0_B)
#define COMMON_KEEPER_EN (1 << 26)
/* CNL Port TX registers */
@@ -1729,6 +1739,16 @@ enum i915_power_well_id {
#define CNL_PORT_TX_DW2_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 2))
#define CNL_PORT_TX_DW2_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 2))
+#define _ICL_PORT_TX_DW2_GRP_A 0x162688
+#define _ICL_PORT_TX_DW2_GRP_B 0x6C688
+#define _ICL_PORT_TX_DW2_LN0_A 0x162888
+#define _ICL_PORT_TX_DW2_LN0_B 0x6C888
+#define ICL_PORT_TX_DW2_GRP(port) _MMIO_PORT(port, \
+ _ICL_PORT_TX_DW2_GRP_A, \
+ _ICL_PORT_TX_DW2_GRP_B)
+#define ICL_PORT_TX_DW2_LN0(port) _MMIO_PORT(port, \
+ _ICL_PORT_TX_DW2_LN0_A, \
+ _ICL_PORT_TX_DW2_LN0_B)
#define SWING_SEL_UPPER(x) ((x >> 3) << 15)
#define SWING_SEL_UPPER_MASK (1 << 15)
#define SWING_SEL_LOWER(x) ((x & 0x7) << 11)
@@ -1743,6 +1763,19 @@ enum i915_power_well_id {
#define CNL_PORT_TX_DW4_LN(port, ln) _MMIO(_CNL_PORT_TX_DW_LN0((port), 4) + \
(ln * (_CNL_PORT_TX_DW4_LN1_AE - \
_CNL_PORT_TX_DW4_LN0_AE)))
+#define _ICL_PORT_TX_DW4_GRP_A 0x162690
+#define _ICL_PORT_TX_DW4_GRP_B 0x6C690
+#define _ICL_PORT_TX_DW4_LN0_A 0x162890
+#define _ICL_PORT_TX_DW4_LN1_A 0x162990
+#define _ICL_PORT_TX_DW4_LN0_B 0x6C890
+#define ICL_PORT_TX_DW4_GRP(port) _MMIO_PORT(port, \
+ _ICL_PORT_TX_DW4_GRP_A, \
+ _ICL_PORT_TX_DW4_GRP_B)
+#define ICL_PORT_TX_DW4_LN(port, ln) _MMIO(_PORT(port, \
+ _ICL_PORT_TX_DW4_LN0_A, \
+ _ICL_PORT_TX_DW4_LN0_B) + \
+ (ln * (_ICL_PORT_TX_DW4_LN1_A - \
+ _ICL_PORT_TX_DW4_LN0_A)))
#define LOADGEN_SELECT (1 << 31)
#define POST_CURSOR_1(x) ((x) << 12)
#define POST_CURSOR_1_MASK (0x3F << 12)
@@ -1753,7 +1786,18 @@ enum i915_power_well_id {
#define CNL_PORT_TX_DW5_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 5))
#define CNL_PORT_TX_DW5_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 5))
+#define _ICL_PORT_TX_DW5_GRP_A 0x162694
+#define _ICL_PORT_TX_DW5_GRP_B 0x6C694
+#define _ICL_PORT_TX_DW5_LN0_A 0x162894
+#define _ICL_PORT_TX_DW5_LN0_B 0x6C894
+#define ICL_PORT_TX_DW5_GRP(port) _MMIO_PORT(port, \
+ _ICL_PORT_TX_DW5_GRP_A, \
+ _ICL_PORT_TX_DW5_GRP_B)
+#define ICL_PORT_TX_DW5_LN0(port) _MMIO_PORT(port, \
+ _ICL_PORT_TX_DW5_LN0_A, \
+ _ICL_PORT_TX_DW5_LN0_B)
#define TX_TRAINING_EN (1 << 31)
+#define TAP2_DISABLE (1 << 30)
#define TAP3_DISABLE (1 << 29)
#define SCALING_MODE_SEL(x) ((x) << 18)
#define SCALING_MODE_SEL_MASK (0x7 << 18)
--
2.14.3
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 2/7] drm/i915/icl: Add Combo PHY DDI Buffer translation tables for Icelake.
2018-03-23 17:24 [PATCH CI 0/7] ICL reviewed mergeable patches Paulo Zanoni
2018-03-23 17:24 ` [PATCH 1/7] drm/i915/icl: Add register definitions for Combo PHY vswing sequences Paulo Zanoni
@ 2018-03-23 17:24 ` Paulo Zanoni
2018-03-23 17:24 ` [PATCH 3/7] drm/i915/icl: Add register defs for voltage swing sequences for MG PHY DDI Paulo Zanoni
` (7 subsequent siblings)
9 siblings, 0 replies; 17+ messages in thread
From: Paulo Zanoni @ 2018-03-23 17:24 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni, Rodrigo Vivi
From: Manasi Navare <manasi.d.navare@intel.com>
These tables are used on voltage vswing sequence initialization on
Icelake.
The swing_sel on the spec's table is defined in a 4 bits binary like
1010. However the register bits are split in upper 1 bit swing_sel
and lower 3 bits swing sel.
In this table here we store this value as a single value in hex like
it is mentioned in the Bspec and split it to the upper and lower bit
values only while programming the registers.
For instance: b1010 is written as 0xA and then while writing to the
register, the upper 1 bit is obtained by (0xA & 0x8) and shifting by
appropriate bits while lower 3 bits are obtained by (0xA & 0x7) and
shifting by appropriate bits.
Some of the columns need to be updated after the spec is updated.
v5 (from Paulo):
* Checkpatch fixes.
v4 (from Paulo):
* Fix minor typo
* Coding style conformance
v3:
* Get rid of HDMI/DVI tables, same as DP (Paulo)
* Use combo_phy in ddi buf trans table defs (Paulo)
v2:
* Added DW4_scaling_hex column to the translation tables (Rodrigo)
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_ddi.c | 99 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 99 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index c449619427da..229b9d5250c4 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -493,6 +493,105 @@ static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
{ 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
};
+struct icl_combo_phy_ddi_buf_trans {
+ u32 dw2_swing_select;
+ u32 dw2_swing_scalar;
+ u32 dw4_scaling;
+};
+
+/* Voltage Swing Programming for VccIO 0.85V for DP */
+static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_85V[] = {
+ /* Voltage mV db */
+ { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
+ { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
+ { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
+ { 0x2, 0x98, 0x900F }, /* 400 9.5 */
+ { 0xB, 0x70, 0x0018 }, /* 600 0.0 */
+ { 0xB, 0x70, 0x3015 }, /* 600 3.5 */
+ { 0xB, 0x70, 0x6012 }, /* 600 6.0 */
+ { 0x5, 0x00, 0x0018 }, /* 800 0.0 */
+ { 0x5, 0x00, 0x3015 }, /* 800 3.5 */
+ { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
+};
+
+/* FIXME - After table is updated in Bspec */
+/* Voltage Swing Programming for VccIO 0.85V for eDP */
+static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_85V[] = {
+ /* Voltage mV db */
+ { 0x0, 0x00, 0x00 }, /* 200 0.0 */
+ { 0x0, 0x00, 0x00 }, /* 200 1.5 */
+ { 0x0, 0x00, 0x00 }, /* 200 4.0 */
+ { 0x0, 0x00, 0x00 }, /* 200 6.0 */
+ { 0x0, 0x00, 0x00 }, /* 250 0.0 */
+ { 0x0, 0x00, 0x00 }, /* 250 1.5 */
+ { 0x0, 0x00, 0x00 }, /* 250 4.0 */
+ { 0x0, 0x00, 0x00 }, /* 300 0.0 */
+ { 0x0, 0x00, 0x00 }, /* 300 1.5 */
+ { 0x0, 0x00, 0x00 }, /* 350 0.0 */
+};
+
+/* Voltage Swing Programming for VccIO 0.95V for DP */
+static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_95V[] = {
+ /* Voltage mV db */
+ { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
+ { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
+ { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
+ { 0x2, 0x98, 0x900F }, /* 400 9.5 */
+ { 0x4, 0x98, 0x0018 }, /* 600 0.0 */
+ { 0x4, 0x98, 0x3015 }, /* 600 3.5 */
+ { 0x4, 0x98, 0x6012 }, /* 600 6.0 */
+ { 0x5, 0x76, 0x0018 }, /* 800 0.0 */
+ { 0x5, 0x76, 0x3015 }, /* 800 3.5 */
+ { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
+};
+
+/* FIXME - After table is updated in Bspec */
+/* Voltage Swing Programming for VccIO 0.95V for eDP */
+static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_95V[] = {
+ /* Voltage mV db */
+ { 0x0, 0x00, 0x00 }, /* 200 0.0 */
+ { 0x0, 0x00, 0x00 }, /* 200 1.5 */
+ { 0x0, 0x00, 0x00 }, /* 200 4.0 */
+ { 0x0, 0x00, 0x00 }, /* 200 6.0 */
+ { 0x0, 0x00, 0x00 }, /* 250 0.0 */
+ { 0x0, 0x00, 0x00 }, /* 250 1.5 */
+ { 0x0, 0x00, 0x00 }, /* 250 4.0 */
+ { 0x0, 0x00, 0x00 }, /* 300 0.0 */
+ { 0x0, 0x00, 0x00 }, /* 300 1.5 */
+ { 0x0, 0x00, 0x00 }, /* 350 0.0 */
+};
+
+/* Voltage Swing Programming for VccIO 1.05V for DP */
+static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_1_05V[] = {
+ /* Voltage mV db */
+ { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
+ { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
+ { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
+ { 0x2, 0x98, 0x900F }, /* 400 9.5 */
+ { 0x4, 0x98, 0x0018 }, /* 600 0.0 */
+ { 0x4, 0x98, 0x3015 }, /* 600 3.5 */
+ { 0x4, 0x98, 0x6012 }, /* 600 6.0 */
+ { 0x5, 0x71, 0x0018 }, /* 800 0.0 */
+ { 0x5, 0x71, 0x3015 }, /* 800 3.5 */
+ { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
+};
+
+/* FIXME - After table is updated in Bspec */
+/* Voltage Swing Programming for VccIO 1.05V for eDP */
+static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_1_05V[] = {
+ /* Voltage mV db */
+ { 0x0, 0x00, 0x00 }, /* 200 0.0 */
+ { 0x0, 0x00, 0x00 }, /* 200 1.5 */
+ { 0x0, 0x00, 0x00 }, /* 200 4.0 */
+ { 0x0, 0x00, 0x00 }, /* 200 6.0 */
+ { 0x0, 0x00, 0x00 }, /* 250 0.0 */
+ { 0x0, 0x00, 0x00 }, /* 250 1.5 */
+ { 0x0, 0x00, 0x00 }, /* 250 4.0 */
+ { 0x0, 0x00, 0x00 }, /* 300 0.0 */
+ { 0x0, 0x00, 0x00 }, /* 300 1.5 */
+ { 0x0, 0x00, 0x00 }, /* 350 0.0 */
+};
+
static const struct ddi_buf_trans *
bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
{
--
2.14.3
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^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 3/7] drm/i915/icl: Add register defs for voltage swing sequences for MG PHY DDI
2018-03-23 17:24 [PATCH CI 0/7] ICL reviewed mergeable patches Paulo Zanoni
2018-03-23 17:24 ` [PATCH 1/7] drm/i915/icl: Add register definitions for Combo PHY vswing sequences Paulo Zanoni
2018-03-23 17:24 ` [PATCH 2/7] drm/i915/icl: Add Combo PHY DDI Buffer translation tables for Icelake Paulo Zanoni
@ 2018-03-23 17:24 ` Paulo Zanoni
2018-03-23 17:24 ` [PATCH 4/7] drm/i915/icl: Add Voltage swing table for MG PHY DDI Buffer Paulo Zanoni
` (6 subsequent siblings)
9 siblings, 0 replies; 17+ messages in thread
From: Paulo Zanoni @ 2018-03-23 17:24 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni, Rodrigo Vivi
From: Manasi Navare <manasi.d.navare@intel.com>
On Icelake platform, MG PHY is used when operating in DP alternate
mode or the legacy HDMI or DP modes. DDI Ports C, D, E, F are MG PHY
DDI ports on ICL.
This patch adds the necessary voltage swing programming related
register definitions and macros for MG PHY DDI ports.
v4 (from Paulo):
* Use _PORT instead of _PICK
* Change some mask names to our current coding standards
* Stay under 80 columns
v3:
* Rebase on new revision of patches
v2:
* Remove whitespaces in the #defines (Paulo)
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 116 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 116 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0299e53f9c49..9bbb2af81e43 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1809,6 +1809,122 @@ enum i915_power_well_id {
#define N_SCALAR(x) ((x) << 24)
#define N_SCALAR_MASK (0x7F << 24)
+#define _ICL_MG_PHY_PORT_LN(port, ln, ln0p1, ln0p2, ln1p1) \
+ _MMIO(_PORT((port) - PORT_C, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
+
+#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT1 0x16812C
+#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT1 0x16852C
+#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT2 0x16912C
+#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT2 0x16952C
+#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT3 0x16A12C
+#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT3 0x16A52C
+#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT4 0x16B12C
+#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT4 0x16B52C
+#define ICL_PORT_MG_TX1_LINK_PARAMS(port, ln) \
+ _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
+ _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT2, \
+ _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT1)
+
+#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT1 0x1680AC
+#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT1 0x1684AC
+#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT2 0x1690AC
+#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT2 0x1694AC
+#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT3 0x16A0AC
+#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT3 0x16A4AC
+#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT4 0x16B0AC
+#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT4 0x16B4AC
+#define ICL_PORT_MG_TX2_LINK_PARAMS(port, ln) \
+ _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
+ _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT2, \
+ _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT1)
+#define CRI_USE_FS32 (1 << 5)
+
+#define _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT1 0x16814C
+#define _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT1 0x16854C
+#define _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT2 0x16914C
+#define _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT2 0x16954C
+#define _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT3 0x16A14C
+#define _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT3 0x16A54C
+#define _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT4 0x16B14C
+#define _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT4 0x16B54C
+#define ICL_PORT_MG_TX1_PISO_READLOAD(port, ln) \
+ _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
+ _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT2, \
+ _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT1)
+
+#define _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT1 0x1680CC
+#define _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT1 0x1684CC
+#define _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT2 0x1690CC
+#define _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT2 0x1694CC
+#define _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT3 0x16A0CC
+#define _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT3 0x16A4CC
+#define _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT4 0x16B0CC
+#define _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT4 0x16B4CC
+#define ICL_PORT_MG_TX2_PISO_READLOAD(port, ln) \
+ _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
+ _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT2, \
+ _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT1)
+#define CRI_CALCINIT (1 << 1)
+
+#define _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT1 0x168148
+#define _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT1 0x168548
+#define _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT2 0x169148
+#define _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT2 0x169548
+#define _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT3 0x16A148
+#define _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT3 0x16A548
+#define _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT4 0x16B148
+#define _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT4 0x16B548
+#define ICL_PORT_MG_TX1_SWINGCTRL(port, ln) \
+ _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT1, \
+ _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT2, \
+ _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT1)
+
+#define _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT1 0x1680C8
+#define _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT1 0x1684C8
+#define _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT2 0x1690C8
+#define _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT2 0x1694C8
+#define _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT3 0x16A0C8
+#define _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT3 0x16A4C8
+#define _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT4 0x16B0C8
+#define _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT4 0x16B4C8
+#define ICL_PORT_MG_TX2_SWINGCTRL(port, ln) \
+ _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT1, \
+ _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT2, \
+ _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT1)
+#define CRI_TXDEEMPH_OVERRIDE_17_12(x) ((x) << 0)
+#define CRI_TXDEEMPH_OVERRIDE_17_12_MASK (0x3F << 0)
+
+#define _ICL_MG_TX_DRVCTRL_TX1LN0_PORT1 0x168144
+#define _ICL_MG_TX_DRVCTRL_TX1LN1_PORT1 0x168544
+#define _ICL_MG_TX_DRVCTRL_TX1LN0_PORT2 0x169144
+#define _ICL_MG_TX_DRVCTRL_TX1LN1_PORT2 0x169544
+#define _ICL_MG_TX_DRVCTRL_TX1LN0_PORT3 0x16A144
+#define _ICL_MG_TX_DRVCTRL_TX1LN1_PORT3 0x16A544
+#define _ICL_MG_TX_DRVCTRL_TX1LN0_PORT4 0x16B144
+#define _ICL_MG_TX_DRVCTRL_TX1LN1_PORT4 0x16B544
+#define ICL_PORT_MG_TX1_DRVCTRL(port, ln) \
+ _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_DRVCTRL_TX1LN0_PORT1, \
+ _ICL_MG_TX_DRVCTRL_TX1LN0_PORT2, \
+ _ICL_MG_TX_DRVCTRL_TX1LN1_PORT1)
+
+#define _ICL_MG_TX_DRVCTRL_TX2LN0_PORT1 0x1680C4
+#define _ICL_MG_TX_DRVCTRL_TX2LN1_PORT1 0x1684C4
+#define _ICL_MG_TX_DRVCTRL_TX2LN0_PORT2 0x1690C4
+#define _ICL_MG_TX_DRVCTRL_TX2LN1_PORT2 0x1694C4
+#define _ICL_MG_TX_DRVCTRL_TX2LN0_PORT3 0x16A0C4
+#define _ICL_MG_TX_DRVCTRL_TX2LN1_PORT3 0x16A4C4
+#define _ICL_MG_TX_DRVCTRL_TX2LN0_PORT4 0x16B0C4
+#define _ICL_MG_TX_DRVCTRL_TX2LN1_PORT4 0x16B4C4
+#define ICL_PORT_MG_TX2_DRVCTRL(port, ln) \
+ _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_DRVCTRL_TX2LN0_PORT1, \
+ _ICL_MG_TX_DRVCTRL_TX2LN0_PORT2, \
+ _ICL_MG_TX_DRVCTRL_TX2LN1_PORT1)
+#define CRI_TXDEEMPH_OVERRIDE_11_6(x) ((x) << 24)
+#define CRI_TXDEEMPH_OVERRIDE_11_6_MASK (0x3F << 24)
+#define CRI_TXDEEMPH_OVERRIDE_EN (1 << 22)
+#define CRI_TXDEEMPH_OVERRIDE_5_0(x) ((x) << 16)
+#define CRI_TXDEEMPH_OVERRIDE_5_0_MASK (0x3F << 16)
+
/* The spec defines this only for BXT PHY0, but lets assume that this
* would exist for PHY1 too if it had a second channel.
*/
--
2.14.3
_______________________________________________
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^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 4/7] drm/i915/icl: Add Voltage swing table for MG PHY DDI Buffer
2018-03-23 17:24 [PATCH CI 0/7] ICL reviewed mergeable patches Paulo Zanoni
` (2 preceding siblings ...)
2018-03-23 17:24 ` [PATCH 3/7] drm/i915/icl: Add register defs for voltage swing sequences for MG PHY DDI Paulo Zanoni
@ 2018-03-23 17:24 ` Paulo Zanoni
2018-04-10 8:51 ` Chris Wilson
2018-03-23 17:24 ` [PATCH 5/7] drm/i915/icl: HPD pin for port F Paulo Zanoni
` (5 subsequent siblings)
9 siblings, 1 reply; 17+ messages in thread
From: Paulo Zanoni @ 2018-03-23 17:24 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni, Rodrigo Vivi
From: Manasi Navare <manasi.d.navare@intel.com>
This table is used for voltage swing programming sequence during DDI
Buffer initialization for MG PHY DDI Buffers on Icelake.
v2 (from Paulo):
* Fix white space issues.
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_ddi.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 229b9d5250c4..359acbfec4b1 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -592,6 +592,26 @@ static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_e
{ 0x0, 0x00, 0x00 }, /* 350 0.0 */
};
+struct icl_mg_phy_ddi_buf_trans {
+ u32 cri_txdeemph_override_5_0;
+ u32 cri_txdeemph_override_11_6;
+ u32 cri_txdeemph_override_17_12;
+};
+
+static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations[] = {
+ /* Voltage swing pre-emphasis */
+ { 0x0, 0x1B, 0x00 }, /* 0 0 */
+ { 0x0, 0x23, 0x08 }, /* 0 1 */
+ { 0x0, 0x2D, 0x12 }, /* 0 2 */
+ { 0x0, 0x00, 0x00 }, /* 0 3 */
+ { 0x0, 0x23, 0x00 }, /* 1 0 */
+ { 0x0, 0x2B, 0x09 }, /* 1 1 */
+ { 0x0, 0x2E, 0x11 }, /* 1 2 */
+ { 0x0, 0x2F, 0x00 }, /* 2 0 */
+ { 0x0, 0x33, 0x0C }, /* 2 1 */
+ { 0x0, 0x00, 0x00 }, /* 3 0 */
+};
+
static const struct ddi_buf_trans *
bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
{
--
2.14.3
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^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 4/7] drm/i915/icl: Add Voltage swing table for MG PHY DDI Buffer
2018-03-23 17:24 ` [PATCH 4/7] drm/i915/icl: Add Voltage swing table for MG PHY DDI Buffer Paulo Zanoni
@ 2018-04-10 8:51 ` Chris Wilson
2018-04-10 20:39 ` Paulo Zanoni
0 siblings, 1 reply; 17+ messages in thread
From: Chris Wilson @ 2018-04-10 8:51 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni, Rodrigo Vivi
Quoting Paulo Zanoni (2018-03-23 17:24:16)
> From: Manasi Navare <manasi.d.navare@intel.com>
>
> This table is used for voltage swing programming sequence during DDI
> Buffer initialization for MG PHY DDI Buffers on Icelake.
Except it is not used at all...
drivers/gpu/drm/i915/intel_ddi.c:601:46: error: ‘icl_mg_phy_ddi_translations’ defined but not used [-Werror=unused-const-variable=]
static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations[] = {
^~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_ddi.c:581:49: error: ‘icl_combo_phy_ddi_translations_edp_1_05V’ defined but not used [-Werror=unused-const-variable=]
static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_1_05V[] = {
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_ddi.c:565:49: error: ‘icl_combo_phy_ddi_translations_dp_hdmi_1_05V’ defined but not used [-Werror=unused-const-variable=]
static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_1_05V[] = {
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_ddi.c:550:49: error: ‘icl_combo_phy_ddi_translations_edp_0_95V’ defined but not used [-Werror=unused-const-variable=]
static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_95V[] = {
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_ddi.c:534:49: error: ‘icl_combo_phy_ddi_translations_dp_hdmi_0_95V’ defined but not used [-Werror=unused-const-variable=]
static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_95V[] = {
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_ddi.c:519:49: error: ‘icl_combo_phy_ddi_translations_edp_0_85V’ defined but not used [-Werror=unused-const-variable=]
static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_85V[] = {
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_ddi.c:503:49: error: ‘icl_combo_phy_ddi_translations_dp_hdmi_0_85V’ defined but not used [-Werror=unused-const-variable=]
static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_85V[] = {
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
> v2 (from Paulo):
> * Fix white space issues.
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 229b9d5250c4..359acbfec4b1 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -592,6 +592,26 @@ static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_e
> { 0x0, 0x00, 0x00 }, /* 350 0.0 */
> };
>
> +struct icl_mg_phy_ddi_buf_trans {
> + u32 cri_txdeemph_override_5_0;
> + u32 cri_txdeemph_override_11_6;
> + u32 cri_txdeemph_override_17_12;
> +};
> +
> +static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations[] = {
> + /* Voltage swing pre-emphasis */
> + { 0x0, 0x1B, 0x00 }, /* 0 0 */
> + { 0x0, 0x23, 0x08 }, /* 0 1 */
> + { 0x0, 0x2D, 0x12 }, /* 0 2 */
> + { 0x0, 0x00, 0x00 }, /* 0 3 */
> + { 0x0, 0x23, 0x00 }, /* 1 0 */
> + { 0x0, 0x2B, 0x09 }, /* 1 1 */
> + { 0x0, 0x2E, 0x11 }, /* 1 2 */
> + { 0x0, 0x2F, 0x00 }, /* 2 0 */
> + { 0x0, 0x33, 0x0C }, /* 2 1 */
> + { 0x0, 0x00, 0x00 }, /* 3 0 */
> +};
> +
> static const struct ddi_buf_trans *
> bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
> {
> --
> 2.14.3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH 4/7] drm/i915/icl: Add Voltage swing table for MG PHY DDI Buffer
2018-04-10 8:51 ` Chris Wilson
@ 2018-04-10 20:39 ` Paulo Zanoni
2018-04-10 21:01 ` Chris Wilson
0 siblings, 1 reply; 17+ messages in thread
From: Paulo Zanoni @ 2018-04-10 20:39 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: Rodrigo Vivi
Em Ter, 2018-04-10 às 09:51 +0100, Chris Wilson escreveu:
> Quoting Paulo Zanoni (2018-03-23 17:24:16)
> > From: Manasi Navare <manasi.d.navare@intel.com>
> >
> > This table is used for voltage swing programming sequence during
> > DDI
> > Buffer initialization for MG PHY DDI Buffers on Icelake.
>
> Except it is not used at all...
It's going to be used later in the series.
>
> drivers/gpu/drm/i915/intel_ddi.c:601:46: error:
> ‘icl_mg_phy_ddi_translations’ defined but not used [-Werror=unused-
> const-variable=]
I have all of the I915 debugging options enabled, including
CONFIG_DRM_I915_WERROR=y, and I don't get this error. I'm using Fedora
27's gcc. Would it be the case that you have somehow enabled the
unused-const-variable warning through some non-traditional way that's
not upstream?
If that's the case, and if we decide that we want Werror=unused-const-
variable to block patches from being merged, then I think we should put
this error/warning under the i915 debugging .config options and force
CI to also use them and tell us about them.
Because I'm pretty sure if we start enabling random gcc warning/error
flags we'll be able to block a huge number of patches from being
upstreamed. I just don't think this is something we should do.
> static const struct icl_mg_phy_ddi_buf_trans
> icl_mg_phy_ddi_translations[] = {
> ^~~~~~~~~~~~~~~~~~~~~~~
> ~~~~
> drivers/gpu/drm/i915/intel_ddi.c:581:49: error:
> ‘icl_combo_phy_ddi_translations_edp_1_05V’ defined but not used [-
> Werror=unused-const-variable=]
> static const struct icl_combo_phy_ddi_buf_trans
> icl_combo_phy_ddi_translations_edp_1_05V[] = {
> ^~~~~~~~~~~~~~~~~~~~
> ~~~~~~~~~~~~~~~~~~~~
> drivers/gpu/drm/i915/intel_ddi.c:565:49: error:
> ‘icl_combo_phy_ddi_translations_dp_hdmi_1_05V’ defined but not used
> [-Werror=unused-const-variable=]
> static const struct icl_combo_phy_ddi_buf_trans
> icl_combo_phy_ddi_translations_dp_hdmi_1_05V[] = {
> ^~~~~~~~~~~~~~~~~~~~
> ~~~~~~~~~~~~~~~~~~~~~~~~
> drivers/gpu/drm/i915/intel_ddi.c:550:49: error:
> ‘icl_combo_phy_ddi_translations_edp_0_95V’ defined but not used [-
> Werror=unused-const-variable=]
> static const struct icl_combo_phy_ddi_buf_trans
> icl_combo_phy_ddi_translations_edp_0_95V[] = {
> ^~~~~~~~~~~~~~~~~~~~
> ~~~~~~~~~~~~~~~~~~~~
> drivers/gpu/drm/i915/intel_ddi.c:534:49: error:
> ‘icl_combo_phy_ddi_translations_dp_hdmi_0_95V’ defined but not used
> [-Werror=unused-const-variable=]
> static const struct icl_combo_phy_ddi_buf_trans
> icl_combo_phy_ddi_translations_dp_hdmi_0_95V[] = {
> ^~~~~~~~~~~~~~~~~~~~
> ~~~~~~~~~~~~~~~~~~~~~~~~
> drivers/gpu/drm/i915/intel_ddi.c:519:49: error:
> ‘icl_combo_phy_ddi_translations_edp_0_85V’ defined but not used [-
> Werror=unused-const-variable=]
> static const struct icl_combo_phy_ddi_buf_trans
> icl_combo_phy_ddi_translations_edp_0_85V[] = {
> ^~~~~~~~~~~~~~~~~~~~
> ~~~~~~~~~~~~~~~~~~~~
> drivers/gpu/drm/i915/intel_ddi.c:503:49: error:
> ‘icl_combo_phy_ddi_translations_dp_hdmi_0_85V’ defined but not used
> [-Werror=unused-const-variable=]
> static const struct icl_combo_phy_ddi_buf_trans
> icl_combo_phy_ddi_translations_dp_hdmi_0_85V[] = {
> ^~~~~~~~~~~~~~~~~~~~
> ~~~~~~~~~~~~~~~~~~~~~~~~
> cc1: all warnings being treated as errors
>
>
> > v2 (from Paulo):
> > * Fix white space issues.
> >
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Cc: Jani Nikula <jani.nikula@linux.intel.com>
> > Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_ddi.c | 20 ++++++++++++++++++++
> > 1 file changed, 20 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> > b/drivers/gpu/drm/i915/intel_ddi.c
> > index 229b9d5250c4..359acbfec4b1 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -592,6 +592,26 @@ static const struct
> > icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_e
> > { 0x0, 0x00, 0x00 }, /* 350 0.0 */
> > };
> >
> > +struct icl_mg_phy_ddi_buf_trans {
> > + u32 cri_txdeemph_override_5_0;
> > + u32 cri_txdeemph_override_11_6;
> > + u32 cri_txdeemph_override_17_12;
> > +};
> > +
> > +static const struct icl_mg_phy_ddi_buf_trans
> > icl_mg_phy_ddi_translations[] = {
> > + /* Voltage swing pre-emphasis */
> > + { 0x0, 0x1B, 0x00 }, /* 0 0 */
> > + { 0x0, 0x23, 0x08 }, /* 0 1 */
> > + { 0x0, 0x2D, 0x12 }, /* 0 2 */
> > + { 0x0, 0x00, 0x00 }, /* 0 3 */
> > + { 0x0, 0x23, 0x00 }, /* 1 0 */
> > + { 0x0, 0x2B, 0x09 }, /* 1 1 */
> > + { 0x0, 0x2E, 0x11 }, /* 1 2 */
> > + { 0x0, 0x2F, 0x00 }, /* 2 0 */
> > + { 0x0, 0x33, 0x0C }, /* 2 1 */
> > + { 0x0, 0x00, 0x00 }, /* 3 0 */
> > +};
> > +
> > static const struct ddi_buf_trans *
> > bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int
> > *n_entries)
> > {
> > --
> > 2.14.3
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH 4/7] drm/i915/icl: Add Voltage swing table for MG PHY DDI Buffer
2018-04-10 20:39 ` Paulo Zanoni
@ 2018-04-10 21:01 ` Chris Wilson
2018-04-10 21:07 ` Chris Wilson
2018-04-10 21:29 ` Paulo Zanoni
0 siblings, 2 replies; 17+ messages in thread
From: Chris Wilson @ 2018-04-10 21:01 UTC (permalink / raw)
To: Paulo Zanoni, intel-gfx; +Cc: Rodrigo Vivi
Quoting Paulo Zanoni (2018-04-10 21:39:31)
> Em Ter, 2018-04-10 às 09:51 +0100, Chris Wilson escreveu:
> > Quoting Paulo Zanoni (2018-03-23 17:24:16)
> > > From: Manasi Navare <manasi.d.navare@intel.com>
> > >
> > > This table is used for voltage swing programming sequence during
> > > DDI
> > > Buffer initialization for MG PHY DDI Buffers on Icelake.
> >
> > Except it is not used at all...
>
> It's going to be used later in the series.
>
> >
> > drivers/gpu/drm/i915/intel_ddi.c:601:46: error:
> > ‘icl_mg_phy_ddi_translations’ defined but not used [-Werror=unused-
> > const-variable=]
>
> I have all of the I915 debugging options enabled, including
> CONFIG_DRM_I915_WERROR=y, and I don't get this error. I'm using Fedora
> 27's gcc. Would it be the case that you have somehow enabled the
> unused-const-variable warning through some non-traditional way that's
> not upstream?
Try make W=1 (which includes kerneldoc checks!). Or clang (don't try
clang unless you are a masochist, especially not right now as -Wvla
upsets it).
> If that's the case, and if we decide that we want Werror=unused-const-
> variable to block patches from being merged, then I think we should put
> this error/warning under the i915 debugging .config options and force
> CI to also use them and tell us about them.
I'm trying to get W=1 as part of the pre-merge warning set, at the same
level of severity as ignoring checkpatch.
> Because I'm pretty sure if we start enabling random gcc warning/error
> flags we'll be able to block a huge number of patches from being
> upstreamed. I just don't think this is something we should do.
We do. Our code is clean at W=1 except for the odd mistake. Let's keep
it that way. As new gcc warnings are developed, we will squash petty
nuisances and sometimes outright bugs from the code (it has happened
before and will happen again).
-Chris
_______________________________________________
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^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 4/7] drm/i915/icl: Add Voltage swing table for MG PHY DDI Buffer
2018-04-10 21:01 ` Chris Wilson
@ 2018-04-10 21:07 ` Chris Wilson
2018-04-10 21:17 ` Paulo Zanoni
2018-04-10 21:29 ` Paulo Zanoni
1 sibling, 1 reply; 17+ messages in thread
From: Chris Wilson @ 2018-04-10 21:07 UTC (permalink / raw)
To: Paulo Zanoni, intel-gfx; +Cc: Rodrigo Vivi
Quoting Chris Wilson (2018-04-10 22:01:33)
> Quoting Paulo Zanoni (2018-04-10 21:39:31)
> > Em Ter, 2018-04-10 às 09:51 +0100, Chris Wilson escreveu:
> > > Quoting Paulo Zanoni (2018-03-23 17:24:16)
> > > > From: Manasi Navare <manasi.d.navare@intel.com>
> > > >
> > > > This table is used for voltage swing programming sequence during
> > > > DDI
> > > > Buffer initialization for MG PHY DDI Buffers on Icelake.
> > >
> > > Except it is not used at all...
> >
> > It's going to be used later in the series.
In the context of this patch in merged series, it means that we have
added unexecuted, untested code. Please justify that. (Unused data
tables have in the past remain unused, leaving the code using old
tables; a bug that would have been caught by the compiler.)
We know our test coverage is lacking, this makes it worse. Yes, it's
icl, yes we won't even have sim coverage for the entire set of freq
tables, so what's stopping us from writing unittests to double check the
code at least conforms to our expectations and is exercised?
-Chris
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^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 4/7] drm/i915/icl: Add Voltage swing table for MG PHY DDI Buffer
2018-04-10 21:07 ` Chris Wilson
@ 2018-04-10 21:17 ` Paulo Zanoni
0 siblings, 0 replies; 17+ messages in thread
From: Paulo Zanoni @ 2018-04-10 21:17 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: Rodrigo Vivi
Em Ter, 2018-04-10 às 22:07 +0100, Chris Wilson escreveu:
> Quoting Chris Wilson (2018-04-10 22:01:33)
> > Quoting Paulo Zanoni (2018-04-10 21:39:31)
> > > Em Ter, 2018-04-10 às 09:51 +0100, Chris Wilson escreveu:
> > > > Quoting Paulo Zanoni (2018-03-23 17:24:16)
> > > > > From: Manasi Navare <manasi.d.navare@intel.com>
> > > > >
> > > > > This table is used for voltage swing programming sequence
> > > > > during
> > > > > DDI
> > > > > Buffer initialization for MG PHY DDI Buffers on Icelake.
> > > >
> > > > Except it is not used at all...
> > >
> > > It's going to be used later in the series.
>
> In the context of this patch in merged series, it means that we have
> added unexecuted, untested code. Please justify that. (Unused data
> tables have in the past remain unused, leaving the code using old
> tables; a bug that would have been caught by the compiler.)
>
> We know our test coverage is lacking, this makes it worse. Yes, it's
> icl, yes we won't even have sim coverage for the entire set of freq
> tables, so what's stopping us from writing unittests to double check
> the
> code at least conforms to our expectations and is exercised?
We have properly tested this code and verified it works. It's just that
we didn't upstream the whole series yet since it's too big. Almost 100
ICL patches already made it to the list already, and about 60 were
merged, but the specific patch that uses that table is not here yet.
I'll take the blame for missing that patch from this series.
> -Chris
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^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 4/7] drm/i915/icl: Add Voltage swing table for MG PHY DDI Buffer
2018-04-10 21:01 ` Chris Wilson
2018-04-10 21:07 ` Chris Wilson
@ 2018-04-10 21:29 ` Paulo Zanoni
1 sibling, 0 replies; 17+ messages in thread
From: Paulo Zanoni @ 2018-04-10 21:29 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: Rodrigo Vivi
Em Ter, 2018-04-10 às 22:01 +0100, Chris Wilson escreveu:
> Quoting Paulo Zanoni (2018-04-10 21:39:31)
> > Em Ter, 2018-04-10 às 09:51 +0100, Chris Wilson escreveu:
> > > Quoting Paulo Zanoni (2018-03-23 17:24:16)
> > > > From: Manasi Navare <manasi.d.navare@intel.com>
> > > >
> > > > This table is used for voltage swing programming sequence
> > > > during
> > > > DDI
> > > > Buffer initialization for MG PHY DDI Buffers on Icelake.
> > >
> > > Except it is not used at all...
> >
> > It's going to be used later in the series.
> >
> > >
> > > drivers/gpu/drm/i915/intel_ddi.c:601:46: error:
> > > ‘icl_mg_phy_ddi_translations’ defined but not used [-
> > > Werror=unused-
> > > const-variable=]
> >
> > I have all of the I915 debugging options enabled, including
> > CONFIG_DRM_I915_WERROR=y, and I don't get this error. I'm using
> > Fedora
> > 27's gcc. Would it be the case that you have somehow enabled the
> > unused-const-variable warning through some non-traditional way
> > that's
> > not upstream?
>
> Try make W=1 (which includes kerneldoc checks!). Or clang (don't try
> clang unless you are a masochist, especially not right now as -Wvla
> upsets it).
>
> > If that's the case, and if we decide that we want Werror=unused-
> > const-
> > variable to block patches from being merged, then I think we should
> > put
> > this error/warning under the i915 debugging .config options and
> > force
> > CI to also use them and tell us about them.
>
> I'm trying to get W=1 as part of the pre-merge warning set, at the
> same
> level of severity as ignoring checkpatch.
Good. Perhaps some CONFIG_I915_DEBUG_SOMETHING option could also force
W=1 for us so developers get it for free?
>
> > Because I'm pretty sure if we start enabling random gcc
> > warning/error
> > flags we'll be able to block a huge number of patches from being
> > upstreamed. I just don't think this is something we should do.
>
> We do. Our code is clean at W=1 except for the odd mistake.
Ok, I'm convinced. I'll add W=1 to my compilation script. If you want
we can revert this patch and I'll squash it to the patch that actually
uses the table.
> Let's keep
> it that way. As new gcc warnings are developed, we will squash petty
> nuisances and sometimes outright bugs from the code (it has happened
> before and will happen again).
> -Chris
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^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 5/7] drm/i915/icl: HPD pin for port F
2018-03-23 17:24 [PATCH CI 0/7] ICL reviewed mergeable patches Paulo Zanoni
` (3 preceding siblings ...)
2018-03-23 17:24 ` [PATCH 4/7] drm/i915/icl: Add Voltage swing table for MG PHY DDI Buffer Paulo Zanoni
@ 2018-03-23 17:24 ` Paulo Zanoni
2018-03-23 17:24 ` [PATCH 6/7] drm/i915/icl: Added 5k source scaling support for Gen11 platform Paulo Zanoni
` (4 subsequent siblings)
9 siblings, 0 replies; 17+ messages in thread
From: Paulo Zanoni @ 2018-03-23 17:24 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni, Dhinakaran Pandiyan, Rodrigo Vivi
From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Extend enum hpd_pin to port F so that we can start using this for ICL.
v2: Rebase.
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_hotplug.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c9c3b2ba6a86..795ce8a86a4a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -262,6 +262,7 @@ enum hpd_pin {
HPD_PORT_C,
HPD_PORT_D,
HPD_PORT_E,
+ HPD_PORT_F,
HPD_NUM_PINS
};
diff --git a/drivers/gpu/drm/i915/intel_hotplug.c b/drivers/gpu/drm/i915/intel_hotplug.c
index 0e3d3e89d66a..43aa92beff2a 100644
--- a/drivers/gpu/drm/i915/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/intel_hotplug.c
@@ -100,6 +100,8 @@ enum port intel_hpd_pin_to_port(struct drm_i915_private *dev_priv,
if (IS_CNL_WITH_PORT_F(dev_priv))
return PORT_F;
return PORT_E;
+ case HPD_PORT_F:
+ return PORT_F;
default:
return PORT_NONE; /* no port for this pin */
}
@@ -132,6 +134,7 @@ enum hpd_pin intel_hpd_pin_default(struct drm_i915_private *dev_priv,
case PORT_F:
if (IS_CNL_WITH_PORT_F(dev_priv))
return HPD_PORT_E;
+ return HPD_PORT_F;
default:
MISSING_CASE(port);
return HPD_NONE;
--
2.14.3
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^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 6/7] drm/i915/icl: Added 5k source scaling support for Gen11 platform
2018-03-23 17:24 [PATCH CI 0/7] ICL reviewed mergeable patches Paulo Zanoni
` (4 preceding siblings ...)
2018-03-23 17:24 ` [PATCH 5/7] drm/i915/icl: HPD pin for port F Paulo Zanoni
@ 2018-03-23 17:24 ` Paulo Zanoni
2018-03-23 17:24 ` [PATCH 7/7] drm/i915/icl: Don't set pipe CSC/Gamma in PLANE_COLOR_CTL Paulo Zanoni
` (3 subsequent siblings)
9 siblings, 0 replies; 17+ messages in thread
From: Paulo Zanoni @ 2018-03-23 17:24 UTC (permalink / raw)
To: intel-gfx
From: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
Gen11 supports upto 5k source scaling
v2: Re-factoring of code as per review
v3: Corrected max Vertical size and indentation
v4: Added max Vertical dst size in same patch
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 11 +++++++----
drivers/gpu/drm/i915/intel_drv.h | 4 ++++
2 files changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3e7ab75e1b41..4c30c7c04f9c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4764,10 +4764,13 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
/* range checks */
if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
- dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
-
- src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
- dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
+ dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
+ (IS_GEN11(dev_priv) &&
+ (src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H ||
+ dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) ||
+ (!IS_GEN11(dev_priv) &&
+ (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
+ dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H))) {
DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
"size is out of scaler range\n",
intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 6e5c0f77b036..d1452fd2a58d 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -548,6 +548,10 @@ struct intel_initial_plane_config {
#define SKL_MAX_DST_W 4096
#define SKL_MIN_DST_H 8
#define SKL_MAX_DST_H 4096
+#define ICL_MAX_SRC_W 5120
+#define ICL_MAX_SRC_H 4096
+#define ICL_MAX_DST_W 5120
+#define ICL_MAX_DST_H 4096
struct intel_scaler {
int in_use;
--
2.14.3
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^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 7/7] drm/i915/icl: Don't set pipe CSC/Gamma in PLANE_COLOR_CTL
2018-03-23 17:24 [PATCH CI 0/7] ICL reviewed mergeable patches Paulo Zanoni
` (5 preceding siblings ...)
2018-03-23 17:24 ` [PATCH 6/7] drm/i915/icl: Added 5k source scaling support for Gen11 platform Paulo Zanoni
@ 2018-03-23 17:24 ` Paulo Zanoni
2018-03-23 18:53 ` ✗ Fi.CI.CHECKPATCH: warning for ICL reviewed mergeable patches Patchwork
` (2 subsequent siblings)
9 siblings, 0 replies; 17+ messages in thread
From: Paulo Zanoni @ 2018-03-23 17:24 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: James Ausmus <james.ausmus@intel.com>
These fields have been deprecated and moved in ICL+. Stop setting the
bits.
They have moved to GAMMA_MODE and CSC_MODE, respectively. This patch
is just to stop incorrectly setting bits in PLANE_COLOR_CTL while
we're waiting for the new replacement functionality to be done.
v2: Drop useless comment, and change !(GEN >= 11) to (GEN < 11). (Ville)
v3: No changes
v4 (from Paulo): Rebase.
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: James Ausmus <james.ausmus@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 4 ++--
drivers/gpu/drm/i915/intel_display.c | 8 ++++++--
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9bbb2af81e43..768a11a2a335 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6353,9 +6353,9 @@ enum {
#define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */
#define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */
#define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */
-#define PLANE_COLOR_PIPE_GAMMA_ENABLE (1 << 30)
+#define PLANE_COLOR_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-ICL */
#define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
-#define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23)
+#define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23) /* Pre-ICL */
#define PLANE_COLOR_CSC_MODE_BYPASS (0 << 17)
#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709 (1 << 17)
#define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 (2 << 17)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 4c30c7c04f9c..09ac58a728b4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3604,11 +3604,15 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
{
+ struct drm_i915_private *dev_priv =
+ to_i915(plane_state->base.plane->dev);
const struct drm_framebuffer *fb = plane_state->base.fb;
u32 plane_color_ctl = 0;
- plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
- plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
+ if (INTEL_GEN(dev_priv) < 11) {
+ plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
+ plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
+ }
plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
plane_color_ctl |= glk_plane_color_ctl_alpha(fb->format->format);
--
2.14.3
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^ permalink raw reply related [flat|nested] 17+ messages in thread* ✗ Fi.CI.CHECKPATCH: warning for ICL reviewed mergeable patches
2018-03-23 17:24 [PATCH CI 0/7] ICL reviewed mergeable patches Paulo Zanoni
` (6 preceding siblings ...)
2018-03-23 17:24 ` [PATCH 7/7] drm/i915/icl: Don't set pipe CSC/Gamma in PLANE_COLOR_CTL Paulo Zanoni
@ 2018-03-23 18:53 ` Patchwork
2018-03-23 19:08 ` ✓ Fi.CI.BAT: success " Patchwork
2018-03-23 23:16 ` ✓ Fi.CI.IGT: " Patchwork
9 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2018-03-23 18:53 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
== Series Details ==
Series: ICL reviewed mergeable patches
URL : https://patchwork.freedesktop.org/series/40585/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
8689ec52c22b drm/i915/icl: Add register definitions for Combo PHY vswing sequences.
a8fa787db803 drm/i915/icl: Add Combo PHY DDI Buffer translation tables for Icelake.
8dda02f88963 drm/i915/icl: Add register defs for voltage swing sequences for MG PHY DDI
-:37: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'ln0p1' - possible side-effects?
#37: FILE: drivers/gpu/drm/i915/i915_reg.h:1812:
+#define _ICL_MG_PHY_PORT_LN(port, ln, ln0p1, ln0p2, ln1p1) \
+ _MMIO(_PORT((port) - PORT_C, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
total: 0 errors, 0 warnings, 1 checks, 122 lines checked
72ee7a1a485c drm/i915/icl: Add Voltage swing table for MG PHY DDI Buffer
984e455fd5ea drm/i915/icl: HPD pin for port F
79f23d6f9352 drm/i915/icl: Added 5k source scaling support for Gen11 platform
7960f70290b5 drm/i915/icl: Don't set pipe CSC/Gamma in PLANE_COLOR_CTL
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^ permalink raw reply [flat|nested] 17+ messages in thread* ✓ Fi.CI.BAT: success for ICL reviewed mergeable patches
2018-03-23 17:24 [PATCH CI 0/7] ICL reviewed mergeable patches Paulo Zanoni
` (7 preceding siblings ...)
2018-03-23 18:53 ` ✗ Fi.CI.CHECKPATCH: warning for ICL reviewed mergeable patches Patchwork
@ 2018-03-23 19:08 ` Patchwork
2018-03-23 23:16 ` ✓ Fi.CI.IGT: " Patchwork
9 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2018-03-23 19:08 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
== Series Details ==
Series: ICL reviewed mergeable patches
URL : https://patchwork.freedesktop.org/series/40585/
State : success
== Summary ==
Series 40585v1 ICL reviewed mergeable patches
https://patchwork.freedesktop.org/api/1.0/series/40585/revisions/1/mbox/
---- Known issues:
Test debugfs_test:
Subgroup read_all_entries:
incomplete -> PASS (fi-snb-2520m) fdo#103713
Test prime_vgem:
Subgroup basic-fence-flip:
fail -> PASS (fi-ilk-650) fdo#104008
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008
fi-bdw-5557u total:285 pass:264 dwarn:0 dfail:0 fail:0 skip:21 time:438s
fi-bdw-gvtdvm total:285 pass:261 dwarn:0 dfail:0 fail:0 skip:24 time:440s
fi-blb-e6850 total:285 pass:220 dwarn:1 dfail:0 fail:0 skip:64 time:380s
fi-bsw-n3050 total:285 pass:239 dwarn:0 dfail:0 fail:0 skip:46 time:539s
fi-bwr-2160 total:285 pass:180 dwarn:0 dfail:0 fail:0 skip:105 time:300s
fi-bxt-dsi total:285 pass:255 dwarn:0 dfail:0 fail:0 skip:30 time:515s
fi-bxt-j4205 total:285 pass:256 dwarn:0 dfail:0 fail:0 skip:29 time:511s
fi-byt-j1900 total:285 pass:250 dwarn:0 dfail:0 fail:0 skip:35 time:519s
fi-byt-n2820 total:285 pass:246 dwarn:0 dfail:0 fail:0 skip:39 time:506s
fi-cfl-8700k total:285 pass:257 dwarn:0 dfail:0 fail:0 skip:28 time:409s
fi-cfl-u total:285 pass:259 dwarn:0 dfail:0 fail:0 skip:26 time:514s
fi-cnl-y3 total:285 pass:259 dwarn:0 dfail:0 fail:0 skip:26 time:578s
fi-elk-e7500 total:285 pass:225 dwarn:1 dfail:0 fail:0 skip:59 time:425s
fi-gdg-551 total:285 pass:177 dwarn:0 dfail:0 fail:0 skip:108 time:319s
fi-glk-1 total:285 pass:257 dwarn:0 dfail:0 fail:0 skip:28 time:534s
fi-hsw-4770 total:285 pass:258 dwarn:0 dfail:0 fail:0 skip:27 time:405s
fi-ilk-650 total:285 pass:225 dwarn:0 dfail:0 fail:0 skip:60 time:418s
fi-ivb-3520m total:285 pass:256 dwarn:0 dfail:0 fail:0 skip:29 time:473s
fi-ivb-3770 total:285 pass:252 dwarn:0 dfail:0 fail:0 skip:33 time:432s
fi-kbl-7500u total:285 pass:260 dwarn:1 dfail:0 fail:0 skip:24 time:476s
fi-kbl-7567u total:285 pass:265 dwarn:0 dfail:0 fail:0 skip:20 time:471s
fi-kbl-r total:285 pass:258 dwarn:0 dfail:0 fail:0 skip:27 time:516s
fi-pnv-d510 total:285 pass:219 dwarn:1 dfail:0 fail:0 skip:65 time:655s
fi-skl-6260u total:285 pass:265 dwarn:0 dfail:0 fail:0 skip:20 time:441s
fi-skl-6600u total:285 pass:258 dwarn:0 dfail:0 fail:0 skip:27 time:532s
fi-skl-6700k2 total:285 pass:261 dwarn:0 dfail:0 fail:0 skip:24 time:508s
fi-skl-6770hq total:285 pass:265 dwarn:0 dfail:0 fail:0 skip:20 time:503s
fi-skl-guc total:285 pass:257 dwarn:0 dfail:0 fail:0 skip:28 time:431s
fi-skl-gvtdvm total:285 pass:262 dwarn:0 dfail:0 fail:0 skip:23 time:442s
fi-snb-2520m total:285 pass:245 dwarn:0 dfail:0 fail:0 skip:40 time:582s
fi-snb-2600 total:285 pass:245 dwarn:0 dfail:0 fail:0 skip:40 time:408s
Blacklisted hosts:
fi-cfl-s3 total:285 pass:259 dwarn:0 dfail:0 fail:0 skip:26 time:568s
fi-cnl-psr total:224 pass:198 dwarn:0 dfail:0 fail:1 skip:24
fi-glk-j4005 total:285 pass:256 dwarn:0 dfail:0 fail:0 skip:29 time:488s
101f8aec6229d54ff241bb46b9d7bfc92cf682e9 drm-tip: 2018y-03m-23d-17h-52m-01s UTC integration manifest
7960f70290b5 drm/i915/icl: Don't set pipe CSC/Gamma in PLANE_COLOR_CTL
79f23d6f9352 drm/i915/icl: Added 5k source scaling support for Gen11 platform
984e455fd5ea drm/i915/icl: HPD pin for port F
72ee7a1a485c drm/i915/icl: Add Voltage swing table for MG PHY DDI Buffer
8dda02f88963 drm/i915/icl: Add register defs for voltage swing sequences for MG PHY DDI
a8fa787db803 drm/i915/icl: Add Combo PHY DDI Buffer translation tables for Icelake.
8689ec52c22b drm/i915/icl: Add register definitions for Combo PHY vswing sequences.
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8480/issues.html
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^ permalink raw reply [flat|nested] 17+ messages in thread* ✓ Fi.CI.IGT: success for ICL reviewed mergeable patches
2018-03-23 17:24 [PATCH CI 0/7] ICL reviewed mergeable patches Paulo Zanoni
` (8 preceding siblings ...)
2018-03-23 19:08 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2018-03-23 23:16 ` Patchwork
9 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2018-03-23 23:16 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
== Series Details ==
Series: ICL reviewed mergeable patches
URL : https://patchwork.freedesktop.org/series/40585/
State : success
== Summary ==
---- Known issues:
Test kms_flip:
Subgroup 2x-plain-flip-fb-recreate-interruptible:
fail -> PASS (shard-hsw) fdo#100368 +2
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
shard-apl total:3484 pass:1820 dwarn:1 dfail:0 fail:7 skip:1655 time:12932s
shard-hsw total:3484 pass:1774 dwarn:1 dfail:0 fail:1 skip:1707 time:11736s
shard-snb total:3484 pass:1363 dwarn:1 dfail:0 fail:3 skip:2117 time:7009s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8480/shards.html
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