[PATCH v2 0/4] Improve MTK NAND driver

[PATCH v2 0/4] Improve MTK NAND driver

[Xiaolei Li]

These patches are mainly to:
  - Add MAINTAINERS entry for Mediatek NAND controller driver.
  - Fix some MTK NAND driver DT binding description errors.
  - Support to maximize FDM ECC protected bytes setting by nfc capability.
  - Replace max_sector_size with sector size array.

Changes relative to:
--------------------

tree    : https://github.com/bbrezillon/linux-0day
branch  : nand/next
commit  :
	'commit ba4150b1ec2a ("mtd: rawnand: s3c2410: enhance the probe
	 function error path")'

Patch v2:
  - Add new nfc capability instead of defining new DT property.
  - Remove not backward compat patches about nand-ecc-maximize.

Tests:
------
  - ubifs and jffs2 are validated on MT2712 platform with NAND device
    MT29F16G08ADBCA by 'dd' command.
  - all drivers/mtd/tests/* pass.

Xiaolei Li (4):
  dt-bindings: mtd: mtk-nand: Update properties description
  MAINTAINERS: Add entry for Mediatek NAND controller driver
  mtd: rawnand: mtk: Replace max_sector_size with sector size array
  mtd: rawnand: mtk: Add new nfc capability maximize_fdm_ecc

 Documentation/devicetree/bindings/mtd/mtk-nand.txt | 18 +++++++---
 MAINTAINERS                                        |  7 ++++
 drivers/mtd/nand/raw/mtk_nand.c                    | 40 ++++++++++++++++++----
 3 files changed, 53 insertions(+), 12 deletions(-)
 mode change 100644 => 100755 drivers/mtd/nand/raw/mtk_nand.c

-- 
1.9.1

[PATCH v2 0/4] Improve MTK NAND driver

[Xiaolei Li]

These patches are mainly to:
  - Add MAINTAINERS entry for Mediatek NAND controller driver.
  - Fix some MTK NAND driver DT binding description errors.
  - Support to maximize FDM ECC protected bytes setting by nfc capability.
  - Replace max_sector_size with sector size array.

Changes relative to:
--------------------

tree    : https://github.com/bbrezillon/linux-0day
branch  : nand/next
commit  :
	'commit ba4150b1ec2a ("mtd: rawnand: s3c2410: enhance the probe
	 function error path")'

Patch v2:
  - Add new nfc capability instead of defining new DT property.
  - Remove not backward compat patches about nand-ecc-maximize.

Tests:
------
  - ubifs and jffs2 are validated on MT2712 platform with NAND device
    MT29F16G08ADBCA by 'dd' command.
  - all drivers/mtd/tests/* pass.

Xiaolei Li (4):
  dt-bindings: mtd: mtk-nand: Update properties description
  MAINTAINERS: Add entry for Mediatek NAND controller driver
  mtd: rawnand: mtk: Replace max_sector_size with sector size array
  mtd: rawnand: mtk: Add new nfc capability maximize_fdm_ecc

 Documentation/devicetree/bindings/mtd/mtk-nand.txt | 18 +++++++---
 MAINTAINERS                                        |  7 ++++
 drivers/mtd/nand/raw/mtk_nand.c                    | 40 ++++++++++++++++++----
 3 files changed, 53 insertions(+), 12 deletions(-)
 mode change 100644 => 100755 drivers/mtd/nand/raw/mtk_nand.c

-- 
1.9.1

[PATCH v2 1/4] dt-bindings: mtd: mtk-nand: Update properties description

[Xiaolei Li]

Update ecc step size, ecc strength, and parity bits supported on
each MTK NAND controller.

Signed-off-by: Xiaolei Li <xiaolei.li@mediatek.com>
---
 Documentation/devicetree/bindings/mtd/mtk-nand.txt | 18 +++++++++++++-----
 1 file changed, 13 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/mtd/mtk-nand.txt b/Documentation/devicetree/bindings/mtd/mtk-nand.txt
index 1c88526..ef786568 100644
--- a/Documentation/devicetree/bindings/mtd/mtk-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/mtk-nand.txt
@@ -50,14 +50,19 @@ Optional:
 - nand-on-flash-bbt:	Store BBT on NAND Flash.
 - nand-ecc-mode:	the NAND ecc mode (check driver for supported modes)
 - nand-ecc-step-size:	Number of data bytes covered by a single ECC step.
-			valid values: 512 and 1024.
+			valid values:
+			512 and 1024 on mt2701 and mt2712.
+			512 only on mt7622.
 			1024 is recommended for large page NANDs.
 - nand-ecc-strength:	Number of bits to correct per ECC step.
-			The valid values that the controller supports are: 4, 6,
-			8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36, 40, 44,
-			48, 52, 56, 60.
+			The valid values that each controller supports:
+			mt2701: 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28,
+				32, 36, 40, 44, 48, 52, 56, 60.
+			mt2712: 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28,
+				32, 36, 40, 44, 48, 52, 56, 60, 68, 72, 80.
+			mt7622: 4, 6, 8, 10, 12, 14, 16.
 			The strength should be calculated as follows:
-			E = (S - F) * 8 / 14
+			E = (S - F) * 8 / B
 			S = O / (P / Q)
 				E :	nand-ecc-strength.
 				S :	spare size per sector.
@@ -66,6 +71,9 @@ Optional:
 				O :	oob size.
 				P :	page size.
 				Q :	nand-ecc-step-size.
+				B :	parity bits to do 1 bit ECC.
+					Be 14 on mt2701 and mt2712.
+					Be 13 on mt7622.
 			If the result does not match any one of the listed
 			choices above, please select the smaller valid value from
 			the list.
-- 
1.9.1

[PATCH v2 1/4] dt-bindings: mtd: mtk-nand: Update properties description

[Xiaolei Li]

Update ecc step size, ecc strength, and parity bits supported on
each MTK NAND controller.

Signed-off-by: Xiaolei Li <xiaolei.li-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
---
 Documentation/devicetree/bindings/mtd/mtk-nand.txt | 18 +++++++++++++-----
 1 file changed, 13 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/mtd/mtk-nand.txt b/Documentation/devicetree/bindings/mtd/mtk-nand.txt
index 1c88526..ef786568 100644
--- a/Documentation/devicetree/bindings/mtd/mtk-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/mtk-nand.txt
@@ -50,14 +50,19 @@ Optional:
 - nand-on-flash-bbt:	Store BBT on NAND Flash.
 - nand-ecc-mode:	the NAND ecc mode (check driver for supported modes)
 - nand-ecc-step-size:	Number of data bytes covered by a single ECC step.
-			valid values: 512 and 1024.
+			valid values:
+			512 and 1024 on mt2701 and mt2712.
+			512 only on mt7622.
 			1024 is recommended for large page NANDs.
 - nand-ecc-strength:	Number of bits to correct per ECC step.
-			The valid values that the controller supports are: 4, 6,
-			8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36, 40, 44,
-			48, 52, 56, 60.
+			The valid values that each controller supports:
+			mt2701: 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28,
+				32, 36, 40, 44, 48, 52, 56, 60.
+			mt2712: 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28,
+				32, 36, 40, 44, 48, 52, 56, 60, 68, 72, 80.
+			mt7622: 4, 6, 8, 10, 12, 14, 16.
 			The strength should be calculated as follows:
-			E = (S - F) * 8 / 14
+			E = (S - F) * 8 / B
 			S = O / (P / Q)
 				E :	nand-ecc-strength.
 				S :	spare size per sector.
@@ -66,6 +71,9 @@ Optional:
 				O :	oob size.
 				P :	page size.
 				Q :	nand-ecc-step-size.
+				B :	parity bits to do 1 bit ECC.
+					Be 14 on mt2701 and mt2712.
+					Be 13 on mt7622.
 			If the result does not match any one of the listed
 			choices above, please select the smaller valid value from
 			the list.
-- 
1.9.1

[PATCH v2 2/4] MAINTAINERS: Add entry for Mediatek NAND controller driver

[Xiaolei Li]

Add entry for Mediatek NAND controller driver and its bindings.

Signed-off-by: Xiaolei Li <xiaolei.li@mediatek.com>
---
 MAINTAINERS | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index d262f17..429ef09 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8838,6 +8838,13 @@ L:	linux-wireless@vger.kernel.org
 S:	Maintained
 F:	drivers/net/wireless/mediatek/mt7601u/
 
+MEDIATEK NAND CONTROLLER DRIVER
+M:	Xiaolei Li <xiaolei.li@mediatek.com>
+L:	linux-mtd@lists.infradead.org
+S:	Maintained
+F:	drivers/mtd/nand/raw/mtk_*
+F:	Documentation/devicetree/bindings/mtd/mtk-nand.txt
+
 MEDIATEK RANDOM NUMBER GENERATOR SUPPORT
 M:	Sean Wang <sean.wang@mediatek.com>
 S:	Maintained
-- 
1.9.1

[PATCH v2 2/4] MAINTAINERS: Add entry for Mediatek NAND controller driver

[Xiaolei Li]

Add entry for Mediatek NAND controller driver and its bindings.

Signed-off-by: Xiaolei Li <xiaolei.li-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
---
 MAINTAINERS | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index d262f17..429ef09 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8838,6 +8838,13 @@ L:	linux-wireless-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
 S:	Maintained
 F:	drivers/net/wireless/mediatek/mt7601u/
 
+MEDIATEK NAND CONTROLLER DRIVER
+M:	Xiaolei Li <xiaolei.li-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
+L:	linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
+S:	Maintained
+F:	drivers/mtd/nand/raw/mtk_*
+F:	Documentation/devicetree/bindings/mtd/mtk-nand.txt
+
 MEDIATEK RANDOM NUMBER GENERATOR SUPPORT
 M:	Sean Wang <sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
 S:	Maintained
-- 
1.9.1

[PATCH v2 3/4] mtd: rawnand: mtk: Replace max_sector_size with sector size array

[Xiaolei Li]

Remove max_sector_size from struct mtk_nfc_caps, and use sector size
array and number of sector size to show sector sizes that controller
supports.

Signed-off-by: Xiaolei Li <xiaolei.li@mediatek.com>
---
 drivers/mtd/nand/raw/mtk_nand.c | 32 +++++++++++++++++++++++++++-----
 1 file changed, 27 insertions(+), 5 deletions(-)

diff --git a/drivers/mtd/nand/raw/mtk_nand.c b/drivers/mtd/nand/raw/mtk_nand.c
index 6977da3..03a4df2 100644
--- a/drivers/mtd/nand/raw/mtk_nand.c
+++ b/drivers/mtd/nand/raw/mtk_nand.c
@@ -106,10 +106,11 @@
 struct mtk_nfc_caps {
 	const u8 *spare_size;
 	u8 num_spare_size;
+	const int *sector_size;
+	int num_sector_size;
 	u8 pageformat_spare_shift;
 	u8 nfi_clk_div;
 	u8 max_sector;
-	u32 max_sector_size;
 };
 
 struct mtk_nfc_bad_mark_ctl {
@@ -178,6 +179,14 @@ struct mtk_nfc {
 	16, 26, 27, 28
 };
 
+static const int sector_size_max_1k[] = {
+	1024, 512
+};
+
+static const int sector_size_max_512[] = {
+	512
+};
+
 static inline struct mtk_nfc_nand_chip *to_mtk_nand(struct nand_chip *nand)
 {
 	return container_of(nand, struct mtk_nfc_nand_chip, nand);
@@ -258,6 +267,16 @@ static inline u8 nfi_readb(struct mtk_nfc *nfc, u32 reg)
 	return readb_relaxed(nfc->regs + reg);
 }
 
+static int mtk_nfc_max_sector_size(struct mtk_nfc *nfc)
+{
+	int i, sector_size = 0;
+
+	for (i = 0; i < nfc->caps->num_sector_size; i++)
+		sector_size = max(sector_size, nfc->caps->sector_size[i]);
+
+	return sector_size;
+}
+
 static void mtk_nfc_hw_reset(struct mtk_nfc *nfc)
 {
 	struct device *dev = nfc->dev;
@@ -1207,7 +1226,7 @@ static int mtk_nfc_ecc_init(struct device *dev, struct mtd_info *mtd)
 		 */
 		if (nand->ecc.size < 1024) {
 			if (mtd->writesize > 512 &&
-			    nfc->caps->max_sector_size > 512) {
+			    mtk_nfc_max_sector_size(nfc) > 512) {
 				nand->ecc.size = 1024;
 				nand->ecc.strength <<= 1;
 			} else {
@@ -1389,28 +1408,31 @@ static int mtk_nfc_nand_chips_init(struct device *dev, struct mtk_nfc *nfc)
 static const struct mtk_nfc_caps mtk_nfc_caps_mt2701 = {
 	.spare_size = spare_size_mt2701,
 	.num_spare_size = 16,
+	.sector_size = sector_size_max_1k,
+	.num_sector_size = 2,
 	.pageformat_spare_shift = 4,
 	.nfi_clk_div = 1,
 	.max_sector = 16,
-	.max_sector_size = 1024,
 };
 
 static const struct mtk_nfc_caps mtk_nfc_caps_mt2712 = {
 	.spare_size = spare_size_mt2712,
 	.num_spare_size = 19,
+	.sector_size = sector_size_max_1k,
+	.num_sector_size = 2,
 	.pageformat_spare_shift = 16,
 	.nfi_clk_div = 2,
 	.max_sector = 16,
-	.max_sector_size = 1024,
 };
 
 static const struct mtk_nfc_caps mtk_nfc_caps_mt7622 = {
 	.spare_size = spare_size_mt7622,
 	.num_spare_size = 4,
+	.sector_size = sector_size_max_512,
+	.num_sector_size = 1,
 	.pageformat_spare_shift = 4,
 	.nfi_clk_div = 1,
 	.max_sector = 8,
-	.max_sector_size = 512,
 };
 
 static const struct of_device_id mtk_nfc_id_table[] = {
-- 
1.9.1

[PATCH v2 3/4] mtd: rawnand: mtk: Replace max_sector_size with sector size array

[Xiaolei Li]

Remove max_sector_size from struct mtk_nfc_caps, and use sector size
array and number of sector size to show sector sizes that controller
supports.

Signed-off-by: Xiaolei Li <xiaolei.li-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
---
 drivers/mtd/nand/raw/mtk_nand.c | 32 +++++++++++++++++++++++++++-----
 1 file changed, 27 insertions(+), 5 deletions(-)

diff --git a/drivers/mtd/nand/raw/mtk_nand.c b/drivers/mtd/nand/raw/mtk_nand.c
index 6977da3..03a4df2 100644
--- a/drivers/mtd/nand/raw/mtk_nand.c
+++ b/drivers/mtd/nand/raw/mtk_nand.c
@@ -106,10 +106,11 @@
 struct mtk_nfc_caps {
 	const u8 *spare_size;
 	u8 num_spare_size;
+	const int *sector_size;
+	int num_sector_size;
 	u8 pageformat_spare_shift;
 	u8 nfi_clk_div;
 	u8 max_sector;
-	u32 max_sector_size;
 };
 
 struct mtk_nfc_bad_mark_ctl {
@@ -178,6 +179,14 @@ struct mtk_nfc {
 	16, 26, 27, 28
 };
 
+static const int sector_size_max_1k[] = {
+	1024, 512
+};
+
+static const int sector_size_max_512[] = {
+	512
+};
+
 static inline struct mtk_nfc_nand_chip *to_mtk_nand(struct nand_chip *nand)
 {
 	return container_of(nand, struct mtk_nfc_nand_chip, nand);
@@ -258,6 +267,16 @@ static inline u8 nfi_readb(struct mtk_nfc *nfc, u32 reg)
 	return readb_relaxed(nfc->regs + reg);
 }
 
+static int mtk_nfc_max_sector_size(struct mtk_nfc *nfc)
+{
+	int i, sector_size = 0;
+
+	for (i = 0; i < nfc->caps->num_sector_size; i++)
+		sector_size = max(sector_size, nfc->caps->sector_size[i]);
+
+	return sector_size;
+}
+
 static void mtk_nfc_hw_reset(struct mtk_nfc *nfc)
 {
 	struct device *dev = nfc->dev;
@@ -1207,7 +1226,7 @@ static int mtk_nfc_ecc_init(struct device *dev, struct mtd_info *mtd)
 		 */
 		if (nand->ecc.size < 1024) {
 			if (mtd->writesize > 512 &&
-			    nfc->caps->max_sector_size > 512) {
+			    mtk_nfc_max_sector_size(nfc) > 512) {
 				nand->ecc.size = 1024;
 				nand->ecc.strength <<= 1;
 			} else {
@@ -1389,28 +1408,31 @@ static int mtk_nfc_nand_chips_init(struct device *dev, struct mtk_nfc *nfc)
 static const struct mtk_nfc_caps mtk_nfc_caps_mt2701 = {
 	.spare_size = spare_size_mt2701,
 	.num_spare_size = 16,
+	.sector_size = sector_size_max_1k,
+	.num_sector_size = 2,
 	.pageformat_spare_shift = 4,
 	.nfi_clk_div = 1,
 	.max_sector = 16,
-	.max_sector_size = 1024,
 };
 
 static const struct mtk_nfc_caps mtk_nfc_caps_mt2712 = {
 	.spare_size = spare_size_mt2712,
 	.num_spare_size = 19,
+	.sector_size = sector_size_max_1k,
+	.num_sector_size = 2,
 	.pageformat_spare_shift = 16,
 	.nfi_clk_div = 2,
 	.max_sector = 16,
-	.max_sector_size = 1024,
 };
 
 static const struct mtk_nfc_caps mtk_nfc_caps_mt7622 = {
 	.spare_size = spare_size_mt7622,
 	.num_spare_size = 4,
+	.sector_size = sector_size_max_512,
+	.num_sector_size = 1,
 	.pageformat_spare_shift = 4,
 	.nfi_clk_div = 1,
 	.max_sector = 8,
-	.max_sector_size = 512,
 };
 
 static const struct of_device_id mtk_nfc_id_table[] = {
-- 
1.9.1

[PATCH v2 4/4] mtd: rawnand: mtk: Add new nfc capability maximize_fdm_ecc

[Xiaolei Li]

For some MTK NAND chips, BootROM will access more than one byte
ECC protected FDM data, but now we fix ECC protected FDM byte as 1.
This will make some chips be failed to boot up.

This patch adds one new nfc capability maximize_fdm_ecc to maximize ECC
protected FDM bytes if it is true.

Signed-off-by: Xiaolei Li <xiaolei.li@mediatek.com>
---
 drivers/mtd/nand/raw/mtk_nand.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)
 mode change 100644 => 100755 drivers/mtd/nand/raw/mtk_nand.c

diff --git a/drivers/mtd/nand/raw/mtk_nand.c b/drivers/mtd/nand/raw/mtk_nand.c
old mode 100644
new mode 100755
index 03a4df2..7025132
--- a/drivers/mtd/nand/raw/mtk_nand.c
+++ b/drivers/mtd/nand/raw/mtk_nand.c
@@ -111,6 +111,7 @@ struct mtk_nfc_caps {
 	u8 pageformat_spare_shift;
 	u8 nfi_clk_div;
 	u8 max_sector;
+	bool maximize_fdm_ecc;
 };
 
 struct mtk_nfc_bad_mark_ctl {
@@ -1151,8 +1152,8 @@ static void mtk_nfc_set_fdm(struct mtk_nfc_fdm *fdm, struct mtd_info *mtd)
 	if (fdm->reg_size > NFI_FDM_MAX_SIZE)
 		fdm->reg_size = NFI_FDM_MAX_SIZE;
 
-	/* bad block mark storage */
-	fdm->ecc_size = 1;
+	/* Reserve at least one byte for bad mark */
+	fdm->ecc_size = nfc->caps->maximize_fdm_ecc ? fdm->reg_size : 1;
 }
 
 static void mtk_nfc_set_bad_mark_ctl(struct mtk_nfc_bad_mark_ctl *bm_ctl,
@@ -1413,6 +1414,7 @@ static int mtk_nfc_nand_chips_init(struct device *dev, struct mtk_nfc *nfc)
 	.pageformat_spare_shift = 4,
 	.nfi_clk_div = 1,
 	.max_sector = 16,
+	.maximize_fdm_ecc = false,
 };
 
 static const struct mtk_nfc_caps mtk_nfc_caps_mt2712 = {
@@ -1423,6 +1425,7 @@ static int mtk_nfc_nand_chips_init(struct device *dev, struct mtk_nfc *nfc)
 	.pageformat_spare_shift = 16,
 	.nfi_clk_div = 2,
 	.max_sector = 16,
+	.maximize_fdm_ecc = false,
 };
 
 static const struct mtk_nfc_caps mtk_nfc_caps_mt7622 = {
@@ -1433,6 +1436,7 @@ static int mtk_nfc_nand_chips_init(struct device *dev, struct mtk_nfc *nfc)
 	.pageformat_spare_shift = 4,
 	.nfi_clk_div = 1,
 	.max_sector = 8,
+	.maximize_fdm_ecc = false,
 };
 
 static const struct of_device_id mtk_nfc_id_table[] = {
-- 
1.9.1

[PATCH v2 4/4] mtd: rawnand: mtk: Add new nfc capability maximize_fdm_ecc

[Xiaolei Li]

For some MTK NAND chips, BootROM will access more than one byte
ECC protected FDM data, but now we fix ECC protected FDM byte as 1.
This will make some chips be failed to boot up.

This patch adds one new nfc capability maximize_fdm_ecc to maximize ECC
protected FDM bytes if it is true.

Signed-off-by: Xiaolei Li <xiaolei.li-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
---
 drivers/mtd/nand/raw/mtk_nand.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)
 mode change 100644 => 100755 drivers/mtd/nand/raw/mtk_nand.c

diff --git a/drivers/mtd/nand/raw/mtk_nand.c b/drivers/mtd/nand/raw/mtk_nand.c
old mode 100644
new mode 100755
index 03a4df2..7025132
--- a/drivers/mtd/nand/raw/mtk_nand.c
+++ b/drivers/mtd/nand/raw/mtk_nand.c
@@ -111,6 +111,7 @@ struct mtk_nfc_caps {
 	u8 pageformat_spare_shift;
 	u8 nfi_clk_div;
 	u8 max_sector;
+	bool maximize_fdm_ecc;
 };
 
 struct mtk_nfc_bad_mark_ctl {
@@ -1151,8 +1152,8 @@ static void mtk_nfc_set_fdm(struct mtk_nfc_fdm *fdm, struct mtd_info *mtd)
 	if (fdm->reg_size > NFI_FDM_MAX_SIZE)
 		fdm->reg_size = NFI_FDM_MAX_SIZE;
 
-	/* bad block mark storage */
-	fdm->ecc_size = 1;
+	/* Reserve at least one byte for bad mark */
+	fdm->ecc_size = nfc->caps->maximize_fdm_ecc ? fdm->reg_size : 1;
 }
 
 static void mtk_nfc_set_bad_mark_ctl(struct mtk_nfc_bad_mark_ctl *bm_ctl,
@@ -1413,6 +1414,7 @@ static int mtk_nfc_nand_chips_init(struct device *dev, struct mtk_nfc *nfc)
 	.pageformat_spare_shift = 4,
 	.nfi_clk_div = 1,
 	.max_sector = 16,
+	.maximize_fdm_ecc = false,
 };
 
 static const struct mtk_nfc_caps mtk_nfc_caps_mt2712 = {
@@ -1423,6 +1425,7 @@ static int mtk_nfc_nand_chips_init(struct device *dev, struct mtk_nfc *nfc)
 	.pageformat_spare_shift = 16,
 	.nfi_clk_div = 2,
 	.max_sector = 16,
+	.maximize_fdm_ecc = false,
 };
 
 static const struct mtk_nfc_caps mtk_nfc_caps_mt7622 = {
@@ -1433,6 +1436,7 @@ static int mtk_nfc_nand_chips_init(struct device *dev, struct mtk_nfc *nfc)
 	.pageformat_spare_shift = 4,
 	.nfi_clk_div = 1,
 	.max_sector = 8,
+	.maximize_fdm_ecc = false,
 };
 
 static const struct of_device_id mtk_nfc_id_table[] = {
-- 
1.9.1

Re: [PATCH v2 1/4] dt-bindings: mtd: mtk-nand: Update properties description

[Boris Brezillon]

On Mon, 16 Apr 2018 15:41:01 +0800
Xiaolei Li <xiaolei.li@mediatek.com> wrote:

> Update ecc step size, ecc strength, and parity bits supported on
> each MTK NAND controller.
> 
> Signed-off-by: Xiaolei Li <xiaolei.li@mediatek.com>
> ---
>  Documentation/devicetree/bindings/mtd/mtk-nand.txt | 18 +++++++++++++-----
>  1 file changed, 13 insertions(+), 5 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/mtd/mtk-nand.txt b/Documentation/devicetree/bindings/mtd/mtk-nand.txt
> index 1c88526..ef786568 100644
> --- a/Documentation/devicetree/bindings/mtd/mtk-nand.txt
> +++ b/Documentation/devicetree/bindings/mtd/mtk-nand.txt
> @@ -50,14 +50,19 @@ Optional:
>  - nand-on-flash-bbt:	Store BBT on NAND Flash.
>  - nand-ecc-mode:	the NAND ecc mode (check driver for supported modes)
>  - nand-ecc-step-size:	Number of data bytes covered by a single ECC step.
> -			valid values: 512 and 1024.
> +			valid values:
> +			512 and 1024 on mt2701 and mt2712.
> +			512 only on mt7622.
>  			1024 is recommended for large page NANDs.
>  - nand-ecc-strength:	Number of bits to correct per ECC step.
> -			The valid values that the controller supports are: 4, 6,
> -			8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36, 40, 44,
> -			48, 52, 56, 60.
> +			The valid values that each controller supports:
> +			mt2701: 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28,
> +				32, 36, 40, 44, 48, 52, 56, 60.
> +			mt2712: 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28,
> +				32, 36, 40, 44, 48, 52, 56, 60, 68, 72, 80.
> +			mt7622: 4, 6, 8, 10, 12, 14, 16.
>  			The strength should be calculated as follows:
> -			E = (S - F) * 8 / 14
> +			E = (S - F) * 8 / B
>  			S = O / (P / Q)
>  				E :	nand-ecc-strength.
>  				S :	spare size per sector.
> @@ -66,6 +71,9 @@ Optional:
>  				O :	oob size.
>  				P :	page size.
>  				Q :	nand-ecc-step-size.
> +				B :	parity bits to do 1 bit ECC.

Hm, this one is not clear. I guess what you wanted to say was "number
of parity bits needed to correct 1 bitflip". Even if what you say is
true, the value actually comes from the ECC step size, so I'm not
sure this is really useful to explain why it's 14 or 13 in the
dt-bindings doc.

> +					Be 14 on mt2701 and mt2712.
> +					Be 13 on mt7622.

					^ Should be

You can keep only that part.

>  			If the result does not match any one of the listed
>  			choices above, please select the smaller valid value from
>  			the list.

Re: [PATCH v2 1/4] dt-bindings: mtd: mtk-nand: Update properties description

[Boris Brezillon]

On Mon, 16 Apr 2018 15:41:01 +0800
Xiaolei Li <xiaolei.li-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> wrote:

> Update ecc step size, ecc strength, and parity bits supported on
> each MTK NAND controller.
> 
> Signed-off-by: Xiaolei Li <xiaolei.li-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> ---
>  Documentation/devicetree/bindings/mtd/mtk-nand.txt | 18 +++++++++++++-----
>  1 file changed, 13 insertions(+), 5 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/mtd/mtk-nand.txt b/Documentation/devicetree/bindings/mtd/mtk-nand.txt
> index 1c88526..ef786568 100644
> --- a/Documentation/devicetree/bindings/mtd/mtk-nand.txt
> +++ b/Documentation/devicetree/bindings/mtd/mtk-nand.txt
> @@ -50,14 +50,19 @@ Optional:
>  - nand-on-flash-bbt:	Store BBT on NAND Flash.
>  - nand-ecc-mode:	the NAND ecc mode (check driver for supported modes)
>  - nand-ecc-step-size:	Number of data bytes covered by a single ECC step.
> -			valid values: 512 and 1024.
> +			valid values:
> +			512 and 1024 on mt2701 and mt2712.
> +			512 only on mt7622.
>  			1024 is recommended for large page NANDs.
>  - nand-ecc-strength:	Number of bits to correct per ECC step.
> -			The valid values that the controller supports are: 4, 6,
> -			8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36, 40, 44,
> -			48, 52, 56, 60.
> +			The valid values that each controller supports:
> +			mt2701: 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28,
> +				32, 36, 40, 44, 48, 52, 56, 60.
> +			mt2712: 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28,
> +				32, 36, 40, 44, 48, 52, 56, 60, 68, 72, 80.
> +			mt7622: 4, 6, 8, 10, 12, 14, 16.
>  			The strength should be calculated as follows:
> -			E = (S - F) * 8 / 14
> +			E = (S - F) * 8 / B
>  			S = O / (P / Q)
>  				E :	nand-ecc-strength.
>  				S :	spare size per sector.
> @@ -66,6 +71,9 @@ Optional:
>  				O :	oob size.
>  				P :	page size.
>  				Q :	nand-ecc-step-size.
> +				B :	parity bits to do 1 bit ECC.

Hm, this one is not clear. I guess what you wanted to say was "number
of parity bits needed to correct 1 bitflip". Even if what you say is
true, the value actually comes from the ECC step size, so I'm not
sure this is really useful to explain why it's 14 or 13 in the
dt-bindings doc.

> +					Be 14 on mt2701 and mt2712.
> +					Be 13 on mt7622.

					^ Should be

You can keep only that part.

>  			If the result does not match any one of the listed
>  			choices above, please select the smaller valid value from
>  			the list.

Re: [PATCH v2 3/4] mtd: rawnand: mtk: Replace max_sector_size with sector size array

[Boris Brezillon]

On Mon, 16 Apr 2018 15:41:03 +0800
Xiaolei Li <xiaolei.li@mediatek.com> wrote:

> Remove max_sector_size from struct mtk_nfc_caps, and use sector size
> array and number of sector size to show sector sizes that controller
> supports.
> 
> Signed-off-by: Xiaolei Li <xiaolei.li@mediatek.com>

I don't see the point of this patch. I was seeing a clear benefit when
you were moving to the generic ECC selection code, but since you've
dropped this part from the patch series, this patch becomes useless.

Am I missing something?

> ---
>  drivers/mtd/nand/raw/mtk_nand.c | 32 +++++++++++++++++++++++++++-----
>  1 file changed, 27 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/mtd/nand/raw/mtk_nand.c b/drivers/mtd/nand/raw/mtk_nand.c
> index 6977da3..03a4df2 100644
> --- a/drivers/mtd/nand/raw/mtk_nand.c
> +++ b/drivers/mtd/nand/raw/mtk_nand.c
> @@ -106,10 +106,11 @@
>  struct mtk_nfc_caps {
>  	const u8 *spare_size;
>  	u8 num_spare_size;
> +	const int *sector_size;
> +	int num_sector_size;
>  	u8 pageformat_spare_shift;
>  	u8 nfi_clk_div;
>  	u8 max_sector;
> -	u32 max_sector_size;
>  };
>  
>  struct mtk_nfc_bad_mark_ctl {
> @@ -178,6 +179,14 @@ struct mtk_nfc {
>  	16, 26, 27, 28
>  };
>  
> +static const int sector_size_max_1k[] = {
> +	1024, 512
> +};
> +
> +static const int sector_size_max_512[] = {
> +	512
> +};
> +
>  static inline struct mtk_nfc_nand_chip *to_mtk_nand(struct nand_chip *nand)
>  {
>  	return container_of(nand, struct mtk_nfc_nand_chip, nand);
> @@ -258,6 +267,16 @@ static inline u8 nfi_readb(struct mtk_nfc *nfc, u32 reg)
>  	return readb_relaxed(nfc->regs + reg);
>  }
>  
> +static int mtk_nfc_max_sector_size(struct mtk_nfc *nfc)
> +{
> +	int i, sector_size = 0;
> +
> +	for (i = 0; i < nfc->caps->num_sector_size; i++)
> +		sector_size = max(sector_size, nfc->caps->sector_size[i]);
> +
> +	return sector_size;
> +}
> +
>  static void mtk_nfc_hw_reset(struct mtk_nfc *nfc)
>  {
>  	struct device *dev = nfc->dev;
> @@ -1207,7 +1226,7 @@ static int mtk_nfc_ecc_init(struct device *dev, struct mtd_info *mtd)
>  		 */
>  		if (nand->ecc.size < 1024) {
>  			if (mtd->writesize > 512 &&
> -			    nfc->caps->max_sector_size > 512) {
> +			    mtk_nfc_max_sector_size(nfc) > 512) {
>  				nand->ecc.size = 1024;
>  				nand->ecc.strength <<= 1;
>  			} else {
> @@ -1389,28 +1408,31 @@ static int mtk_nfc_nand_chips_init(struct device *dev, struct mtk_nfc *nfc)
>  static const struct mtk_nfc_caps mtk_nfc_caps_mt2701 = {
>  	.spare_size = spare_size_mt2701,
>  	.num_spare_size = 16,
> +	.sector_size = sector_size_max_1k,
> +	.num_sector_size = 2,
>  	.pageformat_spare_shift = 4,
>  	.nfi_clk_div = 1,
>  	.max_sector = 16,
> -	.max_sector_size = 1024,
>  };
>  
>  static const struct mtk_nfc_caps mtk_nfc_caps_mt2712 = {
>  	.spare_size = spare_size_mt2712,
>  	.num_spare_size = 19,
> +	.sector_size = sector_size_max_1k,
> +	.num_sector_size = 2,
>  	.pageformat_spare_shift = 16,
>  	.nfi_clk_div = 2,
>  	.max_sector = 16,
> -	.max_sector_size = 1024,
>  };
>  
>  static const struct mtk_nfc_caps mtk_nfc_caps_mt7622 = {
>  	.spare_size = spare_size_mt7622,
>  	.num_spare_size = 4,
> +	.sector_size = sector_size_max_512,
> +	.num_sector_size = 1,
>  	.pageformat_spare_shift = 4,
>  	.nfi_clk_div = 1,
>  	.max_sector = 8,
> -	.max_sector_size = 512,
>  };
>  
>  static const struct of_device_id mtk_nfc_id_table[] = {

Re: [PATCH v2 3/4] mtd: rawnand: mtk: Replace max_sector_size with sector size array

[Boris Brezillon]

On Mon, 16 Apr 2018 15:41:03 +0800
Xiaolei Li <xiaolei.li-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> wrote:

> Remove max_sector_size from struct mtk_nfc_caps, and use sector size
> array and number of sector size to show sector sizes that controller
> supports.
> 
> Signed-off-by: Xiaolei Li <xiaolei.li-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>

I don't see the point of this patch. I was seeing a clear benefit when
you were moving to the generic ECC selection code, but since you've
dropped this part from the patch series, this patch becomes useless.

Am I missing something?

> ---
>  drivers/mtd/nand/raw/mtk_nand.c | 32 +++++++++++++++++++++++++++-----
>  1 file changed, 27 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/mtd/nand/raw/mtk_nand.c b/drivers/mtd/nand/raw/mtk_nand.c
> index 6977da3..03a4df2 100644
> --- a/drivers/mtd/nand/raw/mtk_nand.c
> +++ b/drivers/mtd/nand/raw/mtk_nand.c
> @@ -106,10 +106,11 @@
>  struct mtk_nfc_caps {
>  	const u8 *spare_size;
>  	u8 num_spare_size;
> +	const int *sector_size;
> +	int num_sector_size;
>  	u8 pageformat_spare_shift;
>  	u8 nfi_clk_div;
>  	u8 max_sector;
> -	u32 max_sector_size;
>  };
>  
>  struct mtk_nfc_bad_mark_ctl {
> @@ -178,6 +179,14 @@ struct mtk_nfc {
>  	16, 26, 27, 28
>  };
>  
> +static const int sector_size_max_1k[] = {
> +	1024, 512
> +};
> +
> +static const int sector_size_max_512[] = {
> +	512
> +};
> +
>  static inline struct mtk_nfc_nand_chip *to_mtk_nand(struct nand_chip *nand)
>  {
>  	return container_of(nand, struct mtk_nfc_nand_chip, nand);
> @@ -258,6 +267,16 @@ static inline u8 nfi_readb(struct mtk_nfc *nfc, u32 reg)
>  	return readb_relaxed(nfc->regs + reg);
>  }
>  
> +static int mtk_nfc_max_sector_size(struct mtk_nfc *nfc)
> +{
> +	int i, sector_size = 0;
> +
> +	for (i = 0; i < nfc->caps->num_sector_size; i++)
> +		sector_size = max(sector_size, nfc->caps->sector_size[i]);
> +
> +	return sector_size;
> +}
> +
>  static void mtk_nfc_hw_reset(struct mtk_nfc *nfc)
>  {
>  	struct device *dev = nfc->dev;
> @@ -1207,7 +1226,7 @@ static int mtk_nfc_ecc_init(struct device *dev, struct mtd_info *mtd)
>  		 */
>  		if (nand->ecc.size < 1024) {
>  			if (mtd->writesize > 512 &&
> -			    nfc->caps->max_sector_size > 512) {
> +			    mtk_nfc_max_sector_size(nfc) > 512) {
>  				nand->ecc.size = 1024;
>  				nand->ecc.strength <<= 1;
>  			} else {
> @@ -1389,28 +1408,31 @@ static int mtk_nfc_nand_chips_init(struct device *dev, struct mtk_nfc *nfc)
>  static const struct mtk_nfc_caps mtk_nfc_caps_mt2701 = {
>  	.spare_size = spare_size_mt2701,
>  	.num_spare_size = 16,
> +	.sector_size = sector_size_max_1k,
> +	.num_sector_size = 2,
>  	.pageformat_spare_shift = 4,
>  	.nfi_clk_div = 1,
>  	.max_sector = 16,
> -	.max_sector_size = 1024,
>  };
>  
>  static const struct mtk_nfc_caps mtk_nfc_caps_mt2712 = {
>  	.spare_size = spare_size_mt2712,
>  	.num_spare_size = 19,
> +	.sector_size = sector_size_max_1k,
> +	.num_sector_size = 2,
>  	.pageformat_spare_shift = 16,
>  	.nfi_clk_div = 2,
>  	.max_sector = 16,
> -	.max_sector_size = 1024,
>  };
>  
>  static const struct mtk_nfc_caps mtk_nfc_caps_mt7622 = {
>  	.spare_size = spare_size_mt7622,
>  	.num_spare_size = 4,
> +	.sector_size = sector_size_max_512,
> +	.num_sector_size = 1,
>  	.pageformat_spare_shift = 4,
>  	.nfi_clk_div = 1,
>  	.max_sector = 8,
> -	.max_sector_size = 512,
>  };
>  
>  static const struct of_device_id mtk_nfc_id_table[] = {

Re: [PATCH v2 4/4] mtd: rawnand: mtk: Add new nfc capability maximize_fdm_ecc

[Boris Brezillon]

On Mon, 16 Apr 2018 15:41:04 +0800
Xiaolei Li <xiaolei.li@mediatek.com> wrote:

> For some MTK NAND chips, BootROM will access more than one byte
> ECC protected FDM data, but now we fix ECC protected FDM byte as 1.
> This will make some chips be failed to boot up.
> 
> This patch adds one new nfc capability maximize_fdm_ecc to maximize ECC
> protected FDM bytes if it is true.
> 
> Signed-off-by: Xiaolei Li <xiaolei.li@mediatek.com>
> ---
>  drivers/mtd/nand/raw/mtk_nand.c | 8 ++++++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
>  mode change 100644 => 100755 drivers/mtd/nand/raw/mtk_nand.c
> 
> diff --git a/drivers/mtd/nand/raw/mtk_nand.c b/drivers/mtd/nand/raw/mtk_nand.c
> old mode 100644
> new mode 100755
> index 03a4df2..7025132
> --- a/drivers/mtd/nand/raw/mtk_nand.c
> +++ b/drivers/mtd/nand/raw/mtk_nand.c
> @@ -111,6 +111,7 @@ struct mtk_nfc_caps {
>  	u8 pageformat_spare_shift;
>  	u8 nfi_clk_div;
>  	u8 max_sector;
> +	bool maximize_fdm_ecc;
>  };
>  
>  struct mtk_nfc_bad_mark_ctl {
> @@ -1151,8 +1152,8 @@ static void mtk_nfc_set_fdm(struct mtk_nfc_fdm *fdm, struct mtd_info *mtd)
>  	if (fdm->reg_size > NFI_FDM_MAX_SIZE)
>  		fdm->reg_size = NFI_FDM_MAX_SIZE;
>  
> -	/* bad block mark storage */
> -	fdm->ecc_size = 1;
> +	/* Reserve at least one byte for bad mark */
> +	fdm->ecc_size = nfc->caps->maximize_fdm_ecc ? fdm->reg_size : 1;
>  }
>  
>  static void mtk_nfc_set_bad_mark_ctl(struct mtk_nfc_bad_mark_ctl *bm_ctl,
> @@ -1413,6 +1414,7 @@ static int mtk_nfc_nand_chips_init(struct device *dev, struct mtk_nfc *nfc)
>  	.pageformat_spare_shift = 4,
>  	.nfi_clk_div = 1,
>  	.max_sector = 16,
> +	.maximize_fdm_ecc = false,
>  };
>  
>  static const struct mtk_nfc_caps mtk_nfc_caps_mt2712 = {
> @@ -1423,6 +1425,7 @@ static int mtk_nfc_nand_chips_init(struct device *dev, struct mtk_nfc *nfc)
>  	.pageformat_spare_shift = 16,
>  	.nfi_clk_div = 2,
>  	.max_sector = 16,
> +	.maximize_fdm_ecc = false,
>  };
>  
>  static const struct mtk_nfc_caps mtk_nfc_caps_mt7622 = {
> @@ -1433,6 +1436,7 @@ static int mtk_nfc_nand_chips_init(struct device *dev, struct mtk_nfc *nfc)
>  	.pageformat_spare_shift = 4,
>  	.nfi_clk_div = 1,
>  	.max_sector = 8,
> +	.maximize_fdm_ecc = false,
>  };

So, you introduce a new flag, but all existing SoCs are setting it to
false. Can you please send a patch series containing all the
modifications, or at least point to a branch containing all the changes
you intend to push so that we know why the changes are required?
Your first version of this patchset was better in this regard.

>  
>  static const struct of_device_id mtk_nfc_id_table[] = {

Re: [PATCH v2 4/4] mtd: rawnand: mtk: Add new nfc capability maximize_fdm_ecc

[Boris Brezillon]

On Mon, 16 Apr 2018 15:41:04 +0800
Xiaolei Li <xiaolei.li-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> wrote:

> For some MTK NAND chips, BootROM will access more than one byte
> ECC protected FDM data, but now we fix ECC protected FDM byte as 1.
> This will make some chips be failed to boot up.
> 
> This patch adds one new nfc capability maximize_fdm_ecc to maximize ECC
> protected FDM bytes if it is true.
> 
> Signed-off-by: Xiaolei Li <xiaolei.li-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> ---
>  drivers/mtd/nand/raw/mtk_nand.c | 8 ++++++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
>  mode change 100644 => 100755 drivers/mtd/nand/raw/mtk_nand.c
> 
> diff --git a/drivers/mtd/nand/raw/mtk_nand.c b/drivers/mtd/nand/raw/mtk_nand.c
> old mode 100644
> new mode 100755
> index 03a4df2..7025132
> --- a/drivers/mtd/nand/raw/mtk_nand.c
> +++ b/drivers/mtd/nand/raw/mtk_nand.c
> @@ -111,6 +111,7 @@ struct mtk_nfc_caps {
>  	u8 pageformat_spare_shift;
>  	u8 nfi_clk_div;
>  	u8 max_sector;
> +	bool maximize_fdm_ecc;
>  };
>  
>  struct mtk_nfc_bad_mark_ctl {
> @@ -1151,8 +1152,8 @@ static void mtk_nfc_set_fdm(struct mtk_nfc_fdm *fdm, struct mtd_info *mtd)
>  	if (fdm->reg_size > NFI_FDM_MAX_SIZE)
>  		fdm->reg_size = NFI_FDM_MAX_SIZE;
>  
> -	/* bad block mark storage */
> -	fdm->ecc_size = 1;
> +	/* Reserve at least one byte for bad mark */
> +	fdm->ecc_size = nfc->caps->maximize_fdm_ecc ? fdm->reg_size : 1;
>  }
>  
>  static void mtk_nfc_set_bad_mark_ctl(struct mtk_nfc_bad_mark_ctl *bm_ctl,
> @@ -1413,6 +1414,7 @@ static int mtk_nfc_nand_chips_init(struct device *dev, struct mtk_nfc *nfc)
>  	.pageformat_spare_shift = 4,
>  	.nfi_clk_div = 1,
>  	.max_sector = 16,
> +	.maximize_fdm_ecc = false,
>  };
>  
>  static const struct mtk_nfc_caps mtk_nfc_caps_mt2712 = {
> @@ -1423,6 +1425,7 @@ static int mtk_nfc_nand_chips_init(struct device *dev, struct mtk_nfc *nfc)
>  	.pageformat_spare_shift = 16,
>  	.nfi_clk_div = 2,
>  	.max_sector = 16,
> +	.maximize_fdm_ecc = false,
>  };
>  
>  static const struct mtk_nfc_caps mtk_nfc_caps_mt7622 = {
> @@ -1433,6 +1436,7 @@ static int mtk_nfc_nand_chips_init(struct device *dev, struct mtk_nfc *nfc)
>  	.pageformat_spare_shift = 4,
>  	.nfi_clk_div = 1,
>  	.max_sector = 8,
> +	.maximize_fdm_ecc = false,
>  };

So, you introduce a new flag, but all existing SoCs are setting it to
false. Can you please send a patch series containing all the
modifications, or at least point to a branch containing all the changes
you intend to push so that we know why the changes are required?
Your first version of this patchset was better in this regard.

>  
>  static const struct of_device_id mtk_nfc_id_table[] = {

Re: [PATCH v2 2/4] MAINTAINERS: Add entry for Mediatek NAND controller driver

[Boris Brezillon]

On Mon, 16 Apr 2018 15:41:02 +0800
Xiaolei Li <xiaolei.li@mediatek.com> wrote:

> Add entry for Mediatek NAND controller driver and its bindings.
> 
> Signed-off-by: Xiaolei Li <xiaolei.li@mediatek.com>
> ---
>  MAINTAINERS | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index d262f17..429ef09 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -8838,6 +8838,13 @@ L:	linux-wireless@vger.kernel.org
>  S:	Maintained
>  F:	drivers/net/wireless/mediatek/mt7601u/
>  
> +MEDIATEK NAND CONTROLLER DRIVER
> +M:	Xiaolei Li <xiaolei.li@mediatek.com>
> +L:	linux-mtd@lists.infradead.org
> +S:	Maintained
> +F:	drivers/mtd/nand/raw/mtk_*
> +F:	Documentation/devicetree/bindings/mtd/mtk-nand.txt

Thanks for doing that.

I'll apply the patch, you can drop it from your v3.

> +
>  MEDIATEK RANDOM NUMBER GENERATOR SUPPORT
>  M:	Sean Wang <sean.wang@mediatek.com>
>  S:	Maintained

Re: [PATCH v2 2/4] MAINTAINERS: Add entry for Mediatek NAND controller driver

[Boris Brezillon]

On Mon, 16 Apr 2018 15:41:02 +0800
Xiaolei Li <xiaolei.li-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> wrote:

> Add entry for Mediatek NAND controller driver and its bindings.
> 
> Signed-off-by: Xiaolei Li <xiaolei.li-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> ---
>  MAINTAINERS | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index d262f17..429ef09 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -8838,6 +8838,13 @@ L:	linux-wireless-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
>  S:	Maintained
>  F:	drivers/net/wireless/mediatek/mt7601u/
>  
> +MEDIATEK NAND CONTROLLER DRIVER
> +M:	Xiaolei Li <xiaolei.li-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> +L:	linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> +S:	Maintained
> +F:	drivers/mtd/nand/raw/mtk_*
> +F:	Documentation/devicetree/bindings/mtd/mtk-nand.txt

Thanks for doing that.

I'll apply the patch, you can drop it from your v3.

> +
>  MEDIATEK RANDOM NUMBER GENERATOR SUPPORT
>  M:	Sean Wang <sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
>  S:	Maintained

Re: [PATCH v2 2/4] MAINTAINERS: Add entry for Mediatek NAND controller driver

[Boris Brezillon]

On Fri, 20 Apr 2018 22:24:51 +0200
Boris Brezillon <boris.brezillon@bootlin.com> wrote:

> On Mon, 16 Apr 2018 15:41:02 +0800
> Xiaolei Li <xiaolei.li@mediatek.com> wrote:
> 
> > Add entry for Mediatek NAND controller driver and its bindings.
> > 
> > Signed-off-by: Xiaolei Li <xiaolei.li@mediatek.com>
> > ---
> >  MAINTAINERS | 7 +++++++
> >  1 file changed, 7 insertions(+)
> > 
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index d262f17..429ef09 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -8838,6 +8838,13 @@ L:	linux-wireless@vger.kernel.org
> >  S:	Maintained
> >  F:	drivers/net/wireless/mediatek/mt7601u/
> >  
> > +MEDIATEK NAND CONTROLLER DRIVER
> > +M:	Xiaolei Li <xiaolei.li@mediatek.com>
> > +L:	linux-mtd@lists.infradead.org
> > +S:	Maintained
> > +F:	drivers/mtd/nand/raw/mtk_*
> > +F:	Documentation/devicetree/bindings/mtd/mtk-nand.txt  
> 
> Thanks for doing that.
> 
> I'll apply the patch, you can drop it from your v3.

Applied to nand/next.

Thanks,

Boris

> 
> > +
> >  MEDIATEK RANDOM NUMBER GENERATOR SUPPORT
> >  M:	Sean Wang <sean.wang@mediatek.com>
> >  S:	Maintained  
> 
> 
> ______________________________________________________
> Linux MTD discussion mailing list
> http://lists.infradead.org/mailman/listinfo/linux-mtd/

Re: [PATCH v2 2/4] MAINTAINERS: Add entry for Mediatek NAND controller driver

[Boris Brezillon]

On Fri, 20 Apr 2018 22:24:51 +0200
Boris Brezillon <boris.brezillon-LDxbnhwyfcJBDgjK7y7TUQ@public.gmane.org> wrote:

> On Mon, 16 Apr 2018 15:41:02 +0800
> Xiaolei Li <xiaolei.li-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> wrote:
> 
> > Add entry for Mediatek NAND controller driver and its bindings.
> > 
> > Signed-off-by: Xiaolei Li <xiaolei.li-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> > ---
> >  MAINTAINERS | 7 +++++++
> >  1 file changed, 7 insertions(+)
> > 
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index d262f17..429ef09 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -8838,6 +8838,13 @@ L:	linux-wireless-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> >  S:	Maintained
> >  F:	drivers/net/wireless/mediatek/mt7601u/
> >  
> > +MEDIATEK NAND CONTROLLER DRIVER
> > +M:	Xiaolei Li <xiaolei.li-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> > +L:	linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> > +S:	Maintained
> > +F:	drivers/mtd/nand/raw/mtk_*
> > +F:	Documentation/devicetree/bindings/mtd/mtk-nand.txt  
> 
> Thanks for doing that.
> 
> I'll apply the patch, you can drop it from your v3.

Applied to nand/next.

Thanks,

Boris

> 
> > +
> >  MEDIATEK RANDOM NUMBER GENERATOR SUPPORT
> >  M:	Sean Wang <sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> >  S:	Maintained  
> 
> 
> ______________________________________________________
> Linux MTD discussion mailing list
> http://lists.infradead.org/mailman/listinfo/linux-mtd/

Re: [PATCH v2 1/4] dt-bindings: mtd: mtk-nand: Update properties description

[xiaolei li]

Hi Boris

On Fri, 2018-04-20 at 22:15 +0200, Boris Brezillon wrote:
> On Mon, 16 Apr 2018 15:41:01 +0800
> Xiaolei Li <xiaolei.li@mediatek.com> wrote:
> 
> > Update ecc step size, ecc strength, and parity bits supported on
> > each MTK NAND controller.
> > 
> > Signed-off-by: Xiaolei Li <xiaolei.li@mediatek.com>
> > ---
> >  Documentation/devicetree/bindings/mtd/mtk-nand.txt | 18 +++++++++++++-----
> >  1 file changed, 13 insertions(+), 5 deletions(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/mtd/mtk-nand.txt b/Documentation/devicetree/bindings/mtd/mtk-nand.txt
> > index 1c88526..ef786568 100644
> > --- a/Documentation/devicetree/bindings/mtd/mtk-nand.txt
> > +++ b/Documentation/devicetree/bindings/mtd/mtk-nand.txt
> > @@ -50,14 +50,19 @@ Optional:
> >  - nand-on-flash-bbt:	Store BBT on NAND Flash.
> >  - nand-ecc-mode:	the NAND ecc mode (check driver for supported modes)
> >  - nand-ecc-step-size:	Number of data bytes covered by a single ECC step.
> > -			valid values: 512 and 1024.
> > +			valid values:
> > +			512 and 1024 on mt2701 and mt2712.
> > +			512 only on mt7622.
> >  			1024 is recommended for large page NANDs.
> >  - nand-ecc-strength:	Number of bits to correct per ECC step.
> > -			The valid values that the controller supports are: 4, 6,
> > -			8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36, 40, 44,
> > -			48, 52, 56, 60.
> > +			The valid values that each controller supports:
> > +			mt2701: 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28,
> > +				32, 36, 40, 44, 48, 52, 56, 60.
> > +			mt2712: 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28,
> > +				32, 36, 40, 44, 48, 52, 56, 60, 68, 72, 80.
> > +			mt7622: 4, 6, 8, 10, 12, 14, 16.
> >  			The strength should be calculated as follows:
> > -			E = (S - F) * 8 / 14
> > +			E = (S - F) * 8 / B
> >  			S = O / (P / Q)
> >  				E :	nand-ecc-strength.
> >  				S :	spare size per sector.
> > @@ -66,6 +71,9 @@ Optional:
> >  				O :	oob size.
> >  				P :	page size.
> >  				Q :	nand-ecc-step-size.
> > +				B :	parity bits to do 1 bit ECC.
> 
> Hm, this one is not clear. I guess what you wanted to say was "number
> of parity bits needed to correct 1 bitflip". Even if what you say is
Yes. It is.
> true, the value actually comes from the ECC step size, so I'm not
> sure this is really useful to explain why it's 14 or 13 in the
> dt-bindings doc.

According to MTK NAND controller design, this number depends on max ecc
step size that the MTK NAND controller supports. If max ecc step size
supported is 1024 bytes, then the number of parity bits will be always
14. And if max ecc step size is 512 bytes, it will be 13.

I will add this explanation in patch v3.
 
> 
> > +					Be 14 on mt2701 and mt2712.
> > +					Be 13 on mt7622.

> 					^ Should be
OK. Thanks.

> 
> You can keep only that part.
> 
> >  			If the result does not match any one of the listed
> >  			choices above, please select the smaller valid value from
> >  			the list.
> 

Re: [PATCH v2 1/4] dt-bindings: mtd: mtk-nand: Update properties description

[xiaolei li]

Hi Boris

On Fri, 2018-04-20 at 22:15 +0200, Boris Brezillon wrote:
> On Mon, 16 Apr 2018 15:41:01 +0800
> Xiaolei Li <xiaolei.li-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> wrote:
> 
> > Update ecc step size, ecc strength, and parity bits supported on
> > each MTK NAND controller.
> > 
> > Signed-off-by: Xiaolei Li <xiaolei.li-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> > ---
> >  Documentation/devicetree/bindings/mtd/mtk-nand.txt | 18 +++++++++++++-----
> >  1 file changed, 13 insertions(+), 5 deletions(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/mtd/mtk-nand.txt b/Documentation/devicetree/bindings/mtd/mtk-nand.txt
> > index 1c88526..ef786568 100644
> > --- a/Documentation/devicetree/bindings/mtd/mtk-nand.txt
> > +++ b/Documentation/devicetree/bindings/mtd/mtk-nand.txt
> > @@ -50,14 +50,19 @@ Optional:
> >  - nand-on-flash-bbt:	Store BBT on NAND Flash.
> >  - nand-ecc-mode:	the NAND ecc mode (check driver for supported modes)
> >  - nand-ecc-step-size:	Number of data bytes covered by a single ECC step.
> > -			valid values: 512 and 1024.
> > +			valid values:
> > +			512 and 1024 on mt2701 and mt2712.
> > +			512 only on mt7622.
> >  			1024 is recommended for large page NANDs.
> >  - nand-ecc-strength:	Number of bits to correct per ECC step.
> > -			The valid values that the controller supports are: 4, 6,
> > -			8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36, 40, 44,
> > -			48, 52, 56, 60.
> > +			The valid values that each controller supports:
> > +			mt2701: 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28,
> > +				32, 36, 40, 44, 48, 52, 56, 60.
> > +			mt2712: 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28,
> > +				32, 36, 40, 44, 48, 52, 56, 60, 68, 72, 80.
> > +			mt7622: 4, 6, 8, 10, 12, 14, 16.
> >  			The strength should be calculated as follows:
> > -			E = (S - F) * 8 / 14
> > +			E = (S - F) * 8 / B
> >  			S = O / (P / Q)
> >  				E :	nand-ecc-strength.
> >  				S :	spare size per sector.
> > @@ -66,6 +71,9 @@ Optional:
> >  				O :	oob size.
> >  				P :	page size.
> >  				Q :	nand-ecc-step-size.
> > +				B :	parity bits to do 1 bit ECC.
> 
> Hm, this one is not clear. I guess what you wanted to say was "number
> of parity bits needed to correct 1 bitflip". Even if what you say is
Yes. It is.
> true, the value actually comes from the ECC step size, so I'm not
> sure this is really useful to explain why it's 14 or 13 in the
> dt-bindings doc.

According to MTK NAND controller design, this number depends on max ecc
step size that the MTK NAND controller supports. If max ecc step size
supported is 1024 bytes, then the number of parity bits will be always
14. And if max ecc step size is 512 bytes, it will be 13.

I will add this explanation in patch v3.
 
> 
> > +					Be 14 on mt2701 and mt2712.
> > +					Be 13 on mt7622.

> 					^ Should be
OK. Thanks.

> 
> You can keep only that part.
> 
> >  			If the result does not match any one of the listed
> >  			choices above, please select the smaller valid value from
> >  			the list.
> 

Re: [PATCH v2 2/4] MAINTAINERS: Add entry for Mediatek NAND controller driver

[xiaolei li]

On Fri, 2018-04-20 at 22:24 +0200, Boris Brezillon wrote:
> On Mon, 16 Apr 2018 15:41:02 +0800
> Xiaolei Li <xiaolei.li@mediatek.com> wrote:
> 
> > Add entry for Mediatek NAND controller driver and its bindings.
> > 
> > Signed-off-by: Xiaolei Li <xiaolei.li@mediatek.com>
> > ---
> >  MAINTAINERS | 7 +++++++
> >  1 file changed, 7 insertions(+)
> > 
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index d262f17..429ef09 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -8838,6 +8838,13 @@ L:	linux-wireless@vger.kernel.org
> >  S:	Maintained
> >  F:	drivers/net/wireless/mediatek/mt7601u/
> >  
> > +MEDIATEK NAND CONTROLLER DRIVER
> > +M:	Xiaolei Li <xiaolei.li@mediatek.com>
> > +L:	linux-mtd@lists.infradead.org
> > +S:	Maintained
> > +F:	drivers/mtd/nand/raw/mtk_*
> > +F:	Documentation/devicetree/bindings/mtd/mtk-nand.txt
> 
> Thanks for doing that.
> 
> I'll apply the patch, you can drop it from your v3.
> 
OK. Thanks.

> > +
> >  MEDIATEK RANDOM NUMBER GENERATOR SUPPORT
> >  M:	Sean Wang <sean.wang@mediatek.com>
> >  S:	Maintained
> 

Re: [PATCH v2 2/4] MAINTAINERS: Add entry for Mediatek NAND controller driver

[xiaolei li]

On Fri, 2018-04-20 at 22:24 +0200, Boris Brezillon wrote:
> On Mon, 16 Apr 2018 15:41:02 +0800
> Xiaolei Li <xiaolei.li-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> wrote:
> 
> > Add entry for Mediatek NAND controller driver and its bindings.
> > 
> > Signed-off-by: Xiaolei Li <xiaolei.li-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> > ---
> >  MAINTAINERS | 7 +++++++
> >  1 file changed, 7 insertions(+)
> > 
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index d262f17..429ef09 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -8838,6 +8838,13 @@ L:	linux-wireless-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> >  S:	Maintained
> >  F:	drivers/net/wireless/mediatek/mt7601u/
> >  
> > +MEDIATEK NAND CONTROLLER DRIVER
> > +M:	Xiaolei Li <xiaolei.li-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> > +L:	linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> > +S:	Maintained
> > +F:	drivers/mtd/nand/raw/mtk_*
> > +F:	Documentation/devicetree/bindings/mtd/mtk-nand.txt
> 
> Thanks for doing that.
> 
> I'll apply the patch, you can drop it from your v3.
> 
OK. Thanks.

> > +
> >  MEDIATEK RANDOM NUMBER GENERATOR SUPPORT
> >  M:	Sean Wang <sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> >  S:	Maintained
> 

Re: [PATCH v2 3/4] mtd: rawnand: mtk: Replace max_sector_size with sector size array

[xiaolei li]

On Fri, 2018-04-20 at 22:18 +0200, Boris Brezillon wrote:
> On Mon, 16 Apr 2018 15:41:03 +0800
> Xiaolei Li <xiaolei.li@mediatek.com> wrote:
> 
> > Remove max_sector_size from struct mtk_nfc_caps, and use sector size
> > array and number of sector size to show sector sizes that controller
> > supports.
> > 
> > Signed-off-by: Xiaolei Li <xiaolei.li@mediatek.com>
> 
> I don't see the point of this patch. I was seeing a clear benefit when
> you were moving to the generic ECC selection code, but since you've
> dropped this part from the patch series, this patch becomes useless.
> 
> Am I missing something?

Very sorry. Forget to remove this patch.
Please ignore this patch. Thanks!

> 
> > ---
> >  drivers/mtd/nand/raw/mtk_nand.c | 32 +++++++++++++++++++++++++++-----
> >  1 file changed, 27 insertions(+), 5 deletions(-)
> > 
> > diff --git a/drivers/mtd/nand/raw/mtk_nand.c b/drivers/mtd/nand/raw/mtk_nand.c
> > index 6977da3..03a4df2 100644
> > --- a/drivers/mtd/nand/raw/mtk_nand.c
> > +++ b/drivers/mtd/nand/raw/mtk_nand.c
> > @@ -106,10 +106,11 @@
> >  struct mtk_nfc_caps {
> >  	const u8 *spare_size;
> >  	u8 num_spare_size;
> > +	const int *sector_size;
> > +	int num_sector_size;
> >  	u8 pageformat_spare_shift;
> >  	u8 nfi_clk_div;
> >  	u8 max_sector;
> > -	u32 max_sector_size;
> >  };
> >  
> >  struct mtk_nfc_bad_mark_ctl {
> > @@ -178,6 +179,14 @@ struct mtk_nfc {
> >  	16, 26, 27, 28
> >  };
> >  
> > +static const int sector_size_max_1k[] = {
> > +	1024, 512
> > +};
> > +
> > +static const int sector_size_max_512[] = {
> > +	512
> > +};
> > +
> >  static inline struct mtk_nfc_nand_chip *to_mtk_nand(struct nand_chip *nand)
> >  {
> >  	return container_of(nand, struct mtk_nfc_nand_chip, nand);
> > @@ -258,6 +267,16 @@ static inline u8 nfi_readb(struct mtk_nfc *nfc, u32 reg)
> >  	return readb_relaxed(nfc->regs + reg);
> >  }
> >  
> > +static int mtk_nfc_max_sector_size(struct mtk_nfc *nfc)
> > +{
> > +	int i, sector_size = 0;
> > +
> > +	for (i = 0; i < nfc->caps->num_sector_size; i++)
> > +		sector_size = max(sector_size, nfc->caps->sector_size[i]);
> > +
> > +	return sector_size;
> > +}
> > +
> >  static void mtk_nfc_hw_reset(struct mtk_nfc *nfc)
> >  {
> >  	struct device *dev = nfc->dev;
> > @@ -1207,7 +1226,7 @@ static int mtk_nfc_ecc_init(struct device *dev, struct mtd_info *mtd)
> >  		 */
> >  		if (nand->ecc.size < 1024) {
> >  			if (mtd->writesize > 512 &&
> > -			    nfc->caps->max_sector_size > 512) {
> > +			    mtk_nfc_max_sector_size(nfc) > 512) {
> >  				nand->ecc.size = 1024;
> >  				nand->ecc.strength <<= 1;
> >  			} else {
> > @@ -1389,28 +1408,31 @@ static int mtk_nfc_nand_chips_init(struct device *dev, struct mtk_nfc *nfc)
> >  static const struct mtk_nfc_caps mtk_nfc_caps_mt2701 = {
> >  	.spare_size = spare_size_mt2701,
> >  	.num_spare_size = 16,
> > +	.sector_size = sector_size_max_1k,
> > +	.num_sector_size = 2,
> >  	.pageformat_spare_shift = 4,
> >  	.nfi_clk_div = 1,
> >  	.max_sector = 16,
> > -	.max_sector_size = 1024,
> >  };
> >  
> >  static const struct mtk_nfc_caps mtk_nfc_caps_mt2712 = {
> >  	.spare_size = spare_size_mt2712,
> >  	.num_spare_size = 19,
> > +	.sector_size = sector_size_max_1k,
> > +	.num_sector_size = 2,
> >  	.pageformat_spare_shift = 16,
> >  	.nfi_clk_div = 2,
> >  	.max_sector = 16,
> > -	.max_sector_size = 1024,
> >  };
> >  
> >  static const struct mtk_nfc_caps mtk_nfc_caps_mt7622 = {
> >  	.spare_size = spare_size_mt7622,
> >  	.num_spare_size = 4,
> > +	.sector_size = sector_size_max_512,
> > +	.num_sector_size = 1,
> >  	.pageformat_spare_shift = 4,
> >  	.nfi_clk_div = 1,
> >  	.max_sector = 8,
> > -	.max_sector_size = 512,
> >  };
> >  
> >  static const struct of_device_id mtk_nfc_id_table[] = {
> 

Re: [PATCH v2 3/4] mtd: rawnand: mtk: Replace max_sector_size with sector size array

[xiaolei li]

On Fri, 2018-04-20 at 22:18 +0200, Boris Brezillon wrote:
> On Mon, 16 Apr 2018 15:41:03 +0800
> Xiaolei Li <xiaolei.li-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> wrote:
> 
> > Remove max_sector_size from struct mtk_nfc_caps, and use sector size
> > array and number of sector size to show sector sizes that controller
> > supports.
> > 
> > Signed-off-by: Xiaolei Li <xiaolei.li-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> 
> I don't see the point of this patch. I was seeing a clear benefit when
> you were moving to the generic ECC selection code, but since you've
> dropped this part from the patch series, this patch becomes useless.
> 
> Am I missing something?

Very sorry. Forget to remove this patch.
Please ignore this patch. Thanks!

> 
> > ---
> >  drivers/mtd/nand/raw/mtk_nand.c | 32 +++++++++++++++++++++++++++-----
> >  1 file changed, 27 insertions(+), 5 deletions(-)
> > 
> > diff --git a/drivers/mtd/nand/raw/mtk_nand.c b/drivers/mtd/nand/raw/mtk_nand.c
> > index 6977da3..03a4df2 100644
> > --- a/drivers/mtd/nand/raw/mtk_nand.c
> > +++ b/drivers/mtd/nand/raw/mtk_nand.c
> > @@ -106,10 +106,11 @@
> >  struct mtk_nfc_caps {
> >  	const u8 *spare_size;
> >  	u8 num_spare_size;
> > +	const int *sector_size;
> > +	int num_sector_size;
> >  	u8 pageformat_spare_shift;
> >  	u8 nfi_clk_div;
> >  	u8 max_sector;
> > -	u32 max_sector_size;
> >  };
> >  
> >  struct mtk_nfc_bad_mark_ctl {
> > @@ -178,6 +179,14 @@ struct mtk_nfc {
> >  	16, 26, 27, 28
> >  };
> >  
> > +static const int sector_size_max_1k[] = {
> > +	1024, 512
> > +};
> > +
> > +static const int sector_size_max_512[] = {
> > +	512
> > +};
> > +
> >  static inline struct mtk_nfc_nand_chip *to_mtk_nand(struct nand_chip *nand)
> >  {
> >  	return container_of(nand, struct mtk_nfc_nand_chip, nand);
> > @@ -258,6 +267,16 @@ static inline u8 nfi_readb(struct mtk_nfc *nfc, u32 reg)
> >  	return readb_relaxed(nfc->regs + reg);
> >  }
> >  
> > +static int mtk_nfc_max_sector_size(struct mtk_nfc *nfc)
> > +{
> > +	int i, sector_size = 0;
> > +
> > +	for (i = 0; i < nfc->caps->num_sector_size; i++)
> > +		sector_size = max(sector_size, nfc->caps->sector_size[i]);
> > +
> > +	return sector_size;
> > +}
> > +
> >  static void mtk_nfc_hw_reset(struct mtk_nfc *nfc)
> >  {
> >  	struct device *dev = nfc->dev;
> > @@ -1207,7 +1226,7 @@ static int mtk_nfc_ecc_init(struct device *dev, struct mtd_info *mtd)
> >  		 */
> >  		if (nand->ecc.size < 1024) {
> >  			if (mtd->writesize > 512 &&
> > -			    nfc->caps->max_sector_size > 512) {
> > +			    mtk_nfc_max_sector_size(nfc) > 512) {
> >  				nand->ecc.size = 1024;
> >  				nand->ecc.strength <<= 1;
> >  			} else {
> > @@ -1389,28 +1408,31 @@ static int mtk_nfc_nand_chips_init(struct device *dev, struct mtk_nfc *nfc)
> >  static const struct mtk_nfc_caps mtk_nfc_caps_mt2701 = {
> >  	.spare_size = spare_size_mt2701,
> >  	.num_spare_size = 16,
> > +	.sector_size = sector_size_max_1k,
> > +	.num_sector_size = 2,
> >  	.pageformat_spare_shift = 4,
> >  	.nfi_clk_div = 1,
> >  	.max_sector = 16,
> > -	.max_sector_size = 1024,
> >  };
> >  
> >  static const struct mtk_nfc_caps mtk_nfc_caps_mt2712 = {
> >  	.spare_size = spare_size_mt2712,
> >  	.num_spare_size = 19,
> > +	.sector_size = sector_size_max_1k,
> > +	.num_sector_size = 2,
> >  	.pageformat_spare_shift = 16,
> >  	.nfi_clk_div = 2,
> >  	.max_sector = 16,
> > -	.max_sector_size = 1024,
> >  };
> >  
> >  static const struct mtk_nfc_caps mtk_nfc_caps_mt7622 = {
> >  	.spare_size = spare_size_mt7622,
> >  	.num_spare_size = 4,
> > +	.sector_size = sector_size_max_512,
> > +	.num_sector_size = 1,
> >  	.pageformat_spare_shift = 4,
> >  	.nfi_clk_div = 1,
> >  	.max_sector = 8,
> > -	.max_sector_size = 512,
> >  };
> >  
> >  static const struct of_device_id mtk_nfc_id_table[] = {
> 

Re: [PATCH v2 4/4] mtd: rawnand: mtk: Add new nfc capability maximize_fdm_ecc

[xiaolei li]

Hi Boris

On Fri, 2018-04-20 at 22:23 +0200, Boris Brezillon wrote:
> On Mon, 16 Apr 2018 15:41:04 +0800
> Xiaolei Li <xiaolei.li@mediatek.com> wrote:
> 
> > For some MTK NAND chips, BootROM will access more than one byte
> > ECC protected FDM data, but now we fix ECC protected FDM byte as 1.
> > This will make some chips be failed to boot up.
> > 
> > This patch adds one new nfc capability maximize_fdm_ecc to maximize ECC
> > protected FDM bytes if it is true.
> > 
> > Signed-off-by: Xiaolei Li <xiaolei.li@mediatek.com>
> > ---
> >  drivers/mtd/nand/raw/mtk_nand.c | 8 ++++++--
> >  1 file changed, 6 insertions(+), 2 deletions(-)
> >  mode change 100644 => 100755 drivers/mtd/nand/raw/mtk_nand.c
> > 
> > diff --git a/drivers/mtd/nand/raw/mtk_nand.c b/drivers/mtd/nand/raw/mtk_nand.c
> > old mode 100644
> > new mode 100755
> > index 03a4df2..7025132
> > --- a/drivers/mtd/nand/raw/mtk_nand.c
> > +++ b/drivers/mtd/nand/raw/mtk_nand.c
> > @@ -111,6 +111,7 @@ struct mtk_nfc_caps {
> >  	u8 pageformat_spare_shift;
> >  	u8 nfi_clk_div;
> >  	u8 max_sector;
> > +	bool maximize_fdm_ecc;
> >  };
> >  
> >  struct mtk_nfc_bad_mark_ctl {
> > @@ -1151,8 +1152,8 @@ static void mtk_nfc_set_fdm(struct mtk_nfc_fdm *fdm, struct mtd_info *mtd)
> >  	if (fdm->reg_size > NFI_FDM_MAX_SIZE)
> >  		fdm->reg_size = NFI_FDM_MAX_SIZE;
> >  
> > -	/* bad block mark storage */
> > -	fdm->ecc_size = 1;
> > +	/* Reserve at least one byte for bad mark */
> > +	fdm->ecc_size = nfc->caps->maximize_fdm_ecc ? fdm->reg_size : 1;
> >  }
> >  
> >  static void mtk_nfc_set_bad_mark_ctl(struct mtk_nfc_bad_mark_ctl *bm_ctl,
> > @@ -1413,6 +1414,7 @@ static int mtk_nfc_nand_chips_init(struct device *dev, struct mtk_nfc *nfc)
> >  	.pageformat_spare_shift = 4,
> >  	.nfi_clk_div = 1,
> >  	.max_sector = 16,
> > +	.maximize_fdm_ecc = false,
> >  };
> >  
> >  static const struct mtk_nfc_caps mtk_nfc_caps_mt2712 = {
> > @@ -1423,6 +1425,7 @@ static int mtk_nfc_nand_chips_init(struct device *dev, struct mtk_nfc *nfc)
> >  	.pageformat_spare_shift = 16,
> >  	.nfi_clk_div = 2,
> >  	.max_sector = 16,
> > +	.maximize_fdm_ecc = false,
> >  };
> >  
> >  static const struct mtk_nfc_caps mtk_nfc_caps_mt7622 = {
> > @@ -1433,6 +1436,7 @@ static int mtk_nfc_nand_chips_init(struct device *dev, struct mtk_nfc *nfc)
> >  	.pageformat_spare_shift = 4,
> >  	.nfi_clk_div = 1,
> >  	.max_sector = 8,
> > +	.maximize_fdm_ecc = false,
> >  };
> 
> So, you introduce a new flag, but all existing SoCs are setting it to
> false. Can you please send a patch series containing all the
OK. Because some MTK SoCs that will apply "true" setting have not been
upstreamed now, so I think it is better to send a patch series in the
future as your advice.
I will remove this patch in v3. Sorry for making you confused.

Thanks.
Xiaolei

> modifications, or at least point to a branch containing all the changes
> you intend to push so that we know why the changes are required?
> Your first version of this patchset was better in this regard.
> 
> >  
> >  static const struct of_device_id mtk_nfc_id_table[] = {
> 

Re: [PATCH v2 4/4] mtd: rawnand: mtk: Add new nfc capability maximize_fdm_ecc

[xiaolei li]

Hi Boris

On Fri, 2018-04-20 at 22:23 +0200, Boris Brezillon wrote:
> On Mon, 16 Apr 2018 15:41:04 +0800
> Xiaolei Li <xiaolei.li-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> wrote:
> 
> > For some MTK NAND chips, BootROM will access more than one byte
> > ECC protected FDM data, but now we fix ECC protected FDM byte as 1.
> > This will make some chips be failed to boot up.
> > 
> > This patch adds one new nfc capability maximize_fdm_ecc to maximize ECC
> > protected FDM bytes if it is true.
> > 
> > Signed-off-by: Xiaolei Li <xiaolei.li-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> > ---
> >  drivers/mtd/nand/raw/mtk_nand.c | 8 ++++++--
> >  1 file changed, 6 insertions(+), 2 deletions(-)
> >  mode change 100644 => 100755 drivers/mtd/nand/raw/mtk_nand.c
> > 
> > diff --git a/drivers/mtd/nand/raw/mtk_nand.c b/drivers/mtd/nand/raw/mtk_nand.c
> > old mode 100644
> > new mode 100755
> > index 03a4df2..7025132
> > --- a/drivers/mtd/nand/raw/mtk_nand.c
> > +++ b/drivers/mtd/nand/raw/mtk_nand.c
> > @@ -111,6 +111,7 @@ struct mtk_nfc_caps {
> >  	u8 pageformat_spare_shift;
> >  	u8 nfi_clk_div;
> >  	u8 max_sector;
> > +	bool maximize_fdm_ecc;
> >  };
> >  
> >  struct mtk_nfc_bad_mark_ctl {
> > @@ -1151,8 +1152,8 @@ static void mtk_nfc_set_fdm(struct mtk_nfc_fdm *fdm, struct mtd_info *mtd)
> >  	if (fdm->reg_size > NFI_FDM_MAX_SIZE)
> >  		fdm->reg_size = NFI_FDM_MAX_SIZE;
> >  
> > -	/* bad block mark storage */
> > -	fdm->ecc_size = 1;
> > +	/* Reserve at least one byte for bad mark */
> > +	fdm->ecc_size = nfc->caps->maximize_fdm_ecc ? fdm->reg_size : 1;
> >  }
> >  
> >  static void mtk_nfc_set_bad_mark_ctl(struct mtk_nfc_bad_mark_ctl *bm_ctl,
> > @@ -1413,6 +1414,7 @@ static int mtk_nfc_nand_chips_init(struct device *dev, struct mtk_nfc *nfc)
> >  	.pageformat_spare_shift = 4,
> >  	.nfi_clk_div = 1,
> >  	.max_sector = 16,
> > +	.maximize_fdm_ecc = false,
> >  };
> >  
> >  static const struct mtk_nfc_caps mtk_nfc_caps_mt2712 = {
> > @@ -1423,6 +1425,7 @@ static int mtk_nfc_nand_chips_init(struct device *dev, struct mtk_nfc *nfc)
> >  	.pageformat_spare_shift = 16,
> >  	.nfi_clk_div = 2,
> >  	.max_sector = 16,
> > +	.maximize_fdm_ecc = false,
> >  };
> >  
> >  static const struct mtk_nfc_caps mtk_nfc_caps_mt7622 = {
> > @@ -1433,6 +1436,7 @@ static int mtk_nfc_nand_chips_init(struct device *dev, struct mtk_nfc *nfc)
> >  	.pageformat_spare_shift = 4,
> >  	.nfi_clk_div = 1,
> >  	.max_sector = 8,
> > +	.maximize_fdm_ecc = false,
> >  };
> 
> So, you introduce a new flag, but all existing SoCs are setting it to
> false. Can you please send a patch series containing all the
OK. Because some MTK SoCs that will apply "true" setting have not been
upstreamed now, so I think it is better to send a patch series in the
future as your advice.
I will remove this patch in v3. Sorry for making you confused.

Thanks.
Xiaolei

> modifications, or at least point to a branch containing all the changes
> you intend to push so that we know why the changes are required?
> Your first version of this patchset was better in this regard.
> 
> >  
> >  static const struct of_device_id mtk_nfc_id_table[] = {
>