* [DPU PATCH v3 1/2] drm/msm/dsi: check video mode engine status before waiting
@ 2018-04-17 1:56 Abhinav Kumar
[not found] ` <1523930206-6304-1-git-send-email-abhinavk-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2018-04-17 20:25 ` [DPU PATCH v3 1/2] drm/msm/dsi: check video mode engine status before waiting Sean Paul
0 siblings, 2 replies; 4+ messages in thread
From: Abhinav Kumar @ 2018-04-17 1:56 UTC (permalink / raw)
To: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA
Cc: architt-sgV2jX0FEOL9JmXXK+q4OQ, jeykumar-jfJNa2p1gH1BDgjK7y7TUQ,
Abhinav Kumar, robdclark-Re5JQEeQqe8AvxtiuMwx3w,
nganji-sgV2jX0FEOL9JmXXK+q4OQ, seanpaul-F7+t8E8rja9g9hUCZPvPmw,
hoegsberg-hpIqsD4AKlfQT0dZR+AlfA, jsanka-sgV2jX0FEOL9JmXXK+q4OQ,
chandanu-sgV2jX0FEOL9JmXXK+q4OQ
Make sure the video mode engine is on before waiting
for the video done interrupt.
Changes in v2:
- Replace pr_err with dev_err
- Changed error message
Changes in v3:
- Move the return value check to another
patch
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 7a03a94..8df0d44 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -173,6 +173,7 @@ struct msm_dsi_host {
bool registered;
bool power_on;
+ bool enabled;
int irq;
};
@@ -1001,7 +1002,7 @@ static void dsi_wait4video_eng_busy(struct msm_dsi_host *msm_host)
if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO))
return;
- if (msm_host->power_on) {
+ if (msm_host->power_on && msm_host->enabled) {
dsi_wait4video_done(msm_host);
/* delay 4 ms to skip BLLP */
usleep_range(2000, 4000);
@@ -2203,7 +2204,7 @@ int msm_dsi_host_enable(struct mipi_dsi_host *host)
* pm_runtime_put_autosuspend(&msm_host->pdev->dev);
* }
*/
-
+ msm_host->enabled = true;
return 0;
}
@@ -2219,7 +2220,7 @@ int msm_dsi_host_disable(struct mipi_dsi_host *host)
* Reset to disable video engine so that we can send off cmd.
*/
dsi_sw_reset(msm_host);
-
+ msm_host->enabled = false;
return 0;
}
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
_______________________________________________
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [DPU PATCH v3 2/2] drm/msm/dsi: implement auto PHY timing calculator for 10nm PHY
[not found] ` <1523930206-6304-1-git-send-email-abhinavk-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
@ 2018-04-17 1:56 ` Abhinav Kumar
0 siblings, 0 replies; 4+ messages in thread
From: Abhinav Kumar @ 2018-04-17 1:56 UTC (permalink / raw)
To: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA
Cc: architt-sgV2jX0FEOL9JmXXK+q4OQ, jeykumar-jfJNa2p1gH1BDgjK7y7TUQ,
Abhinav Kumar, robdclark-Re5JQEeQqe8AvxtiuMwx3w,
nganji-sgV2jX0FEOL9JmXXK+q4OQ, seanpaul-F7+t8E8rja9g9hUCZPvPmw,
hoegsberg-hpIqsD4AKlfQT0dZR+AlfA, jsanka-sgV2jX0FEOL9JmXXK+q4OQ,
chandanu-sgV2jX0FEOL9JmXXK+q4OQ
Currently the DSI PHY timings are hard-coded for a specific panel
for the 10nm PHY.
Replace this with the auto PHY timing calculator which can calculate
the PHY timings for any panel.
Changes in v3:
- None
Changes in v2:
- None
Reviewed-by: Sean Paul <seanpaul@chromium.org>
Reviewed-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 109 +++++++++++++++++++++++++++++
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 2 +
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 28 --------
3 files changed, 111 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
index 8e9d5c2..9a9fa0c 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
@@ -265,6 +265,115 @@ int msm_dsi_dphy_timing_calc_v2(struct msm_dsi_dphy_timing *timing,
return 0;
}
+int msm_dsi_dphy_timing_calc_v3(struct msm_dsi_dphy_timing *timing,
+ struct msm_dsi_phy_clk_request *clk_req)
+{
+ const unsigned long bit_rate = clk_req->bitclk_rate;
+ const unsigned long esc_rate = clk_req->escclk_rate;
+ s32 ui, ui_x8, lpx;
+ s32 tmax, tmin;
+ s32 pcnt0 = 50;
+ s32 pcnt1 = 50;
+ s32 pcnt2 = 10;
+ s32 pcnt3 = 30;
+ s32 pcnt4 = 10;
+ s32 pcnt5 = 2;
+ s32 coeff = 1000; /* Precision, should avoid overflow */
+ s32 hb_en, hb_en_ckln;
+ s32 temp;
+
+ if (!bit_rate || !esc_rate)
+ return -EINVAL;
+
+ timing->hs_halfbyte_en = 0;
+ hb_en = 0;
+ timing->hs_halfbyte_en_ckln = 0;
+ hb_en_ckln = 0;
+
+ ui = mult_frac(NSEC_PER_MSEC, coeff, bit_rate / 1000);
+ ui_x8 = ui << 3;
+ lpx = mult_frac(NSEC_PER_MSEC, coeff, esc_rate / 1000);
+
+ temp = S_DIV_ROUND_UP(38 * coeff, ui_x8);
+ tmin = max_t(s32, temp, 0);
+ temp = (95 * coeff) / ui_x8;
+ tmax = max_t(s32, temp, 0);
+ timing->clk_prepare = linear_inter(tmax, tmin, pcnt0, 0, false);
+
+ temp = 300 * coeff - (timing->clk_prepare << 3) * ui;
+ tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1;
+ tmax = (tmin > 255) ? 511 : 255;
+ timing->clk_zero = linear_inter(tmax, tmin, pcnt5, 0, false);
+
+ tmin = DIV_ROUND_UP(60 * coeff + 3 * ui, ui_x8);
+ temp = 105 * coeff + 12 * ui - 20 * coeff;
+ tmax = (temp + 3 * ui) / ui_x8;
+ timing->clk_trail = linear_inter(tmax, tmin, pcnt3, 0, false);
+
+ temp = S_DIV_ROUND_UP(40 * coeff + 4 * ui, ui_x8);
+ tmin = max_t(s32, temp, 0);
+ temp = (85 * coeff + 6 * ui) / ui_x8;
+ tmax = max_t(s32, temp, 0);
+ timing->hs_prepare = linear_inter(tmax, tmin, pcnt1, 0, false);
+
+ temp = 145 * coeff + 10 * ui - (timing->hs_prepare << 3) * ui;
+ tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1;
+ tmax = 255;
+ timing->hs_zero = linear_inter(tmax, tmin, pcnt4, 0, false);
+
+ tmin = DIV_ROUND_UP(60 * coeff + 4 * ui, ui_x8) - 1;
+ temp = 105 * coeff + 12 * ui - 20 * coeff;
+ tmax = (temp / ui_x8) - 1;
+ timing->hs_trail = linear_inter(tmax, tmin, pcnt3, 0, false);
+
+ temp = 50 * coeff + ((hb_en << 2) - 8) * ui;
+ timing->hs_rqst = S_DIV_ROUND_UP(temp, ui_x8);
+
+ tmin = DIV_ROUND_UP(100 * coeff, ui_x8) - 1;
+ tmax = 255;
+ timing->hs_exit = linear_inter(tmax, tmin, pcnt2, 0, false);
+
+ temp = 50 * coeff + ((hb_en_ckln << 2) - 8) * ui;
+ timing->hs_rqst_ckln = S_DIV_ROUND_UP(temp, ui_x8);
+
+ temp = 60 * coeff + 52 * ui - 43 * ui;
+ tmin = DIV_ROUND_UP(temp, ui_x8) - 1;
+ tmax = 63;
+ timing->shared_timings.clk_post =
+ linear_inter(tmax, tmin, pcnt2, 0, false);
+
+ temp = 8 * ui + (timing->clk_prepare << 3) * ui;
+ temp += (((timing->clk_zero + 3) << 3) + 11) * ui;
+ temp += hb_en_ckln ? (((timing->hs_rqst_ckln << 3) + 4) * ui) :
+ (((timing->hs_rqst_ckln << 3) + 8) * ui);
+ tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1;
+ tmax = 63;
+ if (tmin > tmax) {
+ temp = linear_inter(tmax << 1, tmin, pcnt2, 0, false);
+ timing->shared_timings.clk_pre = temp >> 1;
+ timing->shared_timings.clk_pre_inc_by_2 = 1;
+ } else {
+ timing->shared_timings.clk_pre =
+ linear_inter(tmax, tmin, pcnt2, 0, false);
+ timing->shared_timings.clk_pre_inc_by_2 = 0;
+ }
+
+ timing->ta_go = 3;
+ timing->ta_sure = 0;
+ timing->ta_get = 4;
+
+ DBG("%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d",
+ timing->shared_timings.clk_pre, timing->shared_timings.clk_post,
+ timing->shared_timings.clk_pre_inc_by_2, timing->clk_zero,
+ timing->clk_trail, timing->clk_prepare, timing->hs_exit,
+ timing->hs_zero, timing->hs_prepare, timing->hs_trail,
+ timing->hs_rqst, timing->hs_rqst_ckln, timing->hs_halfbyte_en,
+ timing->hs_halfbyte_en_ckln, timing->hs_prep_dly,
+ timing->hs_prep_dly_ckln);
+
+ return 0;
+}
+
void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg,
u32 bit_mask)
{
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
index c56268c..a24ab80 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
@@ -101,6 +101,8 @@ int msm_dsi_dphy_timing_calc(struct msm_dsi_dphy_timing *timing,
struct msm_dsi_phy_clk_request *clk_req);
int msm_dsi_dphy_timing_calc_v2(struct msm_dsi_dphy_timing *timing,
struct msm_dsi_phy_clk_request *clk_req);
+int msm_dsi_dphy_timing_calc_v3(struct msm_dsi_dphy_timing *timing,
+ struct msm_dsi_phy_clk_request *clk_req);
void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg,
u32 bit_mask);
int msm_dsi_phy_init_common(struct msm_dsi_phy *phy);
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
index 0af951a..b3fffc8 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
@@ -79,34 +79,6 @@ static void dsi_phy_hw_v3_0_lane_settings(struct msm_dsi_phy *phy)
dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_TX_DCTRL(3), 0x04);
}
-static int msm_dsi_dphy_timing_calc_v3(struct msm_dsi_dphy_timing *timing,
- struct msm_dsi_phy_clk_request *clk_req)
-{
- /*
- * TODO: These params need to be computed, they're currently hardcoded
- * for a 1440x2560@60Hz panel with a byteclk of 100.618 Mhz, and a
- * default escape clock of 19.2 Mhz.
- */
-
- timing->hs_halfbyte_en = 0;
- timing->clk_zero = 0x1c;
- timing->clk_prepare = 0x07;
- timing->clk_trail = 0x07;
- timing->hs_exit = 0x23;
- timing->hs_zero = 0x21;
- timing->hs_prepare = 0x07;
- timing->hs_trail = 0x07;
- timing->hs_rqst = 0x05;
- timing->ta_sure = 0x00;
- timing->ta_go = 0x03;
- timing->ta_get = 0x04;
-
- timing->shared_timings.clk_pre = 0x2d;
- timing->shared_timings.clk_post = 0x0d;
-
- return 0;
-}
-
static int dsi_10nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
struct msm_dsi_phy_clk_request *clk_req)
{
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
_______________________________________________
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [DPU PATCH v3 1/2] drm/msm/dsi: check video mode engine status before waiting
2018-04-17 1:56 [DPU PATCH v3 1/2] drm/msm/dsi: check video mode engine status before waiting Abhinav Kumar
[not found] ` <1523930206-6304-1-git-send-email-abhinavk-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
@ 2018-04-17 20:25 ` Sean Paul
2018-04-17 20:41 ` abhinavk
1 sibling, 1 reply; 4+ messages in thread
From: Sean Paul @ 2018-04-17 20:25 UTC (permalink / raw)
To: Abhinav Kumar
Cc: jeykumar, linux-arm-msm, dri-devel, hoegsberg, freedreno, chandanu
On Mon, Apr 16, 2018 at 06:56:45PM -0700, Abhinav Kumar wrote:
> Make sure the video mode engine is on before waiting
> for the video done interrupt.
>
> Changes in v2:
> - Replace pr_err with dev_err
> - Changed error message
>
> Changes in v3:
> - Move the return value check to another
> patch
>
> Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
> ---
> drivers/gpu/drm/msm/dsi/dsi_host.c | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
> index 7a03a94..8df0d44 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
> @@ -173,6 +173,7 @@ struct msm_dsi_host {
>
> bool registered;
> bool power_on;
> + bool enabled;
> int irq;
> };
>
> @@ -1001,7 +1002,7 @@ static void dsi_wait4video_eng_busy(struct msm_dsi_host *msm_host)
> if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO))
> return;
>
> - if (msm_host->power_on) {
> + if (msm_host->power_on && msm_host->enabled) {
> dsi_wait4video_done(msm_host);
> /* delay 4 ms to skip BLLP */
> usleep_range(2000, 4000);
> @@ -2203,7 +2204,7 @@ int msm_dsi_host_enable(struct mipi_dsi_host *host)
> * pm_runtime_put_autosuspend(&msm_host->pdev->dev);
> * }
> */
> -
> + msm_host->enabled = true;
> return 0;
> }
>
> @@ -2219,7 +2220,7 @@ int msm_dsi_host_disable(struct mipi_dsi_host *host)
> * Reset to disable video engine so that we can send off cmd.
> */
> dsi_sw_reset(msm_host);
> -
> + msm_host->enabled = false;
I thought this was moving to the start of the function?
> return 0;
> }
>
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
--
Sean Paul, Software Engineer, Google / Chromium OS
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [DPU PATCH v3 1/2] drm/msm/dsi: check video mode engine status before waiting
2018-04-17 20:25 ` [DPU PATCH v3 1/2] drm/msm/dsi: check video mode engine status before waiting Sean Paul
@ 2018-04-17 20:41 ` abhinavk
0 siblings, 0 replies; 4+ messages in thread
From: abhinavk @ 2018-04-17 20:41 UTC (permalink / raw)
To: Sean Paul
Cc: jeykumar, linux-arm-msm, dri-devel, hoegsberg, freedreno, chandanu
On 2018-04-17 13:25, Sean Paul wrote:
> On Mon, Apr 16, 2018 at 06:56:45PM -0700, Abhinav Kumar wrote:
>> Make sure the video mode engine is on before waiting
>> for the video done interrupt.
>>
>> Changes in v2:
>> - Replace pr_err with dev_err
>> - Changed error message
>>
>> Changes in v3:
>> - Move the return value check to another
>> patch
>>
>> Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
>> ---
>> drivers/gpu/drm/msm/dsi/dsi_host.c | 7 ++++---
>> 1 file changed, 4 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
>> b/drivers/gpu/drm/msm/dsi/dsi_host.c
>> index 7a03a94..8df0d44 100644
>> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
>> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
>> @@ -173,6 +173,7 @@ struct msm_dsi_host {
>>
>> bool registered;
>> bool power_on;
>> + bool enabled;
>> int irq;
>> };
>>
>> @@ -1001,7 +1002,7 @@ static void dsi_wait4video_eng_busy(struct
>> msm_dsi_host *msm_host)
>> if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO))
>> return;
>>
>> - if (msm_host->power_on) {
>> + if (msm_host->power_on && msm_host->enabled) {
>> dsi_wait4video_done(msm_host);
>> /* delay 4 ms to skip BLLP */
>> usleep_range(2000, 4000);
>> @@ -2203,7 +2204,7 @@ int msm_dsi_host_enable(struct mipi_dsi_host
>> *host)
>> * pm_runtime_put_autosuspend(&msm_host->pdev->dev);
>> * }
>> */
>> -
>> + msm_host->enabled = true;
>> return 0;
>> }
>>
>> @@ -2219,7 +2220,7 @@ int msm_dsi_host_disable(struct mipi_dsi_host
>> *host)
>> * Reset to disable video engine so that we can send off cmd.
>> */
>> dsi_sw_reset(msm_host);
>> -
>> + msm_host->enabled = false;
>
> I thought this was moving to the start of the function?
>
[Abhinav] Yes, my bad. While rebasing that review comment was left out.
Uploading v4 right now
>> return 0;
>> }
>>
>> --
>> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
>> Forum,
>> a Linux Foundation Collaborative Project
>>
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2018-04-17 20:41 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-04-17 1:56 [DPU PATCH v3 1/2] drm/msm/dsi: check video mode engine status before waiting Abhinav Kumar
[not found] ` <1523930206-6304-1-git-send-email-abhinavk-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2018-04-17 1:56 ` [DPU PATCH v3 2/2] drm/msm/dsi: implement auto PHY timing calculator for 10nm PHY Abhinav Kumar
2018-04-17 20:25 ` [DPU PATCH v3 1/2] drm/msm/dsi: check video mode engine status before waiting Sean Paul
2018-04-17 20:41 ` abhinavk
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