* [PATCH v3] Improve MTK NAND driver
@ 2018-04-24 2:11 ` Xiaolei Li
0 siblings, 0 replies; 6+ messages in thread
From: Xiaolei Li @ 2018-04-24 2:11 UTC (permalink / raw)
To: boris.brezillon; +Cc: linux-mtd, linux-mediatek, srv_heupstream, xiaolei.li
This patch fixes some MTK NAND driver DT binding description errors.
Changes relative to:
--------------------
tree : https://github.com/bbrezillon/linux-0day
branch : nand/next
commit :
'commit ba4150b1ec2a ("mtd: rawnand: s3c2410: enhance the probe
function error path")'
Patch v3:
- Remove max_sector_size change. It is uselees now.
- Remove maximize_fdm_ecc new caps patch. Send a patch series for this
change in the future.
- Remove MTK NAND Controller maintainers entry patch. This patch was
accepted in patch v2.
Patch v2:
- Add new nfc capability instead of defining new DT property.
- Remove not backward compat patches about nand-ecc-maximize.
Xiaolei Li (1):
dt-bindings: mtd: mtk-nand: Update properties description
Documentation/devicetree/bindings/mtd/mtk-nand.txt | 24 +++++++++++++++++-----
1 file changed, 19 insertions(+), 5 deletions(-)
--
1.9.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v3] Improve MTK NAND driver
@ 2018-04-24 2:11 ` Xiaolei Li
0 siblings, 0 replies; 6+ messages in thread
From: Xiaolei Li @ 2018-04-24 2:11 UTC (permalink / raw)
To: boris.brezillon; +Cc: linux-mediatek, xiaolei.li, linux-mtd, srv_heupstream
This patch fixes some MTK NAND driver DT binding description errors.
Changes relative to:
--------------------
tree : https://github.com/bbrezillon/linux-0day
branch : nand/next
commit :
'commit ba4150b1ec2a ("mtd: rawnand: s3c2410: enhance the probe
function error path")'
Patch v3:
- Remove max_sector_size change. It is uselees now.
- Remove maximize_fdm_ecc new caps patch. Send a patch series for this
change in the future.
- Remove MTK NAND Controller maintainers entry patch. This patch was
accepted in patch v2.
Patch v2:
- Add new nfc capability instead of defining new DT property.
- Remove not backward compat patches about nand-ecc-maximize.
Xiaolei Li (1):
dt-bindings: mtd: mtk-nand: Update properties description
Documentation/devicetree/bindings/mtd/mtk-nand.txt | 24 +++++++++++++++++-----
1 file changed, 19 insertions(+), 5 deletions(-)
--
1.9.1
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v3] dt-bindings: mtd: mtk-nand: Update properties description
2018-04-24 2:11 ` Xiaolei Li
@ 2018-04-24 2:11 ` Xiaolei Li
-1 siblings, 0 replies; 6+ messages in thread
From: Xiaolei Li @ 2018-04-24 2:11 UTC (permalink / raw)
To: boris.brezillon; +Cc: linux-mtd, linux-mediatek, srv_heupstream, xiaolei.li
Update ecc step size, ecc strength, and parity bits supported on
each MTK NAND controller.
Signed-off-by: Xiaolei Li <xiaolei.li@mediatek.com>
---
Documentation/devicetree/bindings/mtd/mtk-nand.txt | 24 +++++++++++++++++-----
1 file changed, 19 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/mtd/mtk-nand.txt b/Documentation/devicetree/bindings/mtd/mtk-nand.txt
index 1c88526..f20ab4a 100644
--- a/Documentation/devicetree/bindings/mtd/mtk-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/mtk-nand.txt
@@ -50,14 +50,19 @@ Optional:
- nand-on-flash-bbt: Store BBT on NAND Flash.
- nand-ecc-mode: the NAND ecc mode (check driver for supported modes)
- nand-ecc-step-size: Number of data bytes covered by a single ECC step.
- valid values: 512 and 1024.
+ valid values:
+ 512 and 1024 on mt2701 and mt2712.
+ 512 only on mt7622.
1024 is recommended for large page NANDs.
- nand-ecc-strength: Number of bits to correct per ECC step.
- The valid values that the controller supports are: 4, 6,
- 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36, 40, 44,
- 48, 52, 56, 60.
+ The valid values that each controller supports:
+ mt2701: 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28,
+ 32, 36, 40, 44, 48, 52, 56, 60.
+ mt2712: 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28,
+ 32, 36, 40, 44, 48, 52, 56, 60, 68, 72, 80.
+ mt7622: 4, 6, 8, 10, 12, 14, 16.
The strength should be calculated as follows:
- E = (S - F) * 8 / 14
+ E = (S - F) * 8 / B
S = O / (P / Q)
E : nand-ecc-strength.
S : spare size per sector.
@@ -66,6 +71,15 @@ Optional:
O : oob size.
P : page size.
Q : nand-ecc-step-size.
+ B : number of parity bits needed to correct
+ 1 bitflip.
+ According to MTK NAND controller design,
+ this number depends on max ecc step size
+ that MTK NAND controller supports.
+ If max ecc step size supported is 1024,
+ then it should be always 14. And if max
+ ecc step size is 512, then it should be
+ always 13.
If the result does not match any one of the listed
choices above, please select the smaller valid value from
the list.
--
1.9.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v3] dt-bindings: mtd: mtk-nand: Update properties description
@ 2018-04-24 2:11 ` Xiaolei Li
0 siblings, 0 replies; 6+ messages in thread
From: Xiaolei Li @ 2018-04-24 2:11 UTC (permalink / raw)
To: boris.brezillon; +Cc: linux-mediatek, xiaolei.li, linux-mtd, srv_heupstream
Update ecc step size, ecc strength, and parity bits supported on
each MTK NAND controller.
Signed-off-by: Xiaolei Li <xiaolei.li@mediatek.com>
---
Documentation/devicetree/bindings/mtd/mtk-nand.txt | 24 +++++++++++++++++-----
1 file changed, 19 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/mtd/mtk-nand.txt b/Documentation/devicetree/bindings/mtd/mtk-nand.txt
index 1c88526..f20ab4a 100644
--- a/Documentation/devicetree/bindings/mtd/mtk-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/mtk-nand.txt
@@ -50,14 +50,19 @@ Optional:
- nand-on-flash-bbt: Store BBT on NAND Flash.
- nand-ecc-mode: the NAND ecc mode (check driver for supported modes)
- nand-ecc-step-size: Number of data bytes covered by a single ECC step.
- valid values: 512 and 1024.
+ valid values:
+ 512 and 1024 on mt2701 and mt2712.
+ 512 only on mt7622.
1024 is recommended for large page NANDs.
- nand-ecc-strength: Number of bits to correct per ECC step.
- The valid values that the controller supports are: 4, 6,
- 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36, 40, 44,
- 48, 52, 56, 60.
+ The valid values that each controller supports:
+ mt2701: 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28,
+ 32, 36, 40, 44, 48, 52, 56, 60.
+ mt2712: 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28,
+ 32, 36, 40, 44, 48, 52, 56, 60, 68, 72, 80.
+ mt7622: 4, 6, 8, 10, 12, 14, 16.
The strength should be calculated as follows:
- E = (S - F) * 8 / 14
+ E = (S - F) * 8 / B
S = O / (P / Q)
E : nand-ecc-strength.
S : spare size per sector.
@@ -66,6 +71,15 @@ Optional:
O : oob size.
P : page size.
Q : nand-ecc-step-size.
+ B : number of parity bits needed to correct
+ 1 bitflip.
+ According to MTK NAND controller design,
+ this number depends on max ecc step size
+ that MTK NAND controller supports.
+ If max ecc step size supported is 1024,
+ then it should be always 14. And if max
+ ecc step size is 512, then it should be
+ always 13.
If the result does not match any one of the listed
choices above, please select the smaller valid value from
the list.
--
1.9.1
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v3] dt-bindings: mtd: mtk-nand: Update properties description
@ 2018-04-26 20:09 ` Boris Brezillon
0 siblings, 0 replies; 6+ messages in thread
From: Boris Brezillon @ 2018-04-26 20:09 UTC (permalink / raw)
To: Xiaolei Li; +Cc: linux-mediatek, linux-mtd, srv_heupstream
On Tue, 24 Apr 2018 10:11:07 +0800
Xiaolei Li <xiaolei.li@mediatek.com> wrote:
> Update ecc step size, ecc strength, and parity bits supported on
> each MTK NAND controller.
>
> Signed-off-by: Xiaolei Li <xiaolei.li@mediatek.com>
Applied.
Thanks,
Boris
> ---
> Documentation/devicetree/bindings/mtd/mtk-nand.txt | 24 +++++++++++++++++-----
> 1 file changed, 19 insertions(+), 5 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/mtd/mtk-nand.txt b/Documentation/devicetree/bindings/mtd/mtk-nand.txt
> index 1c88526..f20ab4a 100644
> --- a/Documentation/devicetree/bindings/mtd/mtk-nand.txt
> +++ b/Documentation/devicetree/bindings/mtd/mtk-nand.txt
> @@ -50,14 +50,19 @@ Optional:
> - nand-on-flash-bbt: Store BBT on NAND Flash.
> - nand-ecc-mode: the NAND ecc mode (check driver for supported modes)
> - nand-ecc-step-size: Number of data bytes covered by a single ECC step.
> - valid values: 512 and 1024.
> + valid values:
> + 512 and 1024 on mt2701 and mt2712.
> + 512 only on mt7622.
> 1024 is recommended for large page NANDs.
> - nand-ecc-strength: Number of bits to correct per ECC step.
> - The valid values that the controller supports are: 4, 6,
> - 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36, 40, 44,
> - 48, 52, 56, 60.
> + The valid values that each controller supports:
> + mt2701: 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28,
> + 32, 36, 40, 44, 48, 52, 56, 60.
> + mt2712: 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28,
> + 32, 36, 40, 44, 48, 52, 56, 60, 68, 72, 80.
> + mt7622: 4, 6, 8, 10, 12, 14, 16.
> The strength should be calculated as follows:
> - E = (S - F) * 8 / 14
> + E = (S - F) * 8 / B
> S = O / (P / Q)
> E : nand-ecc-strength.
> S : spare size per sector.
> @@ -66,6 +71,15 @@ Optional:
> O : oob size.
> P : page size.
> Q : nand-ecc-step-size.
> + B : number of parity bits needed to correct
> + 1 bitflip.
> + According to MTK NAND controller design,
> + this number depends on max ecc step size
> + that MTK NAND controller supports.
> + If max ecc step size supported is 1024,
> + then it should be always 14. And if max
> + ecc step size is 512, then it should be
> + always 13.
> If the result does not match any one of the listed
> choices above, please select the smaller valid value from
> the list.
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v3] dt-bindings: mtd: mtk-nand: Update properties description
@ 2018-04-26 20:09 ` Boris Brezillon
0 siblings, 0 replies; 6+ messages in thread
From: Boris Brezillon @ 2018-04-26 20:09 UTC (permalink / raw)
To: Xiaolei Li
Cc: linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
srv_heupstream-NuS5LvNUpcJWk0Htik3J/w
On Tue, 24 Apr 2018 10:11:07 +0800
Xiaolei Li <xiaolei.li-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> wrote:
> Update ecc step size, ecc strength, and parity bits supported on
> each MTK NAND controller.
>
> Signed-off-by: Xiaolei Li <xiaolei.li-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
Applied.
Thanks,
Boris
> ---
> Documentation/devicetree/bindings/mtd/mtk-nand.txt | 24 +++++++++++++++++-----
> 1 file changed, 19 insertions(+), 5 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/mtd/mtk-nand.txt b/Documentation/devicetree/bindings/mtd/mtk-nand.txt
> index 1c88526..f20ab4a 100644
> --- a/Documentation/devicetree/bindings/mtd/mtk-nand.txt
> +++ b/Documentation/devicetree/bindings/mtd/mtk-nand.txt
> @@ -50,14 +50,19 @@ Optional:
> - nand-on-flash-bbt: Store BBT on NAND Flash.
> - nand-ecc-mode: the NAND ecc mode (check driver for supported modes)
> - nand-ecc-step-size: Number of data bytes covered by a single ECC step.
> - valid values: 512 and 1024.
> + valid values:
> + 512 and 1024 on mt2701 and mt2712.
> + 512 only on mt7622.
> 1024 is recommended for large page NANDs.
> - nand-ecc-strength: Number of bits to correct per ECC step.
> - The valid values that the controller supports are: 4, 6,
> - 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36, 40, 44,
> - 48, 52, 56, 60.
> + The valid values that each controller supports:
> + mt2701: 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28,
> + 32, 36, 40, 44, 48, 52, 56, 60.
> + mt2712: 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28,
> + 32, 36, 40, 44, 48, 52, 56, 60, 68, 72, 80.
> + mt7622: 4, 6, 8, 10, 12, 14, 16.
> The strength should be calculated as follows:
> - E = (S - F) * 8 / 14
> + E = (S - F) * 8 / B
> S = O / (P / Q)
> E : nand-ecc-strength.
> S : spare size per sector.
> @@ -66,6 +71,15 @@ Optional:
> O : oob size.
> P : page size.
> Q : nand-ecc-step-size.
> + B : number of parity bits needed to correct
> + 1 bitflip.
> + According to MTK NAND controller design,
> + this number depends on max ecc step size
> + that MTK NAND controller supports.
> + If max ecc step size supported is 1024,
> + then it should be always 14. And if max
> + ecc step size is 512, then it should be
> + always 13.
> If the result does not match any one of the listed
> choices above, please select the smaller valid value from
> the list.
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2018-04-26 20:09 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
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2018-04-24 2:11 [PATCH v3] Improve MTK NAND driver Xiaolei Li
2018-04-24 2:11 ` Xiaolei Li
2018-04-24 2:11 ` [PATCH v3] dt-bindings: mtd: mtk-nand: Update properties description Xiaolei Li
2018-04-24 2:11 ` Xiaolei Li
2018-04-26 20:09 ` Boris Brezillon
2018-04-26 20:09 ` Boris Brezillon
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