[PATCH 0/2] Add QCOM video clock controller driver

[PATCH 0/2] Add QCOM video clock controller driver

[Amit Nischal]

This patch series adds a driver and device tree documentation binding
for the video clock controller on some Qualcomm Technologies, Inc, SoCs
such as SDM845. This would allow video drivers to probe and control their
clocks.

The video clock driver depends upon the RPMh driver[1], command DB driver[2],
RPMh clock driver[3], rcg2 shared ops[4] changes which are undergoing review.

[1]: https://lkml.org/lkml/2018/4/19/914
[2]: https://lkml.org/lkml/2018/4/5/451
[3]: https://lkml.org/lkml/2018/4/24/390
[4]: https://lkml.org/lkml/2018/4/18/367

Amit Nischal (2):
  dt-bindings: clock: Introduce QCOM Video clock bindings
  clk: qcom: Add video clock controller driver for SDM845

 .../devicetree/bindings/clock/qcom,videocc.txt     |  18 ++
 drivers/clk/qcom/Kconfig                           |  11 +
 drivers/clk/qcom/Makefile                          |   1 +
 drivers/clk/qcom/videocc-sdm845.c                  | 359 +++++++++++++++++++++
 include/dt-bindings/clock/qcom,videocc-sdm845.h    |  25 ++
 5 files changed, 414 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,videocc.txt
 create mode 100644 drivers/clk/qcom/videocc-sdm845.c
 create mode 100644 include/dt-bindings/clock/qcom,videocc-sdm845.h

--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

[PATCH 1/2] dt-bindings: clock: Introduce QCOM Video clock bindings

[Amit Nischal]

Add device tree bindings for video clock controller for Qualcomm
Technology Inc's SoCs.

Signed-off-by: Amit Nischal <anischal@codeaurora.org>
---
 .../devicetree/bindings/clock/qcom,videocc.txt     | 18 ++++++++++++++++
 include/dt-bindings/clock/qcom,videocc-sdm845.h    | 25 ++++++++++++++++++++++
 2 files changed, 43 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,videocc.txt
 create mode 100644 include/dt-bindings/clock/qcom,videocc-sdm845.h

diff --git a/Documentation/devicetree/bindings/clock/qcom,videocc.txt b/Documentation/devicetree/bindings/clock/qcom,videocc.txt
new file mode 100644
index 0000000..1c23b41
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,videocc.txt
@@ -0,0 +1,18 @@
+Qualcomm Video Clock & Reset Controller Binding
+-----------------------------------------------
+
+Required properties :
+- compatible : shall contain "qcom,videocc-sdm845"
+- reg : shall contain base register location and length
+- #clock-cells : shall contain 1
+- #reset-cells : shall contain 1
+- #power-domain-cells : shall contain 1
+
+Example:
+	videocc: qcom,videocc@ab00000 {
+		compatible = "qcom,videocc-sdm845";
+		reg = <0xab00000 0x10000>;
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+		#power-domain-cells = <1>;
+	};
diff --git a/include/dt-bindings/clock/qcom,videocc-sdm845.h b/include/dt-bindings/clock/qcom,videocc-sdm845.h
new file mode 100644
index 0000000..f5f7599
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,videocc-sdm845.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. */
+
+#ifndef _DT_BINDINGS_CLK_MSM_VIDEO_CC_SDM845_H
+#define _DT_BINDINGS_CLK_MSM_VIDEO_CC_SDM845_H
+
+#define VIDEO_CC_APB_CLK			0
+#define VIDEO_CC_AT_CLK				1
+#define VIDEO_CC_QDSS_TRIG_CLK			2
+#define VIDEO_CC_QDSS_TSCTR_DIV8_CLK		3
+#define VIDEO_CC_VCODEC0_AXI_CLK		4
+#define VIDEO_CC_VCODEC0_CORE_CLK		5
+#define VIDEO_CC_VCODEC1_AXI_CLK		6
+#define VIDEO_CC_VCODEC1_CORE_CLK		7
+#define VIDEO_CC_VENUS_AHB_CLK			8
+#define VIDEO_CC_VENUS_CLK_SRC			9
+#define VIDEO_CC_VENUS_CTL_AXI_CLK		10
+#define VIDEO_CC_VENUS_CTL_CORE_CLK		11
+#define VIDEO_PLL0				12
+
+#define VENUS_GDSC				0
+#define VCODEC0_GDSC				1
+#define VCODEC1_GDSC				2
+
+#endif
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

[PATCH 2/2] clk: qcom: Add video clock controller driver for SDM845

[Amit Nischal]

Add support for the video clock controller found on SDM845
based devices. This would allow video drivers to probe and
control their clocks.

Signed-off-by: Amit Nischal <anischal@codeaurora.org>
---
 drivers/clk/qcom/Kconfig          |  11 ++
 drivers/clk/qcom/Makefile         |   1 +
 drivers/clk/qcom/videocc-sdm845.c | 359 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 371 insertions(+)
 create mode 100644 drivers/clk/qcom/videocc-sdm845.c

diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index fb03d99..0464477 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -236,6 +236,17 @@ config SDM_GCC_845
 	  Say Y if you want to use peripheral devices such as UART, SPI,
 	  I2C, USB, UFS, SDDC, PCIe, etc.

+config SDM_VIDEOCC_845
+	tristate "SDM845 Video Clock Controller"
+	depends on COMMON_CLK_QCOM
+	select SDM_GCC_845
+	select QCOM_GDSC
+	help
+	  Support for the video clock controller on Qualcomm Technologies, Inc
+	  SDM845 devices.
+	  Say Y if you want to support video devices and functionality such as
+	  video encode and decode.
+
 config SPMI_PMIC_CLKDIV
 	tristate "SPMI PMIC clkdiv Support"
 	depends on (COMMON_CLK_QCOM && SPMI) || COMPILE_TEST
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 23bf50c..7738f50 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -39,4 +39,5 @@ obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o
 obj-$(CONFIG_QCOM_CLK_RPMH) += clk-rpmh.o
 obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
 obj-$(CONFIG_SDM_GCC_845) += gcc-sdm845.o
+obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
 obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
diff --git a/drivers/clk/qcom/videocc-sdm845.c b/drivers/clk/qcom/videocc-sdm845.c
new file mode 100644
index 0000000..726275a
--- /dev/null
+++ b/drivers/clk/qcom/videocc-sdm845.c
@@ -0,0 +1,359 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/clock/qcom,videocc-sdm845.h>
+
+#include "common.h"
+#include "clk-alpha-pll.h"
+#include "clk-branch.h"
+#include "clk-rcg.h"
+#include "clk-regmap.h"
+#include "clk-pll.h"
+#include "gdsc.h"
+#include "reset.h"
+
+#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
+
+enum {
+	P_BI_TCXO,
+	P_CORE_BI_PLL_TEST_SE,
+	P_VIDEO_PLL0_OUT_EVEN,
+	P_VIDEO_PLL0_OUT_MAIN,
+	P_VIDEO_PLL0_OUT_ODD,
+};
+
+static const struct parent_map video_cc_parent_map_0[] = {
+	{ P_BI_TCXO, 0 },
+	{ P_VIDEO_PLL0_OUT_MAIN, 1 },
+	{ P_VIDEO_PLL0_OUT_EVEN, 2 },
+	{ P_VIDEO_PLL0_OUT_ODD, 3 },
+	{ P_CORE_BI_PLL_TEST_SE, 4 },
+};
+
+static const char * const video_cc_parent_names_0[] = {
+	"bi_tcxo",
+	"video_pll0",
+	"video_pll0_out_even",
+	"video_pll0_out_odd",
+	"core_bi_pll_test_se",
+};
+
+static const struct alpha_pll_config video_pll0_config = {
+	.l = 0x10,
+	.alpha = 0xaaab,
+};
+
+static struct clk_alpha_pll video_pll0 = {
+	.offset = 0x42c,
+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
+	.clkr = {
+		.hw.init = &(struct clk_init_data){
+			.name = "video_pll0",
+			.parent_names = (const char *[]){ "bi_tcxo" },
+			.num_parents = 1,
+			.ops = &clk_alpha_pll_fabia_ops,
+		},
+	},
+};
+
+static const struct freq_tbl ftbl_video_cc_venus_clk_src[] = {
+	F(100000000, P_VIDEO_PLL0_OUT_MAIN, 4, 0, 0),
+	F(200000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
+	F(330000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
+	F(404000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
+	F(444000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
+	F(533000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
+	{ }
+};
+
+static struct clk_rcg2 video_cc_venus_clk_src = {
+	.cmd_rcgr = 0x7f0,
+	.mnd_width = 0,
+	.hid_width = 5,
+	.parent_map = video_cc_parent_map_0,
+	.freq_tbl = ftbl_video_cc_venus_clk_src,
+	.clkr.hw.init = &(struct clk_init_data){
+		.name = "video_cc_venus_clk_src",
+		.parent_names = video_cc_parent_names_0,
+		.num_parents = 5,
+		.flags = CLK_SET_RATE_PARENT,
+		.ops = &clk_rcg2_shared_ops,
+	},
+};
+
+static struct clk_branch video_cc_apb_clk = {
+	.halt_reg = 0x990,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x990,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "video_cc_apb_clk",
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch video_cc_at_clk = {
+	.halt_reg = 0x9f0,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x9f0,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "video_cc_at_clk",
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch video_cc_qdss_trig_clk = {
+	.halt_reg = 0x970,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x970,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "video_cc_qdss_trig_clk",
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch video_cc_qdss_tsctr_div8_clk = {
+	.halt_reg = 0x9d0,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x9d0,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "video_cc_qdss_tsctr_div8_clk",
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch video_cc_vcodec0_axi_clk = {
+	.halt_reg = 0x930,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x930,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "video_cc_vcodec0_axi_clk",
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch video_cc_vcodec0_core_clk = {
+	.halt_reg = 0x890,
+	.halt_check = BRANCH_VOTED,
+	.clkr = {
+		.enable_reg = 0x890,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "video_cc_vcodec0_core_clk",
+			.parent_names = (const char *[]){
+				"video_cc_venus_clk_src",
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch video_cc_vcodec1_axi_clk = {
+	.halt_reg = 0x950,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x950,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "video_cc_vcodec1_axi_clk",
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch video_cc_vcodec1_core_clk = {
+	.halt_reg = 0x8d0,
+	.halt_check = BRANCH_VOTED,
+	.clkr = {
+		.enable_reg = 0x8d0,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "video_cc_vcodec1_core_clk",
+			.parent_names = (const char *[]){
+				"video_cc_venus_clk_src",
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch video_cc_venus_ahb_clk = {
+	.halt_reg = 0x9b0,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x9b0,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "video_cc_venus_ahb_clk",
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch video_cc_venus_ctl_axi_clk = {
+	.halt_reg = 0x910,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x910,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "video_cc_venus_ctl_axi_clk",
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch video_cc_venus_ctl_core_clk = {
+	.halt_reg = 0x850,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x850,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "video_cc_venus_ctl_core_clk",
+			.parent_names = (const char *[]){
+				"video_cc_venus_clk_src",
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct gdsc venus_gdsc = {
+	.gdscr = 0x814,
+	.pd = {
+		.name = "venus_gdsc",
+	},
+	.cxcs = (unsigned int []){ 0x850, 0x910 },
+	.cxc_count = 2,
+	.pwrsts = PWRSTS_OFF_ON,
+	.flags = POLL_CFG_GDSCR,
+};
+
+static struct gdsc vcodec0_gdsc = {
+	.gdscr = 0x874,
+	.pd = {
+		.name = "vcodec0_gdsc",
+	},
+	.cxcs = (unsigned int []){ 0x890, 0x930 },
+	.cxc_count = 2,
+	.flags = HW_CTRL | POLL_CFG_GDSCR,
+	.pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc vcodec1_gdsc = {
+	.gdscr = 0x8b4,
+	.pd = {
+		.name = "vcodec1_gdsc",
+	},
+	.cxcs = (unsigned int []){ 0x8d0, 0x950 },
+	.cxc_count = 2,
+	.flags = HW_CTRL | POLL_CFG_GDSCR,
+	.pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct clk_regmap *video_cc_sdm845_clocks[] = {
+	[VIDEO_CC_APB_CLK] = &video_cc_apb_clk.clkr,
+	[VIDEO_CC_AT_CLK] = &video_cc_at_clk.clkr,
+	[VIDEO_CC_QDSS_TRIG_CLK] = &video_cc_qdss_trig_clk.clkr,
+	[VIDEO_CC_QDSS_TSCTR_DIV8_CLK] = &video_cc_qdss_tsctr_div8_clk.clkr,
+	[VIDEO_CC_VCODEC0_AXI_CLK] = &video_cc_vcodec0_axi_clk.clkr,
+	[VIDEO_CC_VCODEC0_CORE_CLK] = &video_cc_vcodec0_core_clk.clkr,
+	[VIDEO_CC_VCODEC1_AXI_CLK] = &video_cc_vcodec1_axi_clk.clkr,
+	[VIDEO_CC_VCODEC1_CORE_CLK] = &video_cc_vcodec1_core_clk.clkr,
+	[VIDEO_CC_VENUS_AHB_CLK] = &video_cc_venus_ahb_clk.clkr,
+	[VIDEO_CC_VENUS_CLK_SRC] = &video_cc_venus_clk_src.clkr,
+	[VIDEO_CC_VENUS_CTL_AXI_CLK] = &video_cc_venus_ctl_axi_clk.clkr,
+	[VIDEO_CC_VENUS_CTL_CORE_CLK] = &video_cc_venus_ctl_core_clk.clkr,
+	[VIDEO_PLL0] = &video_pll0.clkr,
+};
+
+static struct gdsc *video_cc_sdm845_gdscs[] = {
+	[VENUS_GDSC] = &venus_gdsc,
+	[VCODEC0_GDSC] = &vcodec0_gdsc,
+	[VCODEC1_GDSC] = &vcodec1_gdsc,
+};
+
+static const struct regmap_config video_cc_sdm845_regmap_config = {
+	.reg_bits	= 32,
+	.reg_stride	= 4,
+	.val_bits	= 32,
+	.max_register	= 0xb90,
+	.fast_io	= true,
+};
+
+static const struct qcom_cc_desc video_cc_sdm845_desc = {
+	.config = &video_cc_sdm845_regmap_config,
+	.clks = video_cc_sdm845_clocks,
+	.num_clks = ARRAY_SIZE(video_cc_sdm845_clocks),
+	.gdscs = video_cc_sdm845_gdscs,
+	.num_gdscs = ARRAY_SIZE(video_cc_sdm845_gdscs),
+};
+
+static const struct of_device_id video_cc_sdm845_match_table[] = {
+	{ .compatible = "qcom,videocc-sdm845" },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, video_cc_sdm845_match_table);
+
+static int video_cc_sdm845_probe(struct platform_device *pdev)
+{
+	struct regmap *regmap;
+
+	regmap = qcom_cc_map(pdev, &video_cc_sdm845_desc);
+	if (IS_ERR(regmap))
+		return PTR_ERR(regmap);
+
+	clk_fabia_pll_configure(&video_pll0, regmap, &video_pll0_config);
+
+	return qcom_cc_really_probe(pdev, &video_cc_sdm845_desc, regmap);
+}
+
+static struct platform_driver video_cc_sdm845_driver = {
+	.probe		= video_cc_sdm845_probe,
+	.driver		= {
+		.name	= "videocc-sdm845",
+		.of_match_table = video_cc_sdm845_match_table,
+	},
+};
+
+static int __init video_cc_sdm845_init(void)
+{
+	return platform_driver_register(&video_cc_sdm845_driver);
+}
+subsys_initcall(video_cc_sdm845_init);
+
+static void __exit video_cc_sdm845_exit(void)
+{
+	platform_driver_unregister(&video_cc_sdm845_driver);
+}
+module_exit(video_cc_sdm845_exit);
+
+MODULE_LICENSE("GPL v2");
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH 1/2] dt-bindings: clock: Introduce QCOM Video clock bindings

[Rob Herring]

On Tue, Apr 24, 2018 at 07:02:50PM +0530, Amit Nischal wrote:
> Add device tree bindings for video clock controller for Qualcomm
> Technology Inc's SoCs.
> 
> Signed-off-by: Amit Nischal <anischal@codeaurora.org>
> ---
>  .../devicetree/bindings/clock/qcom,videocc.txt     | 18 ++++++++++++++++
>  include/dt-bindings/clock/qcom,videocc-sdm845.h    | 25 ++++++++++++++++++++++
>  2 files changed, 43 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/qcom,videocc.txt
>  create mode 100644 include/dt-bindings/clock/qcom,videocc-sdm845.h
> 
> diff --git a/Documentation/devicetree/bindings/clock/qcom,videocc.txt b/Documentation/devicetree/bindings/clock/qcom,videocc.txt
> new file mode 100644
> index 0000000..1c23b41
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/qcom,videocc.txt
> @@ -0,0 +1,18 @@
> +Qualcomm Video Clock & Reset Controller Binding
> +-----------------------------------------------
> +
> +Required properties :
> +- compatible : shall contain "qcom,videocc-sdm845"

'<vendor>,<soc>-<block>' is the preferred order. 

Every single QCom binding... Can someone spread the word in QCom.

> +- reg : shall contain base register location and length
> +- #clock-cells : shall contain 1
> +- #reset-cells : shall contain 1
> +- #power-domain-cells : shall contain 1

No header definitions for resets and power-domain? There's no 
requirement to have headers, but the binding should be complete even if 
you don't have a driver yet.

> +
> +Example:
> +	videocc: qcom,videocc@ab00000 {

clock-controller@...

> +		compatible = "qcom,videocc-sdm845";
> +		reg = <0xab00000 0x10000>;
> +		#clock-cells = <1>;
> +		#reset-cells = <1>;
> +		#power-domain-cells = <1>;
> +	};
> diff --git a/include/dt-bindings/clock/qcom,videocc-sdm845.h b/include/dt-bindings/clock/qcom,videocc-sdm845.h
> new file mode 100644
> index 0000000..f5f7599
> --- /dev/null
> +++ b/include/dt-bindings/clock/qcom,videocc-sdm845.h
> @@ -0,0 +1,25 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. */
> +
> +#ifndef _DT_BINDINGS_CLK_MSM_VIDEO_CC_SDM845_H
> +#define _DT_BINDINGS_CLK_MSM_VIDEO_CC_SDM845_H
> +
> +#define VIDEO_CC_APB_CLK			0
> +#define VIDEO_CC_AT_CLK				1
> +#define VIDEO_CC_QDSS_TRIG_CLK			2
> +#define VIDEO_CC_QDSS_TSCTR_DIV8_CLK		3
> +#define VIDEO_CC_VCODEC0_AXI_CLK		4
> +#define VIDEO_CC_VCODEC0_CORE_CLK		5
> +#define VIDEO_CC_VCODEC1_AXI_CLK		6
> +#define VIDEO_CC_VCODEC1_CORE_CLK		7
> +#define VIDEO_CC_VENUS_AHB_CLK			8
> +#define VIDEO_CC_VENUS_CLK_SRC			9
> +#define VIDEO_CC_VENUS_CTL_AXI_CLK		10
> +#define VIDEO_CC_VENUS_CTL_CORE_CLK		11
> +#define VIDEO_PLL0				12
> +
> +#define VENUS_GDSC				0
> +#define VCODEC0_GDSC				1
> +#define VCODEC1_GDSC				2
> +
> +#endif
> --
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
> of Code Aurora Forum, hosted by The Linux Foundation
> 
> --
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Re: [PATCH 2/2] clk: qcom: Add video clock controller driver for SDM845

[Stephen Boyd]

Quoting Amit Nischal (2018-04-24 06:32:51)
> Add support for the video clock controller found on SDM845
> based devices. This would allow video drivers to probe and
> control their clocks.
> 
> Signed-off-by: Amit Nischal <anischal@codeaurora.org>

Driver looks small and good. Only concern is that there aren't resets
defined, but the binding says there are resets. Will you add them?

I'm going to wait for the respin on the dts binding anyway.

Re: [PATCH 2/2] clk: qcom: Add video clock controller driver for SDM845

[Stephen Boyd]

Quoting Amit Nischal (2018-04-24 06:32:51)
> Add support for the video clock controller found on SDM845
> based devices. This would allow video drivers to probe and
> control their clocks.
> 
> Signed-off-by: Amit Nischal <anischal@codeaurora.org>

Driver looks small and good. Only concern is that there aren't resets
defined, but the binding says there are resets. Will you add them?

I'm going to wait for the respin on the dts binding anyway.

Re: [PATCH 2/2] clk: qcom: Add video clock controller driver for SDM845

[Stephen Boyd]

Quoting Amit Nischal (2018-04-24 06:32:51)
> Add support for the video clock controller found on SDM845
> based devices. This would allow video drivers to probe and
> control their clocks.
> =

> Signed-off-by: Amit Nischal <anischal@codeaurora.org>

Driver looks small and good. Only concern is that there aren't resets
defined, but the binding says there are resets. Will you add them?

I'm going to wait for the respin on the dts binding anyway.

Re: [PATCH 1/2] dt-bindings: clock: Introduce QCOM Video clock bindings

[Amit Nischal]

On 2018-05-01 19:20, Rob Herring wrote:
> On Tue, Apr 24, 2018 at 07:02:50PM +0530, Amit Nischal wrote:
>> Add device tree bindings for video clock controller for Qualcomm
>> Technology Inc's SoCs.
>> 
>> Signed-off-by: Amit Nischal <anischal@codeaurora.org>
>> ---
>>  .../devicetree/bindings/clock/qcom,videocc.txt     | 18 
>> ++++++++++++++++
>>  include/dt-bindings/clock/qcom,videocc-sdm845.h    | 25 
>> ++++++++++++++++++++++
>>  2 files changed, 43 insertions(+)
>>  create mode 100644 
>> Documentation/devicetree/bindings/clock/qcom,videocc.txt
>>  create mode 100644 include/dt-bindings/clock/qcom,videocc-sdm845.h
>> 
>> diff --git a/Documentation/devicetree/bindings/clock/qcom,videocc.txt 
>> b/Documentation/devicetree/bindings/clock/qcom,videocc.txt
>> new file mode 100644
>> index 0000000..1c23b41
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/qcom,videocc.txt
>> @@ -0,0 +1,18 @@
>> +Qualcomm Video Clock & Reset Controller Binding
>> +-----------------------------------------------
>> +
>> +Required properties :
>> +- compatible : shall contain "qcom,videocc-sdm845"
> 
> '<vendor>,<soc>-<block>' is the preferred order.
> 
> Every single QCom binding... Can someone spread the word in QCom.

Thanks for the review. I will make the suggested change in the next
series.

> 
>> +- reg : shall contain base register location and length
>> +- #clock-cells : shall contain 1
>> +- #reset-cells : shall contain 1
>> +- #power-domain-cells : shall contain 1
> 
> No header definitions for resets and power-domain? There's no
> requirement to have headers, but the binding should be complete even if
> you don't have a driver yet.

Will do the required changes in the next patch series.
> 
>> +
>> +Example:
>> +	videocc: qcom,videocc@ab00000 {
> 
> clock-controller@...

Will be fixed in the next patch series.

> 
>> +		compatible = "qcom,videocc-sdm845";
>> +		reg = <0xab00000 0x10000>;
>> +		#clock-cells = <1>;
>> +		#reset-cells = <1>;
>> +		#power-domain-cells = <1>;
>> +	};
>> diff --git a/include/dt-bindings/clock/qcom,videocc-sdm845.h 
>> b/include/dt-bindings/clock/qcom,videocc-sdm845.h
>> new file mode 100644
>> index 0000000..f5f7599
>> --- /dev/null
>> +++ b/include/dt-bindings/clock/qcom,videocc-sdm845.h
>> @@ -0,0 +1,25 @@
>> +/* SPDX-License-Identifier: GPL-2.0 */
>> +/* Copyright (c) 2016-2018, The Linux Foundation. All rights 
>> reserved. */
>> +
>> +#ifndef _DT_BINDINGS_CLK_MSM_VIDEO_CC_SDM845_H
>> +#define _DT_BINDINGS_CLK_MSM_VIDEO_CC_SDM845_H
>> +
>> +#define VIDEO_CC_APB_CLK			0
>> +#define VIDEO_CC_AT_CLK				1
>> +#define VIDEO_CC_QDSS_TRIG_CLK			2
>> +#define VIDEO_CC_QDSS_TSCTR_DIV8_CLK		3
>> +#define VIDEO_CC_VCODEC0_AXI_CLK		4
>> +#define VIDEO_CC_VCODEC0_CORE_CLK		5
>> +#define VIDEO_CC_VCODEC1_AXI_CLK		6
>> +#define VIDEO_CC_VCODEC1_CORE_CLK		7
>> +#define VIDEO_CC_VENUS_AHB_CLK			8
>> +#define VIDEO_CC_VENUS_CLK_SRC			9
>> +#define VIDEO_CC_VENUS_CTL_AXI_CLK		10
>> +#define VIDEO_CC_VENUS_CTL_CORE_CLK		11
>> +#define VIDEO_PLL0				12
>> +
>> +#define VENUS_GDSC				0
>> +#define VCODEC0_GDSC				1
>> +#define VCODEC1_GDSC				2
>> +
>> +#endif
>> --
>> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a 
>> member
>> of Code Aurora Forum, hosted by The Linux Foundation
>> 
>> --
>> To unsubscribe from this list: send the line "unsubscribe devicetree" 
>> in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH 2/2] clk: qcom: Add video clock controller driver for SDM845

[Nischal, Amit]

On 5/2/2018 3:11 AM, Stephen Boyd wrote:
> Quoting Amit Nischal (2018-04-24 06:32:51)
>> Add support for the video clock controller found on SDM845
>> based devices. This would allow video drivers to probe and
>> control their clocks.
>>
>> Signed-off-by: Amit Nischal <anischal@codeaurora.org>
> Driver looks small and good. Only concern is that there aren't resets
> defined, but the binding says there are resets. Will you add them?
Thanks for the review.
As of now, there are no resets defined for VIDEOCC. So I will move
the #reset-cells tooptional property in the dt-binding.
Same will be updated in the next patch series.
>
> I'm going to wait for the respin on the dts binding anyway.
Yes, I will send the next patch series soon.
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> the body of a message to majordomo@vger.kernel.org
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Re: [PATCH 2/2] clk: qcom: Add video clock controller driver for SDM845

[Stephen Boyd]

Quoting Nischal, Amit (2018-05-02 00:56:35)
> 
> 
> Thanks for the review.
> As of now, there are no resets defined for VIDEOCC. So I will move
> the #reset-cells tooptional property in the dt-binding.
> Same will be updated in the next patch series.

Please don't make it optional. It should be required in the binding,
because there are resets in the hardware. If you don't want to add them
into the driver, that's ok, but it isn't really that hard to add them so
why not add them?

Re: [PATCH 2/2] clk: qcom: Add video clock controller driver for SDM845

[Stephen Boyd]

Quoting Nischal, Amit (2018-05-02 00:56:35)
> =

> =

> Thanks for the review.
> As of now, there are no resets defined for VIDEOCC. So I will move
> the #reset-cells tooptional property in the dt-binding.
> Same will be updated in the next patch series.

Please don't make it optional. It should be required in the binding,
because there are resets in the hardware. If you don't want to add them
into the driver, that's ok, but it isn't really that hard to add them so
why not add them?

Re: [PATCH 2/2] clk: qcom: Add video clock controller driver for SDM845

[Amit Nischal]

On 2018-05-03 00:17, Stephen Boyd wrote:
> Quoting Nischal, Amit (2018-05-02 00:56:35)
>> 
>> 
>> Thanks for the review.
>> As of now, there are no resets defined for VIDEOCC. So I will move
>> the #reset-cells tooptional property in the dt-binding.
>> Same will be updated in the next patch series.
> 
> Please don't make it optional. It should be required in the binding,
> because there are resets in the hardware. If you don't want to add them
> into the driver, that's ok, but it isn't really that hard to add them 
> so
> why not add them?

There is no reset client for VideoCC so that's why we have not
added them in the driver file. However, I will make "#reset-cells"
as required property in the dt-binding.

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