* [PATCH v2] x86/cpu: Add supports for zhaoxin x86 platform
@ 2018-04-25 9:51 Davidwang
2018-04-30 14:15 ` Jan Beulich
0 siblings, 1 reply; 4+ messages in thread
From: Davidwang @ 2018-04-25 9:51 UTC (permalink / raw)
To: xen-devel; +Cc: fionali, jbeulich
From: DavidWang <davidwang@zhaoxin.com>
Zhaoxin is a x86 IC designer. Its SOC products support both CPU
virtualization and I/O virtualization, which are compatible with Intel
VMX and VT-d respectively. Zhaoxin has 'Shanghai' CPU vendor ID.
Signed-off-by: DavidWang <davidwang@zhaoxin.com>
---
xen/arch/x86/cpu/Makefile | 1 +
xen/arch/x86/cpu/common.c | 1 +
xen/arch/x86/cpu/intel_cacheinfo.c | 2 +-
xen/arch/x86/cpu/shanghai.c | 90 ++++++++++++++++++++++++++++++++++++++
xen/include/asm-x86/cpufeature.h | 1 +
xen/include/asm-x86/iommu.h | 2 +
xen/include/asm-x86/setup.h | 1 +
xen/include/asm-x86/x86-vendors.h | 3 +-
8 files changed, 99 insertions(+), 2 deletions(-)
create mode 100644 xen/arch/x86/cpu/shanghai.c
diff --git a/xen/arch/x86/cpu/Makefile b/xen/arch/x86/cpu/Makefile
index 74f23ae..34a01ca 100644
--- a/xen/arch/x86/cpu/Makefile
+++ b/xen/arch/x86/cpu/Makefile
@@ -7,4 +7,5 @@ obj-y += common.o
obj-y += intel.o
obj-y += intel_cacheinfo.o
obj-y += mwait-idle.o
+obj-y += shanghai.o
obj-y += vpmu.o vpmu_amd.o vpmu_intel.o
diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c
index 0a452ae..02863c9 100644
--- a/xen/arch/x86/cpu/common.c
+++ b/xen/arch/x86/cpu/common.c
@@ -709,6 +709,7 @@ void __init early_cpu_init(void)
intel_cpu_init();
amd_init_cpu();
centaur_init_cpu();
+ shanghai_init_cpu();
early_cpu_detect();
}
diff --git a/xen/arch/x86/cpu/intel_cacheinfo.c b/xen/arch/x86/cpu/intel_cacheinfo.c
index 101e297..a3aec13 100644
--- a/xen/arch/x86/cpu/intel_cacheinfo.c
+++ b/xen/arch/x86/cpu/intel_cacheinfo.c
@@ -103,7 +103,7 @@ int cpuid4_cache_lookup(int index, struct cpuid4_info *this_leaf)
return 0;
}
-static int find_num_cache_leaves(void)
+int find_num_cache_leaves(void)
{
unsigned int eax, ebx, ecx, edx;
union _cpuid4_leaf_eax cache_eax;
diff --git a/xen/arch/x86/cpu/shanghai.c b/xen/arch/x86/cpu/shanghai.c
new file mode 100644
index 0000000..ac12ba3
--- /dev/null
+++ b/xen/arch/x86/cpu/shanghai.c
@@ -0,0 +1,90 @@
+#include <xen/bitops.h>
+#include <xen/init.h>
+#include <asm/processor.h>
+#include "cpu.h"
+
+void init_shanghai_cache(struct cpuinfo_x86 *c)
+{
+ unsigned int i = 0, l1d = 0, l1i = 0, l2 = 0, l3 = 0;
+ struct cpuid4_info leaf;
+ static bool is_initialized = false;
+ static unsigned int cache_leaves = 0;
+
+ if ( (!is_initialized) && (c->cpuid_level > 0x00000003) )
+ {
+ /* Init cache_leaves from boot CPU */
+ cache_leaves = find_num_cache_leaves();
+ is_initialized = true;
+ }
+
+ /* Use cpuid:0x00000004 to find the cache details */
+ for (i = 0; i < cache_leaves; i++)
+ {
+ if( c->cpuid_level <= 0x00000003 )
+ break;
+
+ if ( !cpuid4_cache_lookup(i, &leaf) )
+ {
+ switch( leaf.eax.split.level )
+ {
+ case 1:
+ if ( leaf.eax.split.type == CACHE_TYPE_DATA )
+ l1d = leaf.size/1024;
+ else if ( leaf.eax.split.type == CACHE_TYPE_INST )
+ l1i = leaf.size/1024;
+ break;
+ case 2:
+ l2 = leaf.size/1024;
+ break;
+ case 3:
+ l3 = leaf.size/1024;
+ break;
+ default:
+ break;
+ }
+ }
+ }
+
+ if ( opt_cpu_info )
+ {
+ if ( l1i )
+ printk("CPU: L1 I cache: %dK", l1i);
+
+ if ( l1d )
+ printk(", L1 D cache: %dK\n", l1d);
+ else
+ printk("\n");
+
+ if ( l2 )
+ printk("CPU: L2 cache: %dK\n", l2);
+
+ if ( l3 )
+ printk("CPU: L3 cache: %dK\n", l3);
+ }
+
+ c->x86_cache_size = l3 ? l3 : (l2 ? l2 : (l1i + l1d));
+}
+
+static void init_shanghai(struct cpuinfo_x86 *c)
+{
+ if ( cpu_has(c, X86_FEATURE_ITSC) )
+ {
+ __set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);
+ __set_bit(X86_FEATURE_NONSTOP_TSC, c->x86_capability);
+ __set_bit(X86_FEATURE_TSC_RELIABLE, c->x86_capability);
+ }
+
+ init_shanghai_cache(c);
+}
+
+static const struct cpu_dev shanghai_cpu_dev = {
+ .c_vendor = " Shang",
+ .c_ident = {" Shanghai "},
+ .c_init = init_shanghai,
+};
+
+int __init shanghai_init_cpu(void)
+{
+ cpu_devs[X86_VENDOR_SHANGHAI] = &shanghai_cpu_dev;
+ return 0;
+}
diff --git a/xen/include/asm-x86/cpufeature.h b/xen/include/asm-x86/cpufeature.h
index 4c62597..2175bd0 100644
--- a/xen/include/asm-x86/cpufeature.h
+++ b/xen/include/asm-x86/cpufeature.h
@@ -157,6 +157,7 @@ struct cpuid4_info {
};
int cpuid4_cache_lookup(int index, struct cpuid4_info *this_leaf);
+int find_num_cache_leaves(void);
#endif /* !__ASSEMBLY__ */
#endif /* __ASM_I386_CPUFEATURE_H */
diff --git a/xen/include/asm-x86/iommu.h b/xen/include/asm-x86/iommu.h
index 14ad048..6a6d3bf 100644
--- a/xen/include/asm-x86/iommu.h
+++ b/xen/include/asm-x86/iommu.h
@@ -54,6 +54,7 @@ static inline const struct iommu_ops *iommu_get_ops(void)
switch ( boot_cpu_data.x86_vendor )
{
case X86_VENDOR_INTEL:
+ case X86_VENDOR_SHANGHAI:
return &intel_iommu_ops;
case X86_VENDOR_AMD:
return &amd_iommu_ops;
@@ -69,6 +70,7 @@ static inline int iommu_hardware_setup(void)
switch ( boot_cpu_data.x86_vendor )
{
case X86_VENDOR_INTEL:
+ case X86_VENDOR_SHANGHAI:
return intel_vtd_setup();
case X86_VENDOR_AMD:
return amd_iov_detect();
diff --git a/xen/include/asm-x86/setup.h b/xen/include/asm-x86/setup.h
index 19232af..2c2d9fd 100644
--- a/xen/include/asm-x86/setup.h
+++ b/xen/include/asm-x86/setup.h
@@ -23,6 +23,7 @@ int cyrix_init_cpu(void);
int nsc_init_cpu(void);
int centaur_init_cpu(void);
int transmeta_init_cpu(void);
+int shanghai_init_cpu(void);
void set_nr_cpu_ids(unsigned int max_cpus);
diff --git a/xen/include/asm-x86/x86-vendors.h b/xen/include/asm-x86/x86-vendors.h
index cae5507..c53d0b9 100644
--- a/xen/include/asm-x86/x86-vendors.h
+++ b/xen/include/asm-x86/x86-vendors.h
@@ -7,7 +7,8 @@
#define X86_VENDOR_INTEL 0
#define X86_VENDOR_AMD 1
#define X86_VENDOR_CENTAUR 2
-#define X86_VENDOR_NUM 3
+#define X86_VENDOR_SHANGHAI 3
+#define X86_VENDOR_NUM 4
#define X86_VENDOR_UNKNOWN 0xff
#endif /* __XEN_X86_VENDORS_H__ */
--
2.7.4
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^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH v2] x86/cpu: Add supports for zhaoxin x86 platform
2018-04-25 9:51 [PATCH v2] x86/cpu: Add supports for zhaoxin x86 platform Davidwang
@ 2018-04-30 14:15 ` Jan Beulich
2018-05-02 7:47 ` 答复: " David Wang
0 siblings, 1 reply; 4+ messages in thread
From: Jan Beulich @ 2018-04-30 14:15 UTC (permalink / raw)
To: Davidwang; +Cc: xen-devel, Fiona Li(BJ-RD)
[-- Attachment #1: Type: text/plain, Size: 2319 bytes --]
>>> On 25.04.18 at 11:51, <Davidwang@zhaoxin.com> wrote:
> --- a/xen/arch/x86/cpu/intel_cacheinfo.c
> +++ b/xen/arch/x86/cpu/intel_cacheinfo.c
> @@ -103,7 +103,7 @@ int cpuid4_cache_lookup(int index, struct cpuid4_info *this_leaf)
> return 0;
> }
>
> -static int find_num_cache_leaves(void)
> +int find_num_cache_leaves(void)
Instead of making this function non-static, please consider re-using
init_intel_cacheinfo(): All you want is skip the CPUID leaf 2 handling,
and you'd better to this by altering the single if() controlling it in that
function than by effectively introducing a clone. If you're concerned
of some other dead code in that function, attached you'll find a patch
deleting at least some of that.
> --- /dev/null
> +++ b/xen/arch/x86/cpu/shanghai.c
> @@ -0,0 +1,90 @@
> +#include <xen/bitops.h>
> +#include <xen/init.h>
> +#include <asm/processor.h>
> +#include "cpu.h"
> +
> +void init_shanghai_cache(struct cpuinfo_x86 *c)
> +{
> + unsigned int i = 0, l1d = 0, l1i = 0, l2 = 0, l3 = 0;
> + struct cpuid4_info leaf;
> + static bool is_initialized = false;
> + static unsigned int cache_leaves = 0;
> +
> + if ( (!is_initialized) && (c->cpuid_level > 0x00000003) )
> + {
If there was a convincing argument that this clone of the original
function was really needed, then you'd need to go through here
and clean up style (various aspects of it are broken, most notably
the mix of space and tab indentation).
> --- a/xen/include/asm-x86/iommu.h
> +++ b/xen/include/asm-x86/iommu.h
> @@ -54,6 +54,7 @@ static inline const struct iommu_ops *iommu_get_ops(void)
> switch ( boot_cpu_data.x86_vendor )
> {
> case X86_VENDOR_INTEL:
> + case X86_VENDOR_SHANGHAI:
> return &intel_iommu_ops;
> case X86_VENDOR_AMD:
> return &amd_iommu_ops;
> @@ -69,6 +70,7 @@ static inline int iommu_hardware_setup(void)
> switch ( boot_cpu_data.x86_vendor )
> {
> case X86_VENDOR_INTEL:
> + case X86_VENDOR_SHANGHAI:
> return intel_vtd_setup();
> case X86_VENDOR_AMD:
> return amd_iov_detect();
There are numerous further occurrences of X86_VENDOR_INTEL throughout
the code base - is it really the case that no single one of them needs similar
amendment?
Jan
[-- Attachment #2: x86-init-Intel-cacheinfo.patch --]
[-- Type: text/plain, Size: 1628 bytes --]
x86: remove read code from cpuid4_cache_lookup()
... and make num_cache_leaves local to the only function using it.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
--- unstable.orig/xen/arch/x86/cpu/intel_cacheinfo.c 2017-03-03 14:08:33.000000000 +0100
+++ unstable/xen/arch/x86/cpu/intel_cacheinfo.c 2018-04-30 15:59:54.637217413 +0200
@@ -80,8 +80,6 @@ static const struct _cache_table cache_t
{ 0x00, 0, 0}
};
-unsigned short num_cache_leaves;
-
int cpuid4_cache_lookup(int index, struct cpuid4_info *this_leaf)
{
union _cpuid4_leaf_eax eax;
@@ -123,7 +121,7 @@ unsigned int init_intel_cacheinfo(struct
unsigned int trace = 0, l1i = 0, l1d = 0, l2 = 0, l3 = 0; /* Cache sizes */
unsigned int new_l1d = 0, new_l1i = 0; /* Cache sizes from cpuid(4) */
unsigned int new_l2 = 0, new_l3 = 0, i; /* Cache sizes from cpuid(4) */
- unsigned int l2_id = 0, l3_id = 0, num_threads_sharing, index_msb;
+ static unsigned int num_cache_leaves;
if (c->cpuid_level > 3) {
static int is_initialized;
@@ -156,15 +154,9 @@ unsigned int init_intel_cacheinfo(struct
break;
case 2:
new_l2 = this_leaf.size/1024;
- num_threads_sharing = 1 + this_leaf.eax.split.num_threads_sharing;
- index_msb = get_count_order(num_threads_sharing);
- l2_id = c->apicid >> index_msb;
break;
case 3:
new_l3 = this_leaf.size/1024;
- num_threads_sharing = 1 + this_leaf.eax.split.num_threads_sharing;
- index_msb = get_count_order(num_threads_sharing);
- l3_id = c->apicid >> index_msb;
break;
default:
break;
[-- Attachment #3: Type: text/plain, Size: 157 bytes --]
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^ permalink raw reply [flat|nested] 4+ messages in thread
* 答复: [PATCH v2] x86/cpu: Add supports for zhaoxin x86 platform
2018-04-30 14:15 ` Jan Beulich
@ 2018-05-02 7:47 ` David Wang
2018-05-02 9:07 ` Jan Beulich
0 siblings, 1 reply; 4+ messages in thread
From: David Wang @ 2018-05-02 7:47 UTC (permalink / raw)
To: Jan Beulich; +Cc: xen-devel, Fiona Li(BJ-RD)
Hi Jan,
Thanks for your reply. Answer as following.
________________________________________
发件人: Jan Beulich <JBeulich@suse.com>
发送时间: 2018年4月30日 22:15
收件人: David Wang
抄送: xen-devel; Fiona Li(BJ-RD)
主题: Re: [PATCH v2] x86/cpu: Add supports for zhaoxin x86 platform
>>> On 25.04.18 at 11:51, <Davidwang@zhaoxin.com> wrote:
> --- a/xen/arch/x86/cpu/intel_cacheinfo.c
> +++ b/xen/arch/x86/cpu/intel_cacheinfo.c
> @@ -103,7 +103,7 @@ int cpuid4_cache_lookup(int index, struct cpuid4_info *this_leaf)
> return 0;
> }
>
> -static int find_num_cache_leaves(void)
> +int find_num_cache_leaves(void)
Instead of making this function non-static, please consider re-using
init_intel_cacheinfo(): All you want is skip the CPUID leaf 2 handling,
and you'd better to this by altering the single if() controlling it in that
function than by effectively introducing a clone. If you're concerned
of some other dead code in that function, attached you'll find a patch
deleting at least some of that.
[David]: Concerned the dead code in init_intel_cacheinfo(), I rewrite it. Thanks for your patch, i will re-using init_intel_cacheinfo() in next version.
> --- /dev/null
> +++ b/xen/arch/x86/cpu/shanghai.c
> @@ -0,0 +1,90 @@
> +#include <xen/bitops.h>
> +#include <xen/init.h>
> +#include <asm/processor.h>
> +#include "cpu.h"
> +
> +void init_shanghai_cache(struct cpuinfo_x86 *c)
> +{
> + unsigned int i = 0, l1d = 0, l1i = 0, l2 = 0, l3 = 0;
> + struct cpuid4_info leaf;
> + static bool is_initialized = false;
> + static unsigned int cache_leaves = 0;
> +
> + if ( (!is_initialized) && (c->cpuid_level > 0x00000003) )
> + {
If there was a convincing argument that this clone of the original
function was really needed, then you'd need to go through here
and clean up style (various aspects of it are broken, most notably
the mix of space and tab indentation).
[David]: Sorry for my mistake.
> --- a/xen/include/asm-x86/iommu.h
> +++ b/xen/include/asm-x86/iommu.h
> @@ -54,6 +54,7 @@ static inline const struct iommu_ops *iommu_get_ops(void)
> switch ( boot_cpu_data.x86_vendor )
> {
> case X86_VENDOR_INTEL:
> + case X86_VENDOR_SHANGHAI:
> return &intel_iommu_ops;
> case X86_VENDOR_AMD:
> return &amd_iommu_ops;
> @@ -69,6 +70,7 @@ static inline int iommu_hardware_setup(void)
> switch ( boot_cpu_data.x86_vendor )
> {
> case X86_VENDOR_INTEL:
> + case X86_VENDOR_SHANGHAI:
> return intel_vtd_setup();
> case X86_VENDOR_AMD:
> return amd_iov_detect();
There are numerous further occurrences of X86_VENDOR_INTEL throughout
the code base - is it really the case that no single one of them needs similar
amendment?
[David]: Yes, there are numerous occurrences of X86_VENDOR_INTEL, such as supporting idle_nops in arch_init_ideal_nops() or vpmu in vpmu_arch_initialise(). Some of them perfect function, others improve performance. Can we perfect those by submitting separate patches? To support the iommu, we need to re-use intel_iommu_ops() and intel_vtd_setup().
David
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^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: 答复: [PATCH v2] x86/cpu: Add supports for zhaoxin x86 platform
2018-05-02 7:47 ` 答复: " David Wang
@ 2018-05-02 9:07 ` Jan Beulich
0 siblings, 0 replies; 4+ messages in thread
From: Jan Beulich @ 2018-05-02 9:07 UTC (permalink / raw)
To: Davidwang; +Cc: xen-devel, Fiona Li(BJ-RD)
>>> On 02.05.18 at 09:47, <DavidWang@zhaoxin.com> wrote:
> 发件人: Jan Beulich <JBeulich@suse.com>
> 发送时间: 2018年4月30日 22:15
>>>> On 25.04.18 at 11:51, <Davidwang@zhaoxin.com> wrote:
>> --- a/xen/include/asm-x86/iommu.h
>> +++ b/xen/include/asm-x86/iommu.h
>> @@ -54,6 +54,7 @@ static inline const struct iommu_ops *iommu_get_ops(void)
>> switch ( boot_cpu_data.x86_vendor )
>> {
>> case X86_VENDOR_INTEL:
>> + case X86_VENDOR_SHANGHAI:
>> return &intel_iommu_ops;
>> case X86_VENDOR_AMD:
>> return &amd_iommu_ops;
>> @@ -69,6 +70,7 @@ static inline int iommu_hardware_setup(void)
>> switch ( boot_cpu_data.x86_vendor )
>> {
>> case X86_VENDOR_INTEL:
>> + case X86_VENDOR_SHANGHAI:
>> return intel_vtd_setup();
>> case X86_VENDOR_AMD:
>> return amd_iov_detect();
>
> There are numerous further occurrences of X86_VENDOR_INTEL throughout
> the code base - is it really the case that no single one of them needs
> similar
> amendment?
> [David]: Yes, there are numerous occurrences of X86_VENDOR_INTEL, such as
> supporting idle_nops in arch_init_ideal_nops() or vpmu in
> vpmu_arch_initialise(). Some of them perfect function, others improve
> performance. Can we perfect those by submitting separate patches? To
> support the iommu, we need to re-use intel_iommu_ops() and intel_vtd_setup().
Yes, and then even the IOMMU adjustment should be split to a separate patch,
I think.
Also please adjust your quoting style when replying to mails.
Jan
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^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2018-05-02 9:07 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2018-04-25 9:51 [PATCH v2] x86/cpu: Add supports for zhaoxin x86 platform Davidwang
2018-04-30 14:15 ` Jan Beulich
2018-05-02 7:47 ` 答复: " David Wang
2018-05-02 9:07 ` Jan Beulich
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