* [PATCH 0/2] net: stmmac: dwmac-meson: 100M phy mode support for AXG SoC @ 2018-04-26 16:05 ` Yixun Lan 0 siblings, 0 replies; 17+ messages in thread From: Yixun Lan @ 2018-04-26 16:05 UTC (permalink / raw) To: David S. Miller, netdev Cc: Yixun Lan, Kevin Hilman, Carlo Caione, Rob Herring, Martin Blumenstingl, linux-amlogic, linux-arm-kernel, linux-kernel, devicetree Due to the dwmac glue layer register changed, we need to introduce a new compatible name for the Meson-AXG SoC to support for the RMII 100M ethernet PHY. Yixun Lan (2): dt-bindings: net: meson-dwmac: new compatible name for AXG SoC net: stmmac: dwmac-meson: extend phy mode setting .../devicetree/bindings/net/meson-dwmac.txt | 1 + .../ethernet/stmicro/stmmac/dwmac-meson8b.c | 96 ++++++++++++++++--- 2 files changed, 86 insertions(+), 11 deletions(-) -- 2.17.0 ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 0/2] net: stmmac: dwmac-meson: 100M phy mode support for AXG SoC @ 2018-04-26 16:05 ` Yixun Lan 0 siblings, 0 replies; 17+ messages in thread From: Yixun Lan @ 2018-04-26 16:05 UTC (permalink / raw) To: linus-amlogic Due to the dwmac glue layer register changed, we need to introduce a new compatible name for the Meson-AXG SoC to support for the RMII 100M ethernet PHY. Yixun Lan (2): dt-bindings: net: meson-dwmac: new compatible name for AXG SoC net: stmmac: dwmac-meson: extend phy mode setting .../devicetree/bindings/net/meson-dwmac.txt | 1 + .../ethernet/stmicro/stmmac/dwmac-meson8b.c | 96 ++++++++++++++++--- 2 files changed, 86 insertions(+), 11 deletions(-) -- 2.17.0 ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 0/2] net: stmmac: dwmac-meson: 100M phy mode support for AXG SoC @ 2018-04-26 16:05 ` Yixun Lan 0 siblings, 0 replies; 17+ messages in thread From: Yixun Lan @ 2018-04-26 16:05 UTC (permalink / raw) To: linux-arm-kernel Due to the dwmac glue layer register changed, we need to introduce a new compatible name for the Meson-AXG SoC to support for the RMII 100M ethernet PHY. Yixun Lan (2): dt-bindings: net: meson-dwmac: new compatible name for AXG SoC net: stmmac: dwmac-meson: extend phy mode setting .../devicetree/bindings/net/meson-dwmac.txt | 1 + .../ethernet/stmicro/stmmac/dwmac-meson8b.c | 96 ++++++++++++++++--- 2 files changed, 86 insertions(+), 11 deletions(-) -- 2.17.0 ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 0/2] net: stmmac: dwmac-meson: 100M phy mode support for AXG SoC @ 2018-04-26 16:05 ` Yixun Lan 0 siblings, 0 replies; 17+ messages in thread From: Yixun Lan @ 2018-04-26 16:05 UTC (permalink / raw) To: David S. Miller, netdev Cc: Yixun Lan, Kevin Hilman, Carlo Caione, Rob Herring, Martin Blumenstingl, linux-amlogic, linux-arm-kernel, linux-kernel, devicetree Due to the dwmac glue layer register changed, we need to introduce a new compatible name for the Meson-AXG SoC to support for the RMII 100M ethernet PHY. Yixun Lan (2): dt-bindings: net: meson-dwmac: new compatible name for AXG SoC net: stmmac: dwmac-meson: extend phy mode setting .../devicetree/bindings/net/meson-dwmac.txt | 1 + .../ethernet/stmicro/stmmac/dwmac-meson8b.c | 96 ++++++++++++++++--- 2 files changed, 86 insertions(+), 11 deletions(-) -- 2.17.0 ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 1/2] dt-bindings: net: meson-dwmac: new compatible name for AXG SoC 2018-04-26 16:05 ` Yixun Lan (?) (?) @ 2018-04-26 16:05 ` Yixun Lan -1 siblings, 0 replies; 17+ messages in thread From: Yixun Lan @ 2018-04-26 16:05 UTC (permalink / raw) To: David S. Miller, netdev Cc: Yixun Lan, Kevin Hilman, Carlo Caione, Rob Herring, Martin Blumenstingl, linux-amlogic, linux-arm-kernel, linux-kernel, devicetree We need to introduce a new compatible name for the Meson-AXG SoC in order to support the RMII 100M ethernet PHY, since the PRG_ETH0 register of the dwmac glue layer is changed from previous old SoC. Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> --- Documentation/devicetree/bindings/net/meson-dwmac.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/net/meson-dwmac.txt b/Documentation/devicetree/bindings/net/meson-dwmac.txt index 61cada22ae6c..1321bb194ed9 100644 --- a/Documentation/devicetree/bindings/net/meson-dwmac.txt +++ b/Documentation/devicetree/bindings/net/meson-dwmac.txt @@ -11,6 +11,7 @@ Required properties on all platforms: - "amlogic,meson8b-dwmac" - "amlogic,meson8m2-dwmac" - "amlogic,meson-gxbb-dwmac" + - "amlogic,meson-axg-dwmac" Additionally "snps,dwmac" and any applicable more detailed version number described in net/stmmac.txt should be used. -- 2.17.0 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 1/2] dt-bindings: net: meson-dwmac: new compatible name for AXG SoC @ 2018-04-26 16:05 ` Yixun Lan 0 siblings, 0 replies; 17+ messages in thread From: Yixun Lan @ 2018-04-26 16:05 UTC (permalink / raw) To: linus-amlogic We need to introduce a new compatible name for the Meson-AXG SoC in order to support the RMII 100M ethernet PHY, since the PRG_ETH0 register of the dwmac glue layer is changed from previous old SoC. Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> --- Documentation/devicetree/bindings/net/meson-dwmac.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/net/meson-dwmac.txt b/Documentation/devicetree/bindings/net/meson-dwmac.txt index 61cada22ae6c..1321bb194ed9 100644 --- a/Documentation/devicetree/bindings/net/meson-dwmac.txt +++ b/Documentation/devicetree/bindings/net/meson-dwmac.txt @@ -11,6 +11,7 @@ Required properties on all platforms: - "amlogic,meson8b-dwmac" - "amlogic,meson8m2-dwmac" - "amlogic,meson-gxbb-dwmac" + - "amlogic,meson-axg-dwmac" Additionally "snps,dwmac" and any applicable more detailed version number described in net/stmmac.txt should be used. -- 2.17.0 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 1/2] dt-bindings: net: meson-dwmac: new compatible name for AXG SoC @ 2018-04-26 16:05 ` Yixun Lan 0 siblings, 0 replies; 17+ messages in thread From: Yixun Lan @ 2018-04-26 16:05 UTC (permalink / raw) To: linux-arm-kernel We need to introduce a new compatible name for the Meson-AXG SoC in order to support the RMII 100M ethernet PHY, since the PRG_ETH0 register of the dwmac glue layer is changed from previous old SoC. Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> --- Documentation/devicetree/bindings/net/meson-dwmac.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/net/meson-dwmac.txt b/Documentation/devicetree/bindings/net/meson-dwmac.txt index 61cada22ae6c..1321bb194ed9 100644 --- a/Documentation/devicetree/bindings/net/meson-dwmac.txt +++ b/Documentation/devicetree/bindings/net/meson-dwmac.txt @@ -11,6 +11,7 @@ Required properties on all platforms: - "amlogic,meson8b-dwmac" - "amlogic,meson8m2-dwmac" - "amlogic,meson-gxbb-dwmac" + - "amlogic,meson-axg-dwmac" Additionally "snps,dwmac" and any applicable more detailed version number described in net/stmmac.txt should be used. -- 2.17.0 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 1/2] dt-bindings: net: meson-dwmac: new compatible name for AXG SoC @ 2018-04-26 16:05 ` Yixun Lan 0 siblings, 0 replies; 17+ messages in thread From: Yixun Lan @ 2018-04-26 16:05 UTC (permalink / raw) To: David S. Miller, netdev Cc: Yixun Lan, Kevin Hilman, Carlo Caione, Rob Herring, Martin Blumenstingl, linux-amlogic, linux-arm-kernel, linux-kernel, devicetree We need to introduce a new compatible name for the Meson-AXG SoC in order to support the RMII 100M ethernet PHY, since the PRG_ETH0 register of the dwmac glue layer is changed from previous old SoC. Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> --- Documentation/devicetree/bindings/net/meson-dwmac.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/net/meson-dwmac.txt b/Documentation/devicetree/bindings/net/meson-dwmac.txt index 61cada22ae6c..1321bb194ed9 100644 --- a/Documentation/devicetree/bindings/net/meson-dwmac.txt +++ b/Documentation/devicetree/bindings/net/meson-dwmac.txt @@ -11,6 +11,7 @@ Required properties on all platforms: - "amlogic,meson8b-dwmac" - "amlogic,meson8m2-dwmac" - "amlogic,meson-gxbb-dwmac" + - "amlogic,meson-axg-dwmac" Additionally "snps,dwmac" and any applicable more detailed version number described in net/stmmac.txt should be used. -- 2.17.0 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 2/2] net: stmmac: dwmac-meson: extend phy mode setting 2018-04-26 16:05 ` Yixun Lan (?) @ 2018-04-26 16:05 ` Yixun Lan -1 siblings, 0 replies; 17+ messages in thread From: Yixun Lan @ 2018-04-26 16:05 UTC (permalink / raw) To: David S. Miller, netdev Cc: Yixun Lan, Kevin Hilman, Carlo Caione, Rob Herring, Martin Blumenstingl, linux-amlogic, linux-arm-kernel, linux-kernel In the Meson-AXG SoC, the phy mode setting of PRG_ETH0 in the glue layer is extended from bit[0] to bit[2:0]. There is no problem if we configure it to the RGMII 1000M PHY mode, since the register setting is coincidentally compatible with previous one, but for the RMII 100M PHY mode, the configuration need to be changed to value - b100. This patch was verified with a RTL8201F 100M ethernet PHY. Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> --- .../ethernet/stmicro/stmmac/dwmac-meson8b.c | 95 ++++++++++++++++--- 1 file changed, 84 insertions(+), 11 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c index 7cb794094a70..e3688b6dd87c 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c @@ -18,6 +18,7 @@ #include <linux/io.h> #include <linux/ioport.h> #include <linux/module.h> +#include <linux/of_device.h> #include <linux/of_net.h> #include <linux/mfd/syscon.h> #include <linux/platform_device.h> @@ -29,6 +30,10 @@ #define PRG_ETH0_RGMII_MODE BIT(0) +#define PRG_ETH0_EXT_PHY_MODE_MASK GENMASK(2, 0) +#define PRG_ETH0_EXT_RGMII_MODE 1 +#define PRG_ETH0_EXT_RMII_MODE 4 + /* mux to choose between fclk_div2 (bit unset) and mpll2 (bit set) */ #define PRG_ETH0_CLK_M250_SEL_SHIFT 4 #define PRG_ETH0_CLK_M250_SEL_MASK GENMASK(4, 4) @@ -46,10 +51,16 @@ #define PRG_ETH0_TX_AND_PHY_REF_CLK BIT(12) #define MUX_CLK_NUM_PARENTS 2 +struct meson8b_dwmac_data { + bool ext_phy_mode; +}; struct meson8b_dwmac { struct device *dev; void __iomem *regs; + + const struct meson8b_dwmac_data *data; + phy_interface_t phy_mode; struct clk *rgmii_tx_clk; u32 tx_delay_ns; @@ -171,6 +182,46 @@ static int meson8b_init_rgmii_tx_clk(struct meson8b_dwmac *dwmac) return 0; } +static int meson8b_init_set_mode(struct meson8b_dwmac *dwmac) +{ + bool ext_phy_mode = dwmac->data->ext_phy_mode; + + switch (dwmac->phy_mode) { + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_TXID: + /* enable RGMII mode */ + if (ext_phy_mode) + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, + PRG_ETH0_EXT_PHY_MODE_MASK, + PRG_ETH0_EXT_RGMII_MODE); + else + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, + PRG_ETH0_RGMII_MODE, + PRG_ETH0_RGMII_MODE); + + break; + case PHY_INTERFACE_MODE_RMII: + /* disable RGMII mode -> enables RMII mode */ + if (ext_phy_mode) + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, + PRG_ETH0_EXT_PHY_MODE_MASK, + PRG_ETH0_EXT_RMII_MODE); + else + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, + PRG_ETH0_RGMII_MODE, 0); + + break; + default: + dev_err(dwmac->dev, "fail to set phy-mode %s\n", + phy_modes(dwmac->phy_mode)); + return -EINVAL; + } + + return 0; +} + static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac) { int ret; @@ -188,10 +239,6 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac) case PHY_INTERFACE_MODE_RGMII_ID: case PHY_INTERFACE_MODE_RGMII_TXID: - /* enable RGMII mode */ - meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_RGMII_MODE, - PRG_ETH0_RGMII_MODE); - /* only relevant for RMII mode -> disable in RGMII mode */ meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_INVERTED_RMII_CLK, 0); @@ -224,10 +271,6 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac) break; case PHY_INTERFACE_MODE_RMII: - /* disable RGMII mode -> enables RMII mode */ - meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_RGMII_MODE, - 0); - /* invert internal clk_rmii_i to generate 25/2.5 tx_rx_clk */ meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_INVERTED_RMII_CLK, @@ -274,6 +317,11 @@ static int meson8b_dwmac_probe(struct platform_device *pdev) goto err_remove_config_dt; } + dwmac->data = (const struct meson8b_dwmac_data *) + of_device_get_match_data(&pdev->dev); + if (!dwmac->data) + return -EINVAL; + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); dwmac->regs = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(dwmac->regs)) { @@ -298,6 +346,10 @@ static int meson8b_dwmac_probe(struct platform_device *pdev) if (ret) goto err_remove_config_dt; + ret = meson8b_init_set_mode(dwmac); + if (ret) + goto err_remove_config_dt; + ret = meson8b_init_prg_eth(dwmac); if (ret) goto err_remove_config_dt; @@ -316,10 +368,31 @@ static int meson8b_dwmac_probe(struct platform_device *pdev) return ret; } +static const struct meson8b_dwmac_data meson8b_dwmac_data = { + .ext_phy_mode = false, +}; + +static const struct meson8b_dwmac_data meson_axg_dwmac_data = { + .ext_phy_mode = true, +}; + static const struct of_device_id meson8b_dwmac_match[] = { - { .compatible = "amlogic,meson8b-dwmac" }, - { .compatible = "amlogic,meson8m2-dwmac" }, - { .compatible = "amlogic,meson-gxbb-dwmac" }, + { + .compatible = "amlogic,meson8b-dwmac", + .data = &meson8b_dwmac_data, + }, + { + .compatible = "amlogic,meson8m2-dwmac", + .data = &meson8b_dwmac_data, + }, + { + .compatible = "amlogic,meson-gxbb-dwmac", + .data = &meson8b_dwmac_data, + }, + { + .compatible = "amlogic,meson-axg-dwmac", + .data = &meson_axg_dwmac_data, + }, { } }; MODULE_DEVICE_TABLE(of, meson8b_dwmac_match); -- 2.17.0 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 2/2] net: stmmac: dwmac-meson: extend phy mode setting @ 2018-04-26 16:05 ` Yixun Lan 0 siblings, 0 replies; 17+ messages in thread From: Yixun Lan @ 2018-04-26 16:05 UTC (permalink / raw) To: linus-amlogic In the Meson-AXG SoC, the phy mode setting of PRG_ETH0 in the glue layer is extended from bit[0] to bit[2:0]. There is no problem if we configure it to the RGMII 1000M PHY mode, since the register setting is coincidentally compatible with previous one, but for the RMII 100M PHY mode, the configuration need to be changed to value - b100. This patch was verified with a RTL8201F 100M ethernet PHY. Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> --- .../ethernet/stmicro/stmmac/dwmac-meson8b.c | 95 ++++++++++++++++--- 1 file changed, 84 insertions(+), 11 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c index 7cb794094a70..e3688b6dd87c 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c @@ -18,6 +18,7 @@ #include <linux/io.h> #include <linux/ioport.h> #include <linux/module.h> +#include <linux/of_device.h> #include <linux/of_net.h> #include <linux/mfd/syscon.h> #include <linux/platform_device.h> @@ -29,6 +30,10 @@ #define PRG_ETH0_RGMII_MODE BIT(0) +#define PRG_ETH0_EXT_PHY_MODE_MASK GENMASK(2, 0) +#define PRG_ETH0_EXT_RGMII_MODE 1 +#define PRG_ETH0_EXT_RMII_MODE 4 + /* mux to choose between fclk_div2 (bit unset) and mpll2 (bit set) */ #define PRG_ETH0_CLK_M250_SEL_SHIFT 4 #define PRG_ETH0_CLK_M250_SEL_MASK GENMASK(4, 4) @@ -46,10 +51,16 @@ #define PRG_ETH0_TX_AND_PHY_REF_CLK BIT(12) #define MUX_CLK_NUM_PARENTS 2 +struct meson8b_dwmac_data { + bool ext_phy_mode; +}; struct meson8b_dwmac { struct device *dev; void __iomem *regs; + + const struct meson8b_dwmac_data *data; + phy_interface_t phy_mode; struct clk *rgmii_tx_clk; u32 tx_delay_ns; @@ -171,6 +182,46 @@ static int meson8b_init_rgmii_tx_clk(struct meson8b_dwmac *dwmac) return 0; } +static int meson8b_init_set_mode(struct meson8b_dwmac *dwmac) +{ + bool ext_phy_mode = dwmac->data->ext_phy_mode; + + switch (dwmac->phy_mode) { + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_TXID: + /* enable RGMII mode */ + if (ext_phy_mode) + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, + PRG_ETH0_EXT_PHY_MODE_MASK, + PRG_ETH0_EXT_RGMII_MODE); + else + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, + PRG_ETH0_RGMII_MODE, + PRG_ETH0_RGMII_MODE); + + break; + case PHY_INTERFACE_MODE_RMII: + /* disable RGMII mode -> enables RMII mode */ + if (ext_phy_mode) + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, + PRG_ETH0_EXT_PHY_MODE_MASK, + PRG_ETH0_EXT_RMII_MODE); + else + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, + PRG_ETH0_RGMII_MODE, 0); + + break; + default: + dev_err(dwmac->dev, "fail to set phy-mode %s\n", + phy_modes(dwmac->phy_mode)); + return -EINVAL; + } + + return 0; +} + static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac) { int ret; @@ -188,10 +239,6 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac) case PHY_INTERFACE_MODE_RGMII_ID: case PHY_INTERFACE_MODE_RGMII_TXID: - /* enable RGMII mode */ - meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_RGMII_MODE, - PRG_ETH0_RGMII_MODE); - /* only relevant for RMII mode -> disable in RGMII mode */ meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_INVERTED_RMII_CLK, 0); @@ -224,10 +271,6 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac) break; case PHY_INTERFACE_MODE_RMII: - /* disable RGMII mode -> enables RMII mode */ - meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_RGMII_MODE, - 0); - /* invert internal clk_rmii_i to generate 25/2.5 tx_rx_clk */ meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_INVERTED_RMII_CLK, @@ -274,6 +317,11 @@ static int meson8b_dwmac_probe(struct platform_device *pdev) goto err_remove_config_dt; } + dwmac->data = (const struct meson8b_dwmac_data *) + of_device_get_match_data(&pdev->dev); + if (!dwmac->data) + return -EINVAL; + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); dwmac->regs = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(dwmac->regs)) { @@ -298,6 +346,10 @@ static int meson8b_dwmac_probe(struct platform_device *pdev) if (ret) goto err_remove_config_dt; + ret = meson8b_init_set_mode(dwmac); + if (ret) + goto err_remove_config_dt; + ret = meson8b_init_prg_eth(dwmac); if (ret) goto err_remove_config_dt; @@ -316,10 +368,31 @@ static int meson8b_dwmac_probe(struct platform_device *pdev) return ret; } +static const struct meson8b_dwmac_data meson8b_dwmac_data = { + .ext_phy_mode = false, +}; + +static const struct meson8b_dwmac_data meson_axg_dwmac_data = { + .ext_phy_mode = true, +}; + static const struct of_device_id meson8b_dwmac_match[] = { - { .compatible = "amlogic,meson8b-dwmac" }, - { .compatible = "amlogic,meson8m2-dwmac" }, - { .compatible = "amlogic,meson-gxbb-dwmac" }, + { + .compatible = "amlogic,meson8b-dwmac", + .data = &meson8b_dwmac_data, + }, + { + .compatible = "amlogic,meson8m2-dwmac", + .data = &meson8b_dwmac_data, + }, + { + .compatible = "amlogic,meson-gxbb-dwmac", + .data = &meson8b_dwmac_data, + }, + { + .compatible = "amlogic,meson-axg-dwmac", + .data = &meson_axg_dwmac_data, + }, { } }; MODULE_DEVICE_TABLE(of, meson8b_dwmac_match); -- 2.17.0 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 2/2] net: stmmac: dwmac-meson: extend phy mode setting @ 2018-04-26 16:05 ` Yixun Lan 0 siblings, 0 replies; 17+ messages in thread From: Yixun Lan @ 2018-04-26 16:05 UTC (permalink / raw) To: linux-arm-kernel In the Meson-AXG SoC, the phy mode setting of PRG_ETH0 in the glue layer is extended from bit[0] to bit[2:0]. There is no problem if we configure it to the RGMII 1000M PHY mode, since the register setting is coincidentally compatible with previous one, but for the RMII 100M PHY mode, the configuration need to be changed to value - b100. This patch was verified with a RTL8201F 100M ethernet PHY. Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> --- .../ethernet/stmicro/stmmac/dwmac-meson8b.c | 95 ++++++++++++++++--- 1 file changed, 84 insertions(+), 11 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c index 7cb794094a70..e3688b6dd87c 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c @@ -18,6 +18,7 @@ #include <linux/io.h> #include <linux/ioport.h> #include <linux/module.h> +#include <linux/of_device.h> #include <linux/of_net.h> #include <linux/mfd/syscon.h> #include <linux/platform_device.h> @@ -29,6 +30,10 @@ #define PRG_ETH0_RGMII_MODE BIT(0) +#define PRG_ETH0_EXT_PHY_MODE_MASK GENMASK(2, 0) +#define PRG_ETH0_EXT_RGMII_MODE 1 +#define PRG_ETH0_EXT_RMII_MODE 4 + /* mux to choose between fclk_div2 (bit unset) and mpll2 (bit set) */ #define PRG_ETH0_CLK_M250_SEL_SHIFT 4 #define PRG_ETH0_CLK_M250_SEL_MASK GENMASK(4, 4) @@ -46,10 +51,16 @@ #define PRG_ETH0_TX_AND_PHY_REF_CLK BIT(12) #define MUX_CLK_NUM_PARENTS 2 +struct meson8b_dwmac_data { + bool ext_phy_mode; +}; struct meson8b_dwmac { struct device *dev; void __iomem *regs; + + const struct meson8b_dwmac_data *data; + phy_interface_t phy_mode; struct clk *rgmii_tx_clk; u32 tx_delay_ns; @@ -171,6 +182,46 @@ static int meson8b_init_rgmii_tx_clk(struct meson8b_dwmac *dwmac) return 0; } +static int meson8b_init_set_mode(struct meson8b_dwmac *dwmac) +{ + bool ext_phy_mode = dwmac->data->ext_phy_mode; + + switch (dwmac->phy_mode) { + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_TXID: + /* enable RGMII mode */ + if (ext_phy_mode) + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, + PRG_ETH0_EXT_PHY_MODE_MASK, + PRG_ETH0_EXT_RGMII_MODE); + else + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, + PRG_ETH0_RGMII_MODE, + PRG_ETH0_RGMII_MODE); + + break; + case PHY_INTERFACE_MODE_RMII: + /* disable RGMII mode -> enables RMII mode */ + if (ext_phy_mode) + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, + PRG_ETH0_EXT_PHY_MODE_MASK, + PRG_ETH0_EXT_RMII_MODE); + else + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, + PRG_ETH0_RGMII_MODE, 0); + + break; + default: + dev_err(dwmac->dev, "fail to set phy-mode %s\n", + phy_modes(dwmac->phy_mode)); + return -EINVAL; + } + + return 0; +} + static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac) { int ret; @@ -188,10 +239,6 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac) case PHY_INTERFACE_MODE_RGMII_ID: case PHY_INTERFACE_MODE_RGMII_TXID: - /* enable RGMII mode */ - meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_RGMII_MODE, - PRG_ETH0_RGMII_MODE); - /* only relevant for RMII mode -> disable in RGMII mode */ meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_INVERTED_RMII_CLK, 0); @@ -224,10 +271,6 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac) break; case PHY_INTERFACE_MODE_RMII: - /* disable RGMII mode -> enables RMII mode */ - meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_RGMII_MODE, - 0); - /* invert internal clk_rmii_i to generate 25/2.5 tx_rx_clk */ meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_INVERTED_RMII_CLK, @@ -274,6 +317,11 @@ static int meson8b_dwmac_probe(struct platform_device *pdev) goto err_remove_config_dt; } + dwmac->data = (const struct meson8b_dwmac_data *) + of_device_get_match_data(&pdev->dev); + if (!dwmac->data) + return -EINVAL; + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); dwmac->regs = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(dwmac->regs)) { @@ -298,6 +346,10 @@ static int meson8b_dwmac_probe(struct platform_device *pdev) if (ret) goto err_remove_config_dt; + ret = meson8b_init_set_mode(dwmac); + if (ret) + goto err_remove_config_dt; + ret = meson8b_init_prg_eth(dwmac); if (ret) goto err_remove_config_dt; @@ -316,10 +368,31 @@ static int meson8b_dwmac_probe(struct platform_device *pdev) return ret; } +static const struct meson8b_dwmac_data meson8b_dwmac_data = { + .ext_phy_mode = false, +}; + +static const struct meson8b_dwmac_data meson_axg_dwmac_data = { + .ext_phy_mode = true, +}; + static const struct of_device_id meson8b_dwmac_match[] = { - { .compatible = "amlogic,meson8b-dwmac" }, - { .compatible = "amlogic,meson8m2-dwmac" }, - { .compatible = "amlogic,meson-gxbb-dwmac" }, + { + .compatible = "amlogic,meson8b-dwmac", + .data = &meson8b_dwmac_data, + }, + { + .compatible = "amlogic,meson8m2-dwmac", + .data = &meson8b_dwmac_data, + }, + { + .compatible = "amlogic,meson-gxbb-dwmac", + .data = &meson8b_dwmac_data, + }, + { + .compatible = "amlogic,meson-axg-dwmac", + .data = &meson_axg_dwmac_data, + }, { } }; MODULE_DEVICE_TABLE(of, meson8b_dwmac_match); -- 2.17.0 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [PATCH 2/2] net: stmmac: dwmac-meson: extend phy mode setting 2018-04-26 16:05 ` Yixun Lan (?) @ 2018-04-26 8:47 ` Jerome Brunet -1 siblings, 0 replies; 17+ messages in thread From: Jerome Brunet @ 2018-04-26 8:47 UTC (permalink / raw) To: Yixun Lan, David S. Miller, netdev Cc: Kevin Hilman, Carlo Caione, Rob Herring, Martin Blumenstingl, linux-amlogic, linux-arm-kernel, linux-kernel On Thu, 2018-04-26 at 16:05 +0000, Yixun Lan wrote: > In the Meson-AXG SoC, the phy mode setting of PRG_ETH0 in the glue layer > is extended from bit[0] to bit[2:0]. > There is no problem if we configure it to the RGMII 1000M PHY mode, > since the register setting is coincidentally compatible with previous one, > but for the RMII 100M PHY mode, the configuration need to be changed to > value - b100. > This patch was verified with a RTL8201F 100M ethernet PHY. > > Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> > --- > .../ethernet/stmicro/stmmac/dwmac-meson8b.c | 95 ++++++++++++++++--- > 1 file changed, 84 insertions(+), 11 deletions(-) > > diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c > index 7cb794094a70..e3688b6dd87c 100644 > --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c > +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c > @@ -18,6 +18,7 @@ > #include <linux/io.h> > #include <linux/ioport.h> > #include <linux/module.h> > +#include <linux/of_device.h> > #include <linux/of_net.h> > #include <linux/mfd/syscon.h> > #include <linux/platform_device.h> > @@ -29,6 +30,10 @@ > > #define PRG_ETH0_RGMII_MODE BIT(0) > > +#define PRG_ETH0_EXT_PHY_MODE_MASK GENMASK(2, 0) > +#define PRG_ETH0_EXT_RGMII_MODE 1 > +#define PRG_ETH0_EXT_RMII_MODE 4 > + > /* mux to choose between fclk_div2 (bit unset) and mpll2 (bit set) */ > #define PRG_ETH0_CLK_M250_SEL_SHIFT 4 > #define PRG_ETH0_CLK_M250_SEL_MASK GENMASK(4, 4) > @@ -46,10 +51,16 @@ > #define PRG_ETH0_TX_AND_PHY_REF_CLK BIT(12) > > #define MUX_CLK_NUM_PARENTS 2 > +struct meson8b_dwmac_data { > + bool ext_phy_mode; > +}; > > struct meson8b_dwmac { > struct device *dev; > void __iomem *regs; > + > + const struct meson8b_dwmac_data *data; > + > phy_interface_t phy_mode; > struct clk *rgmii_tx_clk; > u32 tx_delay_ns; > @@ -171,6 +182,46 @@ static int meson8b_init_rgmii_tx_clk(struct meson8b_dwmac *dwmac) > return 0; > } > > +static int meson8b_init_set_mode(struct meson8b_dwmac *dwmac) > +{ > + bool ext_phy_mode = dwmac->data->ext_phy_mode; > + > + switch (dwmac->phy_mode) { > + case PHY_INTERFACE_MODE_RGMII: > + case PHY_INTERFACE_MODE_RGMII_RXID: > + case PHY_INTERFACE_MODE_RGMII_ID: > + case PHY_INTERFACE_MODE_RGMII_TXID: > + /* enable RGMII mode */ > + if (ext_phy_mode) Looks weird to have this if target at a specific SoC withing a function named after another SoC Couldn't you make one function per soc type, and pass that function pointer in the match data ? > + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, > + PRG_ETH0_EXT_PHY_MODE_MASK, > + PRG_ETH0_EXT_RGMII_MODE); > + else > + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, > + PRG_ETH0_RGMII_MODE, > + PRG_ETH0_RGMII_MODE); > + > + break; > + case PHY_INTERFACE_MODE_RMII: > + /* disable RGMII mode -> enables RMII mode */ > + if (ext_phy_mode) > + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, > + PRG_ETH0_EXT_PHY_MODE_MASK, > + PRG_ETH0_EXT_RMII_MODE); > + else > + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, > + PRG_ETH0_RGMII_MODE, 0); > + > + break; > + default: > + dev_err(dwmac->dev, "fail to set phy-mode %s\n", > + phy_modes(dwmac->phy_mode)); > + return -EINVAL; > + } > + > + return 0; > +} > + > static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac) > { > int ret; > @@ -188,10 +239,6 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac) > > case PHY_INTERFACE_MODE_RGMII_ID: > case PHY_INTERFACE_MODE_RGMII_TXID: > - /* enable RGMII mode */ > - meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_RGMII_MODE, > - PRG_ETH0_RGMII_MODE); > - > /* only relevant for RMII mode -> disable in RGMII mode */ > meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, > PRG_ETH0_INVERTED_RMII_CLK, 0); > @@ -224,10 +271,6 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac) > break; > > case PHY_INTERFACE_MODE_RMII: > - /* disable RGMII mode -> enables RMII mode */ > - meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_RGMII_MODE, > - 0); > - > /* invert internal clk_rmii_i to generate 25/2.5 tx_rx_clk */ > meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, > PRG_ETH0_INVERTED_RMII_CLK, > @@ -274,6 +317,11 @@ static int meson8b_dwmac_probe(struct platform_device *pdev) > goto err_remove_config_dt; > } > > + dwmac->data = (const struct meson8b_dwmac_data *) > + of_device_get_match_data(&pdev->dev); > + if (!dwmac->data) > + return -EINVAL; > + > res = platform_get_resource(pdev, IORESOURCE_MEM, 1); > dwmac->regs = devm_ioremap_resource(&pdev->dev, res); > if (IS_ERR(dwmac->regs)) { > @@ -298,6 +346,10 @@ static int meson8b_dwmac_probe(struct platform_device *pdev) > if (ret) > goto err_remove_config_dt; > > + ret = meson8b_init_set_mode(dwmac); > + if (ret) > + goto err_remove_config_dt; > + > ret = meson8b_init_prg_eth(dwmac); > if (ret) > goto err_remove_config_dt; > @@ -316,10 +368,31 @@ static int meson8b_dwmac_probe(struct platform_device *pdev) > return ret; > } > > +static const struct meson8b_dwmac_data meson8b_dwmac_data = { > + .ext_phy_mode = false, > +}; > + > +static const struct meson8b_dwmac_data meson_axg_dwmac_data = { > + .ext_phy_mode = true, > +}; > + > static const struct of_device_id meson8b_dwmac_match[] = { > - { .compatible = "amlogic,meson8b-dwmac" }, > - { .compatible = "amlogic,meson8m2-dwmac" }, > - { .compatible = "amlogic,meson-gxbb-dwmac" }, > + { > + .compatible = "amlogic,meson8b-dwmac", > + .data = &meson8b_dwmac_data, > + }, > + { > + .compatible = "amlogic,meson8m2-dwmac", > + .data = &meson8b_dwmac_data, > + }, > + { > + .compatible = "amlogic,meson-gxbb-dwmac", > + .data = &meson8b_dwmac_data, > + }, > + { > + .compatible = "amlogic,meson-axg-dwmac", > + .data = &meson_axg_dwmac_data, > + }, > { } > }; > MODULE_DEVICE_TABLE(of, meson8b_dwmac_match); ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 2/2] net: stmmac: dwmac-meson: extend phy mode setting @ 2018-04-26 8:47 ` Jerome Brunet 0 siblings, 0 replies; 17+ messages in thread From: Jerome Brunet @ 2018-04-26 8:47 UTC (permalink / raw) To: linus-amlogic On Thu, 2018-04-26 at 16:05 +0000, Yixun Lan wrote: > In the Meson-AXG SoC, the phy mode setting of PRG_ETH0 in the glue layer > is extended from bit[0] to bit[2:0]. > There is no problem if we configure it to the RGMII 1000M PHY mode, > since the register setting is coincidentally compatible with previous one, > but for the RMII 100M PHY mode, the configuration need to be changed to > value - b100. > This patch was verified with a RTL8201F 100M ethernet PHY. > > Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> > --- > .../ethernet/stmicro/stmmac/dwmac-meson8b.c | 95 ++++++++++++++++--- > 1 file changed, 84 insertions(+), 11 deletions(-) > > diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c > index 7cb794094a70..e3688b6dd87c 100644 > --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c > +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c > @@ -18,6 +18,7 @@ > #include <linux/io.h> > #include <linux/ioport.h> > #include <linux/module.h> > +#include <linux/of_device.h> > #include <linux/of_net.h> > #include <linux/mfd/syscon.h> > #include <linux/platform_device.h> > @@ -29,6 +30,10 @@ > > #define PRG_ETH0_RGMII_MODE BIT(0) > > +#define PRG_ETH0_EXT_PHY_MODE_MASK GENMASK(2, 0) > +#define PRG_ETH0_EXT_RGMII_MODE 1 > +#define PRG_ETH0_EXT_RMII_MODE 4 > + > /* mux to choose between fclk_div2 (bit unset) and mpll2 (bit set) */ > #define PRG_ETH0_CLK_M250_SEL_SHIFT 4 > #define PRG_ETH0_CLK_M250_SEL_MASK GENMASK(4, 4) > @@ -46,10 +51,16 @@ > #define PRG_ETH0_TX_AND_PHY_REF_CLK BIT(12) > > #define MUX_CLK_NUM_PARENTS 2 > +struct meson8b_dwmac_data { > + bool ext_phy_mode; > +}; > > struct meson8b_dwmac { > struct device *dev; > void __iomem *regs; > + > + const struct meson8b_dwmac_data *data; > + > phy_interface_t phy_mode; > struct clk *rgmii_tx_clk; > u32 tx_delay_ns; > @@ -171,6 +182,46 @@ static int meson8b_init_rgmii_tx_clk(struct meson8b_dwmac *dwmac) > return 0; > } > > +static int meson8b_init_set_mode(struct meson8b_dwmac *dwmac) > +{ > + bool ext_phy_mode = dwmac->data->ext_phy_mode; > + > + switch (dwmac->phy_mode) { > + case PHY_INTERFACE_MODE_RGMII: > + case PHY_INTERFACE_MODE_RGMII_RXID: > + case PHY_INTERFACE_MODE_RGMII_ID: > + case PHY_INTERFACE_MODE_RGMII_TXID: > + /* enable RGMII mode */ > + if (ext_phy_mode) Looks weird to have this if target at a specific SoC withing a function named after another SoC Couldn't you make one function per soc type, and pass that function pointer in the match data ? > + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, > + PRG_ETH0_EXT_PHY_MODE_MASK, > + PRG_ETH0_EXT_RGMII_MODE); > + else > + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, > + PRG_ETH0_RGMII_MODE, > + PRG_ETH0_RGMII_MODE); > + > + break; > + case PHY_INTERFACE_MODE_RMII: > + /* disable RGMII mode -> enables RMII mode */ > + if (ext_phy_mode) > + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, > + PRG_ETH0_EXT_PHY_MODE_MASK, > + PRG_ETH0_EXT_RMII_MODE); > + else > + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, > + PRG_ETH0_RGMII_MODE, 0); > + > + break; > + default: > + dev_err(dwmac->dev, "fail to set phy-mode %s\n", > + phy_modes(dwmac->phy_mode)); > + return -EINVAL; > + } > + > + return 0; > +} > + > static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac) > { > int ret; > @@ -188,10 +239,6 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac) > > case PHY_INTERFACE_MODE_RGMII_ID: > case PHY_INTERFACE_MODE_RGMII_TXID: > - /* enable RGMII mode */ > - meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_RGMII_MODE, > - PRG_ETH0_RGMII_MODE); > - > /* only relevant for RMII mode -> disable in RGMII mode */ > meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, > PRG_ETH0_INVERTED_RMII_CLK, 0); > @@ -224,10 +271,6 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac) > break; > > case PHY_INTERFACE_MODE_RMII: > - /* disable RGMII mode -> enables RMII mode */ > - meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_RGMII_MODE, > - 0); > - > /* invert internal clk_rmii_i to generate 25/2.5 tx_rx_clk */ > meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, > PRG_ETH0_INVERTED_RMII_CLK, > @@ -274,6 +317,11 @@ static int meson8b_dwmac_probe(struct platform_device *pdev) > goto err_remove_config_dt; > } > > + dwmac->data = (const struct meson8b_dwmac_data *) > + of_device_get_match_data(&pdev->dev); > + if (!dwmac->data) > + return -EINVAL; > + > res = platform_get_resource(pdev, IORESOURCE_MEM, 1); > dwmac->regs = devm_ioremap_resource(&pdev->dev, res); > if (IS_ERR(dwmac->regs)) { > @@ -298,6 +346,10 @@ static int meson8b_dwmac_probe(struct platform_device *pdev) > if (ret) > goto err_remove_config_dt; > > + ret = meson8b_init_set_mode(dwmac); > + if (ret) > + goto err_remove_config_dt; > + > ret = meson8b_init_prg_eth(dwmac); > if (ret) > goto err_remove_config_dt; > @@ -316,10 +368,31 @@ static int meson8b_dwmac_probe(struct platform_device *pdev) > return ret; > } > > +static const struct meson8b_dwmac_data meson8b_dwmac_data = { > + .ext_phy_mode = false, > +}; > + > +static const struct meson8b_dwmac_data meson_axg_dwmac_data = { > + .ext_phy_mode = true, > +}; > + > static const struct of_device_id meson8b_dwmac_match[] = { > - { .compatible = "amlogic,meson8b-dwmac" }, > - { .compatible = "amlogic,meson8m2-dwmac" }, > - { .compatible = "amlogic,meson-gxbb-dwmac" }, > + { > + .compatible = "amlogic,meson8b-dwmac", > + .data = &meson8b_dwmac_data, > + }, > + { > + .compatible = "amlogic,meson8m2-dwmac", > + .data = &meson8b_dwmac_data, > + }, > + { > + .compatible = "amlogic,meson-gxbb-dwmac", > + .data = &meson8b_dwmac_data, > + }, > + { > + .compatible = "amlogic,meson-axg-dwmac", > + .data = &meson_axg_dwmac_data, > + }, > { } > }; > MODULE_DEVICE_TABLE(of, meson8b_dwmac_match); ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 2/2] net: stmmac: dwmac-meson: extend phy mode setting @ 2018-04-26 8:47 ` Jerome Brunet 0 siblings, 0 replies; 17+ messages in thread From: Jerome Brunet @ 2018-04-26 8:47 UTC (permalink / raw) To: linux-arm-kernel On Thu, 2018-04-26 at 16:05 +0000, Yixun Lan wrote: > In the Meson-AXG SoC, the phy mode setting of PRG_ETH0 in the glue layer > is extended from bit[0] to bit[2:0]. > There is no problem if we configure it to the RGMII 1000M PHY mode, > since the register setting is coincidentally compatible with previous one, > but for the RMII 100M PHY mode, the configuration need to be changed to > value - b100. > This patch was verified with a RTL8201F 100M ethernet PHY. > > Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> > --- > .../ethernet/stmicro/stmmac/dwmac-meson8b.c | 95 ++++++++++++++++--- > 1 file changed, 84 insertions(+), 11 deletions(-) > > diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c > index 7cb794094a70..e3688b6dd87c 100644 > --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c > +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c > @@ -18,6 +18,7 @@ > #include <linux/io.h> > #include <linux/ioport.h> > #include <linux/module.h> > +#include <linux/of_device.h> > #include <linux/of_net.h> > #include <linux/mfd/syscon.h> > #include <linux/platform_device.h> > @@ -29,6 +30,10 @@ > > #define PRG_ETH0_RGMII_MODE BIT(0) > > +#define PRG_ETH0_EXT_PHY_MODE_MASK GENMASK(2, 0) > +#define PRG_ETH0_EXT_RGMII_MODE 1 > +#define PRG_ETH0_EXT_RMII_MODE 4 > + > /* mux to choose between fclk_div2 (bit unset) and mpll2 (bit set) */ > #define PRG_ETH0_CLK_M250_SEL_SHIFT 4 > #define PRG_ETH0_CLK_M250_SEL_MASK GENMASK(4, 4) > @@ -46,10 +51,16 @@ > #define PRG_ETH0_TX_AND_PHY_REF_CLK BIT(12) > > #define MUX_CLK_NUM_PARENTS 2 > +struct meson8b_dwmac_data { > + bool ext_phy_mode; > +}; > > struct meson8b_dwmac { > struct device *dev; > void __iomem *regs; > + > + const struct meson8b_dwmac_data *data; > + > phy_interface_t phy_mode; > struct clk *rgmii_tx_clk; > u32 tx_delay_ns; > @@ -171,6 +182,46 @@ static int meson8b_init_rgmii_tx_clk(struct meson8b_dwmac *dwmac) > return 0; > } > > +static int meson8b_init_set_mode(struct meson8b_dwmac *dwmac) > +{ > + bool ext_phy_mode = dwmac->data->ext_phy_mode; > + > + switch (dwmac->phy_mode) { > + case PHY_INTERFACE_MODE_RGMII: > + case PHY_INTERFACE_MODE_RGMII_RXID: > + case PHY_INTERFACE_MODE_RGMII_ID: > + case PHY_INTERFACE_MODE_RGMII_TXID: > + /* enable RGMII mode */ > + if (ext_phy_mode) Looks weird to have this if target at a specific SoC withing a function named after another SoC Couldn't you make one function per soc type, and pass that function pointer in the match data ? > + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, > + PRG_ETH0_EXT_PHY_MODE_MASK, > + PRG_ETH0_EXT_RGMII_MODE); > + else > + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, > + PRG_ETH0_RGMII_MODE, > + PRG_ETH0_RGMII_MODE); > + > + break; > + case PHY_INTERFACE_MODE_RMII: > + /* disable RGMII mode -> enables RMII mode */ > + if (ext_phy_mode) > + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, > + PRG_ETH0_EXT_PHY_MODE_MASK, > + PRG_ETH0_EXT_RMII_MODE); > + else > + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, > + PRG_ETH0_RGMII_MODE, 0); > + > + break; > + default: > + dev_err(dwmac->dev, "fail to set phy-mode %s\n", > + phy_modes(dwmac->phy_mode)); > + return -EINVAL; > + } > + > + return 0; > +} > + > static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac) > { > int ret; > @@ -188,10 +239,6 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac) > > case PHY_INTERFACE_MODE_RGMII_ID: > case PHY_INTERFACE_MODE_RGMII_TXID: > - /* enable RGMII mode */ > - meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_RGMII_MODE, > - PRG_ETH0_RGMII_MODE); > - > /* only relevant for RMII mode -> disable in RGMII mode */ > meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, > PRG_ETH0_INVERTED_RMII_CLK, 0); > @@ -224,10 +271,6 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac) > break; > > case PHY_INTERFACE_MODE_RMII: > - /* disable RGMII mode -> enables RMII mode */ > - meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_RGMII_MODE, > - 0); > - > /* invert internal clk_rmii_i to generate 25/2.5 tx_rx_clk */ > meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, > PRG_ETH0_INVERTED_RMII_CLK, > @@ -274,6 +317,11 @@ static int meson8b_dwmac_probe(struct platform_device *pdev) > goto err_remove_config_dt; > } > > + dwmac->data = (const struct meson8b_dwmac_data *) > + of_device_get_match_data(&pdev->dev); > + if (!dwmac->data) > + return -EINVAL; > + > res = platform_get_resource(pdev, IORESOURCE_MEM, 1); > dwmac->regs = devm_ioremap_resource(&pdev->dev, res); > if (IS_ERR(dwmac->regs)) { > @@ -298,6 +346,10 @@ static int meson8b_dwmac_probe(struct platform_device *pdev) > if (ret) > goto err_remove_config_dt; > > + ret = meson8b_init_set_mode(dwmac); > + if (ret) > + goto err_remove_config_dt; > + > ret = meson8b_init_prg_eth(dwmac); > if (ret) > goto err_remove_config_dt; > @@ -316,10 +368,31 @@ static int meson8b_dwmac_probe(struct platform_device *pdev) > return ret; > } > > +static const struct meson8b_dwmac_data meson8b_dwmac_data = { > + .ext_phy_mode = false, > +}; > + > +static const struct meson8b_dwmac_data meson_axg_dwmac_data = { > + .ext_phy_mode = true, > +}; > + > static const struct of_device_id meson8b_dwmac_match[] = { > - { .compatible = "amlogic,meson8b-dwmac" }, > - { .compatible = "amlogic,meson8m2-dwmac" }, > - { .compatible = "amlogic,meson-gxbb-dwmac" }, > + { > + .compatible = "amlogic,meson8b-dwmac", > + .data = &meson8b_dwmac_data, > + }, > + { > + .compatible = "amlogic,meson8m2-dwmac", > + .data = &meson8b_dwmac_data, > + }, > + { > + .compatible = "amlogic,meson-gxbb-dwmac", > + .data = &meson8b_dwmac_data, > + }, > + { > + .compatible = "amlogic,meson-axg-dwmac", > + .data = &meson_axg_dwmac_data, > + }, > { } > }; > MODULE_DEVICE_TABLE(of, meson8b_dwmac_match); ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 2/2] net: stmmac: dwmac-meson: extend phy mode setting 2018-04-26 8:47 ` Jerome Brunet (?) @ 2018-04-27 3:09 ` Yixun Lan -1 siblings, 0 replies; 17+ messages in thread From: Yixun Lan @ 2018-04-27 3:09 UTC (permalink / raw) To: Jerome Brunet, David S. Miller, netdev Cc: yixun.lan, Kevin Hilman, Carlo Caione, Rob Herring, Martin Blumenstingl, linux-amlogic, linux-arm-kernel, linux-kernel Hi Jerome On 04/26/18 16:47, Jerome Brunet wrote: > On Thu, 2018-04-26 at 16:05 +0000, Yixun Lan wrote: >> In the Meson-AXG SoC, the phy mode setting of PRG_ETH0 in the glue layer >> is extended from bit[0] to bit[2:0]. >> There is no problem if we configure it to the RGMII 1000M PHY mode, >> since the register setting is coincidentally compatible with previous one, >> but for the RMII 100M PHY mode, the configuration need to be changed to >> value - b100. >> This patch was verified with a RTL8201F 100M ethernet PHY. >> >> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> >> --- >> .../ethernet/stmicro/stmmac/dwmac-meson8b.c | 95 ++++++++++++++++--- >> 1 file changed, 84 insertions(+), 11 deletions(-) >> >> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c >> index 7cb794094a70..e3688b6dd87c 100644 >> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c >> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c >> @@ -18,6 +18,7 @@ >> #include <linux/io.h> >> #include <linux/ioport.h> >> #include <linux/module.h> >> +#include <linux/of_device.h> >> #include <linux/of_net.h> >> #include <linux/mfd/syscon.h> >> #include <linux/platform_device.h> >> @@ -29,6 +30,10 @@ >> >> #define PRG_ETH0_RGMII_MODE BIT(0) >> >> +#define PRG_ETH0_EXT_PHY_MODE_MASK GENMASK(2, 0) >> +#define PRG_ETH0_EXT_RGMII_MODE 1 >> +#define PRG_ETH0_EXT_RMII_MODE 4 >> + >> /* mux to choose between fclk_div2 (bit unset) and mpll2 (bit set) */ >> #define PRG_ETH0_CLK_M250_SEL_SHIFT 4 >> #define PRG_ETH0_CLK_M250_SEL_MASK GENMASK(4, 4) >> @@ -46,10 +51,16 @@ >> #define PRG_ETH0_TX_AND_PHY_REF_CLK BIT(12) >> >> #define MUX_CLK_NUM_PARENTS 2 >> +struct meson8b_dwmac_data { >> + bool ext_phy_mode; >> +}; >> >> struct meson8b_dwmac { >> struct device *dev; >> void __iomem *regs; >> + >> + const struct meson8b_dwmac_data *data; >> + >> phy_interface_t phy_mode; >> struct clk *rgmii_tx_clk; >> u32 tx_delay_ns; >> @@ -171,6 +182,46 @@ static int meson8b_init_rgmii_tx_clk(struct meson8b_dwmac *dwmac) >> return 0; >> } >> >> +static int meson8b_init_set_mode(struct meson8b_dwmac *dwmac) >> +{ >> + bool ext_phy_mode = dwmac->data->ext_phy_mode; >> + >> + switch (dwmac->phy_mode) { >> + case PHY_INTERFACE_MODE_RGMII: >> + case PHY_INTERFACE_MODE_RGMII_RXID: >> + case PHY_INTERFACE_MODE_RGMII_ID: >> + case PHY_INTERFACE_MODE_RGMII_TXID: >> + /* enable RGMII mode */ >> + if (ext_phy_mode) > > Looks weird to have this if target at a specific SoC withing a function named > after another SoC > > Couldn't you make one function per soc type, and pass that function pointer in > the match data ? > sounds good, I can do this >> + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, >> + PRG_ETH0_EXT_PHY_MODE_MASK, >> + PRG_ETH0_EXT_RGMII_MODE); >> + else >> + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, >> + PRG_ETH0_RGMII_MODE, >> + PRG_ETH0_RGMII_MODE); >> + >> + break; >> + case PHY_INTERFACE_MODE_RMII: >> + /* disable RGMII mode -> enables RMII mode */ >> + if (ext_phy_mode) >> + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, >> + PRG_ETH0_EXT_PHY_MODE_MASK, >> + PRG_ETH0_EXT_RMII_MODE); >> + else >> + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, >> + PRG_ETH0_RGMII_MODE, 0); >> + >> + break; >> + default: >> + dev_err(dwmac->dev, "fail to set phy-mode %s\n", >> + phy_modes(dwmac->phy_mode)); >> + return -EINVAL; >> + } >> + >> + return 0; >> +} >> + >> static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac) >> { >> int ret; >> @@ -188,10 +239,6 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac) >> >> case PHY_INTERFACE_MODE_RGMII_ID: >> case PHY_INTERFACE_MODE_RGMII_TXID: >> - /* enable RGMII mode */ >> - meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_RGMII_MODE, >> - PRG_ETH0_RGMII_MODE); >> - >> /* only relevant for RMII mode -> disable in RGMII mode */ >> meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, >> PRG_ETH0_INVERTED_RMII_CLK, 0); >> @@ -224,10 +271,6 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac) >> break; >> >> case PHY_INTERFACE_MODE_RMII: >> - /* disable RGMII mode -> enables RMII mode */ >> - meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_RGMII_MODE, >> - 0); >> - >> /* invert internal clk_rmii_i to generate 25/2.5 tx_rx_clk */ >> meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, >> PRG_ETH0_INVERTED_RMII_CLK, >> @@ -274,6 +317,11 @@ static int meson8b_dwmac_probe(struct platform_device *pdev) >> goto err_remove_config_dt; >> } >> >> + dwmac->data = (const struct meson8b_dwmac_data *) >> + of_device_get_match_data(&pdev->dev); >> + if (!dwmac->data) >> + return -EINVAL; >> + >> res = platform_get_resource(pdev, IORESOURCE_MEM, 1); >> dwmac->regs = devm_ioremap_resource(&pdev->dev, res); >> if (IS_ERR(dwmac->regs)) { >> @@ -298,6 +346,10 @@ static int meson8b_dwmac_probe(struct platform_device *pdev) >> if (ret) >> goto err_remove_config_dt; >> >> + ret = meson8b_init_set_mode(dwmac); >> + if (ret) >> + goto err_remove_config_dt; >> + >> ret = meson8b_init_prg_eth(dwmac); >> if (ret) >> goto err_remove_config_dt; >> @@ -316,10 +368,31 @@ static int meson8b_dwmac_probe(struct platform_device *pdev) >> return ret; >> } >> >> +static const struct meson8b_dwmac_data meson8b_dwmac_data = { >> + .ext_phy_mode = false, >> +}; >> + >> +static const struct meson8b_dwmac_data meson_axg_dwmac_data = { >> + .ext_phy_mode = true, >> +}; >> + >> static const struct of_device_id meson8b_dwmac_match[] = { >> - { .compatible = "amlogic,meson8b-dwmac" }, >> - { .compatible = "amlogic,meson8m2-dwmac" }, >> - { .compatible = "amlogic,meson-gxbb-dwmac" }, >> + { >> + .compatible = "amlogic,meson8b-dwmac", >> + .data = &meson8b_dwmac_data, >> + }, >> + { >> + .compatible = "amlogic,meson8m2-dwmac", >> + .data = &meson8b_dwmac_data, >> + }, >> + { >> + .compatible = "amlogic,meson-gxbb-dwmac", >> + .data = &meson8b_dwmac_data, >> + }, >> + { >> + .compatible = "amlogic,meson-axg-dwmac", >> + .data = &meson_axg_dwmac_data, >> + }, >> { } >> }; >> MODULE_DEVICE_TABLE(of, meson8b_dwmac_match); > > . > ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 2/2] net: stmmac: dwmac-meson: extend phy mode setting @ 2018-04-27 3:09 ` Yixun Lan 0 siblings, 0 replies; 17+ messages in thread From: Yixun Lan @ 2018-04-27 3:09 UTC (permalink / raw) To: linus-amlogic Hi Jerome On 04/26/18 16:47, Jerome Brunet wrote: > On Thu, 2018-04-26 at 16:05 +0000, Yixun Lan wrote: >> In the Meson-AXG SoC, the phy mode setting of PRG_ETH0 in the glue layer >> is extended from bit[0] to bit[2:0]. >> There is no problem if we configure it to the RGMII 1000M PHY mode, >> since the register setting is coincidentally compatible with previous one, >> but for the RMII 100M PHY mode, the configuration need to be changed to >> value - b100. >> This patch was verified with a RTL8201F 100M ethernet PHY. >> >> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> >> --- >> .../ethernet/stmicro/stmmac/dwmac-meson8b.c | 95 ++++++++++++++++--- >> 1 file changed, 84 insertions(+), 11 deletions(-) >> >> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c >> index 7cb794094a70..e3688b6dd87c 100644 >> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c >> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c >> @@ -18,6 +18,7 @@ >> #include <linux/io.h> >> #include <linux/ioport.h> >> #include <linux/module.h> >> +#include <linux/of_device.h> >> #include <linux/of_net.h> >> #include <linux/mfd/syscon.h> >> #include <linux/platform_device.h> >> @@ -29,6 +30,10 @@ >> >> #define PRG_ETH0_RGMII_MODE BIT(0) >> >> +#define PRG_ETH0_EXT_PHY_MODE_MASK GENMASK(2, 0) >> +#define PRG_ETH0_EXT_RGMII_MODE 1 >> +#define PRG_ETH0_EXT_RMII_MODE 4 >> + >> /* mux to choose between fclk_div2 (bit unset) and mpll2 (bit set) */ >> #define PRG_ETH0_CLK_M250_SEL_SHIFT 4 >> #define PRG_ETH0_CLK_M250_SEL_MASK GENMASK(4, 4) >> @@ -46,10 +51,16 @@ >> #define PRG_ETH0_TX_AND_PHY_REF_CLK BIT(12) >> >> #define MUX_CLK_NUM_PARENTS 2 >> +struct meson8b_dwmac_data { >> + bool ext_phy_mode; >> +}; >> >> struct meson8b_dwmac { >> struct device *dev; >> void __iomem *regs; >> + >> + const struct meson8b_dwmac_data *data; >> + >> phy_interface_t phy_mode; >> struct clk *rgmii_tx_clk; >> u32 tx_delay_ns; >> @@ -171,6 +182,46 @@ static int meson8b_init_rgmii_tx_clk(struct meson8b_dwmac *dwmac) >> return 0; >> } >> >> +static int meson8b_init_set_mode(struct meson8b_dwmac *dwmac) >> +{ >> + bool ext_phy_mode = dwmac->data->ext_phy_mode; >> + >> + switch (dwmac->phy_mode) { >> + case PHY_INTERFACE_MODE_RGMII: >> + case PHY_INTERFACE_MODE_RGMII_RXID: >> + case PHY_INTERFACE_MODE_RGMII_ID: >> + case PHY_INTERFACE_MODE_RGMII_TXID: >> + /* enable RGMII mode */ >> + if (ext_phy_mode) > > Looks weird to have this if target at a specific SoC withing a function named > after another SoC > > Couldn't you make one function per soc type, and pass that function pointer in > the match data ? > sounds good, I can do this >> + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, >> + PRG_ETH0_EXT_PHY_MODE_MASK, >> + PRG_ETH0_EXT_RGMII_MODE); >> + else >> + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, >> + PRG_ETH0_RGMII_MODE, >> + PRG_ETH0_RGMII_MODE); >> + >> + break; >> + case PHY_INTERFACE_MODE_RMII: >> + /* disable RGMII mode -> enables RMII mode */ >> + if (ext_phy_mode) >> + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, >> + PRG_ETH0_EXT_PHY_MODE_MASK, >> + PRG_ETH0_EXT_RMII_MODE); >> + else >> + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, >> + PRG_ETH0_RGMII_MODE, 0); >> + >> + break; >> + default: >> + dev_err(dwmac->dev, "fail to set phy-mode %s\n", >> + phy_modes(dwmac->phy_mode)); >> + return -EINVAL; >> + } >> + >> + return 0; >> +} >> + >> static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac) >> { >> int ret; >> @@ -188,10 +239,6 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac) >> >> case PHY_INTERFACE_MODE_RGMII_ID: >> case PHY_INTERFACE_MODE_RGMII_TXID: >> - /* enable RGMII mode */ >> - meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_RGMII_MODE, >> - PRG_ETH0_RGMII_MODE); >> - >> /* only relevant for RMII mode -> disable in RGMII mode */ >> meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, >> PRG_ETH0_INVERTED_RMII_CLK, 0); >> @@ -224,10 +271,6 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac) >> break; >> >> case PHY_INTERFACE_MODE_RMII: >> - /* disable RGMII mode -> enables RMII mode */ >> - meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_RGMII_MODE, >> - 0); >> - >> /* invert internal clk_rmii_i to generate 25/2.5 tx_rx_clk */ >> meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, >> PRG_ETH0_INVERTED_RMII_CLK, >> @@ -274,6 +317,11 @@ static int meson8b_dwmac_probe(struct platform_device *pdev) >> goto err_remove_config_dt; >> } >> >> + dwmac->data = (const struct meson8b_dwmac_data *) >> + of_device_get_match_data(&pdev->dev); >> + if (!dwmac->data) >> + return -EINVAL; >> + >> res = platform_get_resource(pdev, IORESOURCE_MEM, 1); >> dwmac->regs = devm_ioremap_resource(&pdev->dev, res); >> if (IS_ERR(dwmac->regs)) { >> @@ -298,6 +346,10 @@ static int meson8b_dwmac_probe(struct platform_device *pdev) >> if (ret) >> goto err_remove_config_dt; >> >> + ret = meson8b_init_set_mode(dwmac); >> + if (ret) >> + goto err_remove_config_dt; >> + >> ret = meson8b_init_prg_eth(dwmac); >> if (ret) >> goto err_remove_config_dt; >> @@ -316,10 +368,31 @@ static int meson8b_dwmac_probe(struct platform_device *pdev) >> return ret; >> } >> >> +static const struct meson8b_dwmac_data meson8b_dwmac_data = { >> + .ext_phy_mode = false, >> +}; >> + >> +static const struct meson8b_dwmac_data meson_axg_dwmac_data = { >> + .ext_phy_mode = true, >> +}; >> + >> static const struct of_device_id meson8b_dwmac_match[] = { >> - { .compatible = "amlogic,meson8b-dwmac" }, >> - { .compatible = "amlogic,meson8m2-dwmac" }, >> - { .compatible = "amlogic,meson-gxbb-dwmac" }, >> + { >> + .compatible = "amlogic,meson8b-dwmac", >> + .data = &meson8b_dwmac_data, >> + }, >> + { >> + .compatible = "amlogic,meson8m2-dwmac", >> + .data = &meson8b_dwmac_data, >> + }, >> + { >> + .compatible = "amlogic,meson-gxbb-dwmac", >> + .data = &meson8b_dwmac_data, >> + }, >> + { >> + .compatible = "amlogic,meson-axg-dwmac", >> + .data = &meson_axg_dwmac_data, >> + }, >> { } >> }; >> MODULE_DEVICE_TABLE(of, meson8b_dwmac_match); > > . > ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 2/2] net: stmmac: dwmac-meson: extend phy mode setting @ 2018-04-27 3:09 ` Yixun Lan 0 siblings, 0 replies; 17+ messages in thread From: Yixun Lan @ 2018-04-27 3:09 UTC (permalink / raw) To: linux-arm-kernel Hi Jerome On 04/26/18 16:47, Jerome Brunet wrote: > On Thu, 2018-04-26 at 16:05 +0000, Yixun Lan wrote: >> In the Meson-AXG SoC, the phy mode setting of PRG_ETH0 in the glue layer >> is extended from bit[0] to bit[2:0]. >> There is no problem if we configure it to the RGMII 1000M PHY mode, >> since the register setting is coincidentally compatible with previous one, >> but for the RMII 100M PHY mode, the configuration need to be changed to >> value - b100. >> This patch was verified with a RTL8201F 100M ethernet PHY. >> >> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> >> --- >> .../ethernet/stmicro/stmmac/dwmac-meson8b.c | 95 ++++++++++++++++--- >> 1 file changed, 84 insertions(+), 11 deletions(-) >> >> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c >> index 7cb794094a70..e3688b6dd87c 100644 >> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c >> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c >> @@ -18,6 +18,7 @@ >> #include <linux/io.h> >> #include <linux/ioport.h> >> #include <linux/module.h> >> +#include <linux/of_device.h> >> #include <linux/of_net.h> >> #include <linux/mfd/syscon.h> >> #include <linux/platform_device.h> >> @@ -29,6 +30,10 @@ >> >> #define PRG_ETH0_RGMII_MODE BIT(0) >> >> +#define PRG_ETH0_EXT_PHY_MODE_MASK GENMASK(2, 0) >> +#define PRG_ETH0_EXT_RGMII_MODE 1 >> +#define PRG_ETH0_EXT_RMII_MODE 4 >> + >> /* mux to choose between fclk_div2 (bit unset) and mpll2 (bit set) */ >> #define PRG_ETH0_CLK_M250_SEL_SHIFT 4 >> #define PRG_ETH0_CLK_M250_SEL_MASK GENMASK(4, 4) >> @@ -46,10 +51,16 @@ >> #define PRG_ETH0_TX_AND_PHY_REF_CLK BIT(12) >> >> #define MUX_CLK_NUM_PARENTS 2 >> +struct meson8b_dwmac_data { >> + bool ext_phy_mode; >> +}; >> >> struct meson8b_dwmac { >> struct device *dev; >> void __iomem *regs; >> + >> + const struct meson8b_dwmac_data *data; >> + >> phy_interface_t phy_mode; >> struct clk *rgmii_tx_clk; >> u32 tx_delay_ns; >> @@ -171,6 +182,46 @@ static int meson8b_init_rgmii_tx_clk(struct meson8b_dwmac *dwmac) >> return 0; >> } >> >> +static int meson8b_init_set_mode(struct meson8b_dwmac *dwmac) >> +{ >> + bool ext_phy_mode = dwmac->data->ext_phy_mode; >> + >> + switch (dwmac->phy_mode) { >> + case PHY_INTERFACE_MODE_RGMII: >> + case PHY_INTERFACE_MODE_RGMII_RXID: >> + case PHY_INTERFACE_MODE_RGMII_ID: >> + case PHY_INTERFACE_MODE_RGMII_TXID: >> + /* enable RGMII mode */ >> + if (ext_phy_mode) > > Looks weird to have this if target at a specific SoC withing a function named > after another SoC > > Couldn't you make one function per soc type, and pass that function pointer in > the match data ? > sounds good, I can do this >> + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, >> + PRG_ETH0_EXT_PHY_MODE_MASK, >> + PRG_ETH0_EXT_RGMII_MODE); >> + else >> + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, >> + PRG_ETH0_RGMII_MODE, >> + PRG_ETH0_RGMII_MODE); >> + >> + break; >> + case PHY_INTERFACE_MODE_RMII: >> + /* disable RGMII mode -> enables RMII mode */ >> + if (ext_phy_mode) >> + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, >> + PRG_ETH0_EXT_PHY_MODE_MASK, >> + PRG_ETH0_EXT_RMII_MODE); >> + else >> + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, >> + PRG_ETH0_RGMII_MODE, 0); >> + >> + break; >> + default: >> + dev_err(dwmac->dev, "fail to set phy-mode %s\n", >> + phy_modes(dwmac->phy_mode)); >> + return -EINVAL; >> + } >> + >> + return 0; >> +} >> + >> static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac) >> { >> int ret; >> @@ -188,10 +239,6 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac) >> >> case PHY_INTERFACE_MODE_RGMII_ID: >> case PHY_INTERFACE_MODE_RGMII_TXID: >> - /* enable RGMII mode */ >> - meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_RGMII_MODE, >> - PRG_ETH0_RGMII_MODE); >> - >> /* only relevant for RMII mode -> disable in RGMII mode */ >> meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, >> PRG_ETH0_INVERTED_RMII_CLK, 0); >> @@ -224,10 +271,6 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac) >> break; >> >> case PHY_INTERFACE_MODE_RMII: >> - /* disable RGMII mode -> enables RMII mode */ >> - meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_RGMII_MODE, >> - 0); >> - >> /* invert internal clk_rmii_i to generate 25/2.5 tx_rx_clk */ >> meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, >> PRG_ETH0_INVERTED_RMII_CLK, >> @@ -274,6 +317,11 @@ static int meson8b_dwmac_probe(struct platform_device *pdev) >> goto err_remove_config_dt; >> } >> >> + dwmac->data = (const struct meson8b_dwmac_data *) >> + of_device_get_match_data(&pdev->dev); >> + if (!dwmac->data) >> + return -EINVAL; >> + >> res = platform_get_resource(pdev, IORESOURCE_MEM, 1); >> dwmac->regs = devm_ioremap_resource(&pdev->dev, res); >> if (IS_ERR(dwmac->regs)) { >> @@ -298,6 +346,10 @@ static int meson8b_dwmac_probe(struct platform_device *pdev) >> if (ret) >> goto err_remove_config_dt; >> >> + ret = meson8b_init_set_mode(dwmac); >> + if (ret) >> + goto err_remove_config_dt; >> + >> ret = meson8b_init_prg_eth(dwmac); >> if (ret) >> goto err_remove_config_dt; >> @@ -316,10 +368,31 @@ static int meson8b_dwmac_probe(struct platform_device *pdev) >> return ret; >> } >> >> +static const struct meson8b_dwmac_data meson8b_dwmac_data = { >> + .ext_phy_mode = false, >> +}; >> + >> +static const struct meson8b_dwmac_data meson_axg_dwmac_data = { >> + .ext_phy_mode = true, >> +}; >> + >> static const struct of_device_id meson8b_dwmac_match[] = { >> - { .compatible = "amlogic,meson8b-dwmac" }, >> - { .compatible = "amlogic,meson8m2-dwmac" }, >> - { .compatible = "amlogic,meson-gxbb-dwmac" }, >> + { >> + .compatible = "amlogic,meson8b-dwmac", >> + .data = &meson8b_dwmac_data, >> + }, >> + { >> + .compatible = "amlogic,meson8m2-dwmac", >> + .data = &meson8b_dwmac_data, >> + }, >> + { >> + .compatible = "amlogic,meson-gxbb-dwmac", >> + .data = &meson8b_dwmac_data, >> + }, >> + { >> + .compatible = "amlogic,meson-axg-dwmac", >> + .data = &meson_axg_dwmac_data, >> + }, >> { } >> }; >> MODULE_DEVICE_TABLE(of, meson8b_dwmac_match); > > . > ^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2018-04-27 3:10 UTC | newest] Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2018-04-26 16:05 [PATCH 0/2] net: stmmac: dwmac-meson: 100M phy mode support for AXG SoC Yixun Lan 2018-04-26 16:05 ` Yixun Lan 2018-04-26 16:05 ` Yixun Lan 2018-04-26 16:05 ` Yixun Lan 2018-04-26 16:05 ` [PATCH 1/2] dt-bindings: net: meson-dwmac: new compatible name " Yixun Lan 2018-04-26 16:05 ` Yixun Lan 2018-04-26 16:05 ` Yixun Lan 2018-04-26 16:05 ` Yixun Lan 2018-04-26 16:05 ` [PATCH 2/2] net: stmmac: dwmac-meson: extend phy mode setting Yixun Lan 2018-04-26 16:05 ` Yixun Lan 2018-04-26 16:05 ` Yixun Lan 2018-04-26 8:47 ` Jerome Brunet 2018-04-26 8:47 ` Jerome Brunet 2018-04-26 8:47 ` Jerome Brunet 2018-04-27 3:09 ` Yixun Lan 2018-04-27 3:09 ` Yixun Lan 2018-04-27 3:09 ` Yixun Lan
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