From: Dong Aisheng <aisheng.dong@nxp.com> To: linux-arm-kernel@lists.infradead.org Cc: Dong Aisheng <aisheng.dong@nxp.com>, Mark Rutland <mark.rutland@arm.com>, dongas86@gmail.com, devicetree@vger.kernel.org, Rob Herring <robh+dt@kernel.org>, linux-imx@nxp.com, kernel@pengutronix.de, fabio.estevam@nxp.com, shawnguo@kernel.org Subject: [PATCH 2/4] dt-bindings: arm: fsl: add mu binding doc Date: Sat, 28 Apr 2018 02:46:14 +0800 [thread overview] Message-ID: <1524854776-14863-3-git-send-email-aisheng.dong@nxp.com> (raw) In-Reply-To: <1524854776-14863-1-git-send-email-aisheng.dong@nxp.com> The Messaging Unit module enables two processors within the SoC to communicate and coordinate by passing messages (e.g. data, status and control) through the MU interface. Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> --- .../devicetree/bindings/arm/freescale/fsl,mu.txt | 33 ++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,mu.txt diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,mu.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,mu.txt new file mode 100644 index 0000000..a7ceb1f --- /dev/null +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,mu.txt @@ -0,0 +1,33 @@ +NXP i.MX Messaging Unit (MU) +-------------------------------------------------------------------- + +The Messaging Unit module enables two processors within the SoC to +communicate and coordinate by passing messages (e.g. data, status +and control) through the MU interface. The MU also provides the ability +for one processor to signal the other processor using interrupts. + +Because the MU manages the messaging between processors, the MU uses +different clocks (from each side of the different peripheral buses). +Therefore, the MU must synchronize the accesses from one side to the +other. The MU accomplishes synchronization using two sets of matching +registers (Processor A-facing, Processor Bfacing). + +Messaging Unit Device Node: +============================= + +Required properties: +------------------- +- compatible : should be "fsl,<chip>-mu", the supported chips include + imx6sx, imx7d, imx7ulp, imx8qxp, imx8qm, imx8mq. +- reg : Should contain the registers location and length +- interrupts : Interrupt number. The interrupt specifier format depends + on the interrupt controller parent. + +Examples: +-------- +lsio_mu0: mu@5d1b0000 { + compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + reg = <0x0 0x5d1b0000 0x0 0x10000>; + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; + status = "okay"; +}; -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: aisheng.dong@nxp.com (Dong Aisheng) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 2/4] dt-bindings: arm: fsl: add mu binding doc Date: Sat, 28 Apr 2018 02:46:14 +0800 [thread overview] Message-ID: <1524854776-14863-3-git-send-email-aisheng.dong@nxp.com> (raw) In-Reply-To: <1524854776-14863-1-git-send-email-aisheng.dong@nxp.com> The Messaging Unit module enables two processors within the SoC to communicate and coordinate by passing messages (e.g. data, status and control) through the MU interface. Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree at vger.kernel.org Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> --- .../devicetree/bindings/arm/freescale/fsl,mu.txt | 33 ++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,mu.txt diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,mu.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,mu.txt new file mode 100644 index 0000000..a7ceb1f --- /dev/null +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,mu.txt @@ -0,0 +1,33 @@ +NXP i.MX Messaging Unit (MU) +-------------------------------------------------------------------- + +The Messaging Unit module enables two processors within the SoC to +communicate and coordinate by passing messages (e.g. data, status +and control) through the MU interface. The MU also provides the ability +for one processor to signal the other processor using interrupts. + +Because the MU manages the messaging between processors, the MU uses +different clocks (from each side of the different peripheral buses). +Therefore, the MU must synchronize the accesses from one side to the +other. The MU accomplishes synchronization using two sets of matching +registers (Processor A-facing, Processor Bfacing). + +Messaging Unit Device Node: +============================= + +Required properties: +------------------- +- compatible : should be "fsl,<chip>-mu", the supported chips include + imx6sx, imx7d, imx7ulp, imx8qxp, imx8qm, imx8mq. +- reg : Should contain the registers location and length +- interrupts : Interrupt number. The interrupt specifier format depends + on the interrupt controller parent. + +Examples: +-------- +lsio_mu0: mu at 5d1b0000 { + compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + reg = <0x0 0x5d1b0000 0x0 0x10000>; + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; + status = "okay"; +}; -- 2.7.4
next prev parent reply other threads:[~2018-04-27 18:46 UTC|newest] Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-04-27 18:46 [PATCH 0/4] soc: imx: add scu firmware api support Dong Aisheng 2018-04-27 18:46 ` [PATCH 1/4] soc: imx: add mu library functions support Dong Aisheng 2018-04-27 18:46 ` Dong Aisheng [this message] 2018-04-27 18:46 ` [PATCH 2/4] dt-bindings: arm: fsl: add mu binding doc Dong Aisheng 2018-05-01 15:25 ` Rob Herring 2018-05-01 15:25 ` Rob Herring 2018-05-02 17:29 ` A.s. Dong 2018-05-02 17:29 ` A.s. Dong 2018-04-27 18:46 ` [PATCH 3/4] dt-bindings: arm: fsl: add scu " Dong Aisheng 2018-04-27 18:46 ` Dong Aisheng 2018-05-01 15:29 ` Rob Herring 2018-05-01 15:29 ` Rob Herring 2018-05-01 5:59 ` [PATCH 0/4] soc: imx: add scu firmware api support Oleksij Rempel 2018-05-02 18:54 ` A.s. Dong 2018-05-03 6:24 ` Oleksij Rempel 2018-05-03 7:33 ` A.s. Dong [not found] ` <1524854776-14863-5-git-send-email-aisheng.dong@nxp.com> 2018-05-02 10:04 ` [PATCH 4/4] soc: imx: add SC firmware IPC and APIs Sascha Hauer 2018-05-02 18:40 ` A.s. Dong 2018-05-03 11:06 ` Sascha Hauer 2018-05-03 12:29 ` A.s. Dong 2018-05-03 12:40 ` Sascha Hauer 2018-05-24 8:56 ` A.s. Dong 2018-05-28 9:24 ` A.s. Dong 2018-06-06 10:28 ` A.s. Dong 2018-06-06 14:15 ` Sascha Hauer 2018-06-07 4:18 ` A.s. Dong 2018-06-07 7:08 ` Sascha Hauer 2018-06-07 13:59 ` A.s. Dong 2018-06-08 4:13 ` Sascha Hauer 2018-06-08 5:52 ` A.s. Dong 2018-06-19 11:15 ` A.s. Dong
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=1524854776-14863-3-git-send-email-aisheng.dong@nxp.com \ --to=aisheng.dong@nxp.com \ --cc=devicetree@vger.kernel.org \ --cc=dongas86@gmail.com \ --cc=fabio.estevam@nxp.com \ --cc=kernel@pengutronix.de \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-imx@nxp.com \ --cc=mark.rutland@arm.com \ --cc=robh+dt@kernel.org \ --cc=shawnguo@kernel.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.