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From: "Xu, Rosen" <rosen.xu@intel.com>
To: dev@dpdk.org
Cc: rosen.xu@intel.com, declan.doherty@intel.com,
	bruce.richardson@intel.com, shreyansh.jain@nxp.com,
	ferruh.yigit@intel.com, konstantin.ananyev@intel.com,
	tianfei.zhang@intel.com, song.liu@intel.com, hao.wu@intel.com,
	gaetan.rivet@6wind.com
Subject: [PATCH v7 1/5] bus/ifpga: Add Intel FPGA BUS Library
Date: Fri,  4 May 2018 22:10:58 +0800	[thread overview]
Message-ID: <1525443062-43231-2-git-send-email-rosen.xu@intel.com> (raw)
In-Reply-To: <1525443062-43231-1-git-send-email-rosen.xu@intel.com>

From: Rosen Xu <rosen.xu@intel.com>

Defined FPGA-BUS for Acceleration Drivers of AFUs

1. FPGA PCI Scan (1st Scan) follows DPDK UIO/VFIO PCI Scan Process,
probe Intel FPGA Rawdev Driver, it will be covered in following patches.

2. AFU Scan(2nd Scan) bind DPDK driver to FPGA Partial-Bitstream.
This scan is trigged by hotplug of IFPGA Rawdev probe, in this scan
the AFUs will be created and their drivers are also probed.

This patch will introduce rte_afu_device which describe the AFU device
listed in the FPGA-BUS.

Signed-off-by: Rosen Xu <rosen.xu@intel.com>
Signed-off-by: Figo zhang <tianfei.zhang@intel.com>
---
 config/common_base                          |   5 +
 drivers/bus/Makefile                        |   1 +
 drivers/bus/ifpga/Makefile                  |  32 ++
 drivers/bus/ifpga/ifpga_bus.c               | 500 ++++++++++++++++++++++++++++
 drivers/bus/ifpga/ifpga_common.c            |  88 +++++
 drivers/bus/ifpga/ifpga_common.h            |  18 +
 drivers/bus/ifpga/ifpga_logs.h              |  31 ++
 drivers/bus/ifpga/meson.build               |   8 +
 drivers/bus/ifpga/rte_bus_ifpga.h           | 160 +++++++++
 drivers/bus/ifpga/rte_bus_ifpga_version.map |  10 +
 drivers/bus/meson.build                     |   2 +-
 mk/rte.app.mk                               |   2 +
 12 files changed, 856 insertions(+), 1 deletion(-)
 create mode 100644 drivers/bus/ifpga/Makefile
 create mode 100644 drivers/bus/ifpga/ifpga_bus.c
 create mode 100644 drivers/bus/ifpga/ifpga_common.c
 create mode 100644 drivers/bus/ifpga/ifpga_common.h
 create mode 100644 drivers/bus/ifpga/ifpga_logs.h
 create mode 100644 drivers/bus/ifpga/meson.build
 create mode 100644 drivers/bus/ifpga/rte_bus_ifpga.h
 create mode 100644 drivers/bus/ifpga/rte_bus_ifpga_version.map

diff --git a/config/common_base b/config/common_base
index 03a8688..bd4b356 100644
--- a/config/common_base
+++ b/config/common_base
@@ -149,6 +149,11 @@ CONFIG_RTE_LIBRTE_PCI_BUS=y
 CONFIG_RTE_LIBRTE_VDEV_BUS=y
 
 #
+# Compile the Intel FPGA bus
+#
+CONFIG_RTE_LIBRTE_IFPGA_BUS=y
+
+#
 # Compile ARK PMD
 #
 CONFIG_RTE_LIBRTE_ARK_PMD=y
diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile
index c251b65..cff3567 100644
--- a/drivers/bus/Makefile
+++ b/drivers/bus/Makefile
@@ -9,5 +9,6 @@ DIRS-$(CONFIG_RTE_LIBRTE_FSLMC_BUS) += fslmc
 endif
 DIRS-$(CONFIG_RTE_LIBRTE_PCI_BUS) += pci
 DIRS-$(CONFIG_RTE_LIBRTE_VDEV_BUS) += vdev
+DIRS-$(CONFIG_RTE_LIBRTE_IFPGA_BUS) += ifpga
 
 include $(RTE_SDK)/mk/rte.subdir.mk
diff --git a/drivers/bus/ifpga/Makefile b/drivers/bus/ifpga/Makefile
new file mode 100644
index 0000000..3ff3bdb
--- /dev/null
+++ b/drivers/bus/ifpga/Makefile
@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Intel Corporation
+
+include $(RTE_SDK)/mk/rte.vars.mk
+
+#
+# library name
+#
+LIB = librte_bus_ifpga.a
+
+CFLAGS += -DALLOW_EXPERIMENTAL_API
+CFLAGS += -O3
+CFLAGS += $(WERROR_FLAGS)
+LDLIBS += -lrte_eal
+LDLIBS += -lrte_rawdev
+LDLIBS += -lrte_kvargs
+
+# versioning export map
+EXPORT_MAP := rte_bus_ifpga_version.map
+
+# library version
+LIBABIVER := 1
+
+SRCS-$(CONFIG_RTE_LIBRTE_IFPGA_BUS) += ifpga_bus.c
+SRCS-$(CONFIG_RTE_LIBRTE_IFPGA_BUS) += ifpga_common.c
+
+#
+# Export include files
+#
+SYMLINK-$(CONFIG_RTE_LIBRTE_IFPGA_BUS)-include += rte_bus_ifpga.h
+
+include $(RTE_SDK)/mk/rte.lib.mk
diff --git a/drivers/bus/ifpga/ifpga_bus.c b/drivers/bus/ifpga/ifpga_bus.c
new file mode 100644
index 0000000..8453af5
--- /dev/null
+++ b/drivers/bus/ifpga/ifpga_bus.c
@@ -0,0 +1,500 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2010-2018 Intel Corporation
+ */
+
+#include <string.h>
+#include <inttypes.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <sys/queue.h>
+#include <sys/mman.h>
+#include <sys/types.h>
+#include <unistd.h>
+#include <fcntl.h>
+
+#include <rte_errno.h>
+#include <rte_bus.h>
+#include <rte_per_lcore.h>
+#include <rte_memory.h>
+#include <rte_memzone.h>
+#include <rte_eal.h>
+#include <rte_common.h>
+
+#include <rte_devargs.h>
+#include <rte_kvargs.h>
+#include <rte_alarm.h>
+
+#include "rte_rawdev.h"
+#include "rte_rawdev_pmd.h"
+#include "rte_bus_ifpga.h"
+#include "ifpga_logs.h"
+#include "ifpga_common.h"
+
+int ifpga_bus_logtype;
+
+/* Forward declaration to access Intel FPGA bus
+ * on which iFPGA devices are connected
+ */
+static struct rte_bus rte_ifpga_bus;
+
+/** Double linked list of IFPGA device. */
+TAILQ_HEAD(ifpga_device_list, rte_ifpga_device);
+
+static struct ifpga_device_list ifpga_device_list =
+	TAILQ_HEAD_INITIALIZER(ifpga_device_list);
+static struct afu_driver_list afu_driver_list =
+	TAILQ_HEAD_INITIALIZER(afu_driver_list);
+
+
+/* register a ifpga bus based driver */
+void rte_ifpga_driver_register(struct rte_afu_driver *driver)
+{
+	RTE_VERIFY(driver);
+
+	TAILQ_INSERT_TAIL(&afu_driver_list, driver, next);
+}
+
+/* un-register a fpga bus based driver */
+void rte_ifpga_driver_unregister(struct rte_afu_driver *driver)
+{
+	TAILQ_REMOVE(&afu_driver_list, driver, next);
+}
+
+static struct rte_ifpga_device *
+ifpga_find_ifpga_dev(const struct rte_rawdev *rdev)
+{
+	struct rte_ifpga_device *ifpga_dev = NULL;
+
+	TAILQ_FOREACH(ifpga_dev, &ifpga_device_list, next) {
+		if (rdev &&
+			ifpga_dev->rdev &&
+			ifpga_dev->rdev == rdev)
+			return ifpga_dev;
+	}
+	return NULL;
+}
+
+static struct rte_afu_device *
+ifpga_find_afu_dev(const struct rte_ifpga_device *ifpga_dev,
+	const struct rte_afu_id *afu_id)
+{
+	struct rte_afu_device *afu_dev = NULL;
+
+	TAILQ_FOREACH(afu_dev, &ifpga_dev->afu_list, next) {
+		if (!ifpga_afu_id_cmp(&afu_dev->id, afu_id))
+			return afu_dev;
+	}
+	return NULL;
+}
+
+static const char * const valid_args[] = {
+#define IFPGA_ARG_NAME         "ifpga"
+	IFPGA_ARG_NAME,
+#define IFPGA_ARG_PORT         "port"
+	IFPGA_ARG_PORT,
+#define IFPGA_AFU_BTS          "afu_bts"
+	IFPGA_AFU_BTS,
+	NULL
+};
+
+/*
+ * Scan the content of the FPGA bus, and the devices in the devices
+ * list
+ */
+static struct rte_afu_device *
+ifpga_scan_one(struct rte_devargs *devargs,
+	struct rte_ifpga_device *ifpga_dev)
+{
+	struct rte_kvargs *kvlist = NULL;
+	struct rte_rawdev *rawdev = NULL;
+	struct rte_afu_device *afu_dev = NULL;
+	struct rte_afu_pr_conf afu_pr_conf;
+	int ret = 0;
+	char *path = NULL;
+
+	memset(&afu_pr_conf, 0, sizeof(struct rte_afu_pr_conf));
+
+	kvlist = rte_kvargs_parse(devargs->args, valid_args);
+	if (!kvlist) {
+		IFPGA_BUS_ERR("error when parsing param");
+		goto end;
+	}
+
+	if (rte_kvargs_count(kvlist, IFPGA_ARG_PORT) == 1) {
+		if (rte_kvargs_process(kvlist, IFPGA_ARG_PORT,
+		&ifpga_get_integer32_arg, &afu_pr_conf.afu_id.port) < 0) {
+			IFPGA_BUS_ERR("error to parse %s",
+				     IFPGA_ARG_PORT);
+			goto end;
+		}
+	} else {
+		IFPGA_BUS_ERR("arg %s is mandatory for ifpga bus",
+			  IFPGA_ARG_PORT);
+		goto end;
+	}
+
+	if (rte_kvargs_count(kvlist, IFPGA_AFU_BTS) == 1) {
+		if (rte_kvargs_process(kvlist, IFPGA_AFU_BTS,
+				       &ifpga_get_string_arg, &path) < 0) {
+			IFPGA_BUS_ERR("Failed to parse %s",
+				     IFPGA_AFU_BTS);
+			goto end;
+		}
+	} else {
+		IFPGA_BUS_ERR("arg %s is mandatory for ifpga bus",
+			  IFPGA_AFU_BTS);
+		goto end;
+	}
+
+	afu_pr_conf.afu_id.uuid.uuid_low = 0;
+	afu_pr_conf.afu_id.uuid.uuid_high = 0;
+	afu_pr_conf.pr_enable = path?1:0;
+
+	rawdev = ifpga_dev->rdev;
+	if (ifpga_find_afu_dev(ifpga_dev, &afu_pr_conf.afu_id))
+		goto end;
+
+	afu_dev = calloc(1, sizeof(*afu_dev));
+	if (!afu_dev)
+		goto end;
+
+	afu_dev->device.devargs = devargs;
+	afu_dev->device.numa_node = SOCKET_ID_ANY;
+	afu_dev->device.name = devargs->name;
+	afu_dev->rawdev = rawdev;
+	afu_dev->id.uuid.uuid_low  = 0;
+	afu_dev->id.uuid.uuid_high = 0;
+	afu_dev->id.port      = afu_pr_conf.afu_id.port;
+	afu_dev->ifpga_dev    = ifpga_dev;
+
+	if (rawdev->dev_ops && rawdev->dev_ops->dev_info_get)
+		rawdev->dev_ops->dev_info_get(rawdev, afu_dev);
+
+	if (rawdev->dev_ops &&
+		rawdev->dev_ops->dev_start &&
+		rawdev->dev_ops->dev_start(rawdev))
+		goto free_dev;
+
+	strncpy(afu_pr_conf.bs_path, path, sizeof(afu_pr_conf.bs_path));
+	if (rawdev->dev_ops->firmware_load &&
+		rawdev->dev_ops->firmware_load(rawdev,
+				&afu_pr_conf)){
+		IFPGA_BUS_ERR("firmware load error %d\n", ret);
+		goto free_dev;
+	}
+	afu_dev->id.uuid.uuid_low  = afu_pr_conf.afu_id.uuid.uuid_low;
+	afu_dev->id.uuid.uuid_high = afu_pr_conf.afu_id.uuid.uuid_high;
+
+	return afu_dev;
+
+free_dev:
+	free(afu_dev);
+end:
+	if (kvlist)
+		rte_kvargs_free(kvlist);
+	if (path)
+		free(path);
+
+	return NULL;
+}
+
+/*
+ * Scan the content of the FPGA bus, and the devices in the devices
+ * list
+ */
+static int
+ifpga_scan(void)
+{
+	struct rte_ifpga_device *ifpga_dev;
+	struct rte_devargs *devargs;
+	struct rte_kvargs *kvlist = NULL;
+	struct rte_rawdev *rawdev = NULL;
+	char *name = NULL;
+	char name1[RTE_RAWDEV_NAME_MAX_LEN];
+	struct rte_afu_device *afu_dev = NULL;
+
+	/* for FPGA devices we scan the devargs_list populated via cmdline */
+	RTE_EAL_DEVARGS_FOREACH("ifpga", devargs) {
+		if (devargs->bus != &rte_ifpga_bus)
+			continue;
+
+		kvlist = rte_kvargs_parse(devargs->args, valid_args);
+		if (!kvlist) {
+			IFPGA_BUS_ERR("error when parsing param");
+			goto end;
+		}
+
+		if (rte_kvargs_count(kvlist, IFPGA_ARG_NAME) == 1) {
+			if (rte_kvargs_process(kvlist, IFPGA_ARG_NAME,
+				       &ifpga_get_string_arg, &name) < 0) {
+				IFPGA_BUS_ERR("error to parse %s",
+				     IFPGA_ARG_NAME);
+				goto end;
+			}
+		} else {
+			IFPGA_BUS_ERR("arg %s is mandatory for ifpga bus",
+			  IFPGA_ARG_NAME);
+			goto end;
+		}
+
+		memset(name1, 0, sizeof(name1));
+		snprintf(name1, RTE_RAWDEV_NAME_MAX_LEN, "IFPGA:%s", name);
+
+		rawdev = rte_rawdev_pmd_get_named_dev(name1);
+		if (!rawdev)
+			goto end;
+
+		if (ifpga_find_ifpga_dev(rawdev))
+			continue;
+
+		ifpga_dev = calloc(1, sizeof(*ifpga_dev));
+		if (!ifpga_dev)
+			goto end;
+
+		ifpga_dev->rdev = rawdev;
+		TAILQ_INIT(&ifpga_dev->afu_list);
+
+		TAILQ_INSERT_TAIL(&ifpga_device_list, ifpga_dev, next);
+		afu_dev = ifpga_scan_one(devargs, ifpga_dev);
+		if (afu_dev != NULL)
+			TAILQ_INSERT_TAIL(&ifpga_dev->afu_list, afu_dev, next);
+	}
+
+end:
+	if (kvlist)
+		rte_kvargs_free(kvlist);
+	if (name)
+		free(name);
+
+	return 0;
+}
+
+/*
+ * Match the AFU Driver and AFU Device using the ID Table
+ */
+static int
+rte_afu_match(const struct rte_afu_driver *afu_drv,
+	      const struct rte_afu_device *afu_dev)
+{
+	const struct rte_afu_uuid *id_table;
+
+	for (id_table = afu_drv->id_table;
+		((id_table->uuid_low != 0) && (id_table->uuid_high != 0));
+	     id_table++) {
+		/* check if device's identifiers match the driver's ones */
+		if ((id_table->uuid_low != afu_dev->id.uuid.uuid_low) ||
+				id_table->uuid_high !=
+				 afu_dev->id.uuid.uuid_high)
+			continue;
+
+		return 1;
+	}
+
+	return 0;
+}
+
+static int
+ifpga_probe_one_driver(struct rte_afu_driver *drv,
+			struct rte_afu_device *afu_dev)
+{
+	int ret;
+
+	if (!rte_afu_match(drv, afu_dev))
+		/* Match of device and driver failed */
+		return 1;
+
+	/* reference driver structure */
+	afu_dev->driver = drv;
+	afu_dev->device.driver = &drv->driver;
+
+	/* call the driver probe() function */
+	ret = drv->probe(afu_dev);
+	if (ret) {
+		afu_dev->driver = NULL;
+		afu_dev->device.driver = NULL;
+	}
+
+	return ret;
+}
+
+static int
+ifpga_probe_all_drivers(struct rte_afu_device *afu_dev)
+{
+	struct rte_afu_driver *drv = NULL;
+	int ret = 0;
+
+	if (afu_dev == NULL)
+		return -1;
+
+	/* Check if a driver is already loaded */
+	if (afu_dev->driver != NULL)
+		return 0;
+
+	TAILQ_FOREACH(drv, &afu_driver_list, next) {
+		if (ifpga_probe_one_driver(drv, afu_dev)) {
+			ret = -1;
+			break;
+		}
+	}
+	return ret;
+}
+
+/*
+ * Scan the content of the Intel FPGA bus, and call the probe() function for
+ * all registered drivers that have a matching entry in its id_table
+ * for discovered devices.
+ */
+static int
+ifpga_probe(void)
+{
+	struct rte_ifpga_device *ifpga_dev;
+	struct rte_afu_device *afu_dev = NULL;
+	int ret = 0;
+
+	TAILQ_FOREACH(ifpga_dev, &ifpga_device_list, next) {
+		TAILQ_FOREACH(afu_dev, &ifpga_dev->afu_list, next) {
+
+			if (afu_dev->device.driver)
+				continue;
+
+			ret = ifpga_probe_all_drivers(afu_dev);
+			if (ret < 0)
+				IFPGA_BUS_ERR("failed to initialize %s device\n",
+					rte_ifpga_device_name(afu_dev));
+		}
+	}
+
+	return ret;
+}
+
+static int
+ifpga_plug(struct rte_device *dev)
+{
+	return ifpga_probe_all_drivers(RTE_DEV_TO_AFU(dev));
+}
+
+static int ifpga_remove_driver(struct rte_afu_device *afu_dev)
+{
+	const char *name;
+	const struct rte_afu_driver *driver;
+
+	name = rte_ifpga_device_name(afu_dev);
+	if (!afu_dev->device.driver) {
+		IFPGA_BUS_DEBUG("no driver attach to device %s\n", name);
+		return 1;
+	}
+
+	driver = RTE_DRV_TO_AFU_CONST(afu_dev->device.driver);
+	return driver->remove(afu_dev);
+}
+
+static int
+ifpga_unplug(struct rte_device *dev)
+{
+	struct rte_ifpga_device *ifpga_dev = NULL;
+	struct rte_afu_device *afu_dev = NULL;
+	struct rte_devargs *devargs = NULL;
+	int ret;
+
+	if (dev == NULL)
+		return -EINVAL;
+
+	afu_dev = RTE_DEV_TO_AFU(dev);
+	if (!dev)
+		return -ENOENT;
+
+	ifpga_dev = afu_dev->ifpga_dev;
+	devargs = dev->devargs;
+
+	ret = ifpga_remove_driver(afu_dev);
+	if (ret)
+		return ret;
+
+	TAILQ_REMOVE(&ifpga_dev->afu_list, afu_dev, next);
+
+	rte_devargs_remove(devargs->bus->name, devargs->name);
+	free(afu_dev);
+	return 0;
+
+}
+
+static struct rte_device *
+ifpga_find_device(const struct rte_device *start,
+	rte_dev_cmp_t cmp, const void *data)
+{
+	struct rte_ifpga_device *ifpga_dev;
+	struct rte_afu_device *afu_dev;
+
+	TAILQ_FOREACH(ifpga_dev, &ifpga_device_list, next) {
+		TAILQ_FOREACH(afu_dev, &ifpga_dev->afu_list, next) {
+			if (start && &afu_dev->device == start) {
+				start = NULL;
+				continue;
+			}
+			if (cmp(&afu_dev->device, data) == 0)
+				return &afu_dev->device;
+		}
+	}
+	return NULL;
+}
+static int
+ifpga_parse(const char *name, void *addr)
+{
+	int *out = addr;
+	struct rte_rawdev *rawdev = NULL;
+	char rawdev_name[RTE_RAWDEV_NAME_MAX_LEN];
+	char *c1 = NULL, *c2 = NULL;
+	int port = IFPGA_BUS_DEV_PORT_MAX;
+	char str_port[8];
+	int str_port_len = 0;
+	int ret;
+
+	memset(str_port, 0, 8);
+	c1 = strchr(name, '|');
+	if (c1 != NULL) {
+		str_port_len = c1-name;
+		c2 = c1+1;
+	}
+
+	if (str_port_len < 8 &&
+		str_port_len > 0) {
+		memcpy(str_port, name, str_port_len);
+		ret = sscanf(str_port, "%d", &port);
+		if (ret == -1)
+			return 0;
+	}
+
+	memset(rawdev_name, 0, sizeof(rawdev_name));
+	snprintf(rawdev_name, RTE_RAWDEV_NAME_MAX_LEN, "IFPGA:%s", c2);
+	rawdev = rte_rawdev_pmd_get_named_dev(rawdev_name);
+
+	if ((port < IFPGA_BUS_DEV_PORT_MAX) &&
+		rawdev &&
+		(addr != NULL))
+		*out = port;
+
+	if ((port < IFPGA_BUS_DEV_PORT_MAX) &&
+		rawdev)
+		return 0;
+	else
+		return 1;
+}
+
+static struct rte_bus rte_ifpga_bus = {
+	.scan        = ifpga_scan,
+	.probe       = ifpga_probe,
+	.find_device = ifpga_find_device,
+	.plug        = ifpga_plug,
+	.unplug      = ifpga_unplug,
+	.parse       = ifpga_parse,
+};
+
+RTE_REGISTER_BUS(IFPGA_BUS_NAME, rte_ifpga_bus);
+
+RTE_INIT(ifpga_init_log)
+{
+	ifpga_bus_logtype = rte_log_register("bus.ifpga");
+	if (ifpga_bus_logtype >= 0)
+		rte_log_set_level(ifpga_bus_logtype, RTE_LOG_NOTICE);
+}
diff --git a/drivers/bus/ifpga/ifpga_common.c b/drivers/bus/ifpga/ifpga_common.c
new file mode 100644
index 0000000..b4efc20
--- /dev/null
+++ b/drivers/bus/ifpga/ifpga_common.c
@@ -0,0 +1,88 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2010-2018 Intel Corporation
+ */
+
+#include <string.h>
+#include <inttypes.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <sys/queue.h>
+#include <sys/mman.h>
+#include <sys/types.h>
+#include <unistd.h>
+#include <fcntl.h>
+
+#include <rte_errno.h>
+#include <rte_bus.h>
+#include <rte_per_lcore.h>
+#include <rte_memory.h>
+#include <rte_memzone.h>
+#include <rte_eal.h>
+#include <rte_common.h>
+
+#include <rte_devargs.h>
+#include <rte_kvargs.h>
+#include <rte_alarm.h>
+
+#include "rte_bus_ifpga.h"
+#include "ifpga_logs.h"
+#include "ifpga_common.h"
+
+int ifpga_get_string_arg(const char *key __rte_unused,
+	const char *value, void *extra_args)
+{
+	if (!value || !extra_args)
+		return -EINVAL;
+
+	*(char **)extra_args = strdup(value);
+
+	if (!*(char **)extra_args)
+		return -ENOMEM;
+
+	return 0;
+}
+int ifpga_get_integer32_arg(const char *key __rte_unused,
+	const char *value, void *extra_args)
+{
+	if (!value || !extra_args)
+		return -EINVAL;
+
+	*(int *)extra_args = strtoull(value, NULL, 0);
+
+	return 0;
+}
+int ifpga_get_integer64_arg(const char *key __rte_unused,
+	const char *value, void *extra_args)
+{
+	if (!value || !extra_args)
+		return -EINVAL;
+
+	*(uint64_t *)extra_args = strtoull(value, NULL, 0);
+
+	return 0;
+}
+int ifpga_get_unsigned_long(const char *str, int base)
+{
+	unsigned long num;
+	char *end = NULL;
+
+	errno = 0;
+
+	num = strtoul(str, &end, base);
+	if ((str[0] == '\0') || (end == NULL) || (*end != '\0') || (errno != 0))
+		return -1;
+
+	return num;
+}
+
+int ifpga_afu_id_cmp(const struct rte_afu_id *afu_id0,
+	const struct rte_afu_id *afu_id1)
+{
+	if ((afu_id0->uuid.uuid_low == afu_id1->uuid.uuid_low) &&
+		(afu_id0->uuid.uuid_high == afu_id1->uuid.uuid_high) &&
+		(afu_id0->port == afu_id1->port)) {
+		return 0;
+	} else
+		return 1;
+}
diff --git a/drivers/bus/ifpga/ifpga_common.h b/drivers/bus/ifpga/ifpga_common.h
new file mode 100644
index 0000000..b6662c8
--- /dev/null
+++ b/drivers/bus/ifpga/ifpga_common.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2010-2018 Intel Corporation
+ */
+
+#ifndef _IFPGA_COMMON_H_
+#define _IFPGA_COMMON_H_
+
+int ifpga_get_string_arg(const char *key __rte_unused,
+	const char *value, void *extra_args);
+int ifpga_get_integer32_arg(const char *key __rte_unused,
+	const char *value, void *extra_args);
+int ifpga_get_integer64_arg(const char *key __rte_unused,
+	const char *value, void *extra_args);
+int ifpga_get_unsigned_long(const char *str, int base);
+int ifpga_afu_id_cmp(const struct rte_afu_id *afu_id0,
+	const struct rte_afu_id *afu_id1);
+
+#endif /* _IFPGA_COMMON_H_ */
diff --git a/drivers/bus/ifpga/ifpga_logs.h b/drivers/bus/ifpga/ifpga_logs.h
new file mode 100644
index 0000000..873e0a4
--- /dev/null
+++ b/drivers/bus/ifpga/ifpga_logs.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2010-2018 Intel Corporation
+ */
+
+#ifndef _IFPGA_LOGS_H_
+#define _IFPGA_LOGS_H_
+
+#include <rte_log.h>
+
+extern int ifpga_bus_logtype;
+
+#define IFPGA_LOG(level, fmt, args...) \
+	rte_log(RTE_LOG_ ## level, ifpga_bus_logtype, "%s(): " fmt "\n", \
+		__func__, ##args)
+
+#define IFPGA_BUS_LOG(level, fmt, args...) \
+	rte_log(RTE_LOG_ ## level, ifpga_bus_logtype, "%s(): " fmt "\n", \
+		__func__, ##args)
+
+#define IFPGA_BUS_FUNC_TRACE() IFPGA_BUS_LOG(DEBUG, ">>")
+
+#define IFPGA_BUS_DEBUG(fmt, args...) \
+	IFPGA_BUS_LOG(DEBUG, fmt, ## args)
+#define IFPGA_BUS_INFO(fmt, args...) \
+	IFPGA_BUS_LOG(INFO, fmt, ## args)
+#define IFPGA_BUS_ERR(fmt, args...) \
+	IFPGA_BUS_LOG(ERR, fmt, ## args)
+#define IFPGA_BUS_WARN(fmt, args...) \
+	IFPGA_BUS_LOG(WARNING, fmt, ## args)
+
+#endif /* _IFPGA_BUS_LOGS_H_ */
diff --git a/drivers/bus/ifpga/meson.build b/drivers/bus/ifpga/meson.build
new file mode 100644
index 0000000..c9b08c8
--- /dev/null
+++ b/drivers/bus/ifpga/meson.build
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2010-2018 Intel Corporation
+
+deps += ['pci', 'kvargs', 'rawdev']
+install_headers('rte_bus_ifpga.h')
+sources = files('ifpga_common.c', 'ifpga_bus.c')
+
+allow_experimental_apis = true
diff --git a/drivers/bus/ifpga/rte_bus_ifpga.h b/drivers/bus/ifpga/rte_bus_ifpga.h
new file mode 100644
index 0000000..5c559e1
--- /dev/null
+++ b/drivers/bus/ifpga/rte_bus_ifpga.h
@@ -0,0 +1,160 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2010-2018 Intel Corporation
+ */
+
+#ifndef _RTE_BUS_IFPGA_H_
+#define _RTE_BUS_IFPGA_H_
+
+/**
+ * @file
+ *
+ * RTE Intel FPGA Bus Interface
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rte_bus.h>
+#include <rte_pci.h>
+
+/** Name of Intel FPGA Bus */
+#define IFPGA_BUS_NAME ifpga
+
+/* Forward declarations */
+struct rte_afu_device;
+
+/** List of Intel AFU devices */
+TAILQ_HEAD(afu_device_list, rte_afu_device);
+/** Double linked list of AFU device drivers. */
+TAILQ_HEAD(afu_driver_list, rte_afu_driver);
+
+#define IFPGA_BUS_BITSTREAM_PATH_MAX_LEN 256
+
+struct rte_afu_uuid {
+	uint64_t uuid_low;
+	uint64_t uuid_high;
+} __attribute__ ((packed));
+
+#define IFPGA_BUS_DEV_PORT_MAX 4
+
+/**
+ * A structure describing an ID for a AFU driver. Each driver provides a
+ * table of these IDs for each device that it supports.
+ */
+struct rte_afu_id {
+	struct rte_afu_uuid uuid;
+	int      port; /**< port number */
+} __attribute__ ((packed));
+
+/**
+ * A structure PR (Partial Reconfiguration) configuration AFU driver.
+ */
+
+struct rte_afu_pr_conf {
+	struct rte_afu_id afu_id;
+	int pr_enable;
+	char bs_path[IFPGA_BUS_BITSTREAM_PATH_MAX_LEN];
+};
+
+#define AFU_PRI_STR_SIZE (PCI_PRI_STR_SIZE + 8)
+
+/**
+ * A structure describing a fpga device.
+ */
+struct rte_ifpga_device {
+	TAILQ_ENTRY(rte_ifpga_device) next;       /**< Next in device list. */
+	struct rte_rawdev *rdev;
+	struct afu_device_list afu_list;  /**< List of AFU devices */
+};
+
+/**
+ * A structure describing a AFU device.
+ */
+struct rte_afu_device {
+	TAILQ_ENTRY(rte_afu_device) next;       /**< Next in device list. */
+	struct rte_device device;               /**< Inherit core device */
+	struct rte_rawdev *rawdev;    /**< Point Rawdev */
+	struct rte_ifpga_device *ifpga_dev;    /**< Point ifpga device */
+	struct rte_afu_id id;                   /**< AFU id within FPGA. */
+	uint32_t num_region;   /**< number of regions found */
+	struct rte_mem_resource mem_resource[PCI_MAX_RESOURCE];
+						/**< AFU Memory Resource */
+	struct rte_intr_handle intr_handle;     /**< Interrupt handle */
+	struct rte_afu_driver *driver;          /**< Associated driver */
+	char path[IFPGA_BUS_BITSTREAM_PATH_MAX_LEN];
+} __attribute__ ((packed));
+
+/**
+ * @internal
+ * Helper macro for drivers that need to convert to struct rte_afu_device.
+ */
+#define RTE_DEV_TO_AFU(ptr) \
+	container_of(ptr, struct rte_afu_device, device)
+
+#define RTE_DRV_TO_AFU_CONST(ptr) \
+	container_of(ptr, const struct rte_afu_driver, driver)
+
+/**
+ * Initialisation function for the driver called during FPGA BUS probing.
+ */
+typedef int (afu_probe_t)(struct rte_afu_device *);
+
+/**
+ * Uninitialisation function for the driver called during hotplugging.
+ */
+typedef int (afu_remove_t)(struct rte_afu_device *);
+
+/**
+ * A structure describing a AFU device.
+ */
+struct rte_afu_driver {
+	TAILQ_ENTRY(rte_afu_driver) next;       /**< Next afu driver. */
+	struct rte_driver driver;               /**< Inherit core driver. */
+	afu_probe_t *probe;                     /**< Device Probe function. */
+	afu_remove_t *remove;                   /**< Device Remove function. */
+	const struct rte_afu_uuid *id_table;    /**< AFU uuid within FPGA. */
+	uint32_t drv_flags;         /**< Flags contolling handling of device. */
+};
+
+static inline const char *
+rte_ifpga_device_name(const struct rte_afu_device *afu)
+{
+	if (afu && afu->device.name)
+		return afu->device.name;
+	return NULL;
+}
+
+/**
+ * Register a ifpga afu device driver.
+ *
+ * @param driver
+ *   A pointer to a rte_afu_driver structure describing the driver
+ *   to be registered.
+ */
+void rte_ifpga_driver_register(struct rte_afu_driver *driver);
+
+/**
+ * Unregister a ifpga afu device driver.
+ *
+ * @param driver
+ *   A pointer to a rte_afu_driver structure describing the driver
+ *   to be unregistered.
+ */
+void rte_ifpga_driver_unregister(struct rte_afu_driver *driver);
+
+#define RTE_PMD_REGISTER_AFU(nm, afudrv)\
+RTE_INIT(afudrvinitfn_ ##afudrv);\
+static const char *afudrvinit_ ## nm ## _alias;\
+static void afudrvinitfn_ ##afudrv(void)\
+{\
+	(afudrv).driver.name = RTE_STR(nm);\
+	(afudrv).driver.alias = afudrvinit_ ## nm ## _alias;\
+	rte_ifpga_driver_register(&afudrv);\
+} \
+RTE_PMD_EXPORT_NAME(nm, __COUNTER__)
+
+#define RTE_PMD_REGISTER_AFU_ALIAS(nm, alias)\
+static const char *afudrvinit_ ## nm ## _alias = RTE_STR(alias)
+
+#endif /* _RTE_BUS_IFPGA_H_ */
diff --git a/drivers/bus/ifpga/rte_bus_ifpga_version.map b/drivers/bus/ifpga/rte_bus_ifpga_version.map
new file mode 100644
index 0000000..1304caf
--- /dev/null
+++ b/drivers/bus/ifpga/rte_bus_ifpga_version.map
@@ -0,0 +1,10 @@
+DPDK_18.05 {
+	global:
+
+	ifpga_get_integer32_arg;
+	ifpga_get_string_arg;
+	rte_ifpga_driver_register;
+	rte_ifpga_driver_unregister;
+
+	local: *;
+};
diff --git a/drivers/bus/meson.build b/drivers/bus/meson.build
index 58dfbe2..170df25 100644
--- a/drivers/bus/meson.build
+++ b/drivers/bus/meson.build
@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: BSD-3-Clause
 # Copyright(c) 2017 Intel Corporation
 
-drivers = ['dpaa', 'fslmc', 'pci', 'vdev']
+drivers = ['dpaa', 'fslmc', 'pci', 'vdev', 'ifpga']
 std_deps = ['eal']
 config_flag_fmt = 'RTE_LIBRTE_@0@_BUS'
 driver_name_fmt = 'rte_bus_@0@'
diff --git a/mk/rte.app.mk b/mk/rte.app.mk
index 29a2a60..f47bbe8 100644
--- a/mk/rte.app.mk
+++ b/mk/rte.app.mk
@@ -107,6 +107,8 @@ _LDLIBS-$(CONFIG_RTE_LIBRTE_CMDLINE)        += -lrte_cmdline
 _LDLIBS-$(CONFIG_RTE_LIBRTE_REORDER)        += -lrte_reorder
 _LDLIBS-$(CONFIG_RTE_LIBRTE_SCHED)          += -lrte_sched
 
+_LDLIBS-$(CONFIG_RTE_LIBRTE_IFPGA_BUS)      += -lrte_bus_ifpga
+
 ifeq ($(CONFIG_RTE_EXEC_ENV_LINUXAPP),y)
 _LDLIBS-$(CONFIG_RTE_LIBRTE_KNI)            += -lrte_kni
 endif
-- 
1.8.3.1

  reply	other threads:[~2018-05-04 14:09 UTC|newest]

Thread overview: 149+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-20 13:45 [PATCH V1 0/5] Introduce Intel FPGA BUS Rosen Xu
2018-03-20 13:45 ` [PATCH V1 1/5] Add Intel FPGA BUS Command Parse Code Rosen Xu
2018-03-20 13:45 ` [PATCH V1 2/5] Add Intel FPGA BUS Probe Code Rosen Xu
2018-03-20 13:45 ` [PATCH V1 3/5] Add Intel FPGA BUS Lib Code Rosen Xu
2018-03-20 13:45 ` [PATCH V1 4/5] Add Intel FPGA BUS Rawdev Code Rosen Xu
2018-03-20 13:45 ` [PATCH V1 5/5] Add Intel OPAE Share Code Rosen Xu
2018-03-20 14:58 ` [PATCH V1 0/5] Introduce Intel FPGA BUS Gaëtan Rivet
2018-03-28  9:29 ` [PATCH v3 0/6] " Rosen Xu
2018-03-28  9:29   ` [PATCH v3 1/6] Add Intel FPGA BUS Command Parse Code Rosen Xu
2018-03-28 13:26     ` Gaëtan Rivet
2018-03-31 16:25       ` Xu, Rosen
2018-04-04  1:58         ` Xu, Rosen
2018-03-28  9:29   ` [PATCH v3 2/6] config/common_base: Add Intel FPGA Build Configuration Macro Rosen Xu
2018-03-28 13:27     ` Gaëtan Rivet
2018-03-31 16:26       ` Xu, Rosen
2018-04-04  2:01       ` Xu, Rosen
2018-03-28  9:29   ` [PATCH v3 3/6] mk/rte.app.mk: Add Intel FPGA Bus Build Configuration Macro To App Script Rosen Xu
2018-03-28 13:28     ` Gaëtan Rivet
2018-03-31 16:27       ` Xu, Rosen
2018-04-04  2:02       ` Xu, Rosen
2018-03-28  9:29   ` [PATCH v3 4/6] drivers/bus: Add Intel FPGA Bus Lib Code Rosen Xu
2018-03-28 13:52     ` Gaëtan Rivet
2018-03-31 16:31       ` Xu, Rosen
2018-04-02  4:25         ` Xu, Rosen
2018-04-02  4:31         ` Xu, Rosen
2018-04-04  4:01       ` Xu, Rosen
2018-03-28  9:29   ` [PATCH v3 5/6] drivers/raw/ifpga_rawdev: Add Intel FPGA Rawdev Driver Code Rosen Xu
2018-03-28  9:29   ` [PATCH v3 6/6] drivers/raw/ifpga_rawdev: Add Intel FPGA OPAE Share Code Rosen Xu
2018-03-28  9:37   ` [PATCH v3 0/6] Introduce Intel FPGA BUS Bruce Richardson
2018-03-28 13:17   ` Gaëtan Rivet
2018-03-28 16:15     ` Zhang, Tianfei
2018-04-04  1:57     ` Xu, Rosen
2018-03-31 16:02 ` [PATCH v4 0/3] " Rosen Xu
2018-03-31 16:03   ` [PATCH v4 1/3] Add Intel FPGA BUS Lib Code Rosen Xu
2018-04-03  9:25     ` Shreyansh Jain
2018-04-04  1:44       ` Xu, Rosen
2018-03-31 16:03   ` [PATCH v4 2/3] Add Intel FPGA BUS Rawdev Driver Rosen Xu
2018-04-03  9:34     ` Shreyansh Jain
2018-04-04  1:49       ` Xu, Rosen
2018-04-04 11:31         ` Shreyansh Jain
2018-04-26 10:47           ` Xu, Rosen
2018-03-31 16:03   ` [PATCH v4 3/3] Add Intel FPGA OPAE Share Code Rosen Xu
2018-04-04  6:51 ` [PATCH v5 0/3] Introduce Intel FPGA BUS Rosen Xu
2018-04-04  6:51   ` [PATCH v5 1/3] Add Intel FPGA BUS Library Rosen Xu
2018-04-04  9:55     ` Bruce Richardson
2018-04-04  6:51   ` [PATCH v5 2/3] Add Intel FPGA BUS Rawdev Driver Rosen Xu
2018-04-04  6:51   ` [PATCH v5 3/3] Add Intel FPGA OPAE Share Code Rosen Xu
2018-04-04 11:59     ` Hemant Agrawal
2018-04-26 10:45       ` Xu, Rosen
2018-04-04 10:14   ` [PATCH v5 0/3] Introduce Intel FPGA BUS Shreyansh Jain
2018-04-04 10:38     ` Richardson, Bruce
2018-04-04 11:11       ` Shreyansh Jain
2018-04-26  9:43 ` [PATCH v6 0/5] " Xu, Rosen
2018-04-26  9:43   ` [PATCH v6 1/5] iFPGA: Add Intel FPGA BUS Library Xu, Rosen
2018-05-02 13:14     ` Shreyansh Jain
2018-05-02 13:33       ` Zhang, Tianfei
2018-05-03  3:58     ` Tan, Jianfeng
2018-05-03  8:12       ` Tan, Jianfeng
2018-05-03  8:35       ` Zhang, Tianfei
2018-04-26  9:43   ` [PATCH v6 2/5] iFPGA: Add Intel FPGA OPAE Share Code Xu, Rosen
2018-04-26  9:43   ` [PATCH v6 3/5] iFPGA: Add Intel FPGA BUS Rawdev Driver Xu, Rosen
2018-05-04  9:14     ` Shreyansh Jain
2018-05-04  9:04       ` Zhang, Tianfei
2018-04-26  9:43   ` [PATCH v6 4/5] iFPGA: add meson build Xu, Rosen
2018-05-02  9:46     ` Shreyansh Jain
2018-05-02 13:36       ` Zhang, Tianfei
2018-05-03  9:13         ` Shreyansh Jain
2018-05-03 15:12           ` Zhang, Tianfei
2018-04-26  9:43   ` [PATCH v6 5/5] iFPGA: add document for iFPGA driver Xu, Rosen
2018-05-04 14:10 ` [PATCH v7 0/5] Introduce Intel FPGA BUS Xu, Rosen
2018-05-04 14:10   ` Xu, Rosen [this message]
2018-05-04 14:10   ` [PATCH v7 2/5] iFPGA: Add Intel FPGA OPAE Share Code Xu, Rosen
2018-05-04 14:11   ` [PATCH v7 3/5] iFPGA: Add Intel FPGA BUS Rawdev Driver Xu, Rosen
2018-05-05 18:42     ` Shreyansh Jain
2018-05-06  0:28       ` Zhang, Tianfei
2018-05-05 19:09     ` Shreyansh Jain
2018-05-06  0:52       ` Zhang, Tianfei
2018-05-04 14:11   ` [PATCH v7 4/5] iFPGA: add meson build Xu, Rosen
2018-05-05 18:21     ` Shreyansh Jain
2018-05-06  0:27       ` Zhang, Tianfei
2018-05-04 14:11   ` [PATCH v7 5/5] iFPGA: add document for iFPGA driver Xu, Rosen
2018-05-05 19:19     ` Shreyansh Jain
2018-05-06  8:40 ` [PATCH v8 0/5] Introduce Intel FPGA BUS Xu, Rosen
2018-05-06  8:40   ` [PATCH v8 1/5] bus/ifpga: Add Intel FPGA BUS Library Xu, Rosen
2018-05-06  8:40   ` [PATCH v8 2/5] iFPGA: Add Intel FPGA OPAE Share Code Xu, Rosen
2018-05-06  8:40   ` [PATCH v8 3/5] iFPGA: Add Intel FPGA BUS Rawdev Driver Xu, Rosen
2018-05-06  8:40   ` [PATCH v8 4/5] iFPGA: add meson build Xu, Rosen
2018-05-06  8:40   ` [PATCH v8 5/5] iFPGA: add document for iFPGA driver Xu, Rosen
2018-05-06 11:54     ` Shreyansh Jain
2018-05-06 14:24       ` Zhang, Tianfei
2018-05-08 14:18 ` [PATCH v9 0/4] Introduce Intel FPGA BUS Xu, Rosen
2018-05-08 14:19   ` [PATCH v9 1/4] bus/ifpga: Add Intel FPGA BUS Library Xu, Rosen
2018-05-08 14:42     ` Thomas Monjalon
2018-05-09  1:25       ` Xu, Rosen
2018-05-08 14:19   ` [PATCH v9 2/4] iFPGA: Add Intel FPGA OPAE Share Code Xu, Rosen
2018-05-08 14:45     ` Thomas Monjalon
2018-05-09  1:24       ` Xu, Rosen
2018-05-08 14:19   ` [PATCH v9 3/4] iFPGA: Add Intel FPGA BUS Rawdev Driver Xu, Rosen
2018-05-08 14:19   ` [PATCH v9 4/4] iFPGA: add document for iFPGA driver Xu, Rosen
2018-05-08 14:49     ` Thomas Monjalon
2018-05-09  7:43 ` [PATCH v10 0/3] Introduce Intel FPGA BUS Xu, Rosen
2018-05-09  7:43   ` [PATCH v10 1/3] bus/ifpga: Add Intel FPGA BUS Library Xu, Rosen
2018-05-10  8:43     ` Wu, Jingjing
2018-05-10 12:20       ` Xu, Rosen
2018-05-10 22:39         ` Wu, Jingjing
2018-05-11  3:18           ` Xu, Rosen
2018-05-10 12:26     ` Zhang, Qi Z
2018-05-10 13:29       ` Xu, Rosen
2018-05-10 13:48         ` Zhang, Qi Z
2018-05-10 13:58           ` Xu, Rosen
2018-05-10 14:11             ` Zhang, Qi Z
2018-05-10 13:51         ` Xu, Rosen
2018-05-10 13:58           ` Zhang, Qi Z
2018-05-10 14:49           ` Thomas Monjalon
2018-05-09  7:43   ` [PATCH v10 2/3] iFPGA: Add Intel FPGA OPAE Share Code Xu, Rosen
2018-05-09  7:43   ` [PATCH v10 3/3] iFPGA: Add Intel FPGA BUS Rawdev Driver Xu, Rosen
2018-05-09 14:47     ` Thomas Monjalon
2018-05-09 15:33       ` Zhang, Tianfei
2018-05-09 15:37         ` Bruce Richardson
2018-05-09 15:57           ` Zhang, Tianfei
2018-05-10 13:31             ` Xu, Rosen
2018-05-10  9:21     ` Wu, Jingjing
2018-05-10 13:16       ` Xu, Rosen
2018-05-11  3:21       ` Xu, Rosen
2018-05-10 14:24     ` Zhang, Qi Z
2018-05-11  3:16       ` Xu, Rosen
2018-05-11  5:36         ` Zhang, Qi Z
2018-05-10 14:00 ` [PATCH v11 0/3] Introduce Intel FPGA BUS Xu, Rosen
2018-05-10 14:00   ` [PATCH v11 1/3] bus/ifpga: Add Intel FPGA BUS Library Xu, Rosen
2018-05-10 14:00   ` [PATCH v11 2/3] iFPGA: Add Intel FPGA OPAE Share Code Xu, Rosen
2018-05-10 14:00   ` [PATCH v11 3/3] iFPGA: Add Intel FPGA BUS Rawdev Driver Xu, Rosen
2018-05-11  8:31 ` [PATCH v12 0/3] Introduce Intel FPGA BUS Xu, Rosen
2018-05-11  8:31   ` [PATCH v12 1/3] bus/ifpga: Add Intel FPGA BUS Library Xu, Rosen
2018-05-11  8:31   ` [PATCH v12 2/3] iFPGA: Add Intel FPGA OPAE Share Code Xu, Rosen
2018-05-11  8:31   ` [PATCH v12 3/3] iFPGA: Add Intel FPGA BUS Rawdev Driver Xu, Rosen
2018-05-11 12:11   ` [PATCH v12 0/3] Introduce Intel FPGA BUS Zhang, Qi Z
2018-05-11 13:45     ` Xu, Rosen
2018-05-11 15:12     ` Thomas Monjalon
2018-05-14  9:58 ` [PATCH] raw/ifpga/base: fix compile error on ia32 icc compiler Xu, Rosen
2018-05-14 10:20   ` De Lara Guarch, Pablo
2018-05-14 10:32     ` Thomas Monjalon
2018-05-16 13:48 ` [PATCH] drivers/bus/ifpga/: fix Coverity issue Rosen Xu
2018-05-21 14:00   ` [dpdk-stable] " Thomas Monjalon
2018-05-22 10:26   ` [PATCH v2 0/3] Fix bus/ifpga coverity issue: 279455, 279459 and 279454 Rosen Xu
2018-05-22 10:26     ` [PATCH v2 1/3] bus/ifpga: fix error control flow issue Rosen Xu
2018-05-22 10:26     ` [PATCH v2 2/3] bus/ifpga: fix resource leaks issue Rosen Xu
2018-05-22 10:26     ` [PATCH v2 3/3] bus/ifpga: fix null pointer dereferences issue Rosen Xu
2018-05-22 15:15     ` [PATCH v2 0/3] Fix bus/ifpga coverity issue: 279455, 279459 and 279454 Thomas Monjalon
2018-05-23  0:26       ` Xu, Rosen

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