[PATCH v3 0/2] Add support for general system clock on ST AMD platform

[PATCH v3 0/2] Add support for general system clock on ST AMD platform

[Akshu Agrawal]

AMD ST/CZ platform provides a general system clock which can be used
by any driver. Registration of this clock will done in clk-st driver.
While the ACPI misc device will create the required MMIO mappings
and pass the same to the clk-st driver. The clk-st driver will
use the address to enable/disable and set frequency.

Changelog:
v2:
  clk: x86: Add ST oscout platform clock: v3->v4 unregister clk_hw
  ACPI: APD: Add AMD misc clock handler support: No change (v2)
v3:
  clk: x86: Add ST oscout platform clock:
		v4->v5 use static array, change license
  ACPI: APD: Add AMD misc clock handler support:
		v2->v3 use devm_ioremap, fix warning

Akshu Agrawal (2):
  clk: x86: Add ST oscout platform clock
  ACPI: APD: Add AMD misc clock handler support

 drivers/acpi/acpi_apd.c              | 50 ++++++++++++++++++++
 drivers/clk/x86/Makefile             |  1 +
 drivers/clk/x86/clk-st.c             | 88 ++++++++++++++++++++++++++++++++++++
 include/linux/platform_data/clk-st.h | 35 ++++++++++++++
 4 files changed, 174 insertions(+)
 create mode 100644 drivers/clk/x86/clk-st.c
 create mode 100644 include/linux/platform_data/clk-st.h

-- 
1.9.1

[PATCH v3 0/2] Add support for general system clock on ST AMD platform

[Akshu Agrawal]

AMD ST/CZ platform provides a general system clock which can be used
by any driver. Registration of this clock will done in clk-st driver.
While the ACPI misc device will create the required MMIO mappings
and pass the same to the clk-st driver. The clk-st driver will
use the address to enable/disable and set frequency.

Changelog:
v2:
  clk: x86: Add ST oscout platform clock: v3->v4 unregister clk_hw
  ACPI: APD: Add AMD misc clock handler support: No change (v2)
v3:
  clk: x86: Add ST oscout platform clock:
		v4->v5 use static array, change license
  ACPI: APD: Add AMD misc clock handler support:
		v2->v3 use devm_ioremap, fix warning

Akshu Agrawal (2):
  clk: x86: Add ST oscout platform clock
  ACPI: APD: Add AMD misc clock handler support

 drivers/acpi/acpi_apd.c              | 50 ++++++++++++++++++++
 drivers/clk/x86/Makefile             |  1 +
 drivers/clk/x86/clk-st.c             | 88 ++++++++++++++++++++++++++++++++++++
 include/linux/platform_data/clk-st.h | 35 ++++++++++++++
 4 files changed, 174 insertions(+)
 create mode 100644 drivers/clk/x86/clk-st.c
 create mode 100644 include/linux/platform_data/clk-st.h

-- 
1.9.1

[PATCH v3 0/2] Add support for general system clock on ST AMD platform

[Akshu Agrawal]

AMD ST/CZ platform provides a general system clock which can be used
by any driver. Registration of this clock will done in clk-st driver.
While the ACPI misc device will create the required MMIO mappings
and pass the same to the clk-st driver. The clk-st driver will
use the address to enable/disable and set frequency.

Changelog:
v2:
  clk: x86: Add ST oscout platform clock: v3->v4 unregister clk_hw
  ACPI: APD: Add AMD misc clock handler support: No change (v2)
v3:
  clk: x86: Add ST oscout platform clock:
		v4->v5 use static array, change license
  ACPI: APD: Add AMD misc clock handler support:
		v2->v3 use devm_ioremap, fix warning

Akshu Agrawal (2):
  clk: x86: Add ST oscout platform clock
  ACPI: APD: Add AMD misc clock handler support

 drivers/acpi/acpi_apd.c              | 50 ++++++++++++++++++++
 drivers/clk/x86/Makefile             |  1 +
 drivers/clk/x86/clk-st.c             | 88 ++++++++++++++++++++++++++++++++++++
 include/linux/platform_data/clk-st.h | 35 ++++++++++++++
 4 files changed, 174 insertions(+)
 create mode 100644 drivers/clk/x86/clk-st.c
 create mode 100644 include/linux/platform_data/clk-st.h

-- 
1.9.1

[PATCH v5 1/2] clk: x86: Add ST oscout platform clock

[Akshu Agrawal]

Stoney SoC provides oscout clock. This clock can support 25Mhz and
48Mhz of frequency.
The clock is available for general system use.

Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
---
v2: config change, added SPDX tag and used clk_hw_register_.
v3: Fix kbuild warning for checking of NULL pointer
v4: unregister clk_hw in driver remove, add .suppress_bind_attrs
v5: Fix license, used static array
 drivers/clk/x86/Makefile             |  3 +-
 drivers/clk/x86/clk-st.c             | 77 ++++++++++++++++++++++++++++++++++++
 include/linux/platform_data/clk-st.h | 17 ++++++++
 3 files changed, 96 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/x86/clk-st.c
 create mode 100644 include/linux/platform_data/clk-st.h

diff --git a/drivers/clk/x86/Makefile b/drivers/clk/x86/Makefile
index 1367afb..00303bc 100644
--- a/drivers/clk/x86/Makefile
+++ b/drivers/clk/x86/Makefile
@@ -1,3 +1,4 @@
+obj-$(CONFIG_PMC_ATOM)		+= clk-pmc-atom.o
+obj-$(CONFIG_X86_AMD_PLATFORM_DEVICE)	+= clk-st.o
 clk-x86-lpss-objs		:= clk-lpt.o
 obj-$(CONFIG_X86_INTEL_LPSS)	+= clk-x86-lpss.o
-obj-$(CONFIG_PMC_ATOM)		+= clk-pmc-atom.o
diff --git a/drivers/clk/x86/clk-st.c b/drivers/clk/x86/clk-st.c
new file mode 100644
index 0000000..fb62f39
--- /dev/null
+++ b/drivers/clk/x86/clk-st.c
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: MIT
+/*
+ * clock framework for AMD Stoney based clocks
+ *
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ */
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/platform_data/clk-st.h>
+#include <linux/platform_device.h>
+
+/* Clock Driving Strength 2 register */
+#define CLKDRVSTR2	0x28
+/* Clock Control 1 register */
+#define MISCCLKCNTL1	0x40
+/* Auxiliary clock1 enable bit */
+#define OSCCLKENB	2
+/* 25Mhz auxiliary output clock freq bit */
+#define OSCOUT1CLK25MHZ	16
+
+#define ST_CLK_48M	0
+#define ST_CLK_25M	1
+#define ST_CLK_MUX	2
+#define ST_CLK_GATE	3
+#define ST_MAX_CLKS	4
+
+static const char * const clk_oscout1_parents[] = { "clk48MHz", "clk25MHz" };
+static struct clk_hw *hws[ST_MAX_CLKS];
+
+static int st_clk_probe(struct platform_device *pdev)
+{
+	struct st_clk_data *st_data;
+
+	st_data = dev_get_platdata(&pdev->dev);
+	if (!st_data || !st_data->base)
+		return -EINVAL;
+
+	hws[ST_CLK_48M] = clk_hw_register_fixed_rate(NULL, "clk48MHz", NULL, 0,
+						     48000000);
+	hws[ST_CLK_25M] = clk_hw_register_fixed_rate(NULL, "clk25MHz", NULL, 0,
+						     25000000);
+
+	hws[ST_CLK_MUX] = clk_hw_register_mux(NULL, "oscout1_mux",
+		clk_oscout1_parents, ARRAY_SIZE(clk_oscout1_parents),
+		0, st_data->base + CLKDRVSTR2, OSCOUT1CLK25MHZ, 3, 0, NULL);
+
+	clk_set_parent(hws[ST_CLK_MUX]->clk, hws[ST_CLK_25M]->clk);
+
+	hws[ST_CLK_GATE] = clk_hw_register_gate(NULL, "oscout1", "oscout1_mux",
+		0, st_data->base + MISCCLKCNTL1, OSCCLKENB,
+		CLK_GATE_SET_TO_DISABLE, NULL);
+
+	clk_hw_register_clkdev(hws[ST_CLK_GATE], "oscout1", NULL);
+
+	return 0;
+}
+
+static int st_clk_remove(struct platform_device *pdev)
+{
+	int i;
+
+	for (i = 0; i < ST_MAX_CLKS; i++)
+		clk_hw_unregister(hws[i]);
+	return 0;
+}
+
+static struct platform_driver st_clk_driver = {
+	.driver = {
+		.name = "clk-st",
+		.suppress_bind_attrs = true,
+	},
+	.probe = st_clk_probe,
+	.remove = st_clk_remove,
+};
+builtin_platform_driver(st_clk_driver);
diff --git a/include/linux/platform_data/clk-st.h b/include/linux/platform_data/clk-st.h
new file mode 100644
index 0000000..7cdb6a4
--- /dev/null
+++ b/include/linux/platform_data/clk-st.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * clock framework for AMD Stoney based clock
+ *
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ */
+
+#ifndef __CLK_ST_H
+#define __CLK_ST_H
+
+#include <linux/compiler.h>
+
+struct st_clk_data {
+	void __iomem *base;
+};
+
+#endif /* __CLK_ST_H */
-- 
1.9.1

[PATCH v5 1/2] clk: x86: Add ST oscout platform clock

[Akshu Agrawal]

Stoney SoC provides oscout clock. This clock can support 25Mhz and
48Mhz of frequency.
The clock is available for general system use.

Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
---
v2: config change, added SPDX tag and used clk_hw_register_.
v3: Fix kbuild warning for checking of NULL pointer
v4: unregister clk_hw in driver remove, add .suppress_bind_attrs
v5: Fix license, used static array
 drivers/clk/x86/Makefile             |  3 +-
 drivers/clk/x86/clk-st.c             | 77 ++++++++++++++++++++++++++++++++++++
 include/linux/platform_data/clk-st.h | 17 ++++++++
 3 files changed, 96 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/x86/clk-st.c
 create mode 100644 include/linux/platform_data/clk-st.h

diff --git a/drivers/clk/x86/Makefile b/drivers/clk/x86/Makefile
index 1367afb..00303bc 100644
--- a/drivers/clk/x86/Makefile
+++ b/drivers/clk/x86/Makefile
@@ -1,3 +1,4 @@
+obj-$(CONFIG_PMC_ATOM)		+= clk-pmc-atom.o
+obj-$(CONFIG_X86_AMD_PLATFORM_DEVICE)	+= clk-st.o
 clk-x86-lpss-objs		:= clk-lpt.o
 obj-$(CONFIG_X86_INTEL_LPSS)	+= clk-x86-lpss.o
-obj-$(CONFIG_PMC_ATOM)		+= clk-pmc-atom.o
diff --git a/drivers/clk/x86/clk-st.c b/drivers/clk/x86/clk-st.c
new file mode 100644
index 0000000..fb62f39
--- /dev/null
+++ b/drivers/clk/x86/clk-st.c
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: MIT
+/*
+ * clock framework for AMD Stoney based clocks
+ *
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ */
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/platform_data/clk-st.h>
+#include <linux/platform_device.h>
+
+/* Clock Driving Strength 2 register */
+#define CLKDRVSTR2	0x28
+/* Clock Control 1 register */
+#define MISCCLKCNTL1	0x40
+/* Auxiliary clock1 enable bit */
+#define OSCCLKENB	2
+/* 25Mhz auxiliary output clock freq bit */
+#define OSCOUT1CLK25MHZ	16
+
+#define ST_CLK_48M	0
+#define ST_CLK_25M	1
+#define ST_CLK_MUX	2
+#define ST_CLK_GATE	3
+#define ST_MAX_CLKS	4
+
+static const char * const clk_oscout1_parents[] = { "clk48MHz", "clk25MHz" };
+static struct clk_hw *hws[ST_MAX_CLKS];
+
+static int st_clk_probe(struct platform_device *pdev)
+{
+	struct st_clk_data *st_data;
+
+	st_data = dev_get_platdata(&pdev->dev);
+	if (!st_data || !st_data->base)
+		return -EINVAL;
+
+	hws[ST_CLK_48M] = clk_hw_register_fixed_rate(NULL, "clk48MHz", NULL, 0,
+						     48000000);
+	hws[ST_CLK_25M] = clk_hw_register_fixed_rate(NULL, "clk25MHz", NULL, 0,
+						     25000000);
+
+	hws[ST_CLK_MUX] = clk_hw_register_mux(NULL, "oscout1_mux",
+		clk_oscout1_parents, ARRAY_SIZE(clk_oscout1_parents),
+		0, st_data->base + CLKDRVSTR2, OSCOUT1CLK25MHZ, 3, 0, NULL);
+
+	clk_set_parent(hws[ST_CLK_MUX]->clk, hws[ST_CLK_25M]->clk);
+
+	hws[ST_CLK_GATE] = clk_hw_register_gate(NULL, "oscout1", "oscout1_mux",
+		0, st_data->base + MISCCLKCNTL1, OSCCLKENB,
+		CLK_GATE_SET_TO_DISABLE, NULL);
+
+	clk_hw_register_clkdev(hws[ST_CLK_GATE], "oscout1", NULL);
+
+	return 0;
+}
+
+static int st_clk_remove(struct platform_device *pdev)
+{
+	int i;
+
+	for (i = 0; i < ST_MAX_CLKS; i++)
+		clk_hw_unregister(hws[i]);
+	return 0;
+}
+
+static struct platform_driver st_clk_driver = {
+	.driver = {
+		.name = "clk-st",
+		.suppress_bind_attrs = true,
+	},
+	.probe = st_clk_probe,
+	.remove = st_clk_remove,
+};
+builtin_platform_driver(st_clk_driver);
diff --git a/include/linux/platform_data/clk-st.h b/include/linux/platform_data/clk-st.h
new file mode 100644
index 0000000..7cdb6a4
--- /dev/null
+++ b/include/linux/platform_data/clk-st.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * clock framework for AMD Stoney based clock
+ *
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ */
+
+#ifndef __CLK_ST_H
+#define __CLK_ST_H
+
+#include <linux/compiler.h>
+
+struct st_clk_data {
+	void __iomem *base;
+};
+
+#endif /* __CLK_ST_H */
-- 
1.9.1

[PATCH v5 1/2] clk: x86: Add ST oscout platform clock

[Akshu Agrawal]

Stoney SoC provides oscout clock. This clock can support 25Mhz and
48Mhz of frequency.
The clock is available for general system use.

Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
---
v2: config change, added SPDX tag and used clk_hw_register_.
v3: Fix kbuild warning for checking of NULL pointer
v4: unregister clk_hw in driver remove, add .suppress_bind_attrs
v5: Fix license, used static array
 drivers/clk/x86/Makefile             |  3 +-
 drivers/clk/x86/clk-st.c             | 77 ++++++++++++++++++++++++++++++++++++
 include/linux/platform_data/clk-st.h | 17 ++++++++
 3 files changed, 96 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/x86/clk-st.c
 create mode 100644 include/linux/platform_data/clk-st.h

diff --git a/drivers/clk/x86/Makefile b/drivers/clk/x86/Makefile
index 1367afb..00303bc 100644
--- a/drivers/clk/x86/Makefile
+++ b/drivers/clk/x86/Makefile
@@ -1,3 +1,4 @@
+obj-$(CONFIG_PMC_ATOM)		+= clk-pmc-atom.o
+obj-$(CONFIG_X86_AMD_PLATFORM_DEVICE)	+= clk-st.o
 clk-x86-lpss-objs		:= clk-lpt.o
 obj-$(CONFIG_X86_INTEL_LPSS)	+= clk-x86-lpss.o
-obj-$(CONFIG_PMC_ATOM)		+= clk-pmc-atom.o
diff --git a/drivers/clk/x86/clk-st.c b/drivers/clk/x86/clk-st.c
new file mode 100644
index 0000000..fb62f39
--- /dev/null
+++ b/drivers/clk/x86/clk-st.c
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: MIT
+/*
+ * clock framework for AMD Stoney based clocks
+ *
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ */
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/platform_data/clk-st.h>
+#include <linux/platform_device.h>
+
+/* Clock Driving Strength 2 register */
+#define CLKDRVSTR2	0x28
+/* Clock Control 1 register */
+#define MISCCLKCNTL1	0x40
+/* Auxiliary clock1 enable bit */
+#define OSCCLKENB	2
+/* 25Mhz auxiliary output clock freq bit */
+#define OSCOUT1CLK25MHZ	16
+
+#define ST_CLK_48M	0
+#define ST_CLK_25M	1
+#define ST_CLK_MUX	2
+#define ST_CLK_GATE	3
+#define ST_MAX_CLKS	4
+
+static const char * const clk_oscout1_parents[] = { "clk48MHz", "clk25MHz" };
+static struct clk_hw *hws[ST_MAX_CLKS];
+
+static int st_clk_probe(struct platform_device *pdev)
+{
+	struct st_clk_data *st_data;
+
+	st_data = dev_get_platdata(&pdev->dev);
+	if (!st_data || !st_data->base)
+		return -EINVAL;
+
+	hws[ST_CLK_48M] = clk_hw_register_fixed_rate(NULL, "clk48MHz", NULL, 0,
+						     48000000);
+	hws[ST_CLK_25M] = clk_hw_register_fixed_rate(NULL, "clk25MHz", NULL, 0,
+						     25000000);
+
+	hws[ST_CLK_MUX] = clk_hw_register_mux(NULL, "oscout1_mux",
+		clk_oscout1_parents, ARRAY_SIZE(clk_oscout1_parents),
+		0, st_data->base + CLKDRVSTR2, OSCOUT1CLK25MHZ, 3, 0, NULL);
+
+	clk_set_parent(hws[ST_CLK_MUX]->clk, hws[ST_CLK_25M]->clk);
+
+	hws[ST_CLK_GATE] = clk_hw_register_gate(NULL, "oscout1", "oscout1_mux",
+		0, st_data->base + MISCCLKCNTL1, OSCCLKENB,
+		CLK_GATE_SET_TO_DISABLE, NULL);
+
+	clk_hw_register_clkdev(hws[ST_CLK_GATE], "oscout1", NULL);
+
+	return 0;
+}
+
+static int st_clk_remove(struct platform_device *pdev)
+{
+	int i;
+
+	for (i = 0; i < ST_MAX_CLKS; i++)
+		clk_hw_unregister(hws[i]);
+	return 0;
+}
+
+static struct platform_driver st_clk_driver = {
+	.driver = {
+		.name = "clk-st",
+		.suppress_bind_attrs = true,
+	},
+	.probe = st_clk_probe,
+	.remove = st_clk_remove,
+};
+builtin_platform_driver(st_clk_driver);
diff --git a/include/linux/platform_data/clk-st.h b/include/linux/platform_data/clk-st.h
new file mode 100644
index 0000000..7cdb6a4
--- /dev/null
+++ b/include/linux/platform_data/clk-st.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * clock framework for AMD Stoney based clock
+ *
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ */
+
+#ifndef __CLK_ST_H
+#define __CLK_ST_H
+
+#include <linux/compiler.h>
+
+struct st_clk_data {
+	void __iomem *base;
+};
+
+#endif /* __CLK_ST_H */
-- 
1.9.1

Re: [PATCH v5 1/2] clk: x86: Add ST oscout platform clock

[Daniel Kurtz]

On Wed, May 9, 2018 at 4:01 AM Akshu Agrawal <akshu.agrawal@amd.com> wrote:

> Stoney SoC provides oscout clock. This clock can support 25Mhz and
> 48Mhz of frequency.
> The clock is available for general system use.

> Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>

Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>


> ---
> v2: config change, added SPDX tag and used clk_hw_register_.
> v3: Fix kbuild warning for checking of NULL pointer
> v4: unregister clk_hw in driver remove, add .suppress_bind_attrs
> v5: Fix license, used static array
>   drivers/clk/x86/Makefile             |  3 +-
>   drivers/clk/x86/clk-st.c             | 77
++++++++++++++++++++++++++++++++++++
>   include/linux/platform_data/clk-st.h | 17 ++++++++
>   3 files changed, 96 insertions(+), 1 deletion(-)
>   create mode 100644 drivers/clk/x86/clk-st.c
>   create mode 100644 include/linux/platform_data/clk-st.h

> diff --git a/drivers/clk/x86/Makefile b/drivers/clk/x86/Makefile
> index 1367afb..00303bc 100644
> --- a/drivers/clk/x86/Makefile
> +++ b/drivers/clk/x86/Makefile
> @@ -1,3 +1,4 @@
> +obj-$(CONFIG_PMC_ATOM)         += clk-pmc-atom.o
> +obj-$(CONFIG_X86_AMD_PLATFORM_DEVICE)  += clk-st.o
>   clk-x86-lpss-objs              := clk-lpt.o
>   obj-$(CONFIG_X86_INTEL_LPSS)   += clk-x86-lpss.o
> -obj-$(CONFIG_PMC_ATOM)         += clk-pmc-atom.o
> diff --git a/drivers/clk/x86/clk-st.c b/drivers/clk/x86/clk-st.c
> new file mode 100644
> index 0000000..fb62f39
> --- /dev/null
> +++ b/drivers/clk/x86/clk-st.c
> @@ -0,0 +1,77 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * clock framework for AMD Stoney based clocks
> + *
> + * Copyright 2018 Advanced Micro Devices, Inc.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/clkdev.h>
> +#include <linux/clk-provider.h>
> +#include <linux/platform_data/clk-st.h>
> +#include <linux/platform_device.h>
> +
> +/* Clock Driving Strength 2 register */
> +#define CLKDRVSTR2     0x28
> +/* Clock Control 1 register */
> +#define MISCCLKCNTL1   0x40
> +/* Auxiliary clock1 enable bit */
> +#define OSCCLKENB      2
> +/* 25Mhz auxiliary output clock freq bit */
> +#define OSCOUT1CLK25MHZ        16
> +
> +#define ST_CLK_48M     0
> +#define ST_CLK_25M     1
> +#define ST_CLK_MUX     2
> +#define ST_CLK_GATE    3
> +#define ST_MAX_CLKS    4
> +
> +static const char * const clk_oscout1_parents[] = { "clk48MHz",
"clk25MHz" };
> +static struct clk_hw *hws[ST_MAX_CLKS];
> +
> +static int st_clk_probe(struct platform_device *pdev)
> +{
> +       struct st_clk_data *st_data;
> +
> +       st_data = dev_get_platdata(&pdev->dev);
> +       if (!st_data || !st_data->base)
> +               return -EINVAL;
> +
> +       hws[ST_CLK_48M] = clk_hw_register_fixed_rate(NULL, "clk48MHz",
NULL, 0,
> +                                                    48000000);
> +       hws[ST_CLK_25M] = clk_hw_register_fixed_rate(NULL, "clk25MHz",
NULL, 0,
> +                                                    25000000);
> +
> +       hws[ST_CLK_MUX] = clk_hw_register_mux(NULL, "oscout1_mux",
> +               clk_oscout1_parents, ARRAY_SIZE(clk_oscout1_parents),
> +               0, st_data->base + CLKDRVSTR2, OSCOUT1CLK25MHZ, 3, 0,
NULL);
> +
> +       clk_set_parent(hws[ST_CLK_MUX]->clk, hws[ST_CLK_25M]->clk);
> +
> +       hws[ST_CLK_GATE] = clk_hw_register_gate(NULL, "oscout1",
"oscout1_mux",
> +               0, st_data->base + MISCCLKCNTL1, OSCCLKENB,
> +               CLK_GATE_SET_TO_DISABLE, NULL);
> +
> +       clk_hw_register_clkdev(hws[ST_CLK_GATE], "oscout1", NULL);
> +
> +       return 0;
> +}
> +
> +static int st_clk_remove(struct platform_device *pdev)
> +{
> +       int i;
> +
> +       for (i = 0; i < ST_MAX_CLKS; i++)
> +               clk_hw_unregister(hws[i]);
> +       return 0;
> +}
> +
> +static struct platform_driver st_clk_driver = {
> +       .driver = {
> +               .name = "clk-st",
> +               .suppress_bind_attrs = true,
> +       },
> +       .probe = st_clk_probe,
> +       .remove = st_clk_remove,
> +};
> +builtin_platform_driver(st_clk_driver);
> diff --git a/include/linux/platform_data/clk-st.h
b/include/linux/platform_data/clk-st.h
> new file mode 100644
> index 0000000..7cdb6a4
> --- /dev/null
> +++ b/include/linux/platform_data/clk-st.h
> @@ -0,0 +1,17 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * clock framework for AMD Stoney based clock
> + *
> + * Copyright 2018 Advanced Micro Devices, Inc.
> + */
> +
> +#ifndef __CLK_ST_H
> +#define __CLK_ST_H
> +
> +#include <linux/compiler.h>
> +
> +struct st_clk_data {
> +       void __iomem *base;
> +};
> +
> +#endif /* __CLK_ST_H */
> --
> 1.9.1

Re: [PATCH v5 1/2] clk: x86: Add ST oscout platform clock

[Rafael J. Wysocki]

On Wednesday, May 9, 2018 11:59:00 AM CEST Akshu Agrawal wrote:
> Stoney SoC provides oscout clock. This clock can support 25Mhz and
> 48Mhz of frequency.
> The clock is available for general system use.
> 
> Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>

I'm not sure if the Stephen Boyd's comments on one of the previous
versions of this patch have been addressed.  Have they?

In any case, if I'm expected to take this, I need an ACK from Stephen on it.

Thanks,
Rafael

> ---
> v2: config change, added SPDX tag and used clk_hw_register_.
> v3: Fix kbuild warning for checking of NULL pointer
> v4: unregister clk_hw in driver remove, add .suppress_bind_attrs
> v5: Fix license, used static array
>  drivers/clk/x86/Makefile             |  3 +-
>  drivers/clk/x86/clk-st.c             | 77 ++++++++++++++++++++++++++++++++++++
>  include/linux/platform_data/clk-st.h | 17 ++++++++
>  3 files changed, 96 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/clk/x86/clk-st.c
>  create mode 100644 include/linux/platform_data/clk-st.h
> 
> diff --git a/drivers/clk/x86/Makefile b/drivers/clk/x86/Makefile
> index 1367afb..00303bc 100644
> --- a/drivers/clk/x86/Makefile
> +++ b/drivers/clk/x86/Makefile
> @@ -1,3 +1,4 @@
> +obj-$(CONFIG_PMC_ATOM)		+= clk-pmc-atom.o
> +obj-$(CONFIG_X86_AMD_PLATFORM_DEVICE)	+= clk-st.o
>  clk-x86-lpss-objs		:= clk-lpt.o
>  obj-$(CONFIG_X86_INTEL_LPSS)	+= clk-x86-lpss.o
> -obj-$(CONFIG_PMC_ATOM)		+= clk-pmc-atom.o
> diff --git a/drivers/clk/x86/clk-st.c b/drivers/clk/x86/clk-st.c
> new file mode 100644
> index 0000000..fb62f39
> --- /dev/null
> +++ b/drivers/clk/x86/clk-st.c
> @@ -0,0 +1,77 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * clock framework for AMD Stoney based clocks
> + *
> + * Copyright 2018 Advanced Micro Devices, Inc.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/clkdev.h>
> +#include <linux/clk-provider.h>
> +#include <linux/platform_data/clk-st.h>
> +#include <linux/platform_device.h>
> +
> +/* Clock Driving Strength 2 register */
> +#define CLKDRVSTR2	0x28
> +/* Clock Control 1 register */
> +#define MISCCLKCNTL1	0x40
> +/* Auxiliary clock1 enable bit */
> +#define OSCCLKENB	2
> +/* 25Mhz auxiliary output clock freq bit */
> +#define OSCOUT1CLK25MHZ	16
> +
> +#define ST_CLK_48M	0
> +#define ST_CLK_25M	1
> +#define ST_CLK_MUX	2
> +#define ST_CLK_GATE	3
> +#define ST_MAX_CLKS	4
> +
> +static const char * const clk_oscout1_parents[] = { "clk48MHz", "clk25MHz" };
> +static struct clk_hw *hws[ST_MAX_CLKS];
> +
> +static int st_clk_probe(struct platform_device *pdev)
> +{
> +	struct st_clk_data *st_data;
> +
> +	st_data = dev_get_platdata(&pdev->dev);
> +	if (!st_data || !st_data->base)
> +		return -EINVAL;
> +
> +	hws[ST_CLK_48M] = clk_hw_register_fixed_rate(NULL, "clk48MHz", NULL, 0,
> +						     48000000);
> +	hws[ST_CLK_25M] = clk_hw_register_fixed_rate(NULL, "clk25MHz", NULL, 0,
> +						     25000000);
> +
> +	hws[ST_CLK_MUX] = clk_hw_register_mux(NULL, "oscout1_mux",
> +		clk_oscout1_parents, ARRAY_SIZE(clk_oscout1_parents),
> +		0, st_data->base + CLKDRVSTR2, OSCOUT1CLK25MHZ, 3, 0, NULL);
> +
> +	clk_set_parent(hws[ST_CLK_MUX]->clk, hws[ST_CLK_25M]->clk);
> +
> +	hws[ST_CLK_GATE] = clk_hw_register_gate(NULL, "oscout1", "oscout1_mux",
> +		0, st_data->base + MISCCLKCNTL1, OSCCLKENB,
> +		CLK_GATE_SET_TO_DISABLE, NULL);
> +
> +	clk_hw_register_clkdev(hws[ST_CLK_GATE], "oscout1", NULL);
> +
> +	return 0;
> +}
> +
> +static int st_clk_remove(struct platform_device *pdev)
> +{
> +	int i;
> +
> +	for (i = 0; i < ST_MAX_CLKS; i++)
> +		clk_hw_unregister(hws[i]);
> +	return 0;
> +}
> +
> +static struct platform_driver st_clk_driver = {
> +	.driver = {
> +		.name = "clk-st",
> +		.suppress_bind_attrs = true,
> +	},
> +	.probe = st_clk_probe,
> +	.remove = st_clk_remove,
> +};
> +builtin_platform_driver(st_clk_driver);
> diff --git a/include/linux/platform_data/clk-st.h b/include/linux/platform_data/clk-st.h
> new file mode 100644
> index 0000000..7cdb6a4
> --- /dev/null
> +++ b/include/linux/platform_data/clk-st.h
> @@ -0,0 +1,17 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * clock framework for AMD Stoney based clock
> + *
> + * Copyright 2018 Advanced Micro Devices, Inc.
> + */
> +
> +#ifndef __CLK_ST_H
> +#define __CLK_ST_H
> +
> +#include <linux/compiler.h>
> +
> +struct st_clk_data {
> +	void __iomem *base;
> +};
> +
> +#endif /* __CLK_ST_H */
> 

Re: [PATCH v5 1/2] clk: x86: Add ST oscout platform clock

[Agrawal, Akshu]

On 5/15/2018 3:02 PM, Rafael J. Wysocki wrote:
> On Wednesday, May 9, 2018 11:59:00 AM CEST Akshu Agrawal wrote:
>> Stoney SoC provides oscout clock. This clock can support 25Mhz and
>> 48Mhz of frequency.
>> The clock is available for general system use.
>>
>> Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
> 
> I'm not sure if the Stephen Boyd's comments on one of the previous
> versions of this patch have been addressed.  Have they?
> 
> In any case, if I'm expected to take this, I need an ACK from Stephen on it.
> 
> Thanks,
> Rafael
> 

All comments of Stephen Boyd and Daniel Kurtz have been addressed.

Stephen, if you are Ok with this can you please ACK it.

Thanks,
Akshu

Re: [PATCH v5 1/2] clk: x86: Add ST oscout platform clock

[Stephen Boyd]

Quoting Agrawal, Akshu (2018-05-15 02:39:08)
> 
> 
> On 5/15/2018 3:02 PM, Rafael J. Wysocki wrote:
> > On Wednesday, May 9, 2018 11:59:00 AM CEST Akshu Agrawal wrote:
> >> Stoney SoC provides oscout clock. This clock can support 25Mhz and
> >> 48Mhz of frequency.
> >> The clock is available for general system use.
> >>
> >> Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
> > 
> > I'm not sure if the Stephen Boyd's comments on one of the previous
> > versions of this patch have been addressed.  Have they?
> > 
> > In any case, if I'm expected to take this, I need an ACK from Stephen on it.
> > 
> > Thanks,
> > Rafael
> > 
> 
> All comments of Stephen Boyd and Daniel Kurtz have been addressed.
> 
> Stephen, if you are Ok with this can you please ACK it.
> 

It could go via clk tree and meet up with the acpi patch in -next right?
I'm fine with it going through acpi path though so whichever way works.

Re: [PATCH v5 1/2] clk: x86: Add ST oscout platform clock

[Stephen Boyd]

Quoting Agrawal, Akshu (2018-05-15 02:39:08)
> =

> =

> On 5/15/2018 3:02 PM, Rafael J. Wysocki wrote:
> > On Wednesday, May 9, 2018 11:59:00 AM CEST Akshu Agrawal wrote:
> >> Stoney SoC provides oscout clock. This clock can support 25Mhz and
> >> 48Mhz of frequency.
> >> The clock is available for general system use.
> >>
> >> Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
> > =

> > I'm not sure if the Stephen Boyd's comments on one of the previous
> > versions of this patch have been addressed.  Have they?
> > =

> > In any case, if I'm expected to take this, I need an ACK from Stephen o=
n it.
> > =

> > Thanks,
> > Rafael
> > =

> =

> All comments of Stephen Boyd and Daniel Kurtz have been addressed.
> =

> Stephen, if you are Ok with this can you please ACK it.
> =


It could go via clk tree and meet up with the acpi patch in -next right?
I'm fine with it going through acpi path though so whichever way works.

Re: [PATCH v5 1/2] clk: x86: Add ST oscout platform clock

[Rafael J. Wysocki]

On Tue, May 15, 2018 at 11:14 PM, Stephen Boyd <sboyd@kernel.org> wrote:
> Quoting Agrawal, Akshu (2018-05-15 02:39:08)
>>
>>
>> On 5/15/2018 3:02 PM, Rafael J. Wysocki wrote:
>> > On Wednesday, May 9, 2018 11:59:00 AM CEST Akshu Agrawal wrote:
>> >> Stoney SoC provides oscout clock. This clock can support 25Mhz and
>> >> 48Mhz of frequency.
>> >> The clock is available for general system use.
>> >>
>> >> Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
>> >
>> > I'm not sure if the Stephen Boyd's comments on one of the previous
>> > versions of this patch have been addressed.  Have they?
>> >
>> > In any case, if I'm expected to take this, I need an ACK from Stephen on it.
>> >
>> > Thanks,
>> > Rafael
>> >
>>
>> All comments of Stephen Boyd and Daniel Kurtz have been addressed.
>>
>> Stephen, if you are Ok with this can you please ACK it.
>>
>
> It could go via clk tree and meet up with the acpi patch in -next right?
> I'm fine with it going through acpi path though so whichever way works.

It's better if it goes in as a series IMO and then if it goes via
ACPI, the clock dependency will be clear from the git history.

So if you don't mind, I'll queue this series up for 4.18.

Thanks,
Rafael

Re: [PATCH v5 1/2] clk: x86: Add ST oscout platform clock

[Stephen Boyd]

Quoting Rafael J. Wysocki (2018-05-16 01:23:27)
> On Tue, May 15, 2018 at 11:14 PM, Stephen Boyd <sboyd@kernel.org> wrote:
> > Quoting Agrawal, Akshu (2018-05-15 02:39:08)
> >>
> >>
> >> On 5/15/2018 3:02 PM, Rafael J. Wysocki wrote:
> >> > On Wednesday, May 9, 2018 11:59:00 AM CEST Akshu Agrawal wrote:
> >> >> Stoney SoC provides oscout clock. This clock can support 25Mhz and
> >> >> 48Mhz of frequency.
> >> >> The clock is available for general system use.
> >> >>
> >> >> Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
> >> >
> >> > I'm not sure if the Stephen Boyd's comments on one of the previous
> >> > versions of this patch have been addressed.  Have they?
> >> >
> >> > In any case, if I'm expected to take this, I need an ACK from Stephen on it.
> >> >
> >> > Thanks,
> >> > Rafael
> >> >
> >>
> >> All comments of Stephen Boyd and Daniel Kurtz have been addressed.
> >>
> >> Stephen, if you are Ok with this can you please ACK it.
> >>
> >
> > It could go via clk tree and meet up with the acpi patch in -next right?
> > I'm fine with it going through acpi path though so whichever way works.
> 
> It's better if it goes in as a series IMO and then if it goes via
> ACPI, the clock dependency will be clear from the git history.
> 
> So if you don't mind, I'll queue this series up for 4.18.
> 

Ok

Re: [PATCH v5 1/2] clk: x86: Add ST oscout platform clock

[Stephen Boyd]

Quoting Rafael J. Wysocki (2018-05-16 01:23:27)
> On Tue, May 15, 2018 at 11:14 PM, Stephen Boyd <sboyd@kernel.org> wrote:
> > Quoting Agrawal, Akshu (2018-05-15 02:39:08)
> >>
> >>
> >> On 5/15/2018 3:02 PM, Rafael J. Wysocki wrote:
> >> > On Wednesday, May 9, 2018 11:59:00 AM CEST Akshu Agrawal wrote:
> >> >> Stoney SoC provides oscout clock. This clock can support 25Mhz and
> >> >> 48Mhz of frequency.
> >> >> The clock is available for general system use.
> >> >>
> >> >> Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
> >> >
> >> > I'm not sure if the Stephen Boyd's comments on one of the previous
> >> > versions of this patch have been addressed.  Have they?
> >> >
> >> > In any case, if I'm expected to take this, I need an ACK from Stephe=
n on it.
> >> >
> >> > Thanks,
> >> > Rafael
> >> >
> >>
> >> All comments of Stephen Boyd and Daniel Kurtz have been addressed.
> >>
> >> Stephen, if you are Ok with this can you please ACK it.
> >>
> >
> > It could go via clk tree and meet up with the acpi patch in -next right?
> > I'm fine with it going through acpi path though so whichever way works.
> =

> It's better if it goes in as a series IMO and then if it goes via
> ACPI, the clock dependency will be clear from the git history.
> =

> So if you don't mind, I'll queue this series up for 4.18.
> =


Ok

Re: [PATCH v5 1/2] clk: x86: Add ST oscout platform clock

[Stephen Boyd]

Quoting Akshu Agrawal (2018-05-09 02:59:00)
> Stoney SoC provides oscout clock. This clock can support 25Mhz and
> 48Mhz of frequency.
> The clock is available for general system use.
> 
> Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
> ---

Reviewed-by: Stephen Boyd <sboyd@kernel.org>

Re: [PATCH v5 1/2] clk: x86: Add ST oscout platform clock

[Stephen Boyd]

Quoting Akshu Agrawal (2018-05-09 02:59:00)
> Stoney SoC provides oscout clock. This clock can support 25Mhz and
> 48Mhz of frequency.
> The clock is available for general system use.
> =

> Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
> ---

Reviewed-by: Stephen Boyd <sboyd@kernel.org>

Re: [PATCH v5 1/2] clk: x86: Add ST oscout platform clock

[Stephen Boyd]

Quoting Akshu Agrawal (2018-05-09 02:59:00)
> Stoney SoC provides oscout clock. This clock can support 25Mhz and
> 48Mhz of frequency.
> The clock is available for general system use.
> 
> Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
> ---

Reviewed-by: Stephen Boyd <sboyd@kernel.org>

[PATCH v3 2/2] ACPI: APD: Add AMD misc clock handler support

[Akshu Agrawal]

AMD SoC exposes clock for general purpose use. The clock registration
is done in clk-st driver. The MMIO mapping are passed on to the
clock driver for accessing the registers.
The misc clock handler will create MMIO mappings to access the
clock registers and enable the clock driver to expose the clock
for use of drivers which will connect to it.

Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
---
v2: Submitted with dependent patch, removed unneeded kfree for devm_kzalloc
v3: used devm_ioremap and fix coccinelle warning
 drivers/acpi/acpi_apd.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)

diff --git a/drivers/acpi/acpi_apd.c b/drivers/acpi/acpi_apd.c
index d553b00..2664452 100644
--- a/drivers/acpi/acpi_apd.c
+++ b/drivers/acpi/acpi_apd.c
@@ -11,6 +11,7 @@
  */
 
 #include <linux/clk-provider.h>
+#include <linux/platform_data/clk-st.h>
 #include <linux/platform_device.h>
 #include <linux/pm_domain.h>
 #include <linux/clkdev.h>
@@ -72,6 +73,47 @@ static int acpi_apd_setup(struct apd_private_data *pdata)
 }
 
 #ifdef CONFIG_X86_AMD_PLATFORM_DEVICE
+
+static int misc_check_res(struct acpi_resource *ares, void *data)
+{
+	struct resource res;
+
+	return !acpi_dev_resource_memory(ares, &res);
+}
+
+static int st_misc_setup(struct apd_private_data *pdata)
+{
+	struct acpi_device *adev = pdata->adev;
+	struct platform_device *clkdev;
+	struct st_clk_data *clk_data;
+	struct resource_entry *rentry;
+	struct list_head resource_list;
+	int ret;
+
+	clk_data = devm_kzalloc(&adev->dev, sizeof(*clk_data), GFP_KERNEL);
+	if (!clk_data)
+		return -ENOMEM;
+
+	INIT_LIST_HEAD(&resource_list);
+	ret = acpi_dev_get_resources(adev, &resource_list, misc_check_res,
+				     NULL);
+	if (ret < 0)
+		return -ENOENT;
+
+	list_for_each_entry(rentry, &resource_list, node) {
+		clk_data->base = devm_ioremap(&adev->dev, rentry->res->start,
+					      resource_size(rentry->res));
+		break;
+	}
+
+	acpi_dev_free_resource_list(&resource_list);
+
+	clkdev = platform_device_register_data(&adev->dev, "clk-st",
+					       PLATFORM_DEVID_NONE, clk_data,
+					       sizeof(*clk_data));
+	return PTR_ERR_OR_ZERO(clkdev);
+}
+
 static const struct apd_device_desc cz_i2c_desc = {
 	.setup = acpi_apd_setup,
 	.fixed_clk_rate = 133000000,
@@ -94,6 +136,10 @@ static int acpi_apd_setup(struct apd_private_data *pdata)
 	.fixed_clk_rate = 48000000,
 	.properties = uart_properties,
 };
+
+static const struct apd_device_desc st_misc_desc = {
+	.setup = st_misc_setup,
+};
 #endif
 
 #ifdef CONFIG_ARM64
@@ -179,6 +225,7 @@ static int acpi_apd_create_device(struct acpi_device *adev,
 	{ "AMD0020", APD_ADDR(cz_uart_desc) },
 	{ "AMDI0020", APD_ADDR(cz_uart_desc) },
 	{ "AMD0030", },
+	{ "AMD0040", APD_ADDR(st_misc_desc)},
 #endif
 #ifdef CONFIG_ARM64
 	{ "APMC0D0F", APD_ADDR(xgene_i2c_desc) },
-- 
1.9.1

[PATCH v3 2/2] ACPI: APD: Add AMD misc clock handler support

[Akshu Agrawal]

AMD SoC exposes clock for general purpose use. The clock registration
is done in clk-st driver. The MMIO mapping are passed on to the
clock driver for accessing the registers.
The misc clock handler will create MMIO mappings to access the
clock registers and enable the clock driver to expose the clock
for use of drivers which will connect to it.

Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
---
v2: Submitted with dependent patch, removed unneeded kfree for devm_kzalloc
v3: used devm_ioremap and fix coccinelle warning
 drivers/acpi/acpi_apd.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)

diff --git a/drivers/acpi/acpi_apd.c b/drivers/acpi/acpi_apd.c
index d553b00..2664452 100644
--- a/drivers/acpi/acpi_apd.c
+++ b/drivers/acpi/acpi_apd.c
@@ -11,6 +11,7 @@
  */
 
 #include <linux/clk-provider.h>
+#include <linux/platform_data/clk-st.h>
 #include <linux/platform_device.h>
 #include <linux/pm_domain.h>
 #include <linux/clkdev.h>
@@ -72,6 +73,47 @@ static int acpi_apd_setup(struct apd_private_data *pdata)
 }
 
 #ifdef CONFIG_X86_AMD_PLATFORM_DEVICE
+
+static int misc_check_res(struct acpi_resource *ares, void *data)
+{
+	struct resource res;
+
+	return !acpi_dev_resource_memory(ares, &res);
+}
+
+static int st_misc_setup(struct apd_private_data *pdata)
+{
+	struct acpi_device *adev = pdata->adev;
+	struct platform_device *clkdev;
+	struct st_clk_data *clk_data;
+	struct resource_entry *rentry;
+	struct list_head resource_list;
+	int ret;
+
+	clk_data = devm_kzalloc(&adev->dev, sizeof(*clk_data), GFP_KERNEL);
+	if (!clk_data)
+		return -ENOMEM;
+
+	INIT_LIST_HEAD(&resource_list);
+	ret = acpi_dev_get_resources(adev, &resource_list, misc_check_res,
+				     NULL);
+	if (ret < 0)
+		return -ENOENT;
+
+	list_for_each_entry(rentry, &resource_list, node) {
+		clk_data->base = devm_ioremap(&adev->dev, rentry->res->start,
+					      resource_size(rentry->res));
+		break;
+	}
+
+	acpi_dev_free_resource_list(&resource_list);
+
+	clkdev = platform_device_register_data(&adev->dev, "clk-st",
+					       PLATFORM_DEVID_NONE, clk_data,
+					       sizeof(*clk_data));
+	return PTR_ERR_OR_ZERO(clkdev);
+}
+
 static const struct apd_device_desc cz_i2c_desc = {
 	.setup = acpi_apd_setup,
 	.fixed_clk_rate = 133000000,
@@ -94,6 +136,10 @@ static int acpi_apd_setup(struct apd_private_data *pdata)
 	.fixed_clk_rate = 48000000,
 	.properties = uart_properties,
 };
+
+static const struct apd_device_desc st_misc_desc = {
+	.setup = st_misc_setup,
+};
 #endif
 
 #ifdef CONFIG_ARM64
@@ -179,6 +225,7 @@ static int acpi_apd_create_device(struct acpi_device *adev,
 	{ "AMD0020", APD_ADDR(cz_uart_desc) },
 	{ "AMDI0020", APD_ADDR(cz_uart_desc) },
 	{ "AMD0030", },
+	{ "AMD0040", APD_ADDR(st_misc_desc)},
 #endif
 #ifdef CONFIG_ARM64
 	{ "APMC0D0F", APD_ADDR(xgene_i2c_desc) },
-- 
1.9.1

[PATCH v3 2/2] ACPI: APD: Add AMD misc clock handler support

[Akshu Agrawal]

AMD SoC exposes clock for general purpose use. The clock registration
is done in clk-st driver. The MMIO mapping are passed on to the
clock driver for accessing the registers.
The misc clock handler will create MMIO mappings to access the
clock registers and enable the clock driver to expose the clock
for use of drivers which will connect to it.

Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
---
v2: Submitted with dependent patch, removed unneeded kfree for devm_kzalloc
v3: used devm_ioremap and fix coccinelle warning
 drivers/acpi/acpi_apd.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)

diff --git a/drivers/acpi/acpi_apd.c b/drivers/acpi/acpi_apd.c
index d553b00..2664452 100644
--- a/drivers/acpi/acpi_apd.c
+++ b/drivers/acpi/acpi_apd.c
@@ -11,6 +11,7 @@
  */
 
 #include <linux/clk-provider.h>
+#include <linux/platform_data/clk-st.h>
 #include <linux/platform_device.h>
 #include <linux/pm_domain.h>
 #include <linux/clkdev.h>
@@ -72,6 +73,47 @@ static int acpi_apd_setup(struct apd_private_data *pdata)
 }
 
 #ifdef CONFIG_X86_AMD_PLATFORM_DEVICE
+
+static int misc_check_res(struct acpi_resource *ares, void *data)
+{
+	struct resource res;
+
+	return !acpi_dev_resource_memory(ares, &res);
+}
+
+static int st_misc_setup(struct apd_private_data *pdata)
+{
+	struct acpi_device *adev = pdata->adev;
+	struct platform_device *clkdev;
+	struct st_clk_data *clk_data;
+	struct resource_entry *rentry;
+	struct list_head resource_list;
+	int ret;
+
+	clk_data = devm_kzalloc(&adev->dev, sizeof(*clk_data), GFP_KERNEL);
+	if (!clk_data)
+		return -ENOMEM;
+
+	INIT_LIST_HEAD(&resource_list);
+	ret = acpi_dev_get_resources(adev, &resource_list, misc_check_res,
+				     NULL);
+	if (ret < 0)
+		return -ENOENT;
+
+	list_for_each_entry(rentry, &resource_list, node) {
+		clk_data->base = devm_ioremap(&adev->dev, rentry->res->start,
+					      resource_size(rentry->res));
+		break;
+	}
+
+	acpi_dev_free_resource_list(&resource_list);
+
+	clkdev = platform_device_register_data(&adev->dev, "clk-st",
+					       PLATFORM_DEVID_NONE, clk_data,
+					       sizeof(*clk_data));
+	return PTR_ERR_OR_ZERO(clkdev);
+}
+
 static const struct apd_device_desc cz_i2c_desc = {
 	.setup = acpi_apd_setup,
 	.fixed_clk_rate = 133000000,
@@ -94,6 +136,10 @@ static int acpi_apd_setup(struct apd_private_data *pdata)
 	.fixed_clk_rate = 48000000,
 	.properties = uart_properties,
 };
+
+static const struct apd_device_desc st_misc_desc = {
+	.setup = st_misc_setup,
+};
 #endif
 
 #ifdef CONFIG_ARM64
@@ -179,6 +225,7 @@ static int acpi_apd_create_device(struct acpi_device *adev,
 	{ "AMD0020", APD_ADDR(cz_uart_desc) },
 	{ "AMDI0020", APD_ADDR(cz_uart_desc) },
 	{ "AMD0030", },
+	{ "AMD0040", APD_ADDR(st_misc_desc)},
 #endif
 #ifdef CONFIG_ARM64
 	{ "APMC0D0F", APD_ADDR(xgene_i2c_desc) },
-- 
1.9.1

Re: [PATCH v3 2/2] ACPI: APD: Add AMD misc clock handler support

[Daniel Kurtz]

On Wed, May 9, 2018 at 4:01 AM Akshu Agrawal <akshu.agrawal@amd.com> wrote:

> AMD SoC exposes clock for general purpose use. The clock registration
> is done in clk-st driver. The MMIO mapping are passed on to the
> clock driver for accessing the registers.
> The misc clock handler will create MMIO mappings to access the
> clock registers and enable the clock driver to expose the clock
> for use of drivers which will connect to it.

> Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>

Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>

> ---
> v2: Submitted with dependent patch, removed unneeded kfree for
devm_kzalloc
> v3: used devm_ioremap and fix coccinelle warning
>   drivers/acpi/acpi_apd.c | 47
+++++++++++++++++++++++++++++++++++++++++++++++
>   1 file changed, 47 insertions(+)

> diff --git a/drivers/acpi/acpi_apd.c b/drivers/acpi/acpi_apd.c
> index d553b00..2664452 100644
> --- a/drivers/acpi/acpi_apd.c
> +++ b/drivers/acpi/acpi_apd.c
> @@ -11,6 +11,7 @@
>    */

>   #include <linux/clk-provider.h>
> +#include <linux/platform_data/clk-st.h>
>   #include <linux/platform_device.h>
>   #include <linux/pm_domain.h>
>   #include <linux/clkdev.h>
> @@ -72,6 +73,47 @@ static int acpi_apd_setup(struct apd_private_data
*pdata)
>   }

>   #ifdef CONFIG_X86_AMD_PLATFORM_DEVICE
> +
> +static int misc_check_res(struct acpi_resource *ares, void *data)
> +{
> +       struct resource res;
> +
> +       return !acpi_dev_resource_memory(ares, &res);
> +}
> +
> +static int st_misc_setup(struct apd_private_data *pdata)
> +{
> +       struct acpi_device *adev = pdata->adev;
> +       struct platform_device *clkdev;
> +       struct st_clk_data *clk_data;
> +       struct resource_entry *rentry;
> +       struct list_head resource_list;
> +       int ret;
> +
> +       clk_data = devm_kzalloc(&adev->dev, sizeof(*clk_data),
GFP_KERNEL);
> +       if (!clk_data)
> +               return -ENOMEM;
> +
> +       INIT_LIST_HEAD(&resource_list);
> +       ret = acpi_dev_get_resources(adev, &resource_list, misc_check_res,
> +                                    NULL);
> +       if (ret < 0)
> +               return -ENOENT;
> +
> +       list_for_each_entry(rentry, &resource_list, node) {
> +               clk_data->base = devm_ioremap(&adev->dev,
rentry->res->start,
> +                                             resource_size(rentry->res));
> +               break;
> +       }
> +
> +       acpi_dev_free_resource_list(&resource_list);
> +
> +       clkdev = platform_device_register_data(&adev->dev, "clk-st",
> +                                              PLATFORM_DEVID_NONE,
clk_data,
> +                                              sizeof(*clk_data));
> +       return PTR_ERR_OR_ZERO(clkdev);
> +}
> +
>   static const struct apd_device_desc cz_i2c_desc = {
>          .setup = acpi_apd_setup,
>          .fixed_clk_rate = 133000000,
> @@ -94,6 +136,10 @@ static int acpi_apd_setup(struct apd_private_data
*pdata)
>          .fixed_clk_rate = 48000000,
>          .properties = uart_properties,
>   };
> +
> +static const struct apd_device_desc st_misc_desc = {
> +       .setup = st_misc_setup,
> +};
>   #endif

>   #ifdef CONFIG_ARM64
> @@ -179,6 +225,7 @@ static int acpi_apd_create_device(struct acpi_device
*adev,
>          { "AMD0020", APD_ADDR(cz_uart_desc) },
>          { "AMDI0020", APD_ADDR(cz_uart_desc) },
>          { "AMD0030", },
> +       { "AMD0040", APD_ADDR(st_misc_desc)},
>   #endif
>   #ifdef CONFIG_ARM64
>          { "APMC0D0F", APD_ADDR(xgene_i2c_desc) },
> --
> 1.9.1

Re: [PATCH v3 0/2] Add support for general system clock on ST AMD platform

[Rafael J. Wysocki]

On Wednesday, May 9, 2018 11:58:59 AM CEST Akshu Agrawal wrote:
> AMD ST/CZ platform provides a general system clock which can be used
> by any driver. Registration of this clock will done in clk-st driver.
> While the ACPI misc device will create the required MMIO mappings
> and pass the same to the clk-st driver. The clk-st driver will
> use the address to enable/disable and set frequency.
> 
> Changelog:
> v2:
>   clk: x86: Add ST oscout platform clock: v3->v4 unregister clk_hw
>   ACPI: APD: Add AMD misc clock handler support: No change (v2)
> v3:
>   clk: x86: Add ST oscout platform clock:
> 		v4->v5 use static array, change license
>   ACPI: APD: Add AMD misc clock handler support:
> 		v2->v3 use devm_ioremap, fix warning
> 
> Akshu Agrawal (2):
>   clk: x86: Add ST oscout platform clock
>   ACPI: APD: Add AMD misc clock handler support
> 
>  drivers/acpi/acpi_apd.c              | 50 ++++++++++++++++++++
>  drivers/clk/x86/Makefile             |  1 +
>  drivers/clk/x86/clk-st.c             | 88 ++++++++++++++++++++++++++++++++++++
>  include/linux/platform_data/clk-st.h | 35 ++++++++++++++
>  4 files changed, 174 insertions(+)
>  create mode 100644 drivers/clk/x86/clk-st.c
>  create mode 100644 include/linux/platform_data/clk-st.h
> 
> 

Both patches applied, thanks!