[PATCH 0/4] arm64: dts: renesas: r8a77990: Enable EthernetAVB for ebisu board

[PATCH 0/4] arm64: dts: renesas: r8a77990: Enable EthernetAVB for ebisu board

[Yoshihiro Shimoda]

This patch set is based on renesas-drivers-2018-05-02-v4.17-rc3 tag of
renesas-drivers.git.

The dt-bindings patches of GPIO and EthernetAVB are submitted now:
https://patchwork.kernel.org/patch/10393001/
https://patchwork.kernel.org/patch/10393049/

Yoshihiro Shimoda (4):
  arm64: dts: renesas: r8a77990: Add PFC device node
  arm64: dts: renesas: r8a77990: Add GPIO device nodes
  arm64: dts: renesas: r8a77990: Add EthernetAVB device nodes
  arm64: dts: renesas: r8a77990: ebisu: Enable EthernetAVB

 arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts |  28 +++++
 arch/arm64/boot/dts/renesas/r8a77990.dtsi      | 162 +++++++++++++++++++++++++
 2 files changed, 190 insertions(+)

-- 
1.9.1

[PATCH 1/4] arm64: dts: renesas: r8a77990: Add PFC device node

[Yoshihiro Shimoda]

This patch adds PFC device node for r8a77990 (R-Car E3).

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a77990.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
index 4658029..efc3c0b 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
@@ -60,6 +60,11 @@
 		#size-cells = <2>;
 		ranges;
 
+		pfc: pin-controller@e6060000 {
+			compatible = "renesas,pfc-r8a77990";
+			reg = <0 0xe6060000 0 0x508>;
+		};
+
 		cpg: clock-controller@e6150000 {
 			compatible = "renesas,r8a77990-cpg-mssr";
 			reg = <0 0xe6150000 0 0x1000>;
-- 
1.9.1

[PATCH 2/4] arm64: dts: renesas: r8a77990: Add GPIO device nodes

[Yoshihiro Shimoda]

This patch adds GPIO nodes for r8a77990 (R-Car E3).

Based on a patch from Takeshi Kihara <takeshi.kihara.df@renesas.com>

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a77990.dtsi | 112 ++++++++++++++++++++++++++++++
 1 file changed, 112 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
index efc3c0b..d94e047 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
@@ -60,6 +60,118 @@
 		#size-cells = <2>;
 		ranges;
 
+		gpio0: gpio@e6050000 {
+			compatible = "renesas,gpio-r8a77990",
+				     "renesas,rcar-gen3-gpio",
+				     "renesas,gpio-rcar";
+			reg = <0 0xe6050000 0 0x50>;
+			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			gpio-ranges = <&pfc 0 0 18>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			clocks = <&cpg CPG_MOD 912>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 912>;
+		};
+
+		gpio1: gpio@e6051000 {
+			compatible = "renesas,gpio-r8a77990",
+				     "renesas,rcar-gen3-gpio",
+				     "renesas,gpio-rcar";
+			reg = <0 0xe6051000 0 0x50>;
+			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			gpio-ranges = <&pfc 0 32 23>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			clocks = <&cpg CPG_MOD 911>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 911>;
+		};
+
+		gpio2: gpio@e6052000 {
+			compatible = "renesas,gpio-r8a77990",
+				     "renesas,rcar-gen3-gpio",
+				     "renesas,gpio-rcar";
+			reg = <0 0xe6052000 0 0x50>;
+			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			gpio-ranges = <&pfc 0 64 26>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			clocks = <&cpg CPG_MOD 910>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 910>;
+		};
+
+		gpio3: gpio@e6053000 {
+			compatible = "renesas,gpio-r8a77990",
+				     "renesas,rcar-gen3-gpio",
+				     "renesas,gpio-rcar";
+			reg = <0 0xe6053000 0 0x50>;
+			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			gpio-ranges = <&pfc 0 96 16>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			clocks = <&cpg CPG_MOD 909>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 909>;
+		};
+
+		gpio4: gpio@e6054000 {
+			compatible = "renesas,gpio-r8a77990",
+				     "renesas,rcar-gen3-gpio",
+				     "renesas,gpio-rcar";
+			reg = <0 0xe6054000 0 0x50>;
+			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			gpio-ranges = <&pfc 0 128 11>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			clocks = <&cpg CPG_MOD 908>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 908>;
+		};
+
+		gpio5: gpio@e6055000 {
+			compatible = "renesas,gpio-r8a77990",
+				     "renesas,rcar-gen3-gpio",
+				     "renesas,gpio-rcar";
+			reg = <0 0xe6055000 0 0x50>;
+			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			gpio-ranges = <&pfc 0 160 20>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			clocks = <&cpg CPG_MOD 907>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 907>;
+		};
+
+		gpio6: gpio@e6055400 {
+			compatible = "renesas,gpio-r8a77990",
+				     "renesas,rcar-gen3-gpio",
+				     "renesas,gpio-rcar";
+			reg = <0 0xe6055400 0 0x50>;
+			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			gpio-ranges = <&pfc 0 192 18>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			clocks = <&cpg CPG_MOD 906>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 906>;
+		};
+
 		pfc: pin-controller@e6060000 {
 			compatible = "renesas,pfc-r8a77990";
 			reg = <0 0xe6060000 0 0x508>;
-- 
1.9.1

[PATCH 3/4] arm64: dts: renesas: r8a77990: Add EthernetAVB device nodes

[Yoshihiro Shimoda]

This patch adds EthernetAVB node for r8a77990 (R-Car E3).

Based on a patch from Takeshi Kihara <takeshi.kihara.df@renesas.com>

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a77990.dtsi | 45 +++++++++++++++++++++++++++++++
 1 file changed, 45 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
index d94e047..37d57fd 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
@@ -198,6 +198,51 @@
 			#power-domain-cells = <1>;
 		};
 
+		avb: ethernet@e6800000 {
+			compatible = "renesas,etheravb-r8a77990",
+				     "renesas,etheravb-rcar-gen3";
+			reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
+			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "ch0", "ch1", "ch2", "ch3",
+					  "ch4", "ch5", "ch6", "ch7",
+					  "ch8", "ch9", "ch10", "ch11",
+					  "ch12", "ch13", "ch14", "ch15",
+					  "ch16", "ch17", "ch18", "ch19",
+					  "ch20", "ch21", "ch22", "ch23",
+					  "ch24";
+			clocks = <&cpg CPG_MOD 812>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 812>;
+			phy-mode = "rgmii";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		scif2: serial@e6e88000 {
 			compatible = "renesas,scif-r8a77990",
 				     "renesas,rcar-gen3-scif", "renesas,scif";
-- 
1.9.1

[PATCH 4/4] arm64: dts: renesas: r8a77990: ebisu: Enable EthernetAVB

[Yoshihiro Shimoda]

This patch enables EthernetAVB for r8a77990 Ebisu board.

Based on a patch from Takeshi Kihara <takeshi.kihara.df@renesas.com>

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts | 28 ++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
index 63ee134..7a09d05 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
@@ -7,6 +7,7 @@
 
 /dts-v1/;
 #include "r8a77990.dtsi"
+#include <dt-bindings/gpio/gpio.h>
 
 / {
 	model = "Renesas Ebisu board based on r8a77990";
@@ -14,6 +15,7 @@
 
 	aliases {
 		serial0 = &scif2;
+		ethernet0 = &avb;
 	};
 
 	chosen {
@@ -28,10 +30,36 @@
 	};
 };
 
+&avb {
+	pinctrl-0 = <&avb_pins>;
+	pinctrl-names = "default";
+	renesas,no-ether-link;
+	phy-handle = <&phy0>;
+	phy-mode = "rgmii-txid";
+	status = "okay";
+
+	phy0: ethernet-phy@0 {
+		rxc-skew-ps = <1500>;
+		reg = <0>;
+		interrupt-parent = <&gpio2>;
+		interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
+		reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
+	};
+};
+
 &extal_clk {
 	clock-frequency = <48000000>;
 };
 
+&pfc {
+	avb_pins: avb {
+		mux {
+			groups = "avb_link", "avb_mii";
+			function = "avb";
+		};
+	};
+};
+
 &scif2 {
 	status = "okay";
 };
-- 
1.9.1

Re: [PATCH 1/4] arm64: dts: renesas: r8a77990: Add PFC device node

[Simon Horman]

On Fri, May 11, 2018 at 01:31:18PM +0900, Yoshihiro Shimoda wrote:
> This patch adds PFC device node for r8a77990 (R-Car E3).
> 
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> ---
>  arch/arm64/boot/dts/renesas/r8a77990.dtsi | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
> index 4658029..efc3c0b 100644
> --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
> @@ -60,6 +60,11 @@
>  		#size-cells = <2>;
>  		ranges;
>  
> +		pfc: pin-controller@e6060000 {
> +			compatible = "renesas,pfc-r8a77990";
> +			reg = <0 0xe6060000 0 0x508>;
> +		};

Here the register size is 0x508 which matches r8a77995.dtsi in mainline.
Other variants there are:
* 0x50c: r8a7795.dtsi, r8a77965.dtsi, r8a7796.dtsi
* 0x504: r8a77970.dtsi

My reading of the documentation is that the size of the register range is
0x50c. So I suggest we either use that value consistently or move to a
larger value after some rounding-up. Geert?

> +
>  		cpg: clock-controller@e6150000 {
>  			compatible = "renesas,r8a77990-cpg-mssr";
>  			reg = <0 0xe6150000 0 0x1000>;
> -- 
> 1.9.1
> 

Re: [PATCH 2/4] arm64: dts: renesas: r8a77990: Add GPIO device nodes

[Simon Horman]

On Fri, May 11, 2018 at 01:31:19PM +0900, Yoshihiro Shimoda wrote:
> This patch adds GPIO nodes for r8a77990 (R-Car E3).
> 
> Based on a patch from Takeshi Kihara <takeshi.kihara.df@renesas.com>
> 
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> ---
>  arch/arm64/boot/dts/renesas/r8a77990.dtsi | 112 ++++++++++++++++++++++++++++++
>  1 file changed, 112 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
> index efc3c0b..d94e047 100644
> --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
> @@ -60,6 +60,118 @@
>  		#size-cells = <2>;
>  		ranges;
>  
> +		gpio0: gpio@e6050000 {
> +			compatible = "renesas,gpio-r8a77990",
> +				     "renesas,rcar-gen3-gpio",
> +				     "renesas,gpio-rcar";

"renesas,gpio-rcar" is deprecated and thus should not be added to DT any
more. I will see about removing it from r8a77995.dtsi which seems to be the
only place that it used in mainline.

Otherwise this patch looks good to me.

> +			reg = <0 0xe6050000 0 0x50>;
> +			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
> +			#gpio-cells = <2>;
> +			gpio-controller;
> +			gpio-ranges = <&pfc 0 0 18>;
> +			#interrupt-cells = <2>;
> +			interrupt-controller;
> +			clocks = <&cpg CPG_MOD 912>;
> +			power-domains = <&sysc 32>;
> +			resets = <&cpg 912>;
> +		};

...

Re: [PATCH 3/4] arm64: dts: renesas: r8a77990: Add EthernetAVB device nodes

[Simon Horman]

On Fri, May 11, 2018 at 01:31:20PM +0900, Yoshihiro Shimoda wrote:
> This patch adds EthernetAVB node for r8a77990 (R-Car E3).
> 
> Based on a patch from Takeshi Kihara <takeshi.kihara.df@renesas.com>
> 
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

This looks fine but I will wait to see if there are other reviews before
applying.

Reviewed-by: Simon Horman <horms+renesas@verge.net.au>

Re: [PATCH 4/4] arm64: dts: renesas: r8a77990: ebisu: Enable EthernetAVB

[Simon Horman]

On Fri, May 11, 2018 at 01:31:21PM +0900, Yoshihiro Shimoda wrote:
> This patch enables EthernetAVB for r8a77990 Ebisu board.
> 
> Based on a patch from Takeshi Kihara <takeshi.kihara.df@renesas.com>
> 
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

This looks fine but I will wait to see if there are other reviews before
applying.

Reviewed-by: Simon Horman <horms+renesas@verge.net.au>

Re: [PATCH 1/4] arm64: dts: renesas: r8a77990: Add PFC device node

[Geert Uytterhoeven]

Hi Simon,

On Sun, May 13, 2018 at 10:14 AM, Simon Horman <horms@verge.net.au> wrote:
> On Fri, May 11, 2018 at 01:31:18PM +0900, Yoshihiro Shimoda wrote:
>> This patch adds PFC device node for r8a77990 (R-Car E3).
>>
>> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
>> ---
>>  arch/arm64/boot/dts/renesas/r8a77990.dtsi | 5 +++++
>>  1 file changed, 5 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
>> index 4658029..efc3c0b 100644
>> --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
>> +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
>> @@ -60,6 +60,11 @@
>>               #size-cells = <2>;
>>               ranges;
>>
>> +             pfc: pin-controller@e6060000 {
>> +                     compatible = "renesas,pfc-r8a77990";
>> +                     reg = <0 0xe6060000 0 0x508>;
>> +             };
>
> Here the register size is 0x508 which matches r8a77995.dtsi in mainline.
> Other variants there are:
> * 0x50c: r8a7795.dtsi, r8a77965.dtsi, r8a7796.dtsi
> * 0x504: r8a77970.dtsi

The number of registers is SoC-specific.
R-Car H3, M3-W, and M3-N share PFC documentation.

> My reading of the documentation is that the size of the register range is
> 0x50c. So I suggest we either use that value consistently or move to a
> larger value after some rounding-up. Geert?

According to Section 6D ("Pin Function Controller (PFC)" for R-Car E3)
of the datasheet, the last register is at offset 0x504, so length 0x508 is
correct.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 1/4] arm64: dts: renesas: r8a77990: Add PFC device node

[Simon Horman]

On Mon, May 14, 2018 at 10:27:21PM +0200, Geert Uytterhoeven wrote:
> Hi Simon,
> 
> On Sun, May 13, 2018 at 10:14 AM, Simon Horman <horms@verge.net.au> wrote:
> > On Fri, May 11, 2018 at 01:31:18PM +0900, Yoshihiro Shimoda wrote:
> >> This patch adds PFC device node for r8a77990 (R-Car E3).
> >>
> >> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> >> ---
> >>  arch/arm64/boot/dts/renesas/r8a77990.dtsi | 5 +++++
> >>  1 file changed, 5 insertions(+)
> >>
> >> diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
> >> index 4658029..efc3c0b 100644
> >> --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
> >> +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
> >> @@ -60,6 +60,11 @@
> >>               #size-cells = <2>;
> >>               ranges;
> >>
> >> +             pfc: pin-controller@e6060000 {
> >> +                     compatible = "renesas,pfc-r8a77990";
> >> +                     reg = <0 0xe6060000 0 0x508>;
> >> +             };
> >
> > Here the register size is 0x508 which matches r8a77995.dtsi in mainline.
> > Other variants there are:
> > * 0x50c: r8a7795.dtsi, r8a77965.dtsi, r8a7796.dtsi
> > * 0x504: r8a77970.dtsi
> 
> The number of registers is SoC-specific.
> R-Car H3, M3-W, and M3-N share PFC documentation.
> 
> > My reading of the documentation is that the size of the register range is
> > 0x50c. So I suggest we either use that value consistently or move to a
> > larger value after some rounding-up. Geert?
> 
> According to Section 6D ("Pin Function Controller (PFC)" for R-Car E3)
> of the datasheet, the last register is at offset 0x504, so length 0x508 is
> correct.
> 
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Thanks for the explanation, applied.

Re: [PATCH 2/4] arm64: dts: renesas: r8a77990: Add GPIO device nodes

[Simon Horman]

On Sun, May 13, 2018 at 11:02:05AM +0200, Simon Horman wrote:
> On Fri, May 11, 2018 at 01:31:19PM +0900, Yoshihiro Shimoda wrote:
> > This patch adds GPIO nodes for r8a77990 (R-Car E3).
> > 
> > Based on a patch from Takeshi Kihara <takeshi.kihara.df@renesas.com>
> > 
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > ---
> >  arch/arm64/boot/dts/renesas/r8a77990.dtsi | 112 ++++++++++++++++++++++++++++++
> >  1 file changed, 112 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
> > index efc3c0b..d94e047 100644
> > --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
> > @@ -60,6 +60,118 @@
> >  		#size-cells = <2>;
> >  		ranges;
> >  
> > +		gpio0: gpio@e6050000 {
> > +			compatible = "renesas,gpio-r8a77990",
> > +				     "renesas,rcar-gen3-gpio",
> > +				     "renesas,gpio-rcar";
> 
> "renesas,gpio-rcar" is deprecated and thus should not be added to DT any
> more. I will see about removing it from r8a77995.dtsi which seems to be the
> only place that it used in mainline.
> 
> Otherwise this patch looks good to me.

I have applied this patch after removing "renesas,gpio-rcar".

The result is as follows.


From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Subject: [PATCH] arm64: dts: renesas: r8a77990: Add GPIO device nodes

This patch adds GPIO nodes for r8a77990 (R-Car E3).

Based on a patch from Takeshi Kihara <takeshi.kihara.df@renesas.com>

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
[simon: dropped use of deprecated "renesas,gpio-rcar"]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm64/boot/dts/renesas/r8a77990.dtsi | 105 ++++++++++++++++++++++++++++++
 1 file changed, 105 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
index efc3c0ba36c2..bbc3db50bc01 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
@@ -60,6 +60,111 @@
 		#size-cells = <2>;
 		ranges;
 
+		gpio0: gpio@e6050000 {
+			compatible = "renesas,gpio-r8a77990",
+				     "renesas,rcar-gen3-gpio";
+			reg = <0 0xe6050000 0 0x50>;
+			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			gpio-ranges = <&pfc 0 0 18>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			clocks = <&cpg CPG_MOD 912>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 912>;
+		};
+
+		gpio1: gpio@e6051000 {
+			compatible = "renesas,gpio-r8a77990",
+				     "renesas,rcar-gen3-gpio";
+			reg = <0 0xe6051000 0 0x50>;
+			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			gpio-ranges = <&pfc 0 32 23>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			clocks = <&cpg CPG_MOD 911>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 911>;
+		};
+
+		gpio2: gpio@e6052000 {
+			compatible = "renesas,gpio-r8a77990",
+				     "renesas,rcar-gen3-gpio";
+			reg = <0 0xe6052000 0 0x50>;
+			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			gpio-ranges = <&pfc 0 64 26>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			clocks = <&cpg CPG_MOD 910>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 910>;
+		};
+
+		gpio3: gpio@e6053000 {
+			compatible = "renesas,gpio-r8a77990",
+				     "renesas,rcar-gen3-gpio";
+			reg = <0 0xe6053000 0 0x50>;
+			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			gpio-ranges = <&pfc 0 96 16>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			clocks = <&cpg CPG_MOD 909>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 909>;
+		};
+
+		gpio4: gpio@e6054000 {
+			compatible = "renesas,gpio-r8a77990",
+				     "renesas,rcar-gen3-gpio";
+			reg = <0 0xe6054000 0 0x50>;
+			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			gpio-ranges = <&pfc 0 128 11>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			clocks = <&cpg CPG_MOD 908>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 908>;
+		};
+
+		gpio5: gpio@e6055000 {
+			compatible = "renesas,gpio-r8a77990",
+				     "renesas,rcar-gen3-gpio";
+			reg = <0 0xe6055000 0 0x50>;
+			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			gpio-ranges = <&pfc 0 160 20>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			clocks = <&cpg CPG_MOD 907>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 907>;
+		};
+
+		gpio6: gpio@e6055400 {
+			compatible = "renesas,gpio-r8a77990",
+				     "renesas,rcar-gen3-gpio";
+			reg = <0 0xe6055400 0 0x50>;
+			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			gpio-ranges = <&pfc 0 192 18>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			clocks = <&cpg CPG_MOD 906>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 906>;
+		};
+
 		pfc: pin-controller@e6060000 {
 			compatible = "renesas,pfc-r8a77990";
 			reg = <0 0xe6060000 0 0x508>;
-- 
2.11.0

Re: [PATCH 3/4] arm64: dts: renesas: r8a77990: Add EthernetAVB device nodes

[Simon Horman]

On Sun, May 13, 2018 at 11:16:16AM +0200, Simon Horman wrote:
> On Fri, May 11, 2018 at 01:31:20PM +0900, Yoshihiro Shimoda wrote:
> > This patch adds EthernetAVB node for r8a77990 (R-Car E3).
> > 
> > Based on a patch from Takeshi Kihara <takeshi.kihara.df@renesas.com>
> > 
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> 
> This looks fine but I will wait to see if there are other reviews before
> applying.
> 
> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>

Applied.

Re: [PATCH 4/4] arm64: dts: renesas: r8a77990: ebisu: Enable EthernetAVB

[Simon Horman]

On Sun, May 13, 2018 at 11:28:58AM +0200, Simon Horman wrote:
> On Fri, May 11, 2018 at 01:31:21PM +0900, Yoshihiro Shimoda wrote:
> > This patch enables EthernetAVB for r8a77990 Ebisu board.
> > 
> > Based on a patch from Takeshi Kihara <takeshi.kihara.df@renesas.com>
> > 
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> 
> This looks fine but I will wait to see if there are other reviews before
> applying.
> 
> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>

Applied.