* [PATCH 1/6] drm/i915/psr: Avoid DPCD reads when panel does not support PSR
@ 2018-05-11 19:51 Dhinakaran Pandiyan
2018-05-11 19:51 ` [PATCH 2/6] drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time Dhinakaran Pandiyan
` (8 more replies)
0 siblings, 9 replies; 23+ messages in thread
From: Dhinakaran Pandiyan @ 2018-05-11 19:51 UTC (permalink / raw)
To: intel-gfx; +Cc: Dhinakaran Pandiyan
Ville noticed that we are unncessarily reading DPCD's after knowing
panel did not support PSR. Looks like this check that was present
earlier got removed unintentionally, let's put it back.
While we do this, add the PSR version number in the debug print.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
---
drivers/gpu/drm/i915/intel_psr.c | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index db27f2faa1de..8fe6d2f9ab2b 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -250,10 +250,12 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
sizeof(intel_dp->psr_dpcd));
- if (intel_dp->psr_dpcd[0]) {
- dev_priv->psr.sink_support = true;
- DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
- }
+ if (!intel_dp->psr_dpcd[0])
+ return;
+
+ DRM_DEBUG_KMS("eDP panel supports PSR version %x\n",
+ intel_dp->psr_dpcd[0]);
+ dev_priv->psr.sink_support = true;
if (INTEL_GEN(dev_priv) >= 9 &&
(intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) {
@@ -270,8 +272,8 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
*/
dev_priv->psr.sink_psr2_support =
intel_dp_get_y_coord_required(intel_dp);
- DRM_DEBUG_KMS("PSR2 %s on sink", dev_priv->psr.sink_psr2_support
- ? "supported" : "not supported");
+ DRM_DEBUG_KMS("PSR2 %ssupported\n",
+ dev_priv->psr.sink_psr2_support ? "" : "not ");
if (dev_priv->psr.sink_psr2_support) {
dev_priv->psr.colorimetry_support =
--
2.14.1
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 2/6] drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time.
2018-05-11 19:51 [PATCH 1/6] drm/i915/psr: Avoid DPCD reads when panel does not support PSR Dhinakaran Pandiyan
@ 2018-05-11 19:51 ` Dhinakaran Pandiyan
2018-05-11 22:14 ` Dhinakaran Pandiyan
2018-05-11 19:51 ` [PATCH 3/6] drm/psr: Fix missed entry in PSR setup time table Dhinakaran Pandiyan
` (7 subsequent siblings)
8 siblings, 1 reply; 23+ messages in thread
From: Dhinakaran Pandiyan @ 2018-05-11 19:51 UTC (permalink / raw)
To: intel-gfx; +Cc: Dhinakaran Pandiyan
By moving the check from psr_compute_config() to psr_init_dpcd(), we get
to set the dev_priv->psr.sink_support flag only when the panel is
capable of changing power state. An additional benefit is that the check
will be performed only at init time instead of every atomic_check.
This should change the psr_basic IGT failures on HSW to skips.
v2: Return early when SET_POWER_CAPABLE bit is 0 (Jose)
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 8 ++++++--
drivers/gpu/drm/i915/intel_psr.c | 11 +++++------
2 files changed, 11 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index dde92e4af5d3..cfd95eaa0d0d 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3762,8 +3762,6 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
- intel_psr_init_dpcd(intel_dp);
-
/*
* Read the eDP display control registers.
*
@@ -3779,6 +3777,12 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
DRM_DEBUG_KMS("eDP DPCD: %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
intel_dp->edp_dpcd);
+ /*
+ * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
+ * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
+ */
+ intel_psr_init_dpcd(intel_dp);
+
/* Read the eDP 1.4+ supported link rates. */
if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
__le16 sink_rates[DP_MAX_SUPPORTED_RATES];
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 8fe6d2f9ab2b..61ade81576f5 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -252,9 +252,13 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
if (!intel_dp->psr_dpcd[0])
return;
-
DRM_DEBUG_KMS("eDP panel supports PSR version %x\n",
intel_dp->psr_dpcd[0]);
+
+ if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) {
+ DRM_DEBUG_KMS("Panel lacks power state control, PSR cannot be enabled\n");
+ return;
+ }
dev_priv->psr.sink_support = true;
if (INTEL_GEN(dev_priv) >= 9 &&
@@ -642,11 +646,6 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
return;
}
- if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) {
- DRM_DEBUG_KMS("PSR condition failed: panel lacks power state control\n");
- return;
- }
-
crtc_state->has_psr = true;
crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state);
DRM_DEBUG_KMS("Enabling PSR%s\n", crtc_state->has_psr2 ? "2" : "");
--
2.14.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 3/6] drm/psr: Fix missed entry in PSR setup time table.
2018-05-11 19:51 [PATCH 1/6] drm/i915/psr: Avoid DPCD reads when panel does not support PSR Dhinakaran Pandiyan
2018-05-11 19:51 ` [PATCH 2/6] drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time Dhinakaran Pandiyan
@ 2018-05-11 19:51 ` Dhinakaran Pandiyan
2018-05-24 14:00 ` Jani Nikula
2018-05-11 19:51 ` [PATCH 4/6] drm/i915/psr: Avoid unnecessary DPCD read of DP_PSR_CAPS Dhinakaran Pandiyan
` (6 subsequent siblings)
8 siblings, 1 reply; 23+ messages in thread
From: Dhinakaran Pandiyan @ 2018-05-11 19:51 UTC (permalink / raw)
To: intel-gfx
Cc: Dhinakaran Pandiyan, stable, Ville Syrjälä,
Jose Roberto de Souza, dri-devel
Entry corresponding to 220 us setup time was missing. I am not aware of
any specific bug this fixes, but this could potentially result in enabling
PSR on a panel with a higher setup time requirement than supported by the
hardware.
I verified the value is present in eDP spec versions 1.3, 1.4 and 1.4a.
Fixes: 6608804b3d7f ("drm/dp: Add drm_dp_psr_setup_time()")
Cc: stable@vger.kernel.org
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Jose Roberto de Souza <jose.souza@intel.com>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
---
drivers/gpu/drm/drm_dp_helper.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 36c7609a4bd5..a7ba602a43a8 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -1159,6 +1159,7 @@ int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE])
static const u16 psr_setup_time_us[] = {
PSR_SETUP_TIME(330),
PSR_SETUP_TIME(275),
+ PSR_SETUP_TIME(220),
PSR_SETUP_TIME(165),
PSR_SETUP_TIME(110),
PSR_SETUP_TIME(55),
--
2.14.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 4/6] drm/i915/psr: Avoid unnecessary DPCD read of DP_PSR_CAPS
2018-05-11 19:51 [PATCH 1/6] drm/i915/psr: Avoid DPCD reads when panel does not support PSR Dhinakaran Pandiyan
2018-05-11 19:51 ` [PATCH 2/6] drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time Dhinakaran Pandiyan
2018-05-11 19:51 ` [PATCH 3/6] drm/psr: Fix missed entry in PSR setup time table Dhinakaran Pandiyan
@ 2018-05-11 19:51 ` Dhinakaran Pandiyan
2018-05-20 23:01 ` Tarun Vyas
2018-05-22 12:32 ` Nagaraju, Vathsala
2018-05-11 19:51 ` [PATCH 5/6] drm/i915/psr: Fall back to max. synchronization latency if DPCD read fails Dhinakaran Pandiyan
` (5 subsequent siblings)
8 siblings, 2 replies; 23+ messages in thread
From: Dhinakaran Pandiyan @ 2018-05-11 19:51 UTC (permalink / raw)
To: intel-gfx; +Cc: Dhinakaran Pandiyan
intel_dp->psr_dpcd already has the required values.
Cc: Jose Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
---
drivers/gpu/drm/i915/intel_psr.c | 11 +----------
1 file changed, 1 insertion(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 61ade81576f5..381dbdbf30f4 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -201,15 +201,6 @@ void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir)
}
}
-static bool intel_dp_get_y_coord_required(struct intel_dp *intel_dp)
-{
- uint8_t psr_caps = 0;
-
- if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_CAPS, &psr_caps) != 1)
- return false;
- return psr_caps & DP_PSR2_SU_Y_COORDINATE_REQUIRED;
-}
-
static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
{
uint8_t dprx = 0;
@@ -275,7 +266,7 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
* GTC first.
*/
dev_priv->psr.sink_psr2_support =
- intel_dp_get_y_coord_required(intel_dp);
+ intel_dp->psr_dpcd[1] & DP_PSR2_SU_Y_COORDINATE_REQUIRED;
DRM_DEBUG_KMS("PSR2 %ssupported\n",
dev_priv->psr.sink_psr2_support ? "" : "not ");
--
2.14.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 5/6] drm/i915/psr: Fall back to max. synchronization latency if DPCD read fails
2018-05-11 19:51 [PATCH 1/6] drm/i915/psr: Avoid DPCD reads when panel does not support PSR Dhinakaran Pandiyan
` (2 preceding siblings ...)
2018-05-11 19:51 ` [PATCH 4/6] drm/i915/psr: Avoid unnecessary DPCD read of DP_PSR_CAPS Dhinakaran Pandiyan
@ 2018-05-11 19:51 ` Dhinakaran Pandiyan
2018-05-21 23:58 ` Souza, Jose
2018-05-11 19:51 ` [PATCH 6/6] drm/i915/psr: Fix ALPM cap check for PSR2 Dhinakaran Pandiyan
` (4 subsequent siblings)
8 siblings, 1 reply; 23+ messages in thread
From: Dhinakaran Pandiyan @ 2018-05-11 19:51 UTC (permalink / raw)
To: intel-gfx; +Cc: Dhinakaran Pandiyan
Noticed that we assume the best case of 0 latency when the DPCD read
fails, reasonable pessimism is safer.
eDP spec does say that if latency is greater than 8, the panel
supplier needs to provide it. I didn't see anything specific in the VBT
for this, so let's go with 8 frames as a fallback.
Cc: Jose Roberto de Souza <jose.souza@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
---
drivers/gpu/drm/i915/intel_psr.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 381dbdbf30f4..b4a4f5d3a2bb 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -223,13 +223,13 @@ static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp)
static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp)
{
- u8 val = 0;
+ u8 val = 8; /* assume the worst if we can't read the value */
if (drm_dp_dpcd_readb(&intel_dp->aux,
DP_SYNCHRONIZATION_LATENCY_IN_SINK, &val) == 1)
val &= DP_MAX_RESYNC_FRAME_COUNT_MASK;
else
- DRM_ERROR("Unable to get sink synchronization latency\n");
+ DRM_DEBUG_KMS("Unable to get sink synchronization latency, assuming 8 frames\n");
return val;
}
--
2.14.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 6/6] drm/i915/psr: Fix ALPM cap check for PSR2
2018-05-11 19:51 [PATCH 1/6] drm/i915/psr: Avoid DPCD reads when panel does not support PSR Dhinakaran Pandiyan
` (3 preceding siblings ...)
2018-05-11 19:51 ` [PATCH 5/6] drm/i915/psr: Fall back to max. synchronization latency if DPCD read fails Dhinakaran Pandiyan
@ 2018-05-11 19:51 ` Dhinakaran Pandiyan
2018-05-22 9:33 ` Nagaraju, Vathsala
2018-05-22 14:37 ` Tarun Vyas
2018-05-11 20:26 ` ✓ Fi.CI.BAT: success for series starting with [1/6] drm/i915/psr: Avoid DPCD reads when panel does not support PSR Patchwork
` (3 subsequent siblings)
8 siblings, 2 replies; 23+ messages in thread
From: Dhinakaran Pandiyan @ 2018-05-11 19:51 UTC (permalink / raw)
To: intel-gfx; +Cc: Dhinakaran Pandiyan
While touching the code around this, I noticed that absence of ALPM
capability does not stop us from enabling PSR2. But, the spec
unambiguously states that ALPM is required for PSR2 and so does this
commit that introduced this code
drm/i915/psr: enable ALPM for psr2
As per edp1.4 spec , alpm is required for psr2 operation as it's
used for all psr2 main link power down management and alpm enable
bit must be set for psr2 operation.
Cc: Jose Roberto de Souza <jose.souza@intel.com>
Cc: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
---
drivers/gpu/drm/i915/intel_psr.c | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index b4a4f5d3a2bb..92abf61e234c 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -254,6 +254,10 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
if (INTEL_GEN(dev_priv) >= 9 &&
(intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) {
+ bool y_req = intel_dp->psr_dpcd[1] &
+ DP_PSR2_SU_Y_COORDINATE_REQUIRED;
+ bool alpm = intel_dp_get_alpm_status(intel_dp);
+
/*
* All panels that supports PSR version 03h (PSR2 +
* Y-coordinate) can handle Y-coordinates in VSC but we are
@@ -265,16 +269,13 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
* Y-coordinate requirement panels we would need to enable
* GTC first.
*/
- dev_priv->psr.sink_psr2_support =
- intel_dp->psr_dpcd[1] & DP_PSR2_SU_Y_COORDINATE_REQUIRED;
+ dev_priv->psr.sink_psr2_support = y_req && alpm;
DRM_DEBUG_KMS("PSR2 %ssupported\n",
dev_priv->psr.sink_psr2_support ? "" : "not ");
if (dev_priv->psr.sink_psr2_support) {
dev_priv->psr.colorimetry_support =
intel_dp_get_colorimetry_status(intel_dp);
- dev_priv->psr.alpm =
- intel_dp_get_alpm_status(intel_dp);
dev_priv->psr.sink_sync_latency =
intel_dp_get_sink_sync_latency(intel_dp);
}
@@ -386,13 +387,12 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
u8 dpcd_val = DP_PSR_ENABLE;
/* Enable ALPM at sink for psr2 */
- if (dev_priv->psr.psr2_enabled && dev_priv->psr.alpm)
- drm_dp_dpcd_writeb(&intel_dp->aux,
- DP_RECEIVER_ALPM_CONFIG,
- DP_ALPM_ENABLE);
-
- if (dev_priv->psr.psr2_enabled)
+ if (dev_priv->psr.psr2_enabled) {
+ drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG,
+ DP_ALPM_ENABLE);
dpcd_val |= DP_PSR_ENABLE_PSR2;
+ }
+
if (dev_priv->psr.link_standby)
dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val);
--
2.14.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 23+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/6] drm/i915/psr: Avoid DPCD reads when panel does not support PSR
2018-05-11 19:51 [PATCH 1/6] drm/i915/psr: Avoid DPCD reads when panel does not support PSR Dhinakaran Pandiyan
` (4 preceding siblings ...)
2018-05-11 19:51 ` [PATCH 6/6] drm/i915/psr: Fix ALPM cap check for PSR2 Dhinakaran Pandiyan
@ 2018-05-11 20:26 ` Patchwork
2018-05-11 21:17 ` ✓ Fi.CI.IGT: " Patchwork
` (2 subsequent siblings)
8 siblings, 0 replies; 23+ messages in thread
From: Patchwork @ 2018-05-11 20:26 UTC (permalink / raw)
To: Dhinakaran Pandiyan; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/6] drm/i915/psr: Avoid DPCD reads when panel does not support PSR
URL : https://patchwork.freedesktop.org/series/43077/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4171 -> Patchwork_8984 =
== Summary - SUCCESS ==
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/43077/revisions/1/mbox/
== Known issues ==
Here are the changes found in Patchwork_8984 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@gem_mmap_gtt@basic-small-bo-tiledx:
fi-gdg-551: PASS -> FAIL (fdo#102575)
igt@prime_vgem@basic-fence-flip:
fi-ilk-650: PASS -> FAIL (fdo#104008)
==== Possible fixes ====
igt@kms_chamelium@hdmi-hpd-fast:
fi-kbl-7500u: FAIL (fdo#103841, fdo#102672) -> SKIP
igt@kms_psr_sink_crc@psr_basic:
fi-hsw-4200u: FAIL (fdo#106346, fdo#106217) -> SKIP
fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#102672 https://bugs.freedesktop.org/show_bug.cgi?id=102672
fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841
fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008
fdo#106217 https://bugs.freedesktop.org/show_bug.cgi?id=106217
fdo#106346 https://bugs.freedesktop.org/show_bug.cgi?id=106346
== Participating hosts (40 -> 36) ==
Missing (4): fi-byt-squawks fi-ilk-m540 fi-glk-j4005 fi-skl-6700hq
== Build changes ==
* Linux: CI_DRM_4171 -> Patchwork_8984
CI_DRM_4171: fe5bde58dca53de7b615789c69ed83c6420d2d1a @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4475: 35f08c12aa216d5b62a5b9984b575cee6905098f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_8984: cab2345fd9aa55acc479cc25b17c0e645468479b @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4475: 3ba0657bff4216d1ec7179935590261855f1651e @ git://anongit.freedesktop.org/piglit
== Linux commits ==
cab2345fd9aa drm/i915/psr: Fix ALPM cap check for PSR2
13d41863da93 drm/i915/psr: Fall back to max. synchronization latency if DPCD read fails
dc111208ecd5 drm/i915/psr: Avoid unnecessary DPCD read of DP_PSR_CAPS
f160ad9e30c7 drm/psr: Fix missed entry in PSR setup time table.
96bdaf78241d drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time.
003211c1b5af drm/i915/psr: Avoid DPCD reads when panel does not support PSR
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8984/issues.html
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 23+ messages in thread
* ✓ Fi.CI.IGT: success for series starting with [1/6] drm/i915/psr: Avoid DPCD reads when panel does not support PSR
2018-05-11 19:51 [PATCH 1/6] drm/i915/psr: Avoid DPCD reads when panel does not support PSR Dhinakaran Pandiyan
` (5 preceding siblings ...)
2018-05-11 20:26 ` ✓ Fi.CI.BAT: success for series starting with [1/6] drm/i915/psr: Avoid DPCD reads when panel does not support PSR Patchwork
@ 2018-05-11 21:17 ` Patchwork
2018-05-18 0:27 ` [PATCH 1/6] " Tarun Vyas
2018-05-22 12:29 ` Nagaraju, Vathsala
8 siblings, 0 replies; 23+ messages in thread
From: Patchwork @ 2018-05-11 21:17 UTC (permalink / raw)
To: Dhinakaran Pandiyan; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/6] drm/i915/psr: Avoid DPCD reads when panel does not support PSR
URL : https://patchwork.freedesktop.org/series/43077/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4171_full -> Patchwork_8984_full =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_8984_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_8984_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/43077/revisions/1/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_8984_full:
=== IGT changes ===
==== Warnings ====
igt@gem_mocs_settings@mocs-rc6-vebox:
shard-kbl: PASS -> SKIP +2
igt@gem_pwrite@big-cpu-random:
shard-apl: PASS -> SKIP
== Known issues ==
Here are the changes found in Patchwork_8984_full that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@gem_ppgtt@blt-vs-render-ctx0:
shard-kbl: PASS -> INCOMPLETE (fdo#103665, fdo#106023)
igt@kms_flip@2x-wf_vblank-ts-check:
shard-hsw: PASS -> FAIL (fdo#103928)
igt@kms_flip@plain-flip-ts-check-interruptible:
shard-glk: PASS -> FAIL (fdo#100368) +1
==== Possible fixes ====
igt@gem_exec_await@wide-contexts:
shard-apl: DMESG-FAIL -> PASS
igt@gem_ppgtt@blt-vs-render-ctxn:
shard-kbl: INCOMPLETE (fdo#103665, fdo#106023) -> PASS
igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible:
shard-hsw: FAIL (fdo#103928) -> PASS
igt@kms_flip@flip-vs-expired-vblank-interruptible:
shard-glk: FAIL (fdo#105363, fdo#102887) -> PASS
igt@kms_sysfs_edid_timing:
shard-apl: WARN (fdo#100047) -> PASS
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
fdo#103928 https://bugs.freedesktop.org/show_bug.cgi?id=103928
fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023
== Participating hosts (5 -> 5) ==
No changes in participating hosts
== Build changes ==
* Linux: CI_DRM_4171 -> Patchwork_8984
CI_DRM_4171: fe5bde58dca53de7b615789c69ed83c6420d2d1a @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4475: 35f08c12aa216d5b62a5b9984b575cee6905098f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_8984: cab2345fd9aa55acc479cc25b17c0e645468479b @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4475: 3ba0657bff4216d1ec7179935590261855f1651e @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8984/shards.html
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 2/6] drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time.
2018-05-11 19:51 ` [PATCH 2/6] drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time Dhinakaran Pandiyan
@ 2018-05-11 22:14 ` Dhinakaran Pandiyan
2018-05-24 13:28 ` Jani Nikula
0 siblings, 1 reply; 23+ messages in thread
From: Dhinakaran Pandiyan @ 2018-05-11 22:14 UTC (permalink / raw)
To: intel-gfx
On Fri, 2018-05-11 at 12:51 -0700, Dhinakaran Pandiyan wrote:
> By moving the check from psr_compute_config() to psr_init_dpcd(), we
> get
> to set the dev_priv->psr.sink_support flag only when the panel is
> capable of changing power state. An additional benefit is that the
> check
> will be performed only at init time instead of every atomic_check.
>
> This should change the psr_basic IGT failures on HSW to skips.
>
> v2: Return early when SET_POWER_CAPABLE bit is 0 (Jose)
>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106217
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106346
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 8 ++++++--
> drivers/gpu/drm/i915/intel_psr.c | 11 +++++------
> 2 files changed, 11 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c
> b/drivers/gpu/drm/i915/intel_dp.c
> index dde92e4af5d3..cfd95eaa0d0d 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3762,8 +3762,6 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
> dev_priv->no_aux_handshake = intel_dp-
> >dpcd[DP_MAX_DOWNSPREAD] &
> DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
>
> - intel_psr_init_dpcd(intel_dp);
> -
> /*
> * Read the eDP display control registers.
> *
> @@ -3779,6 +3777,12 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
> DRM_DEBUG_KMS("eDP DPCD: %*ph\n", (int)
> sizeof(intel_dp->edp_dpcd),
> intel_dp->edp_dpcd);
>
> + /*
> + * This has to be called after intel_dp->edp_dpcd is filled,
> PSR checks
> + * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
> + */
> + intel_psr_init_dpcd(intel_dp);
> +
> /* Read the eDP 1.4+ supported link rates. */
> if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
> __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
> index 8fe6d2f9ab2b..61ade81576f5 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -252,9 +252,13 @@ void intel_psr_init_dpcd(struct intel_dp
> *intel_dp)
>
> if (!intel_dp->psr_dpcd[0])
> return;
> -
> DRM_DEBUG_KMS("eDP panel supports PSR version %x\n",
> intel_dp->psr_dpcd[0]);
> +
> + if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) {
> + DRM_DEBUG_KMS("Panel lacks power state control, PSR
> cannot be enabled\n");
> + return;
> + }
> dev_priv->psr.sink_support = true;
>
> if (INTEL_GEN(dev_priv) >= 9 &&
> @@ -642,11 +646,6 @@ void intel_psr_compute_config(struct intel_dp
> *intel_dp,
> return;
> }
>
> - if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) {
> - DRM_DEBUG_KMS("PSR condition failed: panel lacks
> power state control\n");
> - return;
> - }
> -
> crtc_state->has_psr = true;
> crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp,
> crtc_state);
> DRM_DEBUG_KMS("Enabling PSR%s\n", crtc_state->has_psr2 ? "2"
> : "");
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 1/6] drm/i915/psr: Avoid DPCD reads when panel does not support PSR
2018-05-11 19:51 [PATCH 1/6] drm/i915/psr: Avoid DPCD reads when panel does not support PSR Dhinakaran Pandiyan
` (6 preceding siblings ...)
2018-05-11 21:17 ` ✓ Fi.CI.IGT: " Patchwork
@ 2018-05-18 0:27 ` Tarun Vyas
2018-05-21 23:40 ` Dhinakaran Pandiyan
2018-05-24 13:29 ` Jani Nikula
2018-05-22 12:29 ` Nagaraju, Vathsala
8 siblings, 2 replies; 23+ messages in thread
From: Tarun Vyas @ 2018-05-18 0:27 UTC (permalink / raw)
To: Dhinakaran Pandiyan; +Cc: intel-gfx
On Fri, May 11, 2018 at 12:51:40PM -0700, Dhinakaran Pandiyan wrote:
> Ville noticed that we are unncessarily reading DPCD's after knowing
> panel did not support PSR. Looks like this check that was present
> earlier got removed unintentionally, let's put it back.
>
> While we do this, add the PSR version number in the debug print.
>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> ---
> drivers/gpu/drm/i915/intel_psr.c | 14 ++++++++------
> 1 file changed, 8 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index db27f2faa1de..8fe6d2f9ab2b 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -250,10 +250,12 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
> drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
> sizeof(intel_dp->psr_dpcd));
>
> - if (intel_dp->psr_dpcd[0]) {
> - dev_priv->psr.sink_support = true;
> - DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
> - }
> + if (!intel_dp->psr_dpcd[0])
> + return;
> +
> + DRM_DEBUG_KMS("eDP panel supports PSR version %x\n",
> + intel_dp->psr_dpcd[0]);
> + dev_priv->psr.sink_support = true;
>
> if (INTEL_GEN(dev_priv) >= 9 &&
> (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) {
> @@ -270,8 +272,8 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
> */
> dev_priv->psr.sink_psr2_support =
> intel_dp_get_y_coord_required(intel_dp);
> - DRM_DEBUG_KMS("PSR2 %s on sink", dev_priv->psr.sink_psr2_support
> - ? "supported" : "not supported");
> + DRM_DEBUG_KMS("PSR2 %ssupported\n",
> + dev_priv->psr.sink_psr2_support ? "" : "not ");
Would it make sense to make it clearer that PSR2 is not supported b/c of lack of y-coordinate support on the sink ?
Reviewed-by: Tarun Vyas <tarun.vyas@intel.com>
>
> if (dev_priv->psr.sink_psr2_support) {
> dev_priv->psr.colorimetry_support =
> --
> 2.14.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 4/6] drm/i915/psr: Avoid unnecessary DPCD read of DP_PSR_CAPS
2018-05-11 19:51 ` [PATCH 4/6] drm/i915/psr: Avoid unnecessary DPCD read of DP_PSR_CAPS Dhinakaran Pandiyan
@ 2018-05-20 23:01 ` Tarun Vyas
2018-05-24 14:01 ` Jani Nikula
2018-05-22 12:32 ` Nagaraju, Vathsala
1 sibling, 1 reply; 23+ messages in thread
From: Tarun Vyas @ 2018-05-20 23:01 UTC (permalink / raw)
To: Dhinakaran Pandiyan; +Cc: intel-gfx
On Fri, May 11, 2018 at 12:51:43PM -0700, Dhinakaran Pandiyan wrote:
> intel_dp->psr_dpcd already has the required values.
>
> Cc: Jose Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> ---
> drivers/gpu/drm/i915/intel_psr.c | 11 +----------
> 1 file changed, 1 insertion(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 61ade81576f5..381dbdbf30f4 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -201,15 +201,6 @@ void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir)
> }
> }
>
> -static bool intel_dp_get_y_coord_required(struct intel_dp *intel_dp)
> -{
> - uint8_t psr_caps = 0;
> -
> - if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_CAPS, &psr_caps) != 1)
> - return false;
> - return psr_caps & DP_PSR2_SU_Y_COORDINATE_REQUIRED;
> -}
> -
> static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
> {
> uint8_t dprx = 0;
> @@ -275,7 +266,7 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
> * GTC first.
> */
> dev_priv->psr.sink_psr2_support =
> - intel_dp_get_y_coord_required(intel_dp);
> + intel_dp->psr_dpcd[1] & DP_PSR2_SU_Y_COORDINATE_REQUIRED;
> DRM_DEBUG_KMS("PSR2 %ssupported\n",
> dev_priv->psr.sink_psr2_support ? "" : "not ");
The drm_dp_dpcd_read itself reads the first 2 PSR DPCD bytes which is what is needed. Also, no other callers of intel_dp_get_y_coord_required exist. So,
Reviewed-by: Tarun Vyas <tarun.vyas@intel.com>
>
> --
> 2.14.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 1/6] drm/i915/psr: Avoid DPCD reads when panel does not support PSR
2018-05-18 0:27 ` [PATCH 1/6] " Tarun Vyas
@ 2018-05-21 23:40 ` Dhinakaran Pandiyan
2018-05-24 13:29 ` Jani Nikula
1 sibling, 0 replies; 23+ messages in thread
From: Dhinakaran Pandiyan @ 2018-05-21 23:40 UTC (permalink / raw)
To: Tarun Vyas; +Cc: intel-gfx
On Thu, 2018-05-17 at 17:27 -0700, Tarun Vyas wrote:
> On Fri, May 11, 2018 at 12:51:40PM -0700, Dhinakaran Pandiyan wrote:
> >
> > Ville noticed that we are unncessarily reading DPCD's after knowing
> > panel did not support PSR. Looks like this check that was present
> > earlier got removed unintentionally, let's put it back.
> >
> > While we do this, add the PSR version number in the debug print.
> >
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_psr.c | 14 ++++++++------
> > 1 file changed, 8 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_psr.c
> > b/drivers/gpu/drm/i915/intel_psr.c
> > index db27f2faa1de..8fe6d2f9ab2b 100644
> > --- a/drivers/gpu/drm/i915/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > @@ -250,10 +250,12 @@ void intel_psr_init_dpcd(struct intel_dp
> > *intel_dp)
> > drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp-
> > >psr_dpcd,
> > sizeof(intel_dp->psr_dpcd));
> >
> > - if (intel_dp->psr_dpcd[0]) {
> > - dev_priv->psr.sink_support = true;
> > - DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
> > - }
> > + if (!intel_dp->psr_dpcd[0])
> > + return;
> > +
> > + DRM_DEBUG_KMS("eDP panel supports PSR version %x\n",
> > + intel_dp->psr_dpcd[0]);
> > + dev_priv->psr.sink_support = true;
> >
> > if (INTEL_GEN(dev_priv) >= 9 &&
> > (intel_dp->psr_dpcd[0] ==
> > DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) {
> > @@ -270,8 +272,8 @@ void intel_psr_init_dpcd(struct intel_dp
> > *intel_dp)
> > */
> > dev_priv->psr.sink_psr2_support =
> > intel_dp_get_y_coord_required(inte
> > l_dp);
> > - DRM_DEBUG_KMS("PSR2 %s on sink", dev_priv-
> > >psr.sink_psr2_support
> > - ? "supported" : "not supported");
> > + DRM_DEBUG_KMS("PSR2 %ssupported\n",
> > + dev_priv->psr.sink_psr2_support ? ""
> > : "not ");
> Would it make sense to make it clearer that PSR2 is not supported b/c
> of lack of y-coordinate support on the sink ?
We could do something like
dev_priv->psr.sink_psr2_support = y_req && alpm;
DRM_DEBUG_KMS("PSR2 %ssupported ALPM %d Y-req %d\n",
dev_priv->psr.sink_psr2_support ? "" : "not ",
alpm, y_req);
But this would need the code movement done in patch 6/6.
>
> Reviewed-by: Tarun Vyas <tarun.vyas@intel.com>
> >
> >
> > if (dev_priv->psr.sink_psr2_support) {
> > dev_priv->psr.colorimetry_support =
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^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 5/6] drm/i915/psr: Fall back to max. synchronization latency if DPCD read fails
2018-05-11 19:51 ` [PATCH 5/6] drm/i915/psr: Fall back to max. synchronization latency if DPCD read fails Dhinakaran Pandiyan
@ 2018-05-21 23:58 ` Souza, Jose
0 siblings, 0 replies; 23+ messages in thread
From: Souza, Jose @ 2018-05-21 23:58 UTC (permalink / raw)
To: intel-gfx, Pandiyan, Dhinakaran
On Fri, 2018-05-11 at 12:51 -0700, Dhinakaran Pandiyan wrote:
> Noticed that we assume the best case of 0 latency when the DPCD read
> fails, reasonable pessimism is safer.
>
> eDP spec does say that if latency is greater than 8, the panel
> supplier needs to provide it. I didn't see anything specific in the
> VBT
> for this, so let's go with 8 frames as a fallback.
>
> Cc: Jose Roberto de Souza <jose.souza@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> ---
> drivers/gpu/drm/i915/intel_psr.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
> index 381dbdbf30f4..b4a4f5d3a2bb 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -223,13 +223,13 @@ static bool intel_dp_get_alpm_status(struct
> intel_dp *intel_dp)
>
> static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp)
> {
> - u8 val = 0;
> + u8 val = 8; /* assume the worst if we can't read the value
> */
>
> if (drm_dp_dpcd_readb(&intel_dp->aux,
> DP_SYNCHRONIZATION_LATENCY_IN_SINK,
> &val) == 1)
> val &= DP_MAX_RESYNC_FRAME_COUNT_MASK;
> else
> - DRM_ERROR("Unable to get sink synchronization
> latency\n");
> + DRM_DEBUG_KMS("Unable to get sink synchronization
> latency, assuming 8 frames\n");
Maybe have this at least as a warning.
> return val;
> }
>
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^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 6/6] drm/i915/psr: Fix ALPM cap check for PSR2
2018-05-11 19:51 ` [PATCH 6/6] drm/i915/psr: Fix ALPM cap check for PSR2 Dhinakaran Pandiyan
@ 2018-05-22 9:33 ` Nagaraju, Vathsala
2018-05-22 14:37 ` Tarun Vyas
1 sibling, 0 replies; 23+ messages in thread
From: Nagaraju, Vathsala @ 2018-05-22 9:33 UTC (permalink / raw)
To: Dhinakaran Pandiyan, intel-gfx
On 5/12/2018 1:21 AM, Dhinakaran Pandiyan wrote:
> While touching the code around this, I noticed that absence of ALPM
> capability does not stop us from enabling PSR2. But, the spec
> unambiguously states that ALPM is required for PSR2 and so does this
> commit that introduced this code
>
> drm/i915/psr: enable ALPM for psr2
>
> As per edp1.4 spec , alpm is required for psr2 operation as it's
> used for all psr2 main link power down management and alpm enable
> bit must be set for psr2 operation.
>
> Cc: Jose Roberto de Souza <jose.souza@intel.com>
> Cc: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> ---
> drivers/gpu/drm/i915/intel_psr.c | 20 ++++++++++----------
> 1 file changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index b4a4f5d3a2bb..92abf61e234c 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -254,6 +254,10 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
>
> if (INTEL_GEN(dev_priv) >= 9 &&
> (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) {
> + bool y_req = intel_dp->psr_dpcd[1] &
> + DP_PSR2_SU_Y_COORDINATE_REQUIRED;
> + bool alpm = intel_dp_get_alpm_status(intel_dp);
> +
> /*
> * All panels that supports PSR version 03h (PSR2 +
> * Y-coordinate) can handle Y-coordinates in VSC but we are
> @@ -265,16 +269,13 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
> * Y-coordinate requirement panels we would need to enable
> * GTC first.
> */
> - dev_priv->psr.sink_psr2_support =
> - intel_dp->psr_dpcd[1] & DP_PSR2_SU_Y_COORDINATE_REQUIRED;
> + dev_priv->psr.sink_psr2_support = y_req && alpm;
> DRM_DEBUG_KMS("PSR2 %ssupported\n",
> dev_priv->psr.sink_psr2_support ? "" : "not ");
>
> if (dev_priv->psr.sink_psr2_support) {
> dev_priv->psr.colorimetry_support =
> intel_dp_get_colorimetry_status(intel_dp);
> - dev_priv->psr.alpm =
> - intel_dp_get_alpm_status(intel_dp);
> dev_priv->psr.sink_sync_latency =
> intel_dp_get_sink_sync_latency(intel_dp);
> }
> @@ -386,13 +387,12 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
> u8 dpcd_val = DP_PSR_ENABLE;
>
> /* Enable ALPM at sink for psr2 */
> - if (dev_priv->psr.psr2_enabled && dev_priv->psr.alpm)
> - drm_dp_dpcd_writeb(&intel_dp->aux,
> - DP_RECEIVER_ALPM_CONFIG,
> - DP_ALPM_ENABLE);
> -
> - if (dev_priv->psr.psr2_enabled)
> + if (dev_priv->psr.psr2_enabled) {
> + drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG,
> + DP_ALPM_ENABLE);
> dpcd_val |= DP_PSR_ENABLE_PSR2;
> + }
ALPM is needed for fast wake.
Reviewed-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> +
> if (dev_priv->psr.link_standby)
> dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
> drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val);
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^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 1/6] drm/i915/psr: Avoid DPCD reads when panel does not support PSR
2018-05-11 19:51 [PATCH 1/6] drm/i915/psr: Avoid DPCD reads when panel does not support PSR Dhinakaran Pandiyan
` (7 preceding siblings ...)
2018-05-18 0:27 ` [PATCH 1/6] " Tarun Vyas
@ 2018-05-22 12:29 ` Nagaraju, Vathsala
8 siblings, 0 replies; 23+ messages in thread
From: Nagaraju, Vathsala @ 2018-05-22 12:29 UTC (permalink / raw)
To: Dhinakaran Pandiyan, intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 1925 bytes --]
On 5/12/2018 1:21 AM, Dhinakaran Pandiyan wrote:
> Ville noticed that we are unncessarily reading DPCD's after knowing
> panel did not support PSR. Looks like this check that was present
> earlier got removed unintentionally, let's put it back.
>
> While we do this, add the PSR version number in the debug print.
>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> ---
> drivers/gpu/drm/i915/intel_psr.c | 14 ++++++++------
> 1 file changed, 8 insertions(+), 6 deletions(-)
Reviewed-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
>
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index db27f2faa1de..8fe6d2f9ab2b 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -250,10 +250,12 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
> drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
> sizeof(intel_dp->psr_dpcd));
>
> - if (intel_dp->psr_dpcd[0]) {
> - dev_priv->psr.sink_support = true;
> - DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
> - }
> + if (!intel_dp->psr_dpcd[0])
> + return;
> +
> + DRM_DEBUG_KMS("eDP panel supports PSR version %x\n",
> + intel_dp->psr_dpcd[0]);
> + dev_priv->psr.sink_support = true;
>
> if (INTEL_GEN(dev_priv) >= 9 &&
> (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) {
> @@ -270,8 +272,8 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
> */
> dev_priv->psr.sink_psr2_support =
> intel_dp_get_y_coord_required(intel_dp);
> - DRM_DEBUG_KMS("PSR2 %s on sink", dev_priv->psr.sink_psr2_support
> - ? "supported" : "not supported");
> + DRM_DEBUG_KMS("PSR2 %ssupported\n",
> + dev_priv->psr.sink_psr2_support ? "" : "not ");
>
> if (dev_priv->psr.sink_psr2_support) {
> dev_priv->psr.colorimetry_support =
[-- Attachment #1.2: Type: text/html, Size: 2684 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
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^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 4/6] drm/i915/psr: Avoid unnecessary DPCD read of DP_PSR_CAPS
2018-05-11 19:51 ` [PATCH 4/6] drm/i915/psr: Avoid unnecessary DPCD read of DP_PSR_CAPS Dhinakaran Pandiyan
2018-05-20 23:01 ` Tarun Vyas
@ 2018-05-22 12:32 ` Nagaraju, Vathsala
1 sibling, 0 replies; 23+ messages in thread
From: Nagaraju, Vathsala @ 2018-05-22 12:32 UTC (permalink / raw)
To: Dhinakaran Pandiyan, intel-gfx
On 5/12/2018 1:21 AM, Dhinakaran Pandiyan wrote:
> intel_dp->psr_dpcd already has the required values.
>
> Cc: Jose Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> ---
> drivers/gpu/drm/i915/intel_psr.c | 11 +----------
> 1 file changed, 1 insertion(+), 10 deletions(-)
Reviewed-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 61ade81576f5..381dbdbf30f4 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -201,15 +201,6 @@ void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir)
> }
> }
>
> -static bool intel_dp_get_y_coord_required(struct intel_dp *intel_dp)
> -{
> - uint8_t psr_caps = 0;
> -
> - if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_CAPS, &psr_caps) != 1)
> - return false;
> - return psr_caps & DP_PSR2_SU_Y_COORDINATE_REQUIRED;
> -}
> -
> static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
> {
> uint8_t dprx = 0;
> @@ -275,7 +266,7 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
> * GTC first.
> */
> dev_priv->psr.sink_psr2_support =
> - intel_dp_get_y_coord_required(intel_dp);
> + intel_dp->psr_dpcd[1] & DP_PSR2_SU_Y_COORDINATE_REQUIRED;
> DRM_DEBUG_KMS("PSR2 %ssupported\n",
> dev_priv->psr.sink_psr2_support ? "" : "not ");
>
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^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 6/6] drm/i915/psr: Fix ALPM cap check for PSR2
2018-05-11 19:51 ` [PATCH 6/6] drm/i915/psr: Fix ALPM cap check for PSR2 Dhinakaran Pandiyan
2018-05-22 9:33 ` Nagaraju, Vathsala
@ 2018-05-22 14:37 ` Tarun Vyas
2018-05-22 20:21 ` Dhinakaran Pandiyan
1 sibling, 1 reply; 23+ messages in thread
From: Tarun Vyas @ 2018-05-22 14:37 UTC (permalink / raw)
To: Dhinakaran Pandiyan; +Cc: intel-gfx
On Fri, May 11, 2018 at 12:51:45PM -0700, Dhinakaran Pandiyan wrote:
> While touching the code around this, I noticed that absence of ALPM
> capability does not stop us from enabling PSR2. But, the spec
> unambiguously states that ALPM is required for PSR2 and so does this
> commit that introduced this code
>
> drm/i915/psr: enable ALPM for psr2
>
> As per edp1.4 spec , alpm is required for psr2 operation as it's
> used for all psr2 main link power down management and alpm enable
> bit must be set for psr2 operation.
>
Since, the code introduced by "drm/i915/psr: enable ALPM for psr2" enables PSR2 even if ALPM isn't supported, can we add the "Fixes" tag here ? Rest looks good.
Reviewed-by: Tarun Vyas <tarun.vyas@intel.com>
> Cc: Jose Roberto de Souza <jose.souza@intel.com>
> Cc: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> ---
> drivers/gpu/drm/i915/intel_psr.c | 20 ++++++++++----------
> 1 file changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index b4a4f5d3a2bb..92abf61e234c 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -254,6 +254,10 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
>
> if (INTEL_GEN(dev_priv) >= 9 &&
> (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) {
> + bool y_req = intel_dp->psr_dpcd[1] &
> + DP_PSR2_SU_Y_COORDINATE_REQUIRED;
> + bool alpm = intel_dp_get_alpm_status(intel_dp);
> +
> /*
> * All panels that supports PSR version 03h (PSR2 +
> * Y-coordinate) can handle Y-coordinates in VSC but we are
> @@ -265,16 +269,13 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
> * Y-coordinate requirement panels we would need to enable
> * GTC first.
> */
> - dev_priv->psr.sink_psr2_support =
> - intel_dp->psr_dpcd[1] & DP_PSR2_SU_Y_COORDINATE_REQUIRED;
> + dev_priv->psr.sink_psr2_support = y_req && alpm;
> DRM_DEBUG_KMS("PSR2 %ssupported\n",
> dev_priv->psr.sink_psr2_support ? "" : "not ");
>
> if (dev_priv->psr.sink_psr2_support) {
> dev_priv->psr.colorimetry_support =
> intel_dp_get_colorimetry_status(intel_dp);
> - dev_priv->psr.alpm =
> - intel_dp_get_alpm_status(intel_dp);
> dev_priv->psr.sink_sync_latency =
> intel_dp_get_sink_sync_latency(intel_dp);
> }
> @@ -386,13 +387,12 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
> u8 dpcd_val = DP_PSR_ENABLE;
>
> /* Enable ALPM at sink for psr2 */
> - if (dev_priv->psr.psr2_enabled && dev_priv->psr.alpm)
> - drm_dp_dpcd_writeb(&intel_dp->aux,
> - DP_RECEIVER_ALPM_CONFIG,
> - DP_ALPM_ENABLE);
> -
> - if (dev_priv->psr.psr2_enabled)
> + if (dev_priv->psr.psr2_enabled) {
> + drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG,
> + DP_ALPM_ENABLE);
> dpcd_val |= DP_PSR_ENABLE_PSR2;
> + }
> +
> if (dev_priv->psr.link_standby)
> dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
> drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val);
> --
> 2.14.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 6/6] drm/i915/psr: Fix ALPM cap check for PSR2
2018-05-22 14:37 ` Tarun Vyas
@ 2018-05-22 20:21 ` Dhinakaran Pandiyan
0 siblings, 0 replies; 23+ messages in thread
From: Dhinakaran Pandiyan @ 2018-05-22 20:21 UTC (permalink / raw)
To: Tarun Vyas; +Cc: intel-gfx
On Tue, 2018-05-22 at 07:37 -0700, Tarun Vyas wrote:
> On Fri, May 11, 2018 at 12:51:45PM -0700, Dhinakaran Pandiyan wrote:
> >
> > While touching the code around this, I noticed that absence of ALPM
> > capability does not stop us from enabling PSR2. But, the spec
> > unambiguously states that ALPM is required for PSR2 and so does
> > this
> > commit that introduced this code
> >
> > drm/i915/psr: enable ALPM for psr2
> >
> > As per edp1.4 spec , alpm is required for psr2 operation as
> > it's
> > used for all psr2 main link power down management and alpm
> > enable
> > bit must be set for psr2 operation.
> >
> Since, the code introduced by "drm/i915/psr: enable ALPM for psr2"
> enables PSR2 even if ALPM isn't supported, can we add the "Fixes" tag
> here ?
I thought about it. I don't think PSR2 was enabled upstream by default,
so we should be good without Fixes. And I didn't investigate if the
original commit missed the ALPM check or if it was mangled later.
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^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 2/6] drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time.
2018-05-11 22:14 ` Dhinakaran Pandiyan
@ 2018-05-24 13:28 ` Jani Nikula
0 siblings, 0 replies; 23+ messages in thread
From: Jani Nikula @ 2018-05-24 13:28 UTC (permalink / raw)
To: dhinakaran.pandiyan, intel-gfx
On Fri, 11 May 2018, Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> wrote:
> On Fri, 2018-05-11 at 12:51 -0700, Dhinakaran Pandiyan wrote:
>> By moving the check from psr_compute_config() to psr_init_dpcd(), we
>> get
>> to set the dev_priv->psr.sink_support flag only when the panel is
>> capable of changing power state. An additional benefit is that the
>> check
>> will be performed only at init time instead of every atomic_check.
>>
>> This should change the psr_basic IGT failures on HSW to skips.
>>
>> v2: Return early when SET_POWER_CAPABLE bit is 0 (Jose)
>>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106217
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106346
Pushed to dinq, thanks for the patch and review.
BR,
Jani.
>> Cc: José Roberto de Souza <jose.souza@intel.com>
>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
>> Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>> ---
>> drivers/gpu/drm/i915/intel_dp.c | 8 ++++++--
>> drivers/gpu/drm/i915/intel_psr.c | 11 +++++------
>> 2 files changed, 11 insertions(+), 8 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c
>> b/drivers/gpu/drm/i915/intel_dp.c
>> index dde92e4af5d3..cfd95eaa0d0d 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -3762,8 +3762,6 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
>> dev_priv->no_aux_handshake = intel_dp-
>> >dpcd[DP_MAX_DOWNSPREAD] &
>> DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
>>
>> - intel_psr_init_dpcd(intel_dp);
>> -
>> /*
>> * Read the eDP display control registers.
>> *
>> @@ -3779,6 +3777,12 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
>> DRM_DEBUG_KMS("eDP DPCD: %*ph\n", (int)
>> sizeof(intel_dp->edp_dpcd),
>> intel_dp->edp_dpcd);
>>
>> + /*
>> + * This has to be called after intel_dp->edp_dpcd is filled,
>> PSR checks
>> + * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
>> + */
>> + intel_psr_init_dpcd(intel_dp);
>> +
>> /* Read the eDP 1.4+ supported link rates. */
>> if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
>> __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
>> diff --git a/drivers/gpu/drm/i915/intel_psr.c
>> b/drivers/gpu/drm/i915/intel_psr.c
>> index 8fe6d2f9ab2b..61ade81576f5 100644
>> --- a/drivers/gpu/drm/i915/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/intel_psr.c
>> @@ -252,9 +252,13 @@ void intel_psr_init_dpcd(struct intel_dp
>> *intel_dp)
>>
>> if (!intel_dp->psr_dpcd[0])
>> return;
>> -
>> DRM_DEBUG_KMS("eDP panel supports PSR version %x\n",
>> intel_dp->psr_dpcd[0]);
>> +
>> + if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) {
>> + DRM_DEBUG_KMS("Panel lacks power state control, PSR
>> cannot be enabled\n");
>> + return;
>> + }
>> dev_priv->psr.sink_support = true;
>>
>> if (INTEL_GEN(dev_priv) >= 9 &&
>> @@ -642,11 +646,6 @@ void intel_psr_compute_config(struct intel_dp
>> *intel_dp,
>> return;
>> }
>>
>> - if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) {
>> - DRM_DEBUG_KMS("PSR condition failed: panel lacks
>> power state control\n");
>> - return;
>> - }
>> -
>> crtc_state->has_psr = true;
>> crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp,
>> crtc_state);
>> DRM_DEBUG_KMS("Enabling PSR%s\n", crtc_state->has_psr2 ? "2"
>> : "");
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Graphics Center
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^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 1/6] drm/i915/psr: Avoid DPCD reads when panel does not support PSR
2018-05-18 0:27 ` [PATCH 1/6] " Tarun Vyas
2018-05-21 23:40 ` Dhinakaran Pandiyan
@ 2018-05-24 13:29 ` Jani Nikula
1 sibling, 0 replies; 23+ messages in thread
From: Jani Nikula @ 2018-05-24 13:29 UTC (permalink / raw)
To: Tarun Vyas, Dhinakaran Pandiyan; +Cc: intel-gfx
On Thu, 17 May 2018, Tarun Vyas <tarun.vyas@intel.com> wrote:
> On Fri, May 11, 2018 at 12:51:40PM -0700, Dhinakaran Pandiyan wrote:
>> Ville noticed that we are unncessarily reading DPCD's after knowing
>> panel did not support PSR. Looks like this check that was present
>> earlier got removed unintentionally, let's put it back.
>>
>> While we do this, add the PSR version number in the debug print.
>>
>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
>> ---
>> drivers/gpu/drm/i915/intel_psr.c | 14 ++++++++------
>> 1 file changed, 8 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
>> index db27f2faa1de..8fe6d2f9ab2b 100644
>> --- a/drivers/gpu/drm/i915/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/intel_psr.c
>> @@ -250,10 +250,12 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
>> drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
>> sizeof(intel_dp->psr_dpcd));
>>
>> - if (intel_dp->psr_dpcd[0]) {
>> - dev_priv->psr.sink_support = true;
>> - DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
>> - }
>> + if (!intel_dp->psr_dpcd[0])
>> + return;
>> +
>> + DRM_DEBUG_KMS("eDP panel supports PSR version %x\n",
>> + intel_dp->psr_dpcd[0]);
>> + dev_priv->psr.sink_support = true;
>>
>> if (INTEL_GEN(dev_priv) >= 9 &&
>> (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) {
>> @@ -270,8 +272,8 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
>> */
>> dev_priv->psr.sink_psr2_support =
>> intel_dp_get_y_coord_required(intel_dp);
>> - DRM_DEBUG_KMS("PSR2 %s on sink", dev_priv->psr.sink_psr2_support
>> - ? "supported" : "not supported");
>> + DRM_DEBUG_KMS("PSR2 %ssupported\n",
>> + dev_priv->psr.sink_psr2_support ? "" : "not ");
> Would it make sense to make it clearer that PSR2 is not supported b/c of lack of y-coordinate support on the sink ?
>
> Reviewed-by: Tarun Vyas <tarun.vyas@intel.com>
Pushed to dinq, thanks for the patch and review.
BR,
Jani.
>>
>> if (dev_priv->psr.sink_psr2_support) {
>> dev_priv->psr.colorimetry_support =
>> --
>> 2.14.1
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Graphics Center
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 3/6] drm/psr: Fix missed entry in PSR setup time table.
2018-05-11 19:51 ` [PATCH 3/6] drm/psr: Fix missed entry in PSR setup time table Dhinakaran Pandiyan
@ 2018-05-24 14:00 ` Jani Nikula
0 siblings, 0 replies; 23+ messages in thread
From: Jani Nikula @ 2018-05-24 14:00 UTC (permalink / raw)
To: Dhinakaran Pandiyan, intel-gfx
Cc: Jose Roberto de Souza, dri-devel, Dhinakaran Pandiyan, stable, Sean Paul
On Fri, 11 May 2018, Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> wrote:
> Entry corresponding to 220 us setup time was missing. I am not aware of
> any specific bug this fixes, but this could potentially result in enabling
> PSR on a panel with a higher setup time requirement than supported by the
> hardware.
>
> I verified the value is present in eDP spec versions 1.3, 1.4 and 1.4a.
>
> Fixes: 6608804b3d7f ("drm/dp: Add drm_dp_psr_setup_time()")
> Cc: stable@vger.kernel.org
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Jose Roberto de Souza <jose.souza@intel.com>
> Cc: dri-devel@lists.freedesktop.org
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Pushed to drm-misc-fixes with reviews picked up from the earlier posting
[1]. Doesn't look like the function is used by anyone other than i915,
so I didn't bother with further acks from non-Intel devs. Should be a
straightforward fix anyway.
BR,
Jani.
[1] http://mid.mail-archive.com/20180511005419.11199-1-dhinakaran.pandiyan@intel.com
> ---
> drivers/gpu/drm/drm_dp_helper.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
> index 36c7609a4bd5..a7ba602a43a8 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -1159,6 +1159,7 @@ int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE])
> static const u16 psr_setup_time_us[] = {
> PSR_SETUP_TIME(330),
> PSR_SETUP_TIME(275),
> + PSR_SETUP_TIME(220),
> PSR_SETUP_TIME(165),
> PSR_SETUP_TIME(110),
> PSR_SETUP_TIME(55),
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 3/6] drm/psr: Fix missed entry in PSR setup time table.
@ 2018-05-24 14:00 ` Jani Nikula
0 siblings, 0 replies; 23+ messages in thread
From: Jani Nikula @ 2018-05-24 14:00 UTC (permalink / raw)
To: intel-gfx
Cc: Jose Roberto de Souza, dri-devel, Dhinakaran Pandiyan, stable, Sean Paul
On Fri, 11 May 2018, Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> wrote:
> Entry corresponding to 220 us setup time was missing. I am not aware of
> any specific bug this fixes, but this could potentially result in enabling
> PSR on a panel with a higher setup time requirement than supported by the
> hardware.
>
> I verified the value is present in eDP spec versions 1.3, 1.4 and 1.4a.
>
> Fixes: 6608804b3d7f ("drm/dp: Add drm_dp_psr_setup_time()")
> Cc: stable@vger.kernel.org
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Jose Roberto de Souza <jose.souza@intel.com>
> Cc: dri-devel@lists.freedesktop.org
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Pushed to drm-misc-fixes with reviews picked up from the earlier posting
[1]. Doesn't look like the function is used by anyone other than i915,
so I didn't bother with further acks from non-Intel devs. Should be a
straightforward fix anyway.
BR,
Jani.
[1] http://mid.mail-archive.com/20180511005419.11199-1-dhinakaran.pandiyan@intel.com
> ---
> drivers/gpu/drm/drm_dp_helper.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
> index 36c7609a4bd5..a7ba602a43a8 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -1159,6 +1159,7 @@ int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE])
> static const u16 psr_setup_time_us[] = {
> PSR_SETUP_TIME(330),
> PSR_SETUP_TIME(275),
> + PSR_SETUP_TIME(220),
> PSR_SETUP_TIME(165),
> PSR_SETUP_TIME(110),
> PSR_SETUP_TIME(55),
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 4/6] drm/i915/psr: Avoid unnecessary DPCD read of DP_PSR_CAPS
2018-05-20 23:01 ` Tarun Vyas
@ 2018-05-24 14:01 ` Jani Nikula
0 siblings, 0 replies; 23+ messages in thread
From: Jani Nikula @ 2018-05-24 14:01 UTC (permalink / raw)
To: Tarun Vyas, Dhinakaran Pandiyan; +Cc: intel-gfx
On Sun, 20 May 2018, Tarun Vyas <tarun.vyas@intel.com> wrote:
> On Fri, May 11, 2018 at 12:51:43PM -0700, Dhinakaran Pandiyan wrote:
>> intel_dp->psr_dpcd already has the required values.
>>
>> Cc: Jose Roberto de Souza <jose.souza@intel.com>
>> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
>> ---
>> drivers/gpu/drm/i915/intel_psr.c | 11 +----------
>> 1 file changed, 1 insertion(+), 10 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
>> index 61ade81576f5..381dbdbf30f4 100644
>> --- a/drivers/gpu/drm/i915/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/intel_psr.c
>> @@ -201,15 +201,6 @@ void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir)
>> }
>> }
>>
>> -static bool intel_dp_get_y_coord_required(struct intel_dp *intel_dp)
>> -{
>> - uint8_t psr_caps = 0;
>> -
>> - if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_CAPS, &psr_caps) != 1)
>> - return false;
>> - return psr_caps & DP_PSR2_SU_Y_COORDINATE_REQUIRED;
>> -}
>> -
>> static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
>> {
>> uint8_t dprx = 0;
>> @@ -275,7 +266,7 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
>> * GTC first.
>> */
>> dev_priv->psr.sink_psr2_support =
>> - intel_dp_get_y_coord_required(intel_dp);
>> + intel_dp->psr_dpcd[1] & DP_PSR2_SU_Y_COORDINATE_REQUIRED;
>> DRM_DEBUG_KMS("PSR2 %ssupported\n",
>> dev_priv->psr.sink_psr2_support ? "" : "not ");
> The drm_dp_dpcd_read itself reads the first 2 PSR DPCD bytes which is what is needed. Also, no other callers of intel_dp_get_y_coord_required exist. So,
>
> Reviewed-by: Tarun Vyas <tarun.vyas@intel.com>
The rest of the patches in the series pushed to dinq as well, thanks for
the patches and review.
BR,
Jani.
>>
>> --
>> 2.14.1
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 23+ messages in thread
end of thread, other threads:[~2018-05-24 14:00 UTC | newest]
Thread overview: 23+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-05-11 19:51 [PATCH 1/6] drm/i915/psr: Avoid DPCD reads when panel does not support PSR Dhinakaran Pandiyan
2018-05-11 19:51 ` [PATCH 2/6] drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time Dhinakaran Pandiyan
2018-05-11 22:14 ` Dhinakaran Pandiyan
2018-05-24 13:28 ` Jani Nikula
2018-05-11 19:51 ` [PATCH 3/6] drm/psr: Fix missed entry in PSR setup time table Dhinakaran Pandiyan
2018-05-24 14:00 ` Jani Nikula
2018-05-24 14:00 ` Jani Nikula
2018-05-11 19:51 ` [PATCH 4/6] drm/i915/psr: Avoid unnecessary DPCD read of DP_PSR_CAPS Dhinakaran Pandiyan
2018-05-20 23:01 ` Tarun Vyas
2018-05-24 14:01 ` Jani Nikula
2018-05-22 12:32 ` Nagaraju, Vathsala
2018-05-11 19:51 ` [PATCH 5/6] drm/i915/psr: Fall back to max. synchronization latency if DPCD read fails Dhinakaran Pandiyan
2018-05-21 23:58 ` Souza, Jose
2018-05-11 19:51 ` [PATCH 6/6] drm/i915/psr: Fix ALPM cap check for PSR2 Dhinakaran Pandiyan
2018-05-22 9:33 ` Nagaraju, Vathsala
2018-05-22 14:37 ` Tarun Vyas
2018-05-22 20:21 ` Dhinakaran Pandiyan
2018-05-11 20:26 ` ✓ Fi.CI.BAT: success for series starting with [1/6] drm/i915/psr: Avoid DPCD reads when panel does not support PSR Patchwork
2018-05-11 21:17 ` ✓ Fi.CI.IGT: " Patchwork
2018-05-18 0:27 ` [PATCH 1/6] " Tarun Vyas
2018-05-21 23:40 ` Dhinakaran Pandiyan
2018-05-24 13:29 ` Jani Nikula
2018-05-22 12:29 ` Nagaraju, Vathsala
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