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From: Luwei Kang <luwei.kang@intel.com>
To: kvm@vger.kernel.org
Cc: tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com,
	x86@kernel.org, chao.p.peng@linux.intel.com,
	thomas.lendacky@amd.com, bp@suse.de, Kan.liang@intel.com,
	Janakarajan.Natarajan@amd.com, dwmw@amazon.co.uk,
	linux-kernel@vger.kernel.org, alexander.shishkin@linux.intel.com,
	peterz@infradead.org, mathieu.poirier@linaro.org,
	kstewart@linuxfoundation.org, gregkh@linuxfoundation.org,
	pbonzini@redhat.com, rkrcmar@redhat.com, david@redhat.com,
	bsd@redhat.com, yu.c.zhang@linux.intel.com, joro@8bytes.org,
	Luwei Kang <luwei.kang@intel.com>
Subject: [PATCH v8 02/12] perf/x86/intel/pt: Change pt_cap_get() to a public function
Date: Mon, 14 May 2018 18:57:02 +0800	[thread overview]
Message-ID: <1526295432-20640-3-git-send-email-luwei.kang@intel.com> (raw)
In-Reply-To: <1526295432-20640-1-git-send-email-luwei.kang@intel.com>

From: Chao Peng <chao.p.peng@linux.intel.com>

Change pt_cap_get() to a public function that KVM
can access this function to check if specific
feature is supported on hardware.

Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com>
Signed-off-by: Luwei Kang <luwei.kang@intel.com>
---
 arch/x86/events/intel/pt.c      |  3 ++-
 arch/x86/events/intel/pt.h      | 21 ---------------------
 arch/x86/include/asm/intel_pt.h | 23 +++++++++++++++++++++++
 3 files changed, 25 insertions(+), 22 deletions(-)

diff --git a/arch/x86/events/intel/pt.c b/arch/x86/events/intel/pt.c
index 3b99394..c80e2f5 100644
--- a/arch/x86/events/intel/pt.c
+++ b/arch/x86/events/intel/pt.c
@@ -75,7 +75,7 @@
 	PT_CAP(psb_periods,		1, CPUID_EBX, 0xffff0000),
 };
 
-static u32 pt_cap_get(enum pt_capabilities cap)
+u32 pt_cap_get(enum pt_capabilities cap)
 {
 	struct pt_cap_desc *cd = &pt_caps[cap];
 	u32 c = pt_pmu.caps[cd->leaf * PT_CPUID_REGS_NUM + cd->reg];
@@ -83,6 +83,7 @@ static u32 pt_cap_get(enum pt_capabilities cap)
 
 	return (c & cd->mask) >> shift;
 }
+EXPORT_SYMBOL_GPL(pt_cap_get);
 
 static ssize_t pt_cap_show(struct device *cdev,
 			   struct device_attribute *attr,
diff --git a/arch/x86/events/intel/pt.h b/arch/x86/events/intel/pt.h
index 0050ca1..269e15a 100644
--- a/arch/x86/events/intel/pt.h
+++ b/arch/x86/events/intel/pt.h
@@ -45,30 +45,9 @@ struct topa_entry {
 	u64	rsvd4	: 16;
 };
 
-#define PT_CPUID_LEAVES		2
-#define PT_CPUID_REGS_NUM	4 /* number of regsters (eax, ebx, ecx, edx) */
-
 /* TSC to Core Crystal Clock Ratio */
 #define CPUID_TSC_LEAF		0x15
 
-enum pt_capabilities {
-	PT_CAP_max_subleaf = 0,
-	PT_CAP_cr3_filtering,
-	PT_CAP_psb_cyc,
-	PT_CAP_ip_filtering,
-	PT_CAP_mtc,
-	PT_CAP_ptwrite,
-	PT_CAP_power_event_trace,
-	PT_CAP_topa_output,
-	PT_CAP_topa_multiple_entries,
-	PT_CAP_single_range_output,
-	PT_CAP_payloads_lip,
-	PT_CAP_num_address_ranges,
-	PT_CAP_mtc_periods,
-	PT_CAP_cycle_thresholds,
-	PT_CAP_psb_periods,
-};
-
 struct pt_pmu {
 	struct pmu		pmu;
 	u32			caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES];
diff --git a/arch/x86/include/asm/intel_pt.h b/arch/x86/include/asm/intel_pt.h
index b523f51..4270421 100644
--- a/arch/x86/include/asm/intel_pt.h
+++ b/arch/x86/include/asm/intel_pt.h
@@ -2,10 +2,33 @@
 #ifndef _ASM_X86_INTEL_PT_H
 #define _ASM_X86_INTEL_PT_H
 
+#define PT_CPUID_LEAVES		2
+#define PT_CPUID_REGS_NUM	4 /* number of regsters (eax, ebx, ecx, edx) */
+
+enum pt_capabilities {
+	PT_CAP_max_subleaf = 0,
+	PT_CAP_cr3_filtering,
+	PT_CAP_psb_cyc,
+	PT_CAP_ip_filtering,
+	PT_CAP_mtc,
+	PT_CAP_ptwrite,
+	PT_CAP_power_event_trace,
+	PT_CAP_topa_output,
+	PT_CAP_topa_multiple_entries,
+	PT_CAP_single_range_output,
+	PT_CAP_payloads_lip,
+	PT_CAP_num_address_ranges,
+	PT_CAP_mtc_periods,
+	PT_CAP_cycle_thresholds,
+	PT_CAP_psb_periods,
+};
+
 #if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_INTEL)
 void cpu_emergency_stop_pt(void);
+extern u32 pt_cap_get(enum pt_capabilities cap);
 #else
 static inline void cpu_emergency_stop_pt(void) {}
+static inline u32 pt_cap_get(enum pt_capabilities cap) { return 0; }
 #endif
 
 #endif /* _ASM_X86_INTEL_PT_H */
-- 
1.8.3.1

  parent reply	other threads:[~2018-05-14 10:57 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-05-14 10:57 [PATCH v8 00/12] Intel Processor Trace virtualization enabling Luwei Kang
2018-05-14 10:57 ` [PATCH v8 01/12] perf/x86/intel/pt: Move Intel-PT MSRs bit definitions to a public header Luwei Kang
2018-05-14 10:22   ` Alexander Shishkin
2018-05-16  9:42     ` Kang, Luwei
2018-05-16  9:42       ` Kang, Luwei
2018-05-14 10:57 ` Luwei Kang [this message]
2018-05-14 10:57 ` [PATCH v8 03/12] perf/x86/intel/pt: Add new bit definitions for Intel PT MSRs Luwei Kang
2018-05-14 10:57 ` [PATCH v8 04/12] perf/x86/intel/pt: add new capability for Intel PT Luwei Kang
2018-05-14 10:57 ` [PATCH v8 05/12] perf/x86/intel/pt: Introduce a new function to get capability of " Luwei Kang
2018-05-14 10:57 ` [PATCH v8 06/12] KVM: x86: Add Intel Processor Trace virtualization mode Luwei Kang
2018-05-14 10:57 ` [PATCH v8 07/12] KVM: x86: Add Intel Processor Trace cpuid emulation Luwei Kang
2018-05-14 10:57 ` [PATCH v8 08/12] KVM: x86: Add Intel Processor Trace context switch for each vcpu Luwei Kang
2018-05-14 10:57 ` [PATCH v8 09/12] KVM: x86: Introduce a function to initialize the PT configuration Luwei Kang
2018-05-14 10:57 ` [PATCH v8 10/12] KVM: x86: Implement Intel Processor Trace MSRs read/write emulation Luwei Kang
2018-05-14 10:57 ` [PATCH v8 11/12] KVM: x86: Set intercept for Intel PT MSRs read/write Luwei Kang
2018-05-14 10:57 ` [PATCH v8 12/12] KVM: x86: Disable Intel Processor Trace when VMXON in L1 guest Luwei Kang

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