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From: "Kang, Luwei" <luwei.kang@intel.com>
To: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: "kvm@vger.kernel.org" <kvm@vger.kernel.org>,
	"tglx@linutronix.de" <tglx@linutronix.de>,
	"mingo@redhat.com" <mingo@redhat.com>,
	"hpa@zytor.com" <hpa@zytor.com>,
	"x86@kernel.org" <x86@kernel.org>,
	"chao.p.peng@linux.intel.com" <chao.p.peng@linux.intel.com>,
	"thomas.lendacky@amd.com" <thomas.lendacky@amd.com>,
	"bp@suse.de" <bp@suse.de>, "Liang, Kan" <kan.liang@intel.com>,
	"Janakarajan.Natarajan@amd.com" <Janakarajan.Natarajan@amd.com>,
	"dwmw@amazon.co.uk" <dwmw@amazon.co.uk>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"peterz@infradead.org" <peterz@infradead.org>,
	"mathieu.poirier@linaro.org" <mathieu.poirier@linaro.org>,
	"kstewart@linuxfoundation.org" <kstewart@linuxfoundation.org>,
	"gregkh@linuxfoundation.org" <gregkh@linuxfoundation.org>,
	"pbonzini@redhat.com" <pbonzini@redhat.com>,
	"rkrcmar@redhat.com" <rkrcmar@redhat.com>,
	"david@redhat.com" <david@redhat.com>,
	"bsd@redhat.com" <bsd@redhat.com>,
	"yu.c.zhang@linux.intel.com" <yu.c.zhang@linux.intel.com>,
	"joro@8bytes.org" <joro@8bytes.org>
Subject: RE: [PATCH v8 01/12] perf/x86/intel/pt: Move Intel-PT MSRs bit definitions to a public header
Date: Wed, 16 May 2018 09:42:58 +0000	[thread overview]
Message-ID: <82D7661F83C1A047AF7DC287873BF1E167F7B1B8@SHSMSX101.ccr.corp.intel.com> (raw)
In-Reply-To: <20180514102217.uc3kzhu6gs4wapuo@um.fi.intel.com>

> > From: Chao Peng <chao.p.peng@linux.intel.com>
> >
> > Intel Processor Trace virtualization enabling in KVM guest need to
> > access these MSRs bit definitions, so move them to public header file
> > msr-index.h.
> > @@ -115,6 +148,7 @@
> >  #define MSR_IA32_RTIT_ADDR2_B		0x00000585
> >  #define MSR_IA32_RTIT_ADDR3_A		0x00000586
> >  #define MSR_IA32_RTIT_ADDR3_B		0x00000587
> > +#define MSR_IA32_RTIT_ADDR_RANGE	4
> 
> This one wasn't there before, so belongs in a different patch.

What about move this definition to "arch/x86/include/asm/intel_pt.h " and be added in patch 8 (implementation of context switch).

Thanks,
Luwei Kang

> 
> Regards,
> --
> Alex

WARNING: multiple messages have this Message-ID (diff)
From: "Kang, Luwei" <luwei.kang@intel.com>
To: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: "kvm@vger.kernel.org" <kvm@vger.kernel.org>,
	"tglx@linutronix.de" <tglx@linutronix.de>,
	"mingo@redhat.com" <mingo@redhat.com>,
	"hpa@zytor.com" <hpa@zytor.com>,
	"x86@kernel.org" <x86@kernel.org>,
	"chao.p.peng@linux.intel.com" <chao.p.peng@linux.intel.com>,
	"thomas.lendacky@amd.com" <thomas.lendacky@amd.com>,
	"bp@suse.de" <bp@suse.de>, "Liang, Kan" <kan.liang@intel.com>,
	"Janakarajan.Natarajan@amd.com" <Janakarajan.Natarajan@amd.com>,
	"dwmw@amazon.co.uk" <dwmw@amazon.co.uk>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"peterz@infradead.org" <peterz@infradead.org>,
	"mathieu.poirier@linaro.org" <mathieu.poirier@linaro.org>,
	"kstewart@linuxfoundation.org" <kstewart@linuxfoundation.org>,
	"gregkh@linuxfoundation.org" <gregkh@linuxfoundation.org>,
	"pbonzini@redha
Subject: RE: [PATCH v8 01/12] perf/x86/intel/pt: Move Intel-PT MSRs bit definitions to a public header
Date: Wed, 16 May 2018 09:42:58 +0000	[thread overview]
Message-ID: <82D7661F83C1A047AF7DC287873BF1E167F7B1B8@SHSMSX101.ccr.corp.intel.com> (raw)
In-Reply-To: <20180514102217.uc3kzhu6gs4wapuo@um.fi.intel.com>

> > From: Chao Peng <chao.p.peng@linux.intel.com>
> >
> > Intel Processor Trace virtualization enabling in KVM guest need to
> > access these MSRs bit definitions, so move them to public header file
> > msr-index.h.
> > @@ -115,6 +148,7 @@
> >  #define MSR_IA32_RTIT_ADDR2_B		0x00000585
> >  #define MSR_IA32_RTIT_ADDR3_A		0x00000586
> >  #define MSR_IA32_RTIT_ADDR3_B		0x00000587
> > +#define MSR_IA32_RTIT_ADDR_RANGE	4
> 
> This one wasn't there before, so belongs in a different patch.

What about move this definition to "arch/x86/include/asm/intel_pt.h " and be added in patch 8 (implementation of context switch).

Thanks,
Luwei Kang

> 
> Regards,
> --
> Alex

  reply	other threads:[~2018-05-16  9:42 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-05-14 10:57 [PATCH v8 00/12] Intel Processor Trace virtualization enabling Luwei Kang
2018-05-14 10:57 ` [PATCH v8 01/12] perf/x86/intel/pt: Move Intel-PT MSRs bit definitions to a public header Luwei Kang
2018-05-14 10:22   ` Alexander Shishkin
2018-05-16  9:42     ` Kang, Luwei [this message]
2018-05-16  9:42       ` Kang, Luwei
2018-05-14 10:57 ` [PATCH v8 02/12] perf/x86/intel/pt: Change pt_cap_get() to a public function Luwei Kang
2018-05-14 10:57 ` [PATCH v8 03/12] perf/x86/intel/pt: Add new bit definitions for Intel PT MSRs Luwei Kang
2018-05-14 10:57 ` [PATCH v8 04/12] perf/x86/intel/pt: add new capability for Intel PT Luwei Kang
2018-05-14 10:57 ` [PATCH v8 05/12] perf/x86/intel/pt: Introduce a new function to get capability of " Luwei Kang
2018-05-14 10:57 ` [PATCH v8 06/12] KVM: x86: Add Intel Processor Trace virtualization mode Luwei Kang
2018-05-14 10:57 ` [PATCH v8 07/12] KVM: x86: Add Intel Processor Trace cpuid emulation Luwei Kang
2018-05-14 10:57 ` [PATCH v8 08/12] KVM: x86: Add Intel Processor Trace context switch for each vcpu Luwei Kang
2018-05-14 10:57 ` [PATCH v8 09/12] KVM: x86: Introduce a function to initialize the PT configuration Luwei Kang
2018-05-14 10:57 ` [PATCH v8 10/12] KVM: x86: Implement Intel Processor Trace MSRs read/write emulation Luwei Kang
2018-05-14 10:57 ` [PATCH v8 11/12] KVM: x86: Set intercept for Intel PT MSRs read/write Luwei Kang
2018-05-14 10:57 ` [PATCH v8 12/12] KVM: x86: Disable Intel Processor Trace when VMXON in L1 guest Luwei Kang

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