[U-Boot] [PATCH v2 00/10] Update STM32 QSPI driver

[U-Boot] [PATCH v2 00/10] Update STM32 QSPI driver

[Patrice Chotard]

This series :
  _ removes useless CONFIG_CLK flag
  _ fixes checkpatch warnings
  _ sorts include files in alphabetical order
  _ align DT bindings with kernel in DT and in driver code
  _ add chip select management
  _ uses dev_read_xxx API
  _ add reset support


Changes in v2:
 _ remove "update mode management" patch, will be reworked and
   submitted separately

Christophe Kerello (3):
  spi: stm32_qspi: Align reg-names with kernel 4.12 RC1
  spi: stm32_qspi: Add st,stm32f469-qspi compatible string
  spi: stm32_qspi: Add chip select management

Patrice Chotard (6):
  spi: stm32_qspi: Remove CONFIG_CLK flag
  spi: stm32_qspi: Sort include files alphabetically
  spi: stm32_qspi: Use dev_read_xxx API
  spi: stm32_qspi: Add reset support
  ARM: dts: stm32: Add quadspi reset for stm32f746
  ARM: dts: stm32: Update qspi bindings for stm32f746

Patrick Delaunay (1):
  spi: stm32_qspi: Solve issue detected by checkpatch

 arch/arm/dts/stm32f746.dtsi |  3 +-
 drivers/spi/stm32_qspi.c    | 91 ++++++++++++++++++++++++++++++---------------
 2 files changed, 62 insertions(+), 32 deletions(-)

-- 
1.9.1

[U-Boot] [PATCH v2 01/10] spi: stm32_qspi: Remove CONFIG_CLK flag

[Patrice Chotard]

As all platforms which uses this driver have CONFIG_CLK flag
enable in their defconfig, we can remove it from driver code.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---

Changes in v2: None

 drivers/spi/stm32_qspi.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/spi/stm32_qspi.c b/drivers/spi/stm32_qspi.c
index 7d1801280773..41a488097c19 100644
--- a/drivers/spi/stm32_qspi.c
+++ b/drivers/spi/stm32_qspi.c
@@ -448,6 +448,8 @@ static int stm32_qspi_probe(struct udevice *bus)
 	struct stm32_qspi_platdata *plat = dev_get_platdata(bus);
 	struct stm32_qspi_priv *priv = dev_get_priv(bus);
 	struct dm_spi_bus *dm_spi_bus;
+	struct clk clk;
+	int ret;
 
 	dm_spi_bus = bus->uclass_priv;
 
@@ -457,9 +459,6 @@ static int stm32_qspi_probe(struct udevice *bus)
 
 	priv->max_hz = plat->max_hz;
 
-#ifdef CONFIG_CLK
-	int ret;
-	struct clk clk;
 	ret = clk_get_by_index(bus, 0, &clk);
 	if (ret < 0)
 		return ret;
@@ -477,7 +476,6 @@ static int stm32_qspi_probe(struct udevice *bus)
 		return priv->clock_rate;
 	}
 
-#endif
 
 	setbits_le32(&priv->regs->cr, STM32_QSPI_CR_SSHIFT);
 
-- 
1.9.1

[U-Boot] [PATCH v2 02/10] spi: stm32_qspi: Solve issue detected by checkpatch

[Patrice Chotard]

From: Patrick Delaunay <patrick.delaunay@st.com>

Fix parameters function alingemnt
Fix variable declaration

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---

Changes in v2: None

 drivers/spi/stm32_qspi.c | 31 ++++++++++++++++++-------------
 1 file changed, 18 insertions(+), 13 deletions(-)

diff --git a/drivers/spi/stm32_qspi.c b/drivers/spi/stm32_qspi.c
index 41a488097c19..a82c180089e0 100644
--- a/drivers/spi/stm32_qspi.c
+++ b/drivers/spi/stm32_qspi.c
@@ -206,6 +206,7 @@ static void _stm32_qspi_wait_for_ftf(struct stm32_qspi_priv *priv)
 static void _stm32_qspi_set_flash_size(struct stm32_qspi_priv *priv, u32 size)
 {
 	u32 fsize = fls(size) - 1;
+
 	clrsetbits_le32(&priv->regs->dcr,
 			STM32_QSPI_DCR_FSIZE_MASK << STM32_QSPI_DCR_FSIZE_SHIFT,
 			fsize << STM32_QSPI_DCR_FSIZE_SHIFT);
@@ -255,13 +256,15 @@ static unsigned int _stm32_qspi_gen_ccr(struct stm32_qspi_priv *priv)
 }
 
 static void _stm32_qspi_enable_mmap(struct stm32_qspi_priv *priv,
-		struct spi_flash *flash)
+				    struct spi_flash *flash)
 {
+	unsigned int ccr_reg;
+
 	priv->command = flash->read_cmd | CMD_HAS_ADR | CMD_HAS_DATA
 			| CMD_HAS_DUMMY;
 	priv->dummycycles = flash->dummy_byte * 8;
 
-	unsigned int ccr_reg = _stm32_qspi_gen_ccr(priv);
+	ccr_reg = _stm32_qspi_gen_ccr(priv);
 	ccr_reg |= (STM32_QSPI_CCR_MEM_MAP << STM32_QSPI_CCR_FMODE_SHIFT);
 
 	_stm32_qspi_wait_for_not_busy(priv);
@@ -291,10 +294,12 @@ static void _stm32_qspi_start_xfer(struct stm32_qspi_priv *priv, u32 cr_reg)
 }
 
 static int _stm32_qspi_xfer(struct stm32_qspi_priv *priv,
-		struct spi_flash *flash, unsigned int bitlen,
-		const u8 *dout, u8 *din, unsigned long flags)
+			    struct spi_flash *flash, unsigned int bitlen,
+			    const u8 *dout, u8 *din, unsigned long flags)
 {
 	unsigned int words = bitlen / 8;
+	u32 ccr_reg;
+	int i;
 
 	if (flags & SPI_XFER_MMAP) {
 		_stm32_qspi_enable_mmap(priv, flash);
@@ -346,7 +351,7 @@ static int _stm32_qspi_xfer(struct stm32_qspi_priv *priv,
 		}
 
 		if (flags & SPI_XFER_END) {
-			u32 ccr_reg = _stm32_qspi_gen_ccr(priv);
+			ccr_reg = _stm32_qspi_gen_ccr(priv);
 			ccr_reg |= STM32_QSPI_CCR_IND_WRITE
 					<< STM32_QSPI_CCR_FMODE_SHIFT;
 
@@ -365,7 +370,7 @@ static int _stm32_qspi_xfer(struct stm32_qspi_priv *priv,
 
 				debug("%s: words:%d data:", __func__, words);
 
-				int i = 0;
+				i = 0;
 				while (words > i) {
 					writeb(dout[i], &priv->regs->dr);
 					debug("%02x ", dout[i]);
@@ -379,7 +384,7 @@ static int _stm32_qspi_xfer(struct stm32_qspi_priv *priv,
 			}
 		}
 	} else if (din) {
-		u32 ccr_reg = _stm32_qspi_gen_ccr(priv);
+		ccr_reg = _stm32_qspi_gen_ccr(priv);
 		ccr_reg |= STM32_QSPI_CCR_IND_READ
 				<< STM32_QSPI_CCR_FMODE_SHIFT;
 
@@ -394,7 +399,7 @@ static int _stm32_qspi_xfer(struct stm32_qspi_priv *priv,
 
 		debug("%s: data:", __func__);
 
-		int i = 0;
+		i = 0;
 		while (words > i) {
 			din[i] = readb(&priv->regs->dr);
 			debug("%02x ", din[i]);
@@ -518,7 +523,7 @@ static int stm32_qspi_release_bus(struct udevice *dev)
 }
 
 static int stm32_qspi_xfer(struct udevice *dev, unsigned int bitlen,
-		const void *dout, void *din, unsigned long flags)
+			   const void *dout, void *din, unsigned long flags)
 {
 	struct stm32_qspi_priv *priv;
 	struct udevice *bus;
@@ -536,12 +541,13 @@ static int stm32_qspi_set_speed(struct udevice *bus, uint speed)
 {
 	struct stm32_qspi_platdata *plat = bus->platdata;
 	struct stm32_qspi_priv *priv = dev_get_priv(bus);
+	u32 qspi_clk = priv->clock_rate;
+	u32 prescaler = 255;
+	u32 csht;
 
 	if (speed > plat->max_hz)
 		speed = plat->max_hz;
 
-	u32 qspi_clk = priv->clock_rate;
-	u32 prescaler = 255;
 	if (speed > 0) {
 		prescaler = DIV_ROUND_UP(qspi_clk, speed) - 1;
 		if (prescaler > 255)
@@ -550,7 +556,7 @@ static int stm32_qspi_set_speed(struct udevice *bus, uint speed)
 			prescaler = 0;
 	}
 
-	u32 csht = DIV_ROUND_UP((5 * qspi_clk) / (prescaler + 1), 100000000);
+	csht = DIV_ROUND_UP((5 * qspi_clk) / (prescaler + 1), 100000000);
 	csht = (csht - 1) & STM32_QSPI_DCR_CSHT_MASK;
 
 	_stm32_qspi_wait_for_not_busy(priv);
@@ -560,7 +566,6 @@ static int stm32_qspi_set_speed(struct udevice *bus, uint speed)
 			STM32_QSPI_CR_PRESCALER_SHIFT,
 			prescaler << STM32_QSPI_CR_PRESCALER_SHIFT);
 
-
 	clrsetbits_le32(&priv->regs->dcr,
 			STM32_QSPI_DCR_CSHT_MASK << STM32_QSPI_DCR_CSHT_SHIFT,
 			csht << STM32_QSPI_DCR_CSHT_SHIFT);
-- 
1.9.1

[U-Boot] [PATCH v2 03/10] spi: stm32_qspi: Sort include files alphabetically

[Patrice Chotard]

Sort include files by alphabetical order

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---

Changes in v2: None

 drivers/spi/stm32_qspi.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/spi/stm32_qspi.c b/drivers/spi/stm32_qspi.c
index a82c180089e0..4bc4455d2ef9 100644
--- a/drivers/spi/stm32_qspi.c
+++ b/drivers/spi/stm32_qspi.c
@@ -8,14 +8,14 @@
  */
 
 #include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <errno.h>
 #include <malloc.h>
 #include <spi.h>
 #include <spi_flash.h>
 #include <asm/io.h>
-#include <dm.h>
-#include <errno.h>
 #include <asm/arch/stm32.h>
-#include <clk.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-- 
1.9.1

[U-Boot] [PATCH v2 04/10] spi: stm32_qspi: Align reg-names with kernel 4.12 RC1

[Patrice Chotard]

From: Christophe Kerello <christophe.kerello@st.com>

Align qspi bindings following kernel dt-bindings
Documentation/devicetree/bindings/mtd/stm32-quadspi.txt
from kernel v4.12-rc1.

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---

Changes in v2: None

 drivers/spi/stm32_qspi.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/spi/stm32_qspi.c b/drivers/spi/stm32_qspi.c
index 4bc4455d2ef9..fc1a34ea442c 100644
--- a/drivers/spi/stm32_qspi.c
+++ b/drivers/spi/stm32_qspi.c
@@ -420,13 +420,13 @@ static int stm32_qspi_ofdata_to_platdata(struct udevice *bus)
 	int ret;
 
 	ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
-				     "QuadSPI", &res_regs);
+				     "qspi", &res_regs);
 	if (ret) {
 		debug("Error: can't get regs base addresses(ret = %d)!\n", ret);
 		return -ENOMEM;
 	}
 	ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
-				     "QuadSPI-memory", &res_mem);
+				     "qspi_mm", &res_mem);
 	if (ret) {
 		debug("Error: can't get mmap base address(ret = %d)!\n", ret);
 		return -ENOMEM;
-- 
1.9.1

[U-Boot] [PATCH v2 05/10] spi: stm32_qspi: Add st, stm32f469-qspi compatible string

[Patrice Chotard]

From: Christophe Kerello <christophe.kerello@st.com>

Add "st,stm32f469-qspi" compatible which is used on kernel side.
This will be necessary when DT will be synchronised from kernel.

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---

Changes in v2: None

 drivers/spi/stm32_qspi.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/spi/stm32_qspi.c b/drivers/spi/stm32_qspi.c
index fc1a34ea442c..9fe8b297a458 100644
--- a/drivers/spi/stm32_qspi.c
+++ b/drivers/spi/stm32_qspi.c
@@ -635,6 +635,7 @@ static const struct dm_spi_ops stm32_qspi_ops = {
 
 static const struct udevice_id stm32_qspi_ids[] = {
 	{ .compatible = "st,stm32-qspi" },
+	{ .compatible = "st,stm32f469-qspi" },
 	{ }
 };
 
-- 
1.9.1

[U-Boot] [PATCH v2 06/10] spi: stm32_qspi: Add chip select management

[Patrice Chotard]

From: Christophe Kerello <christophe.kerello@st.com>

Quad-SPI interface is able to manage 2 spi nor devices.
FSEL bit selects the flash memory to be addressed in single flash mode.

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---

Changes in v2: None

 drivers/spi/stm32_qspi.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/spi/stm32_qspi.c b/drivers/spi/stm32_qspi.c
index 9fe8b297a458..56ea5911239a 100644
--- a/drivers/spi/stm32_qspi.c
+++ b/drivers/spi/stm32_qspi.c
@@ -155,6 +155,8 @@ enum STM32_QSPI_CCR_FMODE {
 /* default SCK frequency, unit: HZ */
 #define STM32_QSPI_DEFAULT_SCK_FREQ 108000000
 
+#define STM32_MAX_NORCHIP 2
+
 struct stm32_qspi_platdata {
 	u32 base;
 	u32 memory_map;
@@ -212,6 +214,12 @@ static void _stm32_qspi_set_flash_size(struct stm32_qspi_priv *priv, u32 size)
 			fsize << STM32_QSPI_DCR_FSIZE_SHIFT);
 }
 
+static void _stm32_qspi_set_cs(struct stm32_qspi_priv *priv, unsigned int cs)
+{
+	clrsetbits_le32(&priv->regs->cr, STM32_QSPI_CR_FSEL,
+			cs ? STM32_QSPI_CR_FSEL : 0);
+}
+
 static unsigned int _stm32_qspi_gen_ccr(struct stm32_qspi_priv *priv)
 {
 	unsigned int ccr_reg = 0;
@@ -497,10 +505,17 @@ static int stm32_qspi_claim_bus(struct udevice *dev)
 	struct stm32_qspi_priv *priv;
 	struct udevice *bus;
 	struct spi_flash *flash;
+	struct dm_spi_slave_platdata *slave_plat;
 
 	bus = dev->parent;
 	priv = dev_get_priv(bus);
 	flash = dev_get_uclass_priv(dev);
+	slave_plat = dev_get_parent_platdata(dev);
+
+	if (slave_plat->cs >= STM32_MAX_NORCHIP)
+		return -ENODEV;
+
+	_stm32_qspi_set_cs(priv, slave_plat->cs);
 
 	_stm32_qspi_set_flash_size(priv, flash->size);
 
-- 
1.9.1

[U-Boot] [PATCH v2 07/10] spi: stm32_qspi: Use dev_read_xxx API

[Patrice Chotard]

Use dev_read_xxx() instead of old manner fdt_xxx() API

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---

Changes in v2: None

 drivers/spi/stm32_qspi.c | 17 ++++++-----------
 1 file changed, 6 insertions(+), 11 deletions(-)

diff --git a/drivers/spi/stm32_qspi.c b/drivers/spi/stm32_qspi.c
index 56ea5911239a..62875e2e4c89 100644
--- a/drivers/spi/stm32_qspi.c
+++ b/drivers/spi/stm32_qspi.c
@@ -16,8 +16,7 @@
 #include <spi_flash.h>
 #include <asm/io.h>
 #include <asm/arch/stm32.h>
-
-DECLARE_GLOBAL_DATA_PTR;
+#include <linux/ioport.h>
 
 struct stm32_qspi_regs {
 	u32 cr;		/* 0x00 */
@@ -421,27 +420,23 @@ static int _stm32_qspi_xfer(struct stm32_qspi_priv *priv,
 
 static int stm32_qspi_ofdata_to_platdata(struct udevice *bus)
 {
-	struct fdt_resource res_regs, res_mem;
+	struct resource res_regs, res_mem;
 	struct stm32_qspi_platdata *plat = bus->platdata;
-	const void *blob = gd->fdt_blob;
-	int node = dev_of_offset(bus);
 	int ret;
 
-	ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
-				     "qspi", &res_regs);
+	ret = dev_read_resource_byname(bus, "qspi", &res_regs);
 	if (ret) {
 		debug("Error: can't get regs base addresses(ret = %d)!\n", ret);
 		return -ENOMEM;
 	}
-	ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
-				     "qspi_mm", &res_mem);
+	ret = dev_read_resource_byname(bus, "qspi_mm", &res_mem);
 	if (ret) {
 		debug("Error: can't get mmap base address(ret = %d)!\n", ret);
 		return -ENOMEM;
 	}
 
-	plat->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
-					STM32_QSPI_DEFAULT_SCK_FREQ);
+	plat->max_hz = dev_read_u32_default(bus, "spi-max-frequency",
+					    STM32_QSPI_DEFAULT_SCK_FREQ);
 
 	plat->base = res_regs.start;
 	plat->memory_map = res_mem.start;
-- 
1.9.1

[U-Boot] [PATCH v2 08/10] spi: stm32_qspi: Add reset support

[Patrice Chotard]

In some situation, QSPI controller is already configured by an early
boot stage, adding reset support will insure that QSPI controller is
started from a pristine state.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---

Changes in v2: None

 drivers/spi/stm32_qspi.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/spi/stm32_qspi.c b/drivers/spi/stm32_qspi.c
index 62875e2e4c89..f6cc35336320 100644
--- a/drivers/spi/stm32_qspi.c
+++ b/drivers/spi/stm32_qspi.c
@@ -12,6 +12,7 @@
 #include <dm.h>
 #include <errno.h>
 #include <malloc.h>
+#include <reset.h>
 #include <spi.h>
 #include <spi_flash.h>
 #include <asm/io.h>
@@ -457,6 +458,7 @@ static int stm32_qspi_probe(struct udevice *bus)
 	struct stm32_qspi_priv *priv = dev_get_priv(bus);
 	struct dm_spi_bus *dm_spi_bus;
 	struct clk clk;
+	struct reset_ctl reset_ctl;
 	int ret;
 
 	dm_spi_bus = bus->uclass_priv;
@@ -484,6 +486,19 @@ static int stm32_qspi_probe(struct udevice *bus)
 		return priv->clock_rate;
 	}
 
+	ret = reset_get_by_index(bus, 0, &reset_ctl);
+	if (ret) {
+		if (ret != -ENOENT) {
+			dev_err(bus, "failed to get reset\n");
+			clk_disable(&clk);
+			return ret;
+		}
+	} else {
+		/* Reset QSPI controller */
+		reset_assert(&reset_ctl);
+		udelay(2);
+		reset_deassert(&reset_ctl);
+	}
 
 	setbits_le32(&priv->regs->cr, STM32_QSPI_CR_SSHIFT);
 
-- 
1.9.1

[U-Boot] [PATCH v2 09/10] ARM: dts: stm32: Add quadspi reset for stm32f746

[Patrice Chotard]

Add missing reset property in quadspi node.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---

Changes in v2: None

 arch/arm/dts/stm32f746.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi
index 8581df9a2778..4845279ccfca 100644
--- a/arch/arm/dts/stm32f746.dtsi
+++ b/arch/arm/dts/stm32f746.dtsi
@@ -92,6 +92,7 @@
 			interrupts = <92>;
 			spi-max-frequency = <108000000>;
 			clocks = <&rcc 0 STM32F7_AHB3_CLOCK(QSPI)>;
+			resets = <&rcc STM32F7_AHB3_RESET(QSPI)>;
 			status = "disabled";
 		};
 		usart1: serial at 40011000 {
-- 
1.9.1

[U-Boot] [PATCH v2 10/10] ARM: dts: stm32: Update qspi bindings for stm32f746

[Patrice Chotard]

Align qspi bindings following kernel dt-bindings
Documentation/devicetree/bindings/mtd/stm32-quadspi.txt
from kernel v4.17-rc1.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---

Changes in v2:
 _ remove "update mode management" patch, will be reworked and
   submitted separately

 arch/arm/dts/stm32f746.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi
index 4845279ccfca..afa7832f8936 100644
--- a/arch/arm/dts/stm32f746.dtsi
+++ b/arch/arm/dts/stm32f746.dtsi
@@ -88,7 +88,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>;
-			reg-names = "QuadSPI", "QuadSPI-memory";
+			reg-names = "qspi", "qspi_mm";
 			interrupts = <92>;
 			spi-max-frequency = <108000000>;
 			clocks = <&rcc 0 STM32F7_AHB3_CLOCK(QSPI)>;
-- 
1.9.1

[U-Boot] [PATCH v2 00/10] Update STM32 QSPI driver

[Jagan Teki]

On Mon, May 14, 2018 at 7:12 PM, Patrice Chotard <patrice.chotard@st.com> wrote:
> This series :
>   _ removes useless CONFIG_CLK flag
>   _ fixes checkpatch warnings
>   _ sorts include files in alphabetical order
>   _ align DT bindings with kernel in DT and in driver code
>   _ add chip select management
>   _ uses dev_read_xxx API
>   _ add reset support
>
>
> Changes in v2:
>  _ remove "update mode management" patch, will be reworked and
>    submitted separately
>
> Christophe Kerello (3):
>   spi: stm32_qspi: Align reg-names with kernel 4.12 RC1
>   spi: stm32_qspi: Add st,stm32f469-qspi compatible string
>   spi: stm32_qspi: Add chip select management
>
> Patrice Chotard (6):
>   spi: stm32_qspi: Remove CONFIG_CLK flag
>   spi: stm32_qspi: Sort include files alphabetically
>   spi: stm32_qspi: Use dev_read_xxx API
>   spi: stm32_qspi: Add reset support
>   ARM: dts: stm32: Add quadspi reset for stm32f746
>   ARM: dts: stm32: Update qspi bindings for stm32f746

Reviewed-by: Jagan Teki <jagan@openedev.com>

Applied to u-boot-spi/master