From: Rishabh Bhatnagar <rishabhb@codeaurora.org> To: linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-arm@lists.infradead.org, tsoni@codeaurora.org, ckadabi@codeaurora.org, evgreen@chromium.org, robh@kernel.org, andy.shevchenko@gmail.com, Rishabh Bhatnagar <rishabhb@codeaurora.org> Subject: [PATCH v8 1/2] dt-bindings: Documentation for qcom, llcc Date: Wed, 23 May 2018 17:35:20 -0700 [thread overview] Message-ID: <1527122121-31452-2-git-send-email-rishabhb@codeaurora.org> (raw) In-Reply-To: <1527122121-31452-1-git-send-email-rishabhb@codeaurora.org> Documentation for last level cache controller device tree bindings, client bindings usage examples. Signed-off-by: Channagoud Kadabi <ckadabi@codeaurora.org> Signed-off-by: Rishabh Bhatnagar <rishabhb@codeaurora.org> Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Rob Herring <robh@kernel.org> --- .../devicetree/bindings/arm/msm/qcom,llcc.txt | 26 ++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt new file mode 100644 index 0000000..5e85749 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt @@ -0,0 +1,26 @@ +== Introduction== + +LLCC (Last Level Cache Controller) provides last level of cache memory in SOC, +that can be shared by multiple clients. Clients here are different cores in the +SOC, the idea is to minimize the local caches at the clients and migrate to +common pool of memory. Cache memory is divided into partitions called slices +which are assigned to clients. Clients can query the slice details, activate +and deactivate them. + +Properties: +- compatible: + Usage: required + Value type: <string> + Definition: must be "qcom,sdm845-llcc" + +- reg: + Usage: required + Value Type: <prop-encoded-array> + Definition: Start address and the the size of the register region. + +Example: + + cache-controller@1100000 { + compatible = "qcom,sdm845-llcc"; + reg = <0x1100000 0x250000>; + }; -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
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From: rishabhb@codeaurora.org (Rishabh Bhatnagar) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v8 1/2] dt-bindings: Documentation for qcom, llcc Date: Wed, 23 May 2018 17:35:20 -0700 [thread overview] Message-ID: <1527122121-31452-2-git-send-email-rishabhb@codeaurora.org> (raw) In-Reply-To: <1527122121-31452-1-git-send-email-rishabhb@codeaurora.org> Documentation for last level cache controller device tree bindings, client bindings usage examples. Signed-off-by: Channagoud Kadabi <ckadabi@codeaurora.org> Signed-off-by: Rishabh Bhatnagar <rishabhb@codeaurora.org> Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Rob Herring <robh@kernel.org> --- .../devicetree/bindings/arm/msm/qcom,llcc.txt | 26 ++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt new file mode 100644 index 0000000..5e85749 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt @@ -0,0 +1,26 @@ +== Introduction== + +LLCC (Last Level Cache Controller) provides last level of cache memory in SOC, +that can be shared by multiple clients. Clients here are different cores in the +SOC, the idea is to minimize the local caches at the clients and migrate to +common pool of memory. Cache memory is divided into partitions called slices +which are assigned to clients. Clients can query the slice details, activate +and deactivate them. + +Properties: +- compatible: + Usage: required + Value type: <string> + Definition: must be "qcom,sdm845-llcc" + +- reg: + Usage: required + Value Type: <prop-encoded-array> + Definition: Start address and the the size of the register region. + +Example: + + cache-controller at 1100000 { + compatible = "qcom,sdm845-llcc"; + reg = <0x1100000 0x250000>; + }; -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2018-05-24 0:35 UTC|newest] Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-05-24 0:35 [PATCH v8 0/2] SDM845 System Cache Driver Rishabh Bhatnagar 2018-05-24 0:35 ` Rishabh Bhatnagar 2018-05-24 0:35 ` Rishabh Bhatnagar [this message] 2018-05-24 0:35 ` [PATCH v8 1/2] dt-bindings: Documentation for qcom, llcc Rishabh Bhatnagar 2018-06-22 17:07 ` Bjorn Andersson 2018-06-22 17:07 ` Bjorn Andersson 2018-05-24 0:35 ` [PATCH v8 2/2] drivers: soc: Add LLCC driver Rishabh Bhatnagar 2018-05-24 0:35 ` Rishabh Bhatnagar 2018-06-22 17:13 ` Bjorn Andersson 2018-06-22 17:13 ` Bjorn Andersson 2018-06-04 16:18 ` [PATCH v8 0/2] SDM845 System Cache Driver rishabhb 2018-06-04 16:18 ` rishabhb at codeaurora.org
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