* [PATCH v3 0/8] Add support for mediatek SOC MT2712 @ 2018-05-25 2:34 ` stu.hsieh 0 siblings, 0 replies; 66+ messages in thread From: stu.hsieh @ 2018-05-25 2:34 UTC (permalink / raw) To: CK Hu, Philipp Zabel Cc: David Airlie, Rob Herring, Mark Rutland, Matthias Brugger, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, srv_heupstream, Stu Hsieh From: Stu Hsieh <stu.hsieh@mediatek.com> This patch add support for the Mediatek MT2712 DISP subsystem. MT2712 is base on MT8173, there are some difference as following: MT2712 support three disp output(two ovl and one rdma) Change in v3: - Added patch for ddp component AAL1 - Added patch for ddp component OD1 - Added patch for ddp component PWM2 - Added patch to create third ddp path - Rebase patch "support maximum 64 mutex mod" before "Add support for mediatek SOC MT2712" - Rebase patch "add connection from OD1 to RDMA1" before "Add support for mediatek SOC MT2712" - Remove two definition about RDMA0 and RDMA2 - Change the definition about mutex module from bitwise to index Changes in v2: - update dt-bindings for mt2712 - Added patch to connection from OD1 to RDMA1 - Added patch to support maximum 64 mutex mod - rewrite mutex mod condition for reducing one byte - Change the component name AAL/OD to AAL0/OD0 for naming consistency - Move the compatible infomation about dpi to other patch which modify the dpi driver for mt2712 Stu Hsieh (8): drm/mediatek: update dt-bindings for mt2712 drm/mediatek: support maximum 64 mutex mod drm/mediatek: add connection from OD1 to RDMA1 drm/mediatek: add ddp component AAL1 drm/mediatek: add ddp component OD1 drm/mediatek: add ddp component PWM2 drm/mediatek: Add support for mediatek SOC MT2712 drm/mediatek: add third ddp path .../bindings/display/mediatek/mediatek,disp.txt | 2 +- drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 124 +++++++++++++++------ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 8 +- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 7 +- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 47 +++++++- drivers/gpu/drm/mediatek/mtk_drm_drv.h | 7 +- 6 files changed, 155 insertions(+), 40 deletions(-) -- 2.12.5 ^ permalink raw reply [flat|nested] 66+ messages in thread
* [PATCH v3 0/8] Add support for mediatek SOC MT2712 @ 2018-05-25 2:34 ` stu.hsieh 0 siblings, 0 replies; 66+ messages in thread From: stu.hsieh at mediatek.com @ 2018-05-25 2:34 UTC (permalink / raw) To: linux-arm-kernel From: Stu Hsieh <stu.hsieh@mediatek.com> This patch add support for the Mediatek MT2712 DISP subsystem. MT2712 is base on MT8173, there are some difference as following: MT2712 support three disp output(two ovl and one rdma) Change in v3: - Added patch for ddp component AAL1 - Added patch for ddp component OD1 - Added patch for ddp component PWM2 - Added patch to create third ddp path - Rebase patch "support maximum 64 mutex mod" before "Add support for mediatek SOC MT2712" - Rebase patch "add connection from OD1 to RDMA1" before "Add support for mediatek SOC MT2712" - Remove two definition about RDMA0 and RDMA2 - Change the definition about mutex module from bitwise to index Changes in v2: - update dt-bindings for mt2712 - Added patch to connection from OD1 to RDMA1 - Added patch to support maximum 64 mutex mod - rewrite mutex mod condition for reducing one byte - Change the component name AAL/OD to AAL0/OD0 for naming consistency - Move the compatible infomation about dpi to other patch which modify the dpi driver for mt2712 Stu Hsieh (8): drm/mediatek: update dt-bindings for mt2712 drm/mediatek: support maximum 64 mutex mod drm/mediatek: add connection from OD1 to RDMA1 drm/mediatek: add ddp component AAL1 drm/mediatek: add ddp component OD1 drm/mediatek: add ddp component PWM2 drm/mediatek: Add support for mediatek SOC MT2712 drm/mediatek: add third ddp path .../bindings/display/mediatek/mediatek,disp.txt | 2 +- drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 124 +++++++++++++++------ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 8 +- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 7 +- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 47 +++++++- drivers/gpu/drm/mediatek/mtk_drm_drv.h | 7 +- 6 files changed, 155 insertions(+), 40 deletions(-) -- 2.12.5 ^ permalink raw reply [flat|nested] 66+ messages in thread
* [PATCH v3 0/8] Add support for mediatek SOC MT2712 @ 2018-05-25 2:34 ` stu.hsieh 0 siblings, 0 replies; 66+ messages in thread From: stu.hsieh @ 2018-05-25 2:34 UTC (permalink / raw) To: CK Hu, Philipp Zabel Cc: Mark Rutland, devicetree, srv_heupstream, David Airlie, linux-kernel, dri-devel, Rob Herring, linux-mediatek, Stu Hsieh, Matthias Brugger, linux-arm-kernel From: Stu Hsieh <stu.hsieh@mediatek.com> This patch add support for the Mediatek MT2712 DISP subsystem. MT2712 is base on MT8173, there are some difference as following: MT2712 support three disp output(two ovl and one rdma) Change in v3: - Added patch for ddp component AAL1 - Added patch for ddp component OD1 - Added patch for ddp component PWM2 - Added patch to create third ddp path - Rebase patch "support maximum 64 mutex mod" before "Add support for mediatek SOC MT2712" - Rebase patch "add connection from OD1 to RDMA1" before "Add support for mediatek SOC MT2712" - Remove two definition about RDMA0 and RDMA2 - Change the definition about mutex module from bitwise to index Changes in v2: - update dt-bindings for mt2712 - Added patch to connection from OD1 to RDMA1 - Added patch to support maximum 64 mutex mod - rewrite mutex mod condition for reducing one byte - Change the component name AAL/OD to AAL0/OD0 for naming consistency - Move the compatible infomation about dpi to other patch which modify the dpi driver for mt2712 Stu Hsieh (8): drm/mediatek: update dt-bindings for mt2712 drm/mediatek: support maximum 64 mutex mod drm/mediatek: add connection from OD1 to RDMA1 drm/mediatek: add ddp component AAL1 drm/mediatek: add ddp component OD1 drm/mediatek: add ddp component PWM2 drm/mediatek: Add support for mediatek SOC MT2712 drm/mediatek: add third ddp path .../bindings/display/mediatek/mediatek,disp.txt | 2 +- drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 124 +++++++++++++++------ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 8 +- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 7 +- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 47 +++++++- drivers/gpu/drm/mediatek/mtk_drm_drv.h | 7 +- 6 files changed, 155 insertions(+), 40 deletions(-) -- 2.12.5 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 66+ messages in thread
* [PATCH v3 1/8] drm/mediatek: update dt-bindings for mt2712 2018-05-25 2:34 ` stu.hsieh (?) @ 2018-05-25 2:34 ` stu.hsieh -1 siblings, 0 replies; 66+ messages in thread From: stu.hsieh @ 2018-05-25 2:34 UTC (permalink / raw) To: CK Hu, Philipp Zabel Cc: David Airlie, Rob Herring, Mark Rutland, Matthias Brugger, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, srv_heupstream, Stu Hsieh From: Stu Hsieh <stu.hsieh@mediatek.com> Update device tree binding documentation for the display subsystem for Mediatek MT2712 SoCs. Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> --- Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt index 383183a89164..8469de510001 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt @@ -40,7 +40,7 @@ Required properties (all function blocks): "mediatek,<chip>-dpi" - DPI controller, see mediatek,dpi.txt "mediatek,<chip>-disp-mutex" - display mutex "mediatek,<chip>-disp-od" - overdrive - the supported chips are mt2701 and mt8173. + the supported chips are mt2701, mt2712 and mt8173. - reg: Physical base address and length of the function block register space - interrupts: The interrupt signal from the function block (required, except for merge and split function blocks). -- 2.12.5 ^ permalink raw reply related [flat|nested] 66+ messages in thread
* [PATCH v3 1/8] drm/mediatek: update dt-bindings for mt2712 @ 2018-05-25 2:34 ` stu.hsieh 0 siblings, 0 replies; 66+ messages in thread From: stu.hsieh at mediatek.com @ 2018-05-25 2:34 UTC (permalink / raw) To: linux-arm-kernel From: Stu Hsieh <stu.hsieh@mediatek.com> Update device tree binding documentation for the display subsystem for Mediatek MT2712 SoCs. Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> --- Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt index 383183a89164..8469de510001 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt @@ -40,7 +40,7 @@ Required properties (all function blocks): "mediatek,<chip>-dpi" - DPI controller, see mediatek,dpi.txt "mediatek,<chip>-disp-mutex" - display mutex "mediatek,<chip>-disp-od" - overdrive - the supported chips are mt2701 and mt8173. + the supported chips are mt2701, mt2712 and mt8173. - reg: Physical base address and length of the function block register space - interrupts: The interrupt signal from the function block (required, except for merge and split function blocks). -- 2.12.5 ^ permalink raw reply related [flat|nested] 66+ messages in thread
* [PATCH v3 1/8] drm/mediatek: update dt-bindings for mt2712 @ 2018-05-25 2:34 ` stu.hsieh 0 siblings, 0 replies; 66+ messages in thread From: stu.hsieh @ 2018-05-25 2:34 UTC (permalink / raw) To: CK Hu, Philipp Zabel Cc: Mark Rutland, devicetree, srv_heupstream, David Airlie, linux-kernel, dri-devel, Rob Herring, linux-mediatek, Stu Hsieh, Matthias Brugger, linux-arm-kernel From: Stu Hsieh <stu.hsieh@mediatek.com> Update device tree binding documentation for the display subsystem for Mediatek MT2712 SoCs. Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> --- Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt index 383183a89164..8469de510001 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt @@ -40,7 +40,7 @@ Required properties (all function blocks): "mediatek,<chip>-dpi" - DPI controller, see mediatek,dpi.txt "mediatek,<chip>-disp-mutex" - display mutex "mediatek,<chip>-disp-od" - overdrive - the supported chips are mt2701 and mt8173. + the supported chips are mt2701, mt2712 and mt8173. - reg: Physical base address and length of the function block register space - interrupts: The interrupt signal from the function block (required, except for merge and split function blocks). -- 2.12.5 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 66+ messages in thread
* Re: [PATCH v3 1/8] drm/mediatek: update dt-bindings for mt2712 2018-05-25 2:34 ` stu.hsieh (?) @ 2018-05-25 3:18 ` CK Hu -1 siblings, 0 replies; 66+ messages in thread From: CK Hu @ 2018-05-25 3:18 UTC (permalink / raw) To: stu.hsieh Cc: Philipp Zabel, David Airlie, Rob Herring, Mark Rutland, Matthias Brugger, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, srv_heupstream Hi, Stu: On Fri, 2018-05-25 at 10:34 +0800, stu.hsieh@mediatek.com wrote: > From: Stu Hsieh <stu.hsieh@mediatek.com> > > Update device tree binding documentation for the display subsystem for > Mediatek MT2712 SoCs. > I've acked v2 of this patch and v3 is the same as v2, so you should keep my ack in commit message. Regards, CK > Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> > --- > Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > index 383183a89164..8469de510001 100644 > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > @@ -40,7 +40,7 @@ Required properties (all function blocks): > "mediatek,<chip>-dpi" - DPI controller, see mediatek,dpi.txt > "mediatek,<chip>-disp-mutex" - display mutex > "mediatek,<chip>-disp-od" - overdrive > - the supported chips are mt2701 and mt8173. > + the supported chips are mt2701, mt2712 and mt8173. > - reg: Physical base address and length of the function block register space > - interrupts: The interrupt signal from the function block (required, except for > merge and split function blocks). ^ permalink raw reply [flat|nested] 66+ messages in thread
* [PATCH v3 1/8] drm/mediatek: update dt-bindings for mt2712 @ 2018-05-25 3:18 ` CK Hu 0 siblings, 0 replies; 66+ messages in thread From: CK Hu @ 2018-05-25 3:18 UTC (permalink / raw) To: linux-arm-kernel Hi, Stu: On Fri, 2018-05-25 at 10:34 +0800, stu.hsieh at mediatek.com wrote: > From: Stu Hsieh <stu.hsieh@mediatek.com> > > Update device tree binding documentation for the display subsystem for > Mediatek MT2712 SoCs. > I've acked v2 of this patch and v3 is the same as v2, so you should keep my ack in commit message. Regards, CK > Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> > --- > Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > index 383183a89164..8469de510001 100644 > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > @@ -40,7 +40,7 @@ Required properties (all function blocks): > "mediatek,<chip>-dpi" - DPI controller, see mediatek,dpi.txt > "mediatek,<chip>-disp-mutex" - display mutex > "mediatek,<chip>-disp-od" - overdrive > - the supported chips are mt2701 and mt8173. > + the supported chips are mt2701, mt2712 and mt8173. > - reg: Physical base address and length of the function block register space > - interrupts: The interrupt signal from the function block (required, except for > merge and split function blocks). ^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [PATCH v3 1/8] drm/mediatek: update dt-bindings for mt2712 @ 2018-05-25 3:18 ` CK Hu 0 siblings, 0 replies; 66+ messages in thread From: CK Hu @ 2018-05-25 3:18 UTC (permalink / raw) To: stu.hsieh Cc: Mark Rutland, devicetree, srv_heupstream, David Airlie, linux-kernel, dri-devel, Rob Herring, linux-mediatek, Matthias Brugger, linux-arm-kernel Hi, Stu: On Fri, 2018-05-25 at 10:34 +0800, stu.hsieh@mediatek.com wrote: > From: Stu Hsieh <stu.hsieh@mediatek.com> > > Update device tree binding documentation for the display subsystem for > Mediatek MT2712 SoCs. > I've acked v2 of this patch and v3 is the same as v2, so you should keep my ack in commit message. Regards, CK > Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> > --- > Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > index 383183a89164..8469de510001 100644 > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > @@ -40,7 +40,7 @@ Required properties (all function blocks): > "mediatek,<chip>-dpi" - DPI controller, see mediatek,dpi.txt > "mediatek,<chip>-disp-mutex" - display mutex > "mediatek,<chip>-disp-od" - overdrive > - the supported chips are mt2701 and mt8173. > + the supported chips are mt2701, mt2712 and mt8173. > - reg: Physical base address and length of the function block register space > - interrupts: The interrupt signal from the function block (required, except for > merge and split function blocks). _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [PATCH v3 1/8] drm/mediatek: update dt-bindings for mt2712 2018-05-25 3:18 ` CK Hu (?) @ 2018-05-25 9:20 ` Stu Hsieh -1 siblings, 0 replies; 66+ messages in thread From: Stu Hsieh @ 2018-05-25 9:20 UTC (permalink / raw) To: CK Hu Cc: Philipp Zabel, David Airlie, Rob Herring, Mark Rutland, Matthias Brugger, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, srv_heupstream Hi, CK: On Fri, 2018-05-25 at 11:18 +0800, CK Hu wrote: > Hi, Stu: > > On Fri, 2018-05-25 at 10:34 +0800, stu.hsieh@mediatek.com wrote: > > From: Stu Hsieh <stu.hsieh@mediatek.com> > > > > Update device tree binding documentation for the display subsystem for > > Mediatek MT2712 SoCs. > > > > I've acked v2 of this patch and v3 is the same as v2, so you should keep > my ack in commit message. > > Regards, > CK OK Regards, Stu > > > Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> > > --- > > Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > > index 383183a89164..8469de510001 100644 > > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > > @@ -40,7 +40,7 @@ Required properties (all function blocks): > > "mediatek,<chip>-dpi" - DPI controller, see mediatek,dpi.txt > > "mediatek,<chip>-disp-mutex" - display mutex > > "mediatek,<chip>-disp-od" - overdrive > > - the supported chips are mt2701 and mt8173. > > + the supported chips are mt2701, mt2712 and mt8173. > > - reg: Physical base address and length of the function block register space > > - interrupts: The interrupt signal from the function block (required, except for > > merge and split function blocks). > > ^ permalink raw reply [flat|nested] 66+ messages in thread
* [PATCH v3 1/8] drm/mediatek: update dt-bindings for mt2712 @ 2018-05-25 9:20 ` Stu Hsieh 0 siblings, 0 replies; 66+ messages in thread From: Stu Hsieh @ 2018-05-25 9:20 UTC (permalink / raw) To: linux-arm-kernel Hi, CK: On Fri, 2018-05-25 at 11:18 +0800, CK Hu wrote: > Hi, Stu: > > On Fri, 2018-05-25 at 10:34 +0800, stu.hsieh at mediatek.com wrote: > > From: Stu Hsieh <stu.hsieh@mediatek.com> > > > > Update device tree binding documentation for the display subsystem for > > Mediatek MT2712 SoCs. > > > > I've acked v2 of this patch and v3 is the same as v2, so you should keep > my ack in commit message. > > Regards, > CK OK Regards, Stu > > > Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> > > --- > > Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > > index 383183a89164..8469de510001 100644 > > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > > @@ -40,7 +40,7 @@ Required properties (all function blocks): > > "mediatek,<chip>-dpi" - DPI controller, see mediatek,dpi.txt > > "mediatek,<chip>-disp-mutex" - display mutex > > "mediatek,<chip>-disp-od" - overdrive > > - the supported chips are mt2701 and mt8173. > > + the supported chips are mt2701, mt2712 and mt8173. > > - reg: Physical base address and length of the function block register space > > - interrupts: The interrupt signal from the function block (required, except for > > merge and split function blocks). > > ^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [PATCH v3 1/8] drm/mediatek: update dt-bindings for mt2712 @ 2018-05-25 9:20 ` Stu Hsieh 0 siblings, 0 replies; 66+ messages in thread From: Stu Hsieh @ 2018-05-25 9:20 UTC (permalink / raw) To: CK Hu Cc: Philipp Zabel, David Airlie, Rob Herring, Mark Rutland, Matthias Brugger, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, srv_heupstream Hi, CK: On Fri, 2018-05-25 at 11:18 +0800, CK Hu wrote: > Hi, Stu: > > On Fri, 2018-05-25 at 10:34 +0800, stu.hsieh@mediatek.com wrote: > > From: Stu Hsieh <stu.hsieh@mediatek.com> > > > > Update device tree binding documentation for the display subsystem for > > Mediatek MT2712 SoCs. > > > > I've acked v2 of this patch and v3 is the same as v2, so you should keep > my ack in commit message. > > Regards, > CK OK Regards, Stu > > > Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> > > --- > > Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > > index 383183a89164..8469de510001 100644 > > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > > @@ -40,7 +40,7 @@ Required properties (all function blocks): > > "mediatek,<chip>-dpi" - DPI controller, see mediatek,dpi.txt > > "mediatek,<chip>-disp-mutex" - display mutex > > "mediatek,<chip>-disp-od" - overdrive > > - the supported chips are mt2701 and mt8173. > > + the supported chips are mt2701, mt2712 and mt8173. > > - reg: Physical base address and length of the function block register space > > - interrupts: The interrupt signal from the function block (required, except for > > merge and split function blocks). > > ^ permalink raw reply [flat|nested] 66+ messages in thread
* [PATCH v3 2/8] drm/mediatek: support maximum 64 mutex mod 2018-05-25 2:34 ` stu.hsieh (?) @ 2018-05-25 2:34 ` stu.hsieh -1 siblings, 0 replies; 66+ messages in thread From: stu.hsieh @ 2018-05-25 2:34 UTC (permalink / raw) To: CK Hu, Philipp Zabel Cc: David Airlie, Rob Herring, Mark Rutland, Matthias Brugger, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, srv_heupstream, Stu Hsieh From: Stu Hsieh <stu.hsieh@mediatek.com> This patch support that if modules more than 32, add index more than 31 when using DISP_REG_MUTEX_MOD2 bit Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> --- drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 75 +++++++++++++++++++++------------- 1 file changed, 47 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c index 8130f3dab661..47ffa240bd25 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c @@ -41,31 +41,32 @@ #define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n)) #define DISP_REG_MUTEX_MOD(n) (0x2c + 0x20 * (n)) #define DISP_REG_MUTEX_SOF(n) (0x30 + 0x20 * (n)) +#define DISP_REG_MUTEX_MOD2(n) (0x34 + 0x20 * (n)) #define INT_MUTEX BIT(1) -#define MT8173_MUTEX_MOD_DISP_OVL0 BIT(11) -#define MT8173_MUTEX_MOD_DISP_OVL1 BIT(12) -#define MT8173_MUTEX_MOD_DISP_RDMA0 BIT(13) -#define MT8173_MUTEX_MOD_DISP_RDMA1 BIT(14) -#define MT8173_MUTEX_MOD_DISP_RDMA2 BIT(15) -#define MT8173_MUTEX_MOD_DISP_WDMA0 BIT(16) -#define MT8173_MUTEX_MOD_DISP_WDMA1 BIT(17) -#define MT8173_MUTEX_MOD_DISP_COLOR0 BIT(18) -#define MT8173_MUTEX_MOD_DISP_COLOR1 BIT(19) -#define MT8173_MUTEX_MOD_DISP_AAL BIT(20) -#define MT8173_MUTEX_MOD_DISP_GAMMA BIT(21) -#define MT8173_MUTEX_MOD_DISP_UFOE BIT(22) -#define MT8173_MUTEX_MOD_DISP_PWM0 BIT(23) -#define MT8173_MUTEX_MOD_DISP_PWM1 BIT(24) -#define MT8173_MUTEX_MOD_DISP_OD BIT(25) - -#define MT2701_MUTEX_MOD_DISP_OVL BIT(3) -#define MT2701_MUTEX_MOD_DISP_WDMA BIT(6) -#define MT2701_MUTEX_MOD_DISP_COLOR BIT(7) -#define MT2701_MUTEX_MOD_DISP_BLS BIT(9) -#define MT2701_MUTEX_MOD_DISP_RDMA0 BIT(10) -#define MT2701_MUTEX_MOD_DISP_RDMA1 BIT(12) +#define MT8173_MUTEX_MOD_DISP_OVL0 11 +#define MT8173_MUTEX_MOD_DISP_OVL1 12 +#define MT8173_MUTEX_MOD_DISP_RDMA0 13 +#define MT8173_MUTEX_MOD_DISP_RDMA1 14 +#define MT8173_MUTEX_MOD_DISP_RDMA2 15 +#define MT8173_MUTEX_MOD_DISP_WDMA0 16 +#define MT8173_MUTEX_MOD_DISP_WDMA1 17 +#define MT8173_MUTEX_MOD_DISP_COLOR0 18 +#define MT8173_MUTEX_MOD_DISP_COLOR1 19 +#define MT8173_MUTEX_MOD_DISP_AAL 20 +#define MT8173_MUTEX_MOD_DISP_GAMMA 21 +#define MT8173_MUTEX_MOD_DISP_UFOE 22 +#define MT8173_MUTEX_MOD_DISP_PWM0 23 +#define MT8173_MUTEX_MOD_DISP_PWM1 24 +#define MT8173_MUTEX_MOD_DISP_OD 25 + +#define MT2701_MUTEX_MOD_DISP_OVL 3 +#define MT2701_MUTEX_MOD_DISP_WDMA 6 +#define MT2701_MUTEX_MOD_DISP_COLOR 7 +#define MT2701_MUTEX_MOD_DISP_BLS 9 +#define MT2701_MUTEX_MOD_DISP_RDMA0 10 +#define MT2701_MUTEX_MOD_DISP_RDMA1 12 #define MUTEX_SOF_SINGLE_MODE 0 #define MUTEX_SOF_DSI0 1 @@ -278,6 +279,7 @@ void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex, struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, mutex[mutex->id]); unsigned int reg; + unsigned int offset; WARN_ON(&ddp->mutex[mutex->id] != mutex); @@ -292,9 +294,17 @@ void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex, reg = MUTEX_SOF_DPI0; break; default: - reg = readl_relaxed(ddp->regs + DISP_REG_MUTEX_MOD(mutex->id)); - reg |= ddp->mutex_mod[id]; - writel_relaxed(reg, ddp->regs + DISP_REG_MUTEX_MOD(mutex->id)); + if (ddp->mutex_mod[id] < 32) { + offset = DISP_REG_MUTEX_MOD(mutex->id); + reg = readl_relaxed(ddp->regs + offset); + reg |= 1 << ddp->mutex_mod[id]; + writel_relaxed(reg, ddp->regs + offset); + } else { + offset = DISP_REG_MUTEX_MOD2(mutex->id); + reg = readl_relaxed(ddp->regs + offset); + reg |= 1 << (ddp->mutex_mod[id] - 32); + writel_relaxed(reg, ddp->regs + offset); + } return; } @@ -307,6 +317,7 @@ void mtk_disp_mutex_remove_comp(struct mtk_disp_mutex *mutex, struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, mutex[mutex->id]); unsigned int reg; + unsigned int offset; WARN_ON(&ddp->mutex[mutex->id] != mutex); @@ -318,9 +329,17 @@ void mtk_disp_mutex_remove_comp(struct mtk_disp_mutex *mutex, ddp->regs + DISP_REG_MUTEX_SOF(mutex->id)); break; default: - reg = readl_relaxed(ddp->regs + DISP_REG_MUTEX_MOD(mutex->id)); - reg &= ~(ddp->mutex_mod[id]); - writel_relaxed(reg, ddp->regs + DISP_REG_MUTEX_MOD(mutex->id)); + if (ddp->mutex_mod[id] < 32) { + offset = DISP_REG_MUTEX_MOD(mutex->id); + reg = readl_relaxed(ddp->regs + offset); + reg &= ~(1 << ddp->mutex_mod[id]); + writel_relaxed(reg, ddp->regs + offset); + } else { + offset = DISP_REG_MUTEX_MOD2(mutex->id); + reg = readl_relaxed(ddp->regs + offset); + reg &= ~(1 << (ddp->mutex_mod[id] - 32)); + writel_relaxed(reg, ddp->regs + offset); + } break; } } -- 2.12.5 ^ permalink raw reply related [flat|nested] 66+ messages in thread
* [PATCH v3 2/8] drm/mediatek: support maximum 64 mutex mod @ 2018-05-25 2:34 ` stu.hsieh 0 siblings, 0 replies; 66+ messages in thread From: stu.hsieh at mediatek.com @ 2018-05-25 2:34 UTC (permalink / raw) To: linux-arm-kernel From: Stu Hsieh <stu.hsieh@mediatek.com> This patch support that if modules more than 32, add index more than 31 when using DISP_REG_MUTEX_MOD2 bit Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> --- drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 75 +++++++++++++++++++++------------- 1 file changed, 47 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c index 8130f3dab661..47ffa240bd25 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c @@ -41,31 +41,32 @@ #define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n)) #define DISP_REG_MUTEX_MOD(n) (0x2c + 0x20 * (n)) #define DISP_REG_MUTEX_SOF(n) (0x30 + 0x20 * (n)) +#define DISP_REG_MUTEX_MOD2(n) (0x34 + 0x20 * (n)) #define INT_MUTEX BIT(1) -#define MT8173_MUTEX_MOD_DISP_OVL0 BIT(11) -#define MT8173_MUTEX_MOD_DISP_OVL1 BIT(12) -#define MT8173_MUTEX_MOD_DISP_RDMA0 BIT(13) -#define MT8173_MUTEX_MOD_DISP_RDMA1 BIT(14) -#define MT8173_MUTEX_MOD_DISP_RDMA2 BIT(15) -#define MT8173_MUTEX_MOD_DISP_WDMA0 BIT(16) -#define MT8173_MUTEX_MOD_DISP_WDMA1 BIT(17) -#define MT8173_MUTEX_MOD_DISP_COLOR0 BIT(18) -#define MT8173_MUTEX_MOD_DISP_COLOR1 BIT(19) -#define MT8173_MUTEX_MOD_DISP_AAL BIT(20) -#define MT8173_MUTEX_MOD_DISP_GAMMA BIT(21) -#define MT8173_MUTEX_MOD_DISP_UFOE BIT(22) -#define MT8173_MUTEX_MOD_DISP_PWM0 BIT(23) -#define MT8173_MUTEX_MOD_DISP_PWM1 BIT(24) -#define MT8173_MUTEX_MOD_DISP_OD BIT(25) - -#define MT2701_MUTEX_MOD_DISP_OVL BIT(3) -#define MT2701_MUTEX_MOD_DISP_WDMA BIT(6) -#define MT2701_MUTEX_MOD_DISP_COLOR BIT(7) -#define MT2701_MUTEX_MOD_DISP_BLS BIT(9) -#define MT2701_MUTEX_MOD_DISP_RDMA0 BIT(10) -#define MT2701_MUTEX_MOD_DISP_RDMA1 BIT(12) +#define MT8173_MUTEX_MOD_DISP_OVL0 11 +#define MT8173_MUTEX_MOD_DISP_OVL1 12 +#define MT8173_MUTEX_MOD_DISP_RDMA0 13 +#define MT8173_MUTEX_MOD_DISP_RDMA1 14 +#define MT8173_MUTEX_MOD_DISP_RDMA2 15 +#define MT8173_MUTEX_MOD_DISP_WDMA0 16 +#define MT8173_MUTEX_MOD_DISP_WDMA1 17 +#define MT8173_MUTEX_MOD_DISP_COLOR0 18 +#define MT8173_MUTEX_MOD_DISP_COLOR1 19 +#define MT8173_MUTEX_MOD_DISP_AAL 20 +#define MT8173_MUTEX_MOD_DISP_GAMMA 21 +#define MT8173_MUTEX_MOD_DISP_UFOE 22 +#define MT8173_MUTEX_MOD_DISP_PWM0 23 +#define MT8173_MUTEX_MOD_DISP_PWM1 24 +#define MT8173_MUTEX_MOD_DISP_OD 25 + +#define MT2701_MUTEX_MOD_DISP_OVL 3 +#define MT2701_MUTEX_MOD_DISP_WDMA 6 +#define MT2701_MUTEX_MOD_DISP_COLOR 7 +#define MT2701_MUTEX_MOD_DISP_BLS 9 +#define MT2701_MUTEX_MOD_DISP_RDMA0 10 +#define MT2701_MUTEX_MOD_DISP_RDMA1 12 #define MUTEX_SOF_SINGLE_MODE 0 #define MUTEX_SOF_DSI0 1 @@ -278,6 +279,7 @@ void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex, struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, mutex[mutex->id]); unsigned int reg; + unsigned int offset; WARN_ON(&ddp->mutex[mutex->id] != mutex); @@ -292,9 +294,17 @@ void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex, reg = MUTEX_SOF_DPI0; break; default: - reg = readl_relaxed(ddp->regs + DISP_REG_MUTEX_MOD(mutex->id)); - reg |= ddp->mutex_mod[id]; - writel_relaxed(reg, ddp->regs + DISP_REG_MUTEX_MOD(mutex->id)); + if (ddp->mutex_mod[id] < 32) { + offset = DISP_REG_MUTEX_MOD(mutex->id); + reg = readl_relaxed(ddp->regs + offset); + reg |= 1 << ddp->mutex_mod[id]; + writel_relaxed(reg, ddp->regs + offset); + } else { + offset = DISP_REG_MUTEX_MOD2(mutex->id); + reg = readl_relaxed(ddp->regs + offset); + reg |= 1 << (ddp->mutex_mod[id] - 32); + writel_relaxed(reg, ddp->regs + offset); + } return; } @@ -307,6 +317,7 @@ void mtk_disp_mutex_remove_comp(struct mtk_disp_mutex *mutex, struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, mutex[mutex->id]); unsigned int reg; + unsigned int offset; WARN_ON(&ddp->mutex[mutex->id] != mutex); @@ -318,9 +329,17 @@ void mtk_disp_mutex_remove_comp(struct mtk_disp_mutex *mutex, ddp->regs + DISP_REG_MUTEX_SOF(mutex->id)); break; default: - reg = readl_relaxed(ddp->regs + DISP_REG_MUTEX_MOD(mutex->id)); - reg &= ~(ddp->mutex_mod[id]); - writel_relaxed(reg, ddp->regs + DISP_REG_MUTEX_MOD(mutex->id)); + if (ddp->mutex_mod[id] < 32) { + offset = DISP_REG_MUTEX_MOD(mutex->id); + reg = readl_relaxed(ddp->regs + offset); + reg &= ~(1 << ddp->mutex_mod[id]); + writel_relaxed(reg, ddp->regs + offset); + } else { + offset = DISP_REG_MUTEX_MOD2(mutex->id); + reg = readl_relaxed(ddp->regs + offset); + reg &= ~(1 << (ddp->mutex_mod[id] - 32)); + writel_relaxed(reg, ddp->regs + offset); + } break; } } -- 2.12.5 ^ permalink raw reply related [flat|nested] 66+ messages in thread
* [PATCH v3 2/8] drm/mediatek: support maximum 64 mutex mod @ 2018-05-25 2:34 ` stu.hsieh 0 siblings, 0 replies; 66+ messages in thread From: stu.hsieh @ 2018-05-25 2:34 UTC (permalink / raw) To: CK Hu, Philipp Zabel Cc: Mark Rutland, devicetree, srv_heupstream, David Airlie, linux-kernel, dri-devel, Rob Herring, linux-mediatek, Stu Hsieh, Matthias Brugger, linux-arm-kernel From: Stu Hsieh <stu.hsieh@mediatek.com> This patch support that if modules more than 32, add index more than 31 when using DISP_REG_MUTEX_MOD2 bit Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> --- drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 75 +++++++++++++++++++++------------- 1 file changed, 47 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c index 8130f3dab661..47ffa240bd25 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c @@ -41,31 +41,32 @@ #define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n)) #define DISP_REG_MUTEX_MOD(n) (0x2c + 0x20 * (n)) #define DISP_REG_MUTEX_SOF(n) (0x30 + 0x20 * (n)) +#define DISP_REG_MUTEX_MOD2(n) (0x34 + 0x20 * (n)) #define INT_MUTEX BIT(1) -#define MT8173_MUTEX_MOD_DISP_OVL0 BIT(11) -#define MT8173_MUTEX_MOD_DISP_OVL1 BIT(12) -#define MT8173_MUTEX_MOD_DISP_RDMA0 BIT(13) -#define MT8173_MUTEX_MOD_DISP_RDMA1 BIT(14) -#define MT8173_MUTEX_MOD_DISP_RDMA2 BIT(15) -#define MT8173_MUTEX_MOD_DISP_WDMA0 BIT(16) -#define MT8173_MUTEX_MOD_DISP_WDMA1 BIT(17) -#define MT8173_MUTEX_MOD_DISP_COLOR0 BIT(18) -#define MT8173_MUTEX_MOD_DISP_COLOR1 BIT(19) -#define MT8173_MUTEX_MOD_DISP_AAL BIT(20) -#define MT8173_MUTEX_MOD_DISP_GAMMA BIT(21) -#define MT8173_MUTEX_MOD_DISP_UFOE BIT(22) -#define MT8173_MUTEX_MOD_DISP_PWM0 BIT(23) -#define MT8173_MUTEX_MOD_DISP_PWM1 BIT(24) -#define MT8173_MUTEX_MOD_DISP_OD BIT(25) - -#define MT2701_MUTEX_MOD_DISP_OVL BIT(3) -#define MT2701_MUTEX_MOD_DISP_WDMA BIT(6) -#define MT2701_MUTEX_MOD_DISP_COLOR BIT(7) -#define MT2701_MUTEX_MOD_DISP_BLS BIT(9) -#define MT2701_MUTEX_MOD_DISP_RDMA0 BIT(10) -#define MT2701_MUTEX_MOD_DISP_RDMA1 BIT(12) +#define MT8173_MUTEX_MOD_DISP_OVL0 11 +#define MT8173_MUTEX_MOD_DISP_OVL1 12 +#define MT8173_MUTEX_MOD_DISP_RDMA0 13 +#define MT8173_MUTEX_MOD_DISP_RDMA1 14 +#define MT8173_MUTEX_MOD_DISP_RDMA2 15 +#define MT8173_MUTEX_MOD_DISP_WDMA0 16 +#define MT8173_MUTEX_MOD_DISP_WDMA1 17 +#define MT8173_MUTEX_MOD_DISP_COLOR0 18 +#define MT8173_MUTEX_MOD_DISP_COLOR1 19 +#define MT8173_MUTEX_MOD_DISP_AAL 20 +#define MT8173_MUTEX_MOD_DISP_GAMMA 21 +#define MT8173_MUTEX_MOD_DISP_UFOE 22 +#define MT8173_MUTEX_MOD_DISP_PWM0 23 +#define MT8173_MUTEX_MOD_DISP_PWM1 24 +#define MT8173_MUTEX_MOD_DISP_OD 25 + +#define MT2701_MUTEX_MOD_DISP_OVL 3 +#define MT2701_MUTEX_MOD_DISP_WDMA 6 +#define MT2701_MUTEX_MOD_DISP_COLOR 7 +#define MT2701_MUTEX_MOD_DISP_BLS 9 +#define MT2701_MUTEX_MOD_DISP_RDMA0 10 +#define MT2701_MUTEX_MOD_DISP_RDMA1 12 #define MUTEX_SOF_SINGLE_MODE 0 #define MUTEX_SOF_DSI0 1 @@ -278,6 +279,7 @@ void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex, struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, mutex[mutex->id]); unsigned int reg; + unsigned int offset; WARN_ON(&ddp->mutex[mutex->id] != mutex); @@ -292,9 +294,17 @@ void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex, reg = MUTEX_SOF_DPI0; break; default: - reg = readl_relaxed(ddp->regs + DISP_REG_MUTEX_MOD(mutex->id)); - reg |= ddp->mutex_mod[id]; - writel_relaxed(reg, ddp->regs + DISP_REG_MUTEX_MOD(mutex->id)); + if (ddp->mutex_mod[id] < 32) { + offset = DISP_REG_MUTEX_MOD(mutex->id); + reg = readl_relaxed(ddp->regs + offset); + reg |= 1 << ddp->mutex_mod[id]; + writel_relaxed(reg, ddp->regs + offset); + } else { + offset = DISP_REG_MUTEX_MOD2(mutex->id); + reg = readl_relaxed(ddp->regs + offset); + reg |= 1 << (ddp->mutex_mod[id] - 32); + writel_relaxed(reg, ddp->regs + offset); + } return; } @@ -307,6 +317,7 @@ void mtk_disp_mutex_remove_comp(struct mtk_disp_mutex *mutex, struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, mutex[mutex->id]); unsigned int reg; + unsigned int offset; WARN_ON(&ddp->mutex[mutex->id] != mutex); @@ -318,9 +329,17 @@ void mtk_disp_mutex_remove_comp(struct mtk_disp_mutex *mutex, ddp->regs + DISP_REG_MUTEX_SOF(mutex->id)); break; default: - reg = readl_relaxed(ddp->regs + DISP_REG_MUTEX_MOD(mutex->id)); - reg &= ~(ddp->mutex_mod[id]); - writel_relaxed(reg, ddp->regs + DISP_REG_MUTEX_MOD(mutex->id)); + if (ddp->mutex_mod[id] < 32) { + offset = DISP_REG_MUTEX_MOD(mutex->id); + reg = readl_relaxed(ddp->regs + offset); + reg &= ~(1 << ddp->mutex_mod[id]); + writel_relaxed(reg, ddp->regs + offset); + } else { + offset = DISP_REG_MUTEX_MOD2(mutex->id); + reg = readl_relaxed(ddp->regs + offset); + reg &= ~(1 << (ddp->mutex_mod[id] - 32)); + writel_relaxed(reg, ddp->regs + offset); + } break; } } -- 2.12.5 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 66+ messages in thread
* Re: [PATCH v3 2/8] drm/mediatek: support maximum 64 mutex mod 2018-05-25 2:34 ` stu.hsieh (?) @ 2018-05-25 3:24 ` CK Hu -1 siblings, 0 replies; 66+ messages in thread From: CK Hu @ 2018-05-25 3:24 UTC (permalink / raw) To: stu.hsieh Cc: Philipp Zabel, David Airlie, Rob Herring, Mark Rutland, Matthias Brugger, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, srv_heupstream Hi, Stu: On Fri, 2018-05-25 at 10:34 +0800, stu.hsieh@mediatek.com wrote: > From: Stu Hsieh <stu.hsieh@mediatek.com> > > This patch support that if modules more than 32, > add index more than 31 when using DISP_REG_MUTEX_MOD2 bit > Reviewed-by: CK Hu <ck.hu@mediatek.com> > Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 75 +++++++++++++++++++++------------- > 1 file changed, 47 insertions(+), 28 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > index 8130f3dab661..47ffa240bd25 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > @@ -41,31 +41,32 @@ > #define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n)) > #define DISP_REG_MUTEX_MOD(n) (0x2c + 0x20 * (n)) > #define DISP_REG_MUTEX_SOF(n) (0x30 + 0x20 * (n)) > +#define DISP_REG_MUTEX_MOD2(n) (0x34 + 0x20 * (n)) > > #define INT_MUTEX BIT(1) > > -#define MT8173_MUTEX_MOD_DISP_OVL0 BIT(11) > -#define MT8173_MUTEX_MOD_DISP_OVL1 BIT(12) > -#define MT8173_MUTEX_MOD_DISP_RDMA0 BIT(13) > -#define MT8173_MUTEX_MOD_DISP_RDMA1 BIT(14) > -#define MT8173_MUTEX_MOD_DISP_RDMA2 BIT(15) > -#define MT8173_MUTEX_MOD_DISP_WDMA0 BIT(16) > -#define MT8173_MUTEX_MOD_DISP_WDMA1 BIT(17) > -#define MT8173_MUTEX_MOD_DISP_COLOR0 BIT(18) > -#define MT8173_MUTEX_MOD_DISP_COLOR1 BIT(19) > -#define MT8173_MUTEX_MOD_DISP_AAL BIT(20) > -#define MT8173_MUTEX_MOD_DISP_GAMMA BIT(21) > -#define MT8173_MUTEX_MOD_DISP_UFOE BIT(22) > -#define MT8173_MUTEX_MOD_DISP_PWM0 BIT(23) > -#define MT8173_MUTEX_MOD_DISP_PWM1 BIT(24) > -#define MT8173_MUTEX_MOD_DISP_OD BIT(25) > - > -#define MT2701_MUTEX_MOD_DISP_OVL BIT(3) > -#define MT2701_MUTEX_MOD_DISP_WDMA BIT(6) > -#define MT2701_MUTEX_MOD_DISP_COLOR BIT(7) > -#define MT2701_MUTEX_MOD_DISP_BLS BIT(9) > -#define MT2701_MUTEX_MOD_DISP_RDMA0 BIT(10) > -#define MT2701_MUTEX_MOD_DISP_RDMA1 BIT(12) > +#define MT8173_MUTEX_MOD_DISP_OVL0 11 > +#define MT8173_MUTEX_MOD_DISP_OVL1 12 > +#define MT8173_MUTEX_MOD_DISP_RDMA0 13 > +#define MT8173_MUTEX_MOD_DISP_RDMA1 14 > +#define MT8173_MUTEX_MOD_DISP_RDMA2 15 > +#define MT8173_MUTEX_MOD_DISP_WDMA0 16 > +#define MT8173_MUTEX_MOD_DISP_WDMA1 17 > +#define MT8173_MUTEX_MOD_DISP_COLOR0 18 > +#define MT8173_MUTEX_MOD_DISP_COLOR1 19 > +#define MT8173_MUTEX_MOD_DISP_AAL 20 > +#define MT8173_MUTEX_MOD_DISP_GAMMA 21 > +#define MT8173_MUTEX_MOD_DISP_UFOE 22 > +#define MT8173_MUTEX_MOD_DISP_PWM0 23 > +#define MT8173_MUTEX_MOD_DISP_PWM1 24 > +#define MT8173_MUTEX_MOD_DISP_OD 25 > + > +#define MT2701_MUTEX_MOD_DISP_OVL 3 > +#define MT2701_MUTEX_MOD_DISP_WDMA 6 > +#define MT2701_MUTEX_MOD_DISP_COLOR 7 > +#define MT2701_MUTEX_MOD_DISP_BLS 9 > +#define MT2701_MUTEX_MOD_DISP_RDMA0 10 > +#define MT2701_MUTEX_MOD_DISP_RDMA1 12 > > #define MUTEX_SOF_SINGLE_MODE 0 > #define MUTEX_SOF_DSI0 1 > @@ -278,6 +279,7 @@ void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex, > struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, > mutex[mutex->id]); > unsigned int reg; > + unsigned int offset; > > WARN_ON(&ddp->mutex[mutex->id] != mutex); > > @@ -292,9 +294,17 @@ void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex, > reg = MUTEX_SOF_DPI0; > break; > default: > - reg = readl_relaxed(ddp->regs + DISP_REG_MUTEX_MOD(mutex->id)); > - reg |= ddp->mutex_mod[id]; > - writel_relaxed(reg, ddp->regs + DISP_REG_MUTEX_MOD(mutex->id)); > + if (ddp->mutex_mod[id] < 32) { > + offset = DISP_REG_MUTEX_MOD(mutex->id); > + reg = readl_relaxed(ddp->regs + offset); > + reg |= 1 << ddp->mutex_mod[id]; > + writel_relaxed(reg, ddp->regs + offset); > + } else { > + offset = DISP_REG_MUTEX_MOD2(mutex->id); > + reg = readl_relaxed(ddp->regs + offset); > + reg |= 1 << (ddp->mutex_mod[id] - 32); > + writel_relaxed(reg, ddp->regs + offset); > + } > return; > } > > @@ -307,6 +317,7 @@ void mtk_disp_mutex_remove_comp(struct mtk_disp_mutex *mutex, > struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, > mutex[mutex->id]); > unsigned int reg; > + unsigned int offset; > > WARN_ON(&ddp->mutex[mutex->id] != mutex); > > @@ -318,9 +329,17 @@ void mtk_disp_mutex_remove_comp(struct mtk_disp_mutex *mutex, > ddp->regs + DISP_REG_MUTEX_SOF(mutex->id)); > break; > default: > - reg = readl_relaxed(ddp->regs + DISP_REG_MUTEX_MOD(mutex->id)); > - reg &= ~(ddp->mutex_mod[id]); > - writel_relaxed(reg, ddp->regs + DISP_REG_MUTEX_MOD(mutex->id)); > + if (ddp->mutex_mod[id] < 32) { > + offset = DISP_REG_MUTEX_MOD(mutex->id); > + reg = readl_relaxed(ddp->regs + offset); > + reg &= ~(1 << ddp->mutex_mod[id]); > + writel_relaxed(reg, ddp->regs + offset); > + } else { > + offset = DISP_REG_MUTEX_MOD2(mutex->id); > + reg = readl_relaxed(ddp->regs + offset); > + reg &= ~(1 << (ddp->mutex_mod[id] - 32)); > + writel_relaxed(reg, ddp->regs + offset); > + } > break; > } > } ^ permalink raw reply [flat|nested] 66+ messages in thread
* [PATCH v3 2/8] drm/mediatek: support maximum 64 mutex mod @ 2018-05-25 3:24 ` CK Hu 0 siblings, 0 replies; 66+ messages in thread From: CK Hu @ 2018-05-25 3:24 UTC (permalink / raw) To: linux-arm-kernel Hi, Stu: On Fri, 2018-05-25 at 10:34 +0800, stu.hsieh at mediatek.com wrote: > From: Stu Hsieh <stu.hsieh@mediatek.com> > > This patch support that if modules more than 32, > add index more than 31 when using DISP_REG_MUTEX_MOD2 bit > Reviewed-by: CK Hu <ck.hu@mediatek.com> > Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 75 +++++++++++++++++++++------------- > 1 file changed, 47 insertions(+), 28 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > index 8130f3dab661..47ffa240bd25 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > @@ -41,31 +41,32 @@ > #define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n)) > #define DISP_REG_MUTEX_MOD(n) (0x2c + 0x20 * (n)) > #define DISP_REG_MUTEX_SOF(n) (0x30 + 0x20 * (n)) > +#define DISP_REG_MUTEX_MOD2(n) (0x34 + 0x20 * (n)) > > #define INT_MUTEX BIT(1) > > -#define MT8173_MUTEX_MOD_DISP_OVL0 BIT(11) > -#define MT8173_MUTEX_MOD_DISP_OVL1 BIT(12) > -#define MT8173_MUTEX_MOD_DISP_RDMA0 BIT(13) > -#define MT8173_MUTEX_MOD_DISP_RDMA1 BIT(14) > -#define MT8173_MUTEX_MOD_DISP_RDMA2 BIT(15) > -#define MT8173_MUTEX_MOD_DISP_WDMA0 BIT(16) > -#define MT8173_MUTEX_MOD_DISP_WDMA1 BIT(17) > -#define MT8173_MUTEX_MOD_DISP_COLOR0 BIT(18) > -#define MT8173_MUTEX_MOD_DISP_COLOR1 BIT(19) > -#define MT8173_MUTEX_MOD_DISP_AAL BIT(20) > -#define MT8173_MUTEX_MOD_DISP_GAMMA BIT(21) > -#define MT8173_MUTEX_MOD_DISP_UFOE BIT(22) > -#define MT8173_MUTEX_MOD_DISP_PWM0 BIT(23) > -#define MT8173_MUTEX_MOD_DISP_PWM1 BIT(24) > -#define MT8173_MUTEX_MOD_DISP_OD BIT(25) > - > -#define MT2701_MUTEX_MOD_DISP_OVL BIT(3) > -#define MT2701_MUTEX_MOD_DISP_WDMA BIT(6) > -#define MT2701_MUTEX_MOD_DISP_COLOR BIT(7) > -#define MT2701_MUTEX_MOD_DISP_BLS BIT(9) > -#define MT2701_MUTEX_MOD_DISP_RDMA0 BIT(10) > -#define MT2701_MUTEX_MOD_DISP_RDMA1 BIT(12) > +#define MT8173_MUTEX_MOD_DISP_OVL0 11 > +#define MT8173_MUTEX_MOD_DISP_OVL1 12 > +#define MT8173_MUTEX_MOD_DISP_RDMA0 13 > +#define MT8173_MUTEX_MOD_DISP_RDMA1 14 > +#define MT8173_MUTEX_MOD_DISP_RDMA2 15 > +#define MT8173_MUTEX_MOD_DISP_WDMA0 16 > +#define MT8173_MUTEX_MOD_DISP_WDMA1 17 > +#define MT8173_MUTEX_MOD_DISP_COLOR0 18 > +#define MT8173_MUTEX_MOD_DISP_COLOR1 19 > +#define MT8173_MUTEX_MOD_DISP_AAL 20 > +#define MT8173_MUTEX_MOD_DISP_GAMMA 21 > +#define MT8173_MUTEX_MOD_DISP_UFOE 22 > +#define MT8173_MUTEX_MOD_DISP_PWM0 23 > +#define MT8173_MUTEX_MOD_DISP_PWM1 24 > +#define MT8173_MUTEX_MOD_DISP_OD 25 > + > +#define MT2701_MUTEX_MOD_DISP_OVL 3 > +#define MT2701_MUTEX_MOD_DISP_WDMA 6 > +#define MT2701_MUTEX_MOD_DISP_COLOR 7 > +#define MT2701_MUTEX_MOD_DISP_BLS 9 > +#define MT2701_MUTEX_MOD_DISP_RDMA0 10 > +#define MT2701_MUTEX_MOD_DISP_RDMA1 12 > > #define MUTEX_SOF_SINGLE_MODE 0 > #define MUTEX_SOF_DSI0 1 > @@ -278,6 +279,7 @@ void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex, > struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, > mutex[mutex->id]); > unsigned int reg; > + unsigned int offset; > > WARN_ON(&ddp->mutex[mutex->id] != mutex); > > @@ -292,9 +294,17 @@ void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex, > reg = MUTEX_SOF_DPI0; > break; > default: > - reg = readl_relaxed(ddp->regs + DISP_REG_MUTEX_MOD(mutex->id)); > - reg |= ddp->mutex_mod[id]; > - writel_relaxed(reg, ddp->regs + DISP_REG_MUTEX_MOD(mutex->id)); > + if (ddp->mutex_mod[id] < 32) { > + offset = DISP_REG_MUTEX_MOD(mutex->id); > + reg = readl_relaxed(ddp->regs + offset); > + reg |= 1 << ddp->mutex_mod[id]; > + writel_relaxed(reg, ddp->regs + offset); > + } else { > + offset = DISP_REG_MUTEX_MOD2(mutex->id); > + reg = readl_relaxed(ddp->regs + offset); > + reg |= 1 << (ddp->mutex_mod[id] - 32); > + writel_relaxed(reg, ddp->regs + offset); > + } > return; > } > > @@ -307,6 +317,7 @@ void mtk_disp_mutex_remove_comp(struct mtk_disp_mutex *mutex, > struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, > mutex[mutex->id]); > unsigned int reg; > + unsigned int offset; > > WARN_ON(&ddp->mutex[mutex->id] != mutex); > > @@ -318,9 +329,17 @@ void mtk_disp_mutex_remove_comp(struct mtk_disp_mutex *mutex, > ddp->regs + DISP_REG_MUTEX_SOF(mutex->id)); > break; > default: > - reg = readl_relaxed(ddp->regs + DISP_REG_MUTEX_MOD(mutex->id)); > - reg &= ~(ddp->mutex_mod[id]); > - writel_relaxed(reg, ddp->regs + DISP_REG_MUTEX_MOD(mutex->id)); > + if (ddp->mutex_mod[id] < 32) { > + offset = DISP_REG_MUTEX_MOD(mutex->id); > + reg = readl_relaxed(ddp->regs + offset); > + reg &= ~(1 << ddp->mutex_mod[id]); > + writel_relaxed(reg, ddp->regs + offset); > + } else { > + offset = DISP_REG_MUTEX_MOD2(mutex->id); > + reg = readl_relaxed(ddp->regs + offset); > + reg &= ~(1 << (ddp->mutex_mod[id] - 32)); > + writel_relaxed(reg, ddp->regs + offset); > + } > break; > } > } ^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [PATCH v3 2/8] drm/mediatek: support maximum 64 mutex mod @ 2018-05-25 3:24 ` CK Hu 0 siblings, 0 replies; 66+ messages in thread From: CK Hu @ 2018-05-25 3:24 UTC (permalink / raw) To: stu.hsieh Cc: Mark Rutland, devicetree, srv_heupstream, David Airlie, linux-kernel, dri-devel, Rob Herring, linux-mediatek, Matthias Brugger, linux-arm-kernel Hi, Stu: On Fri, 2018-05-25 at 10:34 +0800, stu.hsieh@mediatek.com wrote: > From: Stu Hsieh <stu.hsieh@mediatek.com> > > This patch support that if modules more than 32, > add index more than 31 when using DISP_REG_MUTEX_MOD2 bit > Reviewed-by: CK Hu <ck.hu@mediatek.com> > Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 75 +++++++++++++++++++++------------- > 1 file changed, 47 insertions(+), 28 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > index 8130f3dab661..47ffa240bd25 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > @@ -41,31 +41,32 @@ > #define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n)) > #define DISP_REG_MUTEX_MOD(n) (0x2c + 0x20 * (n)) > #define DISP_REG_MUTEX_SOF(n) (0x30 + 0x20 * (n)) > +#define DISP_REG_MUTEX_MOD2(n) (0x34 + 0x20 * (n)) > > #define INT_MUTEX BIT(1) > > -#define MT8173_MUTEX_MOD_DISP_OVL0 BIT(11) > -#define MT8173_MUTEX_MOD_DISP_OVL1 BIT(12) > -#define MT8173_MUTEX_MOD_DISP_RDMA0 BIT(13) > -#define MT8173_MUTEX_MOD_DISP_RDMA1 BIT(14) > -#define MT8173_MUTEX_MOD_DISP_RDMA2 BIT(15) > -#define MT8173_MUTEX_MOD_DISP_WDMA0 BIT(16) > -#define MT8173_MUTEX_MOD_DISP_WDMA1 BIT(17) > -#define MT8173_MUTEX_MOD_DISP_COLOR0 BIT(18) > -#define MT8173_MUTEX_MOD_DISP_COLOR1 BIT(19) > -#define MT8173_MUTEX_MOD_DISP_AAL BIT(20) > -#define MT8173_MUTEX_MOD_DISP_GAMMA BIT(21) > -#define MT8173_MUTEX_MOD_DISP_UFOE BIT(22) > -#define MT8173_MUTEX_MOD_DISP_PWM0 BIT(23) > -#define MT8173_MUTEX_MOD_DISP_PWM1 BIT(24) > -#define MT8173_MUTEX_MOD_DISP_OD BIT(25) > - > -#define MT2701_MUTEX_MOD_DISP_OVL BIT(3) > -#define MT2701_MUTEX_MOD_DISP_WDMA BIT(6) > -#define MT2701_MUTEX_MOD_DISP_COLOR BIT(7) > -#define MT2701_MUTEX_MOD_DISP_BLS BIT(9) > -#define MT2701_MUTEX_MOD_DISP_RDMA0 BIT(10) > -#define MT2701_MUTEX_MOD_DISP_RDMA1 BIT(12) > +#define MT8173_MUTEX_MOD_DISP_OVL0 11 > +#define MT8173_MUTEX_MOD_DISP_OVL1 12 > +#define MT8173_MUTEX_MOD_DISP_RDMA0 13 > +#define MT8173_MUTEX_MOD_DISP_RDMA1 14 > +#define MT8173_MUTEX_MOD_DISP_RDMA2 15 > +#define MT8173_MUTEX_MOD_DISP_WDMA0 16 > +#define MT8173_MUTEX_MOD_DISP_WDMA1 17 > +#define MT8173_MUTEX_MOD_DISP_COLOR0 18 > +#define MT8173_MUTEX_MOD_DISP_COLOR1 19 > +#define MT8173_MUTEX_MOD_DISP_AAL 20 > +#define MT8173_MUTEX_MOD_DISP_GAMMA 21 > +#define MT8173_MUTEX_MOD_DISP_UFOE 22 > +#define MT8173_MUTEX_MOD_DISP_PWM0 23 > +#define MT8173_MUTEX_MOD_DISP_PWM1 24 > +#define MT8173_MUTEX_MOD_DISP_OD 25 > + > +#define MT2701_MUTEX_MOD_DISP_OVL 3 > +#define MT2701_MUTEX_MOD_DISP_WDMA 6 > +#define MT2701_MUTEX_MOD_DISP_COLOR 7 > +#define MT2701_MUTEX_MOD_DISP_BLS 9 > +#define MT2701_MUTEX_MOD_DISP_RDMA0 10 > +#define MT2701_MUTEX_MOD_DISP_RDMA1 12 > > #define MUTEX_SOF_SINGLE_MODE 0 > #define MUTEX_SOF_DSI0 1 > @@ -278,6 +279,7 @@ void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex, > struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, > mutex[mutex->id]); > unsigned int reg; > + unsigned int offset; > > WARN_ON(&ddp->mutex[mutex->id] != mutex); > > @@ -292,9 +294,17 @@ void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex, > reg = MUTEX_SOF_DPI0; > break; > default: > - reg = readl_relaxed(ddp->regs + DISP_REG_MUTEX_MOD(mutex->id)); > - reg |= ddp->mutex_mod[id]; > - writel_relaxed(reg, ddp->regs + DISP_REG_MUTEX_MOD(mutex->id)); > + if (ddp->mutex_mod[id] < 32) { > + offset = DISP_REG_MUTEX_MOD(mutex->id); > + reg = readl_relaxed(ddp->regs + offset); > + reg |= 1 << ddp->mutex_mod[id]; > + writel_relaxed(reg, ddp->regs + offset); > + } else { > + offset = DISP_REG_MUTEX_MOD2(mutex->id); > + reg = readl_relaxed(ddp->regs + offset); > + reg |= 1 << (ddp->mutex_mod[id] - 32); > + writel_relaxed(reg, ddp->regs + offset); > + } > return; > } > > @@ -307,6 +317,7 @@ void mtk_disp_mutex_remove_comp(struct mtk_disp_mutex *mutex, > struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, > mutex[mutex->id]); > unsigned int reg; > + unsigned int offset; > > WARN_ON(&ddp->mutex[mutex->id] != mutex); > > @@ -318,9 +329,17 @@ void mtk_disp_mutex_remove_comp(struct mtk_disp_mutex *mutex, > ddp->regs + DISP_REG_MUTEX_SOF(mutex->id)); > break; > default: > - reg = readl_relaxed(ddp->regs + DISP_REG_MUTEX_MOD(mutex->id)); > - reg &= ~(ddp->mutex_mod[id]); > - writel_relaxed(reg, ddp->regs + DISP_REG_MUTEX_MOD(mutex->id)); > + if (ddp->mutex_mod[id] < 32) { > + offset = DISP_REG_MUTEX_MOD(mutex->id); > + reg = readl_relaxed(ddp->regs + offset); > + reg &= ~(1 << ddp->mutex_mod[id]); > + writel_relaxed(reg, ddp->regs + offset); > + } else { > + offset = DISP_REG_MUTEX_MOD2(mutex->id); > + reg = readl_relaxed(ddp->regs + offset); > + reg &= ~(1 << (ddp->mutex_mod[id] - 32)); > + writel_relaxed(reg, ddp->regs + offset); > + } > break; > } > } _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 66+ messages in thread
* [PATCH v3 3/8] drm/mediatek: add connection from OD1 to RDMA1 2018-05-25 2:34 ` stu.hsieh (?) @ 2018-05-25 2:34 ` stu.hsieh -1 siblings, 0 replies; 66+ messages in thread From: stu.hsieh @ 2018-05-25 2:34 UTC (permalink / raw) To: CK Hu, Philipp Zabel Cc: David Airlie, Rob Herring, Mark Rutland, Matthias Brugger, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, srv_heupstream, Stu Hsieh From: Stu Hsieh <stu.hsieh@mediatek.com> This patch add the connection from OD1 to RDMA1 for ext path. Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> --- drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c index 47ffa240bd25..0f568dd853d8 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c @@ -151,6 +151,9 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur, } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; value = GAMMA_MOUT_EN_RDMA1; + } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; + value = OD1_MOUT_EN_RDMA1; } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { *addr = DISP_REG_CONFIG_DISP_RDMA1_MOUT_EN; value = RDMA1_MOUT_DPI0; -- 2.12.5 ^ permalink raw reply related [flat|nested] 66+ messages in thread
* [PATCH v3 3/8] drm/mediatek: add connection from OD1 to RDMA1 @ 2018-05-25 2:34 ` stu.hsieh 0 siblings, 0 replies; 66+ messages in thread From: stu.hsieh at mediatek.com @ 2018-05-25 2:34 UTC (permalink / raw) To: linux-arm-kernel From: Stu Hsieh <stu.hsieh@mediatek.com> This patch add the connection from OD1 to RDMA1 for ext path. Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> --- drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c index 47ffa240bd25..0f568dd853d8 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c @@ -151,6 +151,9 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur, } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; value = GAMMA_MOUT_EN_RDMA1; + } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; + value = OD1_MOUT_EN_RDMA1; } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { *addr = DISP_REG_CONFIG_DISP_RDMA1_MOUT_EN; value = RDMA1_MOUT_DPI0; -- 2.12.5 ^ permalink raw reply related [flat|nested] 66+ messages in thread
* [PATCH v3 3/8] drm/mediatek: add connection from OD1 to RDMA1 @ 2018-05-25 2:34 ` stu.hsieh 0 siblings, 0 replies; 66+ messages in thread From: stu.hsieh @ 2018-05-25 2:34 UTC (permalink / raw) To: CK Hu, Philipp Zabel Cc: Mark Rutland, devicetree, srv_heupstream, David Airlie, linux-kernel, dri-devel, Rob Herring, linux-mediatek, Stu Hsieh, Matthias Brugger, linux-arm-kernel From: Stu Hsieh <stu.hsieh@mediatek.com> This patch add the connection from OD1 to RDMA1 for ext path. Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> --- drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c index 47ffa240bd25..0f568dd853d8 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c @@ -151,6 +151,9 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur, } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; value = GAMMA_MOUT_EN_RDMA1; + } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; + value = OD1_MOUT_EN_RDMA1; } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { *addr = DISP_REG_CONFIG_DISP_RDMA1_MOUT_EN; value = RDMA1_MOUT_DPI0; -- 2.12.5 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 66+ messages in thread
* Re: [PATCH v3 3/8] drm/mediatek: add connection from OD1 to RDMA1 2018-05-25 2:34 ` stu.hsieh (?) @ 2018-05-25 3:26 ` CK Hu -1 siblings, 0 replies; 66+ messages in thread From: CK Hu @ 2018-05-25 3:26 UTC (permalink / raw) To: stu.hsieh Cc: Philipp Zabel, David Airlie, Rob Herring, Mark Rutland, Matthias Brugger, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, srv_heupstream Hi, Stu: On Fri, 2018-05-25 at 10:34 +0800, stu.hsieh@mediatek.com wrote: > From: Stu Hsieh <stu.hsieh@mediatek.com> > > This patch add the connection from OD1 to RDMA1 for ext path. > Reviewed-by: CK Hu <ck.hu@mediatek.com> > Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > index 47ffa240bd25..0f568dd853d8 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > @@ -151,6 +151,9 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur, > } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { > *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; > value = GAMMA_MOUT_EN_RDMA1; > + } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { > + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > + value = OD1_MOUT_EN_RDMA1; > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > *addr = DISP_REG_CONFIG_DISP_RDMA1_MOUT_EN; > value = RDMA1_MOUT_DPI0; ^ permalink raw reply [flat|nested] 66+ messages in thread
* [PATCH v3 3/8] drm/mediatek: add connection from OD1 to RDMA1 @ 2018-05-25 3:26 ` CK Hu 0 siblings, 0 replies; 66+ messages in thread From: CK Hu @ 2018-05-25 3:26 UTC (permalink / raw) To: linux-arm-kernel Hi, Stu: On Fri, 2018-05-25 at 10:34 +0800, stu.hsieh at mediatek.com wrote: > From: Stu Hsieh <stu.hsieh@mediatek.com> > > This patch add the connection from OD1 to RDMA1 for ext path. > Reviewed-by: CK Hu <ck.hu@mediatek.com> > Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > index 47ffa240bd25..0f568dd853d8 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > @@ -151,6 +151,9 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur, > } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { > *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; > value = GAMMA_MOUT_EN_RDMA1; > + } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { > + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > + value = OD1_MOUT_EN_RDMA1; > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > *addr = DISP_REG_CONFIG_DISP_RDMA1_MOUT_EN; > value = RDMA1_MOUT_DPI0; ^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [PATCH v3 3/8] drm/mediatek: add connection from OD1 to RDMA1 @ 2018-05-25 3:26 ` CK Hu 0 siblings, 0 replies; 66+ messages in thread From: CK Hu @ 2018-05-25 3:26 UTC (permalink / raw) To: stu.hsieh Cc: Mark Rutland, devicetree, srv_heupstream, David Airlie, linux-kernel, dri-devel, Rob Herring, linux-mediatek, Matthias Brugger, linux-arm-kernel Hi, Stu: On Fri, 2018-05-25 at 10:34 +0800, stu.hsieh@mediatek.com wrote: > From: Stu Hsieh <stu.hsieh@mediatek.com> > > This patch add the connection from OD1 to RDMA1 for ext path. > Reviewed-by: CK Hu <ck.hu@mediatek.com> > Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > index 47ffa240bd25..0f568dd853d8 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > @@ -151,6 +151,9 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur, > } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { > *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; > value = GAMMA_MOUT_EN_RDMA1; > + } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { > + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > + value = OD1_MOUT_EN_RDMA1; > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > *addr = DISP_REG_CONFIG_DISP_RDMA1_MOUT_EN; > value = RDMA1_MOUT_DPI0; _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [PATCH v3 3/8] drm/mediatek: add connection from OD1 to RDMA1 2018-05-25 3:26 ` CK Hu (?) @ 2018-05-25 9:36 ` Stu Hsieh -1 siblings, 0 replies; 66+ messages in thread From: Stu Hsieh @ 2018-05-25 9:36 UTC (permalink / raw) To: CK Hu Cc: Philipp Zabel, David Airlie, Rob Herring, Mark Rutland, Matthias Brugger, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, srv_heupstream Hi, CK: For this patch, I would move it after "add ddp component OD1" And add this line "#define OD1_MOUT_EN_RDMA1 BIT(16)" from the path "Add support for mediatek SOC MT2712" to this patch Regards, Stu On Fri, 2018-05-25 at 11:26 +0800, CK Hu wrote: > Hi, Stu: > > On Fri, 2018-05-25 at 10:34 +0800, stu.hsieh@mediatek.com wrote: > > From: Stu Hsieh <stu.hsieh@mediatek.com> > > > > This patch add the connection from OD1 to RDMA1 for ext path. > > > > Reviewed-by: CK Hu <ck.hu@mediatek.com> > > > Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> > > --- > > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 3 +++ > > 1 file changed, 3 insertions(+) > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > index 47ffa240bd25..0f568dd853d8 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > @@ -151,6 +151,9 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur, > > } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { > > *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; > > value = GAMMA_MOUT_EN_RDMA1; > > + } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { > > + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > > + value = OD1_MOUT_EN_RDMA1; > > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > > *addr = DISP_REG_CONFIG_DISP_RDMA1_MOUT_EN; > > value = RDMA1_MOUT_DPI0; > > ^ permalink raw reply [flat|nested] 66+ messages in thread
* [PATCH v3 3/8] drm/mediatek: add connection from OD1 to RDMA1 @ 2018-05-25 9:36 ` Stu Hsieh 0 siblings, 0 replies; 66+ messages in thread From: Stu Hsieh @ 2018-05-25 9:36 UTC (permalink / raw) To: linux-arm-kernel Hi, CK: For this patch, I would move it after "add ddp component OD1" And add this line "#define OD1_MOUT_EN_RDMA1 BIT(16)" from the path "Add support for mediatek SOC MT2712" to this patch Regards, Stu On Fri, 2018-05-25 at 11:26 +0800, CK Hu wrote: > Hi, Stu: > > On Fri, 2018-05-25 at 10:34 +0800, stu.hsieh at mediatek.com wrote: > > From: Stu Hsieh <stu.hsieh@mediatek.com> > > > > This patch add the connection from OD1 to RDMA1 for ext path. > > > > Reviewed-by: CK Hu <ck.hu@mediatek.com> > > > Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> > > --- > > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 3 +++ > > 1 file changed, 3 insertions(+) > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > index 47ffa240bd25..0f568dd853d8 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > @@ -151,6 +151,9 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur, > > } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { > > *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; > > value = GAMMA_MOUT_EN_RDMA1; > > + } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { > > + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > > + value = OD1_MOUT_EN_RDMA1; > > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > > *addr = DISP_REG_CONFIG_DISP_RDMA1_MOUT_EN; > > value = RDMA1_MOUT_DPI0; > > ^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [PATCH v3 3/8] drm/mediatek: add connection from OD1 to RDMA1 @ 2018-05-25 9:36 ` Stu Hsieh 0 siblings, 0 replies; 66+ messages in thread From: Stu Hsieh @ 2018-05-25 9:36 UTC (permalink / raw) To: CK Hu Cc: Mark Rutland, devicetree, srv_heupstream, David Airlie, linux-kernel, dri-devel, Rob Herring, linux-mediatek, Matthias Brugger, linux-arm-kernel Hi, CK: For this patch, I would move it after "add ddp component OD1" And add this line "#define OD1_MOUT_EN_RDMA1 BIT(16)" from the path "Add support for mediatek SOC MT2712" to this patch Regards, Stu On Fri, 2018-05-25 at 11:26 +0800, CK Hu wrote: > Hi, Stu: > > On Fri, 2018-05-25 at 10:34 +0800, stu.hsieh@mediatek.com wrote: > > From: Stu Hsieh <stu.hsieh@mediatek.com> > > > > This patch add the connection from OD1 to RDMA1 for ext path. > > > > Reviewed-by: CK Hu <ck.hu@mediatek.com> > > > Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> > > --- > > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 3 +++ > > 1 file changed, 3 insertions(+) > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > index 47ffa240bd25..0f568dd853d8 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > @@ -151,6 +151,9 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur, > > } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { > > *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; > > value = GAMMA_MOUT_EN_RDMA1; > > + } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { > > + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > > + value = OD1_MOUT_EN_RDMA1; > > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > > *addr = DISP_REG_CONFIG_DISP_RDMA1_MOUT_EN; > > value = RDMA1_MOUT_DPI0; > > _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 66+ messages in thread
* [PATCH v3 4/8] drm/mediatek: add ddp component AAL1 2018-05-25 2:34 ` stu.hsieh (?) @ 2018-05-25 2:34 ` stu.hsieh -1 siblings, 0 replies; 66+ messages in thread From: stu.hsieh @ 2018-05-25 2:34 UTC (permalink / raw) To: CK Hu, Philipp Zabel Cc: David Airlie, Rob Herring, Mark Rutland, Matthias Brugger, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, srv_heupstream, Stu Hsieh From: Stu Hsieh <stu.hsieh@mediatek.com> This patch add component AAL1 and rename AAL to AAL0 Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> --- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index 0828cf8bf85c..eee3c0cc2632 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -41,7 +41,8 @@ enum mtk_ddp_comp_type { }; enum mtk_ddp_comp_id { - DDP_COMPONENT_AAL, + DDP_COMPONENT_AAL0, + DDP_COMPONENT_AAL1, DDP_COMPONENT_BLS, DDP_COMPONENT_COLOR0, DDP_COMPONENT_COLOR1, -- 2.12.5 ^ permalink raw reply related [flat|nested] 66+ messages in thread
* [PATCH v3 4/8] drm/mediatek: add ddp component AAL1 @ 2018-05-25 2:34 ` stu.hsieh 0 siblings, 0 replies; 66+ messages in thread From: stu.hsieh at mediatek.com @ 2018-05-25 2:34 UTC (permalink / raw) To: linux-arm-kernel From: Stu Hsieh <stu.hsieh@mediatek.com> This patch add component AAL1 and rename AAL to AAL0 Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> --- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index 0828cf8bf85c..eee3c0cc2632 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -41,7 +41,8 @@ enum mtk_ddp_comp_type { }; enum mtk_ddp_comp_id { - DDP_COMPONENT_AAL, + DDP_COMPONENT_AAL0, + DDP_COMPONENT_AAL1, DDP_COMPONENT_BLS, DDP_COMPONENT_COLOR0, DDP_COMPONENT_COLOR1, -- 2.12.5 ^ permalink raw reply related [flat|nested] 66+ messages in thread
* [PATCH v3 4/8] drm/mediatek: add ddp component AAL1 @ 2018-05-25 2:34 ` stu.hsieh 0 siblings, 0 replies; 66+ messages in thread From: stu.hsieh @ 2018-05-25 2:34 UTC (permalink / raw) To: CK Hu, Philipp Zabel Cc: Mark Rutland, devicetree, srv_heupstream, David Airlie, linux-kernel, dri-devel, Rob Herring, linux-mediatek, Stu Hsieh, Matthias Brugger, linux-arm-kernel From: Stu Hsieh <stu.hsieh@mediatek.com> This patch add component AAL1 and rename AAL to AAL0 Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> --- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index 0828cf8bf85c..eee3c0cc2632 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -41,7 +41,8 @@ enum mtk_ddp_comp_type { }; enum mtk_ddp_comp_id { - DDP_COMPONENT_AAL, + DDP_COMPONENT_AAL0, + DDP_COMPONENT_AAL1, DDP_COMPONENT_BLS, DDP_COMPONENT_COLOR0, DDP_COMPONENT_COLOR1, -- 2.12.5 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 66+ messages in thread
* Re: [PATCH v3 4/8] drm/mediatek: add ddp component AAL1 2018-05-25 2:34 ` stu.hsieh (?) @ 2018-05-25 4:23 ` CK Hu -1 siblings, 0 replies; 66+ messages in thread From: CK Hu @ 2018-05-25 4:23 UTC (permalink / raw) To: stu.hsieh Cc: Philipp Zabel, David Airlie, Rob Herring, Mark Rutland, Matthias Brugger, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, srv_heupstream Hi, Stu: On Fri, 2018-05-25 at 10:34 +0800, stu.hsieh@mediatek.com wrote: > From: Stu Hsieh <stu.hsieh@mediatek.com> > > This patch add component AAL1 and > rename AAL to AAL0 > > Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > index 0828cf8bf85c..eee3c0cc2632 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > @@ -41,7 +41,8 @@ enum mtk_ddp_comp_type { > }; > > enum mtk_ddp_comp_id { > - DDP_COMPONENT_AAL, > + DDP_COMPONENT_AAL0, > + DDP_COMPONENT_AAL1, Be sure compiling is success when you apply each patch of a series. I think when you apply to this patch, it would cause compiling error because some related modification is in the patch 'Add support for mediatek SOC MT2712'. So move the modification from that patch to this patch. Regards, CK > DDP_COMPONENT_BLS, > DDP_COMPONENT_COLOR0, > DDP_COMPONENT_COLOR1, ^ permalink raw reply [flat|nested] 66+ messages in thread
* [PATCH v3 4/8] drm/mediatek: add ddp component AAL1 @ 2018-05-25 4:23 ` CK Hu 0 siblings, 0 replies; 66+ messages in thread From: CK Hu @ 2018-05-25 4:23 UTC (permalink / raw) To: linux-arm-kernel Hi, Stu: On Fri, 2018-05-25 at 10:34 +0800, stu.hsieh at mediatek.com wrote: > From: Stu Hsieh <stu.hsieh@mediatek.com> > > This patch add component AAL1 and > rename AAL to AAL0 > > Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > index 0828cf8bf85c..eee3c0cc2632 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > @@ -41,7 +41,8 @@ enum mtk_ddp_comp_type { > }; > > enum mtk_ddp_comp_id { > - DDP_COMPONENT_AAL, > + DDP_COMPONENT_AAL0, > + DDP_COMPONENT_AAL1, Be sure compiling is success when you apply each patch of a series. I think when you apply to this patch, it would cause compiling error because some related modification is in the patch 'Add support for mediatek SOC MT2712'. So move the modification from that patch to this patch. Regards, CK > DDP_COMPONENT_BLS, > DDP_COMPONENT_COLOR0, > DDP_COMPONENT_COLOR1, ^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [PATCH v3 4/8] drm/mediatek: add ddp component AAL1 @ 2018-05-25 4:23 ` CK Hu 0 siblings, 0 replies; 66+ messages in thread From: CK Hu @ 2018-05-25 4:23 UTC (permalink / raw) To: stu.hsieh Cc: Mark Rutland, devicetree, srv_heupstream, David Airlie, linux-kernel, dri-devel, Rob Herring, linux-mediatek, Matthias Brugger, linux-arm-kernel Hi, Stu: On Fri, 2018-05-25 at 10:34 +0800, stu.hsieh@mediatek.com wrote: > From: Stu Hsieh <stu.hsieh@mediatek.com> > > This patch add component AAL1 and > rename AAL to AAL0 > > Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > index 0828cf8bf85c..eee3c0cc2632 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > @@ -41,7 +41,8 @@ enum mtk_ddp_comp_type { > }; > > enum mtk_ddp_comp_id { > - DDP_COMPONENT_AAL, > + DDP_COMPONENT_AAL0, > + DDP_COMPONENT_AAL1, Be sure compiling is success when you apply each patch of a series. I think when you apply to this patch, it would cause compiling error because some related modification is in the patch 'Add support for mediatek SOC MT2712'. So move the modification from that patch to this patch. Regards, CK > DDP_COMPONENT_BLS, > DDP_COMPONENT_COLOR0, > DDP_COMPONENT_COLOR1, _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [PATCH v3 4/8] drm/mediatek: add ddp component AAL1 2018-05-25 4:23 ` CK Hu (?) @ 2018-05-25 9:25 ` Stu Hsieh -1 siblings, 0 replies; 66+ messages in thread From: Stu Hsieh @ 2018-05-25 9:25 UTC (permalink / raw) To: CK Hu Cc: Philipp Zabel, David Airlie, Rob Herring, Mark Rutland, Matthias Brugger, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, srv_heupstream Hi. CK: On Fri, 2018-05-25 at 12:23 +0800, CK Hu wrote: > Hi, Stu: > > On Fri, 2018-05-25 at 10:34 +0800, stu.hsieh@mediatek.com wrote: > > From: Stu Hsieh <stu.hsieh@mediatek.com> > > > > This patch add component AAL1 and > > rename AAL to AAL0 > > > > Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> > > --- > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 3 ++- > > 1 file changed, 2 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > > index 0828cf8bf85c..eee3c0cc2632 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > > @@ -41,7 +41,8 @@ enum mtk_ddp_comp_type { > > }; > > > > enum mtk_ddp_comp_id { > > - DDP_COMPONENT_AAL, > > + DDP_COMPONENT_AAL0, > > + DDP_COMPONENT_AAL1, > > Be sure compiling is success when you apply each patch of a series. I > think when you apply to this patch, it would cause compiling error > because some related modification is in the patch 'Add support for > mediatek SOC MT2712'. So move the modification from that patch to this > patch. > > Regards, > CK I would move some modification related some component to associated patch from the patch 'Add support for mediatek SOC MT2712' Regards, Stu > > > DDP_COMPONENT_BLS, > > DDP_COMPONENT_COLOR0, > > DDP_COMPONENT_COLOR1, > > ^ permalink raw reply [flat|nested] 66+ messages in thread
* [PATCH v3 4/8] drm/mediatek: add ddp component AAL1 @ 2018-05-25 9:25 ` Stu Hsieh 0 siblings, 0 replies; 66+ messages in thread From: Stu Hsieh @ 2018-05-25 9:25 UTC (permalink / raw) To: linux-arm-kernel Hi. CK: On Fri, 2018-05-25 at 12:23 +0800, CK Hu wrote: > Hi, Stu: > > On Fri, 2018-05-25 at 10:34 +0800, stu.hsieh at mediatek.com wrote: > > From: Stu Hsieh <stu.hsieh@mediatek.com> > > > > This patch add component AAL1 and > > rename AAL to AAL0 > > > > Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> > > --- > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 3 ++- > > 1 file changed, 2 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > > index 0828cf8bf85c..eee3c0cc2632 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > > @@ -41,7 +41,8 @@ enum mtk_ddp_comp_type { > > }; > > > > enum mtk_ddp_comp_id { > > - DDP_COMPONENT_AAL, > > + DDP_COMPONENT_AAL0, > > + DDP_COMPONENT_AAL1, > > Be sure compiling is success when you apply each patch of a series. I > think when you apply to this patch, it would cause compiling error > because some related modification is in the patch 'Add support for > mediatek SOC MT2712'. So move the modification from that patch to this > patch. > > Regards, > CK I would move some modification related some component to associated patch from the patch 'Add support for mediatek SOC MT2712' Regards, Stu > > > DDP_COMPONENT_BLS, > > DDP_COMPONENT_COLOR0, > > DDP_COMPONENT_COLOR1, > > ^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [PATCH v3 4/8] drm/mediatek: add ddp component AAL1 @ 2018-05-25 9:25 ` Stu Hsieh 0 siblings, 0 replies; 66+ messages in thread From: Stu Hsieh @ 2018-05-25 9:25 UTC (permalink / raw) To: CK Hu Cc: Philipp Zabel, David Airlie, Rob Herring, Mark Rutland, Matthias Brugger, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, srv_heupstream Hi. CK: On Fri, 2018-05-25 at 12:23 +0800, CK Hu wrote: > Hi, Stu: > > On Fri, 2018-05-25 at 10:34 +0800, stu.hsieh@mediatek.com wrote: > > From: Stu Hsieh <stu.hsieh@mediatek.com> > > > > This patch add component AAL1 and > > rename AAL to AAL0 > > > > Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> > > --- > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 3 ++- > > 1 file changed, 2 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > > index 0828cf8bf85c..eee3c0cc2632 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > > @@ -41,7 +41,8 @@ enum mtk_ddp_comp_type { > > }; > > > > enum mtk_ddp_comp_id { > > - DDP_COMPONENT_AAL, > > + DDP_COMPONENT_AAL0, > > + DDP_COMPONENT_AAL1, > > Be sure compiling is success when you apply each patch of a series. I > think when you apply to this patch, it would cause compiling error > because some related modification is in the patch 'Add support for > mediatek SOC MT2712'. So move the modification from that patch to this > patch. > > Regards, > CK I would move some modification related some component to associated patch from the patch 'Add support for mediatek SOC MT2712' Regards, Stu > > > DDP_COMPONENT_BLS, > > DDP_COMPONENT_COLOR0, > > DDP_COMPONENT_COLOR1, > > ^ permalink raw reply [flat|nested] 66+ messages in thread
* [PATCH v3 5/8] drm/mediatek: add ddp component OD1 2018-05-25 2:34 ` stu.hsieh (?) @ 2018-05-25 2:34 ` stu.hsieh -1 siblings, 0 replies; 66+ messages in thread From: stu.hsieh @ 2018-05-25 2:34 UTC (permalink / raw) To: CK Hu, Philipp Zabel Cc: David Airlie, Rob Herring, Mark Rutland, Matthias Brugger, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, srv_heupstream, Stu Hsieh From: Stu Hsieh <stu.hsieh@mediatek.com> This patch add the component OD1 and rename the OD to OD1 Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> --- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index eee3c0cc2632..9b19fc4423f1 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -50,7 +50,8 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_DSI0, DDP_COMPONENT_DSI1, DDP_COMPONENT_GAMMA, - DDP_COMPONENT_OD, + DDP_COMPONENT_OD0, + DDP_COMPONENT_OD1, DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL1, DDP_COMPONENT_PWM0, -- 2.12.5 ^ permalink raw reply related [flat|nested] 66+ messages in thread
* [PATCH v3 5/8] drm/mediatek: add ddp component OD1 @ 2018-05-25 2:34 ` stu.hsieh 0 siblings, 0 replies; 66+ messages in thread From: stu.hsieh at mediatek.com @ 2018-05-25 2:34 UTC (permalink / raw) To: linux-arm-kernel From: Stu Hsieh <stu.hsieh@mediatek.com> This patch add the component OD1 and rename the OD to OD1 Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> --- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index eee3c0cc2632..9b19fc4423f1 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -50,7 +50,8 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_DSI0, DDP_COMPONENT_DSI1, DDP_COMPONENT_GAMMA, - DDP_COMPONENT_OD, + DDP_COMPONENT_OD0, + DDP_COMPONENT_OD1, DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL1, DDP_COMPONENT_PWM0, -- 2.12.5 ^ permalink raw reply related [flat|nested] 66+ messages in thread
* [PATCH v3 5/8] drm/mediatek: add ddp component OD1 @ 2018-05-25 2:34 ` stu.hsieh 0 siblings, 0 replies; 66+ messages in thread From: stu.hsieh @ 2018-05-25 2:34 UTC (permalink / raw) To: CK Hu, Philipp Zabel Cc: Mark Rutland, devicetree, srv_heupstream, David Airlie, linux-kernel, dri-devel, Rob Herring, linux-mediatek, Stu Hsieh, Matthias Brugger, linux-arm-kernel From: Stu Hsieh <stu.hsieh@mediatek.com> This patch add the component OD1 and rename the OD to OD1 Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> --- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index eee3c0cc2632..9b19fc4423f1 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -50,7 +50,8 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_DSI0, DDP_COMPONENT_DSI1, DDP_COMPONENT_GAMMA, - DDP_COMPONENT_OD, + DDP_COMPONENT_OD0, + DDP_COMPONENT_OD1, DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL1, DDP_COMPONENT_PWM0, -- 2.12.5 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 66+ messages in thread
* [PATCH v3 6/8] drm/mediatek: add ddp component PWM2 2018-05-25 2:34 ` stu.hsieh (?) @ 2018-05-25 2:34 ` stu.hsieh -1 siblings, 0 replies; 66+ messages in thread From: stu.hsieh @ 2018-05-25 2:34 UTC (permalink / raw) To: CK Hu, Philipp Zabel Cc: David Airlie, Rob Herring, Mark Rutland, Matthias Brugger, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, srv_heupstream, Stu Hsieh From: Stu Hsieh <stu.hsieh@mediatek.com> This patch add component PWM2 Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> --- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index 9b19fc4423f1..e00c2e798abd 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -56,6 +56,7 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_OVL1, DDP_COMPONENT_PWM0, DDP_COMPONENT_PWM1, + DDP_COMPONENT_PWM2, DDP_COMPONENT_RDMA0, DDP_COMPONENT_RDMA1, DDP_COMPONENT_RDMA2, -- 2.12.5 ^ permalink raw reply related [flat|nested] 66+ messages in thread
* [PATCH v3 6/8] drm/mediatek: add ddp component PWM2 @ 2018-05-25 2:34 ` stu.hsieh 0 siblings, 0 replies; 66+ messages in thread From: stu.hsieh at mediatek.com @ 2018-05-25 2:34 UTC (permalink / raw) To: linux-arm-kernel From: Stu Hsieh <stu.hsieh@mediatek.com> This patch add component PWM2 Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> --- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index 9b19fc4423f1..e00c2e798abd 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -56,6 +56,7 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_OVL1, DDP_COMPONENT_PWM0, DDP_COMPONENT_PWM1, + DDP_COMPONENT_PWM2, DDP_COMPONENT_RDMA0, DDP_COMPONENT_RDMA1, DDP_COMPONENT_RDMA2, -- 2.12.5 ^ permalink raw reply related [flat|nested] 66+ messages in thread
* [PATCH v3 6/8] drm/mediatek: add ddp component PWM2 @ 2018-05-25 2:34 ` stu.hsieh 0 siblings, 0 replies; 66+ messages in thread From: stu.hsieh @ 2018-05-25 2:34 UTC (permalink / raw) To: CK Hu, Philipp Zabel Cc: David Airlie, Rob Herring, Mark Rutland, Matthias Brugger, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, srv_heupstream, Stu Hsieh From: Stu Hsieh <stu.hsieh@mediatek.com> This patch add component PWM2 Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> --- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index 9b19fc4423f1..e00c2e798abd 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -56,6 +56,7 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_OVL1, DDP_COMPONENT_PWM0, DDP_COMPONENT_PWM1, + DDP_COMPONENT_PWM2, DDP_COMPONENT_RDMA0, DDP_COMPONENT_RDMA1, DDP_COMPONENT_RDMA2, -- 2.12.5 ^ permalink raw reply related [flat|nested] 66+ messages in thread
* [PATCH v3 7/8] drm/mediatek: Add support for mediatek SOC MT2712 2018-05-25 2:34 ` stu.hsieh (?) @ 2018-05-25 2:34 ` stu.hsieh -1 siblings, 0 replies; 66+ messages in thread From: stu.hsieh @ 2018-05-25 2:34 UTC (permalink / raw) To: CK Hu, Philipp Zabel Cc: David Airlie, Rob Herring, Mark Rutland, Matthias Brugger, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, srv_heupstream, Stu Hsieh From: Stu Hsieh <stu.hsieh@mediatek.com> This patch add support for the Mediatek MT2712 DISP subsystem. There are two OVL engine and three disp output in MT2712. Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> --- drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 46 +++++++++++++++++++++++++++-- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 8 +++-- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 42 ++++++++++++++++++++++++-- drivers/gpu/drm/mediatek/mtk_drm_drv.h | 7 +++-- 4 files changed, 94 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c index 0f568dd853d8..676726249ae0 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c @@ -61,6 +61,24 @@ #define MT8173_MUTEX_MOD_DISP_PWM1 24 #define MT8173_MUTEX_MOD_DISP_OD 25 +#define MT2712_MUTEX_MOD_DISP_OVL0 11 +#define MT2712_MUTEX_MOD_DISP_OVL1 12 +#define MT2712_MUTEX_MOD_DISP_RDMA0 13 +#define MT2712_MUTEX_MOD_DISP_RDMA1 14 +#define MT2712_MUTEX_MOD_DISP_RDMA2 15 +#define MT2712_MUTEX_MOD_DISP_WDMA0 16 +#define MT2712_MUTEX_MOD_DISP_WDMA1 17 +#define MT2712_MUTEX_MOD_DISP_COLOR0 18 +#define MT2712_MUTEX_MOD_DISP_COLOR1 19 +#define MT2712_MUTEX_MOD_DISP_AAL0 20 +#define MT2712_MUTEX_MOD_DISP_UFOE 22 +#define MT2712_MUTEX_MOD_DISP_PWM0 23 +#define MT2712_MUTEX_MOD_DISP_PWM1 24 +#define MT2712_MUTEX_MOD_DISP_PWM2 10 +#define MT2712_MUTEX_MOD_DISP_OD0 25 +#define MT2712_MUTEX_MOD2_DISP_AAL1 33 +#define MT2712_MUTEX_MOD2_DISP_OD1 34 + #define MT2701_MUTEX_MOD_DISP_OVL 3 #define MT2701_MUTEX_MOD_DISP_WDMA 6 #define MT2701_MUTEX_MOD_DISP_COLOR 7 @@ -75,6 +93,7 @@ #define OVL0_MOUT_EN_COLOR0 0x1 #define OD_MOUT_EN_RDMA0 0x1 +#define OD1_MOUT_EN_RDMA1 BIT(16) #define UFOE_MOUT_EN_DSI0 0x1 #define COLOR0_SEL_IN_OVL0 0x1 #define OVL1_MOUT_EN_COLOR1 0x1 @@ -109,12 +128,32 @@ static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA, }; +static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = { + [DDP_COMPONENT_AAL0] = MT2712_MUTEX_MOD_DISP_AAL0, + [DDP_COMPONENT_AAL1] = MT2712_MUTEX_MOD2_DISP_AAL1, + [DDP_COMPONENT_COLOR0] = MT2712_MUTEX_MOD_DISP_COLOR0, + [DDP_COMPONENT_COLOR1] = MT2712_MUTEX_MOD_DISP_COLOR1, + [DDP_COMPONENT_OD0] = MT2712_MUTEX_MOD_DISP_OD0, + [DDP_COMPONENT_OD1] = MT2712_MUTEX_MOD2_DISP_OD1, + [DDP_COMPONENT_OVL0] = MT2712_MUTEX_MOD_DISP_OVL0, + [DDP_COMPONENT_OVL1] = MT2712_MUTEX_MOD_DISP_OVL1, + [DDP_COMPONENT_PWM0] = MT2712_MUTEX_MOD_DISP_PWM0, + [DDP_COMPONENT_PWM1] = MT2712_MUTEX_MOD_DISP_PWM1, + [DDP_COMPONENT_PWM2] = MT2712_MUTEX_MOD_DISP_PWM2, + [DDP_COMPONENT_RDMA0] = MT2712_MUTEX_MOD_DISP_RDMA0, + [DDP_COMPONENT_RDMA1] = MT2712_MUTEX_MOD_DISP_RDMA1, + [DDP_COMPONENT_RDMA2] = MT2712_MUTEX_MOD_DISP_RDMA2, + [DDP_COMPONENT_UFOE] = MT2712_MUTEX_MOD_DISP_UFOE, + [DDP_COMPONENT_WDMA0] = MT2712_MUTEX_MOD_DISP_WDMA0, + [DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1, +}; + static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = { - [DDP_COMPONENT_AAL] = MT8173_MUTEX_MOD_DISP_AAL, + [DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL, [DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0, [DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1, [DDP_COMPONENT_GAMMA] = MT8173_MUTEX_MOD_DISP_GAMMA, - [DDP_COMPONENT_OD] = MT8173_MUTEX_MOD_DISP_OD, + [DDP_COMPONENT_OD0] = MT8173_MUTEX_MOD_DISP_OD, [DDP_COMPONENT_OVL0] = MT8173_MUTEX_MOD_DISP_OVL0, [DDP_COMPONENT_OVL1] = MT8173_MUTEX_MOD_DISP_OVL1, [DDP_COMPONENT_PWM0] = MT8173_MUTEX_MOD_DISP_PWM0, @@ -139,7 +178,7 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur, } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; value = OVL_MOUT_EN_RDMA; - } else if (cur == DDP_COMPONENT_OD && next == DDP_COMPONENT_RDMA0) { + } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; value = OD_MOUT_EN_RDMA0; } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { @@ -429,6 +468,7 @@ static int mtk_ddp_remove(struct platform_device *pdev) static const struct of_device_id ddp_driver_dt_match[] = { { .compatible = "mediatek,mt2701-disp-mutex", .data = mt2701_mutex_mod}, + { .compatible = "mediatek,mt2712-disp-mutex", .data = mt2712_mutex_mod}, { .compatible = "mediatek,mt8173-disp-mutex", .data = mt8173_mutex_mod}, {}, }; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 4672317e3ad1..86e8c9e5df41 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -218,7 +218,8 @@ struct mtk_ddp_comp_match { }; static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { - [DDP_COMPONENT_AAL] = { MTK_DISP_AAL, 0, &ddp_aal }, + [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal }, + [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal }, [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL }, [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, NULL }, [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, NULL }, @@ -226,10 +227,13 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, NULL }, [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, NULL }, [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma }, - [DDP_COMPONENT_OD] = { MTK_DISP_OD, 0, &ddp_od }, + [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od }, + [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od }, [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, NULL }, [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, NULL }, [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, + [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, + [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL }, [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, NULL }, [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, NULL }, [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, NULL }, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index a2ca90fc403c..b32c4cc8d051 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -146,11 +146,37 @@ static const enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = { DDP_COMPONENT_DPI0, }; +static const enum mtk_ddp_comp_id mt2712_mtk_ddp_main[] = { + DDP_COMPONENT_OVL0, + DDP_COMPONENT_COLOR0, + DDP_COMPONENT_AAL0, + DDP_COMPONENT_OD0, + DDP_COMPONENT_RDMA0, + DDP_COMPONENT_DPI0, + DDP_COMPONENT_PWM0, +}; + +static const enum mtk_ddp_comp_id mt2712_mtk_ddp_ext[] = { + DDP_COMPONENT_OVL1, + DDP_COMPONENT_COLOR1, + DDP_COMPONENT_AAL1, + DDP_COMPONENT_OD1, + DDP_COMPONENT_RDMA1, + DDP_COMPONENT_DPI1, + DDP_COMPONENT_PWM1, +}; + +static const enum mtk_ddp_comp_id mt2712_mtk_ddp_third[] = { + DDP_COMPONENT_RDMA2, + DDP_COMPONENT_DSI2, + DDP_COMPONENT_PWM2, +}; + static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = { DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0, - DDP_COMPONENT_AAL, - DDP_COMPONENT_OD, + DDP_COMPONENT_AAL0, + DDP_COMPONENT_OD0, DDP_COMPONENT_RDMA0, DDP_COMPONENT_UFOE, DDP_COMPONENT_DSI0, @@ -173,6 +199,15 @@ static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { .shadow_register = true, }; +static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { + .main_path = mt2712_mtk_ddp_main, + .main_len = ARRAY_SIZE(mt2712_mtk_ddp_main), + .ext_path = mt2712_mtk_ddp_ext, + .ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext), + .third_path = mt2712_mtk_ddp_third, + .third_len = ARRAY_SIZE(mt2712_mtk_ddp_third), +}; + static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { .main_path = mt8173_mtk_ddp_main, .main_len = ARRAY_SIZE(mt8173_mtk_ddp_main), @@ -374,6 +409,7 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { { .compatible = "mediatek,mt8173-dsi", .data = (void *)MTK_DSI }, { .compatible = "mediatek,mt8173-dpi", .data = (void *)MTK_DPI }, { .compatible = "mediatek,mt2701-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, + { .compatible = "mediatek,mt2712-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt8173-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt2701-disp-pwm", .data = (void *)MTK_DISP_BLS }, { .compatible = "mediatek,mt8173-disp-pwm", .data = (void *)MTK_DISP_PWM }, @@ -552,6 +588,8 @@ static SIMPLE_DEV_PM_OPS(mtk_drm_pm_ops, mtk_drm_sys_suspend, static const struct of_device_id mtk_drm_of_ids[] = { { .compatible = "mediatek,mt2701-mmsys", .data = &mt2701_mmsys_driver_data}, + { .compatible = "mediatek,mt2712-mmsys", + .data = &mt2712_mmsys_driver_data}, { .compatible = "mediatek,mt8173-mmsys", .data = &mt8173_mmsys_driver_data}, { } diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h index c3378c452c0a..e821342bc2d3 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h @@ -17,8 +17,8 @@ #include <linux/io.h> #include "mtk_drm_ddp_comp.h" -#define MAX_CRTC 2 -#define MAX_CONNECTOR 2 +#define MAX_CRTC 3 +#define MAX_CONNECTOR 3 struct device; struct device_node; @@ -33,6 +33,9 @@ struct mtk_mmsys_driver_data { unsigned int main_len; const enum mtk_ddp_comp_id *ext_path; unsigned int ext_len; + enum mtk_ddp_comp_id *third_path; + unsigned int third_len; + bool shadow_register; }; -- 2.12.5 ^ permalink raw reply related [flat|nested] 66+ messages in thread
* [PATCH v3 7/8] drm/mediatek: Add support for mediatek SOC MT2712 @ 2018-05-25 2:34 ` stu.hsieh 0 siblings, 0 replies; 66+ messages in thread From: stu.hsieh at mediatek.com @ 2018-05-25 2:34 UTC (permalink / raw) To: linux-arm-kernel From: Stu Hsieh <stu.hsieh@mediatek.com> This patch add support for the Mediatek MT2712 DISP subsystem. There are two OVL engine and three disp output in MT2712. Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> --- drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 46 +++++++++++++++++++++++++++-- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 8 +++-- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 42 ++++++++++++++++++++++++-- drivers/gpu/drm/mediatek/mtk_drm_drv.h | 7 +++-- 4 files changed, 94 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c index 0f568dd853d8..676726249ae0 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c @@ -61,6 +61,24 @@ #define MT8173_MUTEX_MOD_DISP_PWM1 24 #define MT8173_MUTEX_MOD_DISP_OD 25 +#define MT2712_MUTEX_MOD_DISP_OVL0 11 +#define MT2712_MUTEX_MOD_DISP_OVL1 12 +#define MT2712_MUTEX_MOD_DISP_RDMA0 13 +#define MT2712_MUTEX_MOD_DISP_RDMA1 14 +#define MT2712_MUTEX_MOD_DISP_RDMA2 15 +#define MT2712_MUTEX_MOD_DISP_WDMA0 16 +#define MT2712_MUTEX_MOD_DISP_WDMA1 17 +#define MT2712_MUTEX_MOD_DISP_COLOR0 18 +#define MT2712_MUTEX_MOD_DISP_COLOR1 19 +#define MT2712_MUTEX_MOD_DISP_AAL0 20 +#define MT2712_MUTEX_MOD_DISP_UFOE 22 +#define MT2712_MUTEX_MOD_DISP_PWM0 23 +#define MT2712_MUTEX_MOD_DISP_PWM1 24 +#define MT2712_MUTEX_MOD_DISP_PWM2 10 +#define MT2712_MUTEX_MOD_DISP_OD0 25 +#define MT2712_MUTEX_MOD2_DISP_AAL1 33 +#define MT2712_MUTEX_MOD2_DISP_OD1 34 + #define MT2701_MUTEX_MOD_DISP_OVL 3 #define MT2701_MUTEX_MOD_DISP_WDMA 6 #define MT2701_MUTEX_MOD_DISP_COLOR 7 @@ -75,6 +93,7 @@ #define OVL0_MOUT_EN_COLOR0 0x1 #define OD_MOUT_EN_RDMA0 0x1 +#define OD1_MOUT_EN_RDMA1 BIT(16) #define UFOE_MOUT_EN_DSI0 0x1 #define COLOR0_SEL_IN_OVL0 0x1 #define OVL1_MOUT_EN_COLOR1 0x1 @@ -109,12 +128,32 @@ static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA, }; +static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = { + [DDP_COMPONENT_AAL0] = MT2712_MUTEX_MOD_DISP_AAL0, + [DDP_COMPONENT_AAL1] = MT2712_MUTEX_MOD2_DISP_AAL1, + [DDP_COMPONENT_COLOR0] = MT2712_MUTEX_MOD_DISP_COLOR0, + [DDP_COMPONENT_COLOR1] = MT2712_MUTEX_MOD_DISP_COLOR1, + [DDP_COMPONENT_OD0] = MT2712_MUTEX_MOD_DISP_OD0, + [DDP_COMPONENT_OD1] = MT2712_MUTEX_MOD2_DISP_OD1, + [DDP_COMPONENT_OVL0] = MT2712_MUTEX_MOD_DISP_OVL0, + [DDP_COMPONENT_OVL1] = MT2712_MUTEX_MOD_DISP_OVL1, + [DDP_COMPONENT_PWM0] = MT2712_MUTEX_MOD_DISP_PWM0, + [DDP_COMPONENT_PWM1] = MT2712_MUTEX_MOD_DISP_PWM1, + [DDP_COMPONENT_PWM2] = MT2712_MUTEX_MOD_DISP_PWM2, + [DDP_COMPONENT_RDMA0] = MT2712_MUTEX_MOD_DISP_RDMA0, + [DDP_COMPONENT_RDMA1] = MT2712_MUTEX_MOD_DISP_RDMA1, + [DDP_COMPONENT_RDMA2] = MT2712_MUTEX_MOD_DISP_RDMA2, + [DDP_COMPONENT_UFOE] = MT2712_MUTEX_MOD_DISP_UFOE, + [DDP_COMPONENT_WDMA0] = MT2712_MUTEX_MOD_DISP_WDMA0, + [DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1, +}; + static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = { - [DDP_COMPONENT_AAL] = MT8173_MUTEX_MOD_DISP_AAL, + [DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL, [DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0, [DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1, [DDP_COMPONENT_GAMMA] = MT8173_MUTEX_MOD_DISP_GAMMA, - [DDP_COMPONENT_OD] = MT8173_MUTEX_MOD_DISP_OD, + [DDP_COMPONENT_OD0] = MT8173_MUTEX_MOD_DISP_OD, [DDP_COMPONENT_OVL0] = MT8173_MUTEX_MOD_DISP_OVL0, [DDP_COMPONENT_OVL1] = MT8173_MUTEX_MOD_DISP_OVL1, [DDP_COMPONENT_PWM0] = MT8173_MUTEX_MOD_DISP_PWM0, @@ -139,7 +178,7 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur, } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; value = OVL_MOUT_EN_RDMA; - } else if (cur == DDP_COMPONENT_OD && next == DDP_COMPONENT_RDMA0) { + } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; value = OD_MOUT_EN_RDMA0; } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { @@ -429,6 +468,7 @@ static int mtk_ddp_remove(struct platform_device *pdev) static const struct of_device_id ddp_driver_dt_match[] = { { .compatible = "mediatek,mt2701-disp-mutex", .data = mt2701_mutex_mod}, + { .compatible = "mediatek,mt2712-disp-mutex", .data = mt2712_mutex_mod}, { .compatible = "mediatek,mt8173-disp-mutex", .data = mt8173_mutex_mod}, {}, }; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 4672317e3ad1..86e8c9e5df41 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -218,7 +218,8 @@ struct mtk_ddp_comp_match { }; static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { - [DDP_COMPONENT_AAL] = { MTK_DISP_AAL, 0, &ddp_aal }, + [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal }, + [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal }, [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL }, [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, NULL }, [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, NULL }, @@ -226,10 +227,13 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, NULL }, [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, NULL }, [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma }, - [DDP_COMPONENT_OD] = { MTK_DISP_OD, 0, &ddp_od }, + [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od }, + [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od }, [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, NULL }, [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, NULL }, [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, + [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, + [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL }, [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, NULL }, [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, NULL }, [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, NULL }, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index a2ca90fc403c..b32c4cc8d051 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -146,11 +146,37 @@ static const enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = { DDP_COMPONENT_DPI0, }; +static const enum mtk_ddp_comp_id mt2712_mtk_ddp_main[] = { + DDP_COMPONENT_OVL0, + DDP_COMPONENT_COLOR0, + DDP_COMPONENT_AAL0, + DDP_COMPONENT_OD0, + DDP_COMPONENT_RDMA0, + DDP_COMPONENT_DPI0, + DDP_COMPONENT_PWM0, +}; + +static const enum mtk_ddp_comp_id mt2712_mtk_ddp_ext[] = { + DDP_COMPONENT_OVL1, + DDP_COMPONENT_COLOR1, + DDP_COMPONENT_AAL1, + DDP_COMPONENT_OD1, + DDP_COMPONENT_RDMA1, + DDP_COMPONENT_DPI1, + DDP_COMPONENT_PWM1, +}; + +static const enum mtk_ddp_comp_id mt2712_mtk_ddp_third[] = { + DDP_COMPONENT_RDMA2, + DDP_COMPONENT_DSI2, + DDP_COMPONENT_PWM2, +}; + static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = { DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0, - DDP_COMPONENT_AAL, - DDP_COMPONENT_OD, + DDP_COMPONENT_AAL0, + DDP_COMPONENT_OD0, DDP_COMPONENT_RDMA0, DDP_COMPONENT_UFOE, DDP_COMPONENT_DSI0, @@ -173,6 +199,15 @@ static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { .shadow_register = true, }; +static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { + .main_path = mt2712_mtk_ddp_main, + .main_len = ARRAY_SIZE(mt2712_mtk_ddp_main), + .ext_path = mt2712_mtk_ddp_ext, + .ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext), + .third_path = mt2712_mtk_ddp_third, + .third_len = ARRAY_SIZE(mt2712_mtk_ddp_third), +}; + static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { .main_path = mt8173_mtk_ddp_main, .main_len = ARRAY_SIZE(mt8173_mtk_ddp_main), @@ -374,6 +409,7 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { { .compatible = "mediatek,mt8173-dsi", .data = (void *)MTK_DSI }, { .compatible = "mediatek,mt8173-dpi", .data = (void *)MTK_DPI }, { .compatible = "mediatek,mt2701-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, + { .compatible = "mediatek,mt2712-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt8173-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt2701-disp-pwm", .data = (void *)MTK_DISP_BLS }, { .compatible = "mediatek,mt8173-disp-pwm", .data = (void *)MTK_DISP_PWM }, @@ -552,6 +588,8 @@ static SIMPLE_DEV_PM_OPS(mtk_drm_pm_ops, mtk_drm_sys_suspend, static const struct of_device_id mtk_drm_of_ids[] = { { .compatible = "mediatek,mt2701-mmsys", .data = &mt2701_mmsys_driver_data}, + { .compatible = "mediatek,mt2712-mmsys", + .data = &mt2712_mmsys_driver_data}, { .compatible = "mediatek,mt8173-mmsys", .data = &mt8173_mmsys_driver_data}, { } diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h index c3378c452c0a..e821342bc2d3 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h @@ -17,8 +17,8 @@ #include <linux/io.h> #include "mtk_drm_ddp_comp.h" -#define MAX_CRTC 2 -#define MAX_CONNECTOR 2 +#define MAX_CRTC 3 +#define MAX_CONNECTOR 3 struct device; struct device_node; @@ -33,6 +33,9 @@ struct mtk_mmsys_driver_data { unsigned int main_len; const enum mtk_ddp_comp_id *ext_path; unsigned int ext_len; + enum mtk_ddp_comp_id *third_path; + unsigned int third_len; + bool shadow_register; }; -- 2.12.5 ^ permalink raw reply related [flat|nested] 66+ messages in thread
* [PATCH v3 7/8] drm/mediatek: Add support for mediatek SOC MT2712 @ 2018-05-25 2:34 ` stu.hsieh 0 siblings, 0 replies; 66+ messages in thread From: stu.hsieh @ 2018-05-25 2:34 UTC (permalink / raw) To: CK Hu, Philipp Zabel Cc: Mark Rutland, devicetree, srv_heupstream, David Airlie, linux-kernel, dri-devel, Rob Herring, linux-mediatek, Stu Hsieh, Matthias Brugger, linux-arm-kernel From: Stu Hsieh <stu.hsieh@mediatek.com> This patch add support for the Mediatek MT2712 DISP subsystem. There are two OVL engine and three disp output in MT2712. Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> --- drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 46 +++++++++++++++++++++++++++-- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 8 +++-- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 42 ++++++++++++++++++++++++-- drivers/gpu/drm/mediatek/mtk_drm_drv.h | 7 +++-- 4 files changed, 94 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c index 0f568dd853d8..676726249ae0 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c @@ -61,6 +61,24 @@ #define MT8173_MUTEX_MOD_DISP_PWM1 24 #define MT8173_MUTEX_MOD_DISP_OD 25 +#define MT2712_MUTEX_MOD_DISP_OVL0 11 +#define MT2712_MUTEX_MOD_DISP_OVL1 12 +#define MT2712_MUTEX_MOD_DISP_RDMA0 13 +#define MT2712_MUTEX_MOD_DISP_RDMA1 14 +#define MT2712_MUTEX_MOD_DISP_RDMA2 15 +#define MT2712_MUTEX_MOD_DISP_WDMA0 16 +#define MT2712_MUTEX_MOD_DISP_WDMA1 17 +#define MT2712_MUTEX_MOD_DISP_COLOR0 18 +#define MT2712_MUTEX_MOD_DISP_COLOR1 19 +#define MT2712_MUTEX_MOD_DISP_AAL0 20 +#define MT2712_MUTEX_MOD_DISP_UFOE 22 +#define MT2712_MUTEX_MOD_DISP_PWM0 23 +#define MT2712_MUTEX_MOD_DISP_PWM1 24 +#define MT2712_MUTEX_MOD_DISP_PWM2 10 +#define MT2712_MUTEX_MOD_DISP_OD0 25 +#define MT2712_MUTEX_MOD2_DISP_AAL1 33 +#define MT2712_MUTEX_MOD2_DISP_OD1 34 + #define MT2701_MUTEX_MOD_DISP_OVL 3 #define MT2701_MUTEX_MOD_DISP_WDMA 6 #define MT2701_MUTEX_MOD_DISP_COLOR 7 @@ -75,6 +93,7 @@ #define OVL0_MOUT_EN_COLOR0 0x1 #define OD_MOUT_EN_RDMA0 0x1 +#define OD1_MOUT_EN_RDMA1 BIT(16) #define UFOE_MOUT_EN_DSI0 0x1 #define COLOR0_SEL_IN_OVL0 0x1 #define OVL1_MOUT_EN_COLOR1 0x1 @@ -109,12 +128,32 @@ static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA, }; +static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = { + [DDP_COMPONENT_AAL0] = MT2712_MUTEX_MOD_DISP_AAL0, + [DDP_COMPONENT_AAL1] = MT2712_MUTEX_MOD2_DISP_AAL1, + [DDP_COMPONENT_COLOR0] = MT2712_MUTEX_MOD_DISP_COLOR0, + [DDP_COMPONENT_COLOR1] = MT2712_MUTEX_MOD_DISP_COLOR1, + [DDP_COMPONENT_OD0] = MT2712_MUTEX_MOD_DISP_OD0, + [DDP_COMPONENT_OD1] = MT2712_MUTEX_MOD2_DISP_OD1, + [DDP_COMPONENT_OVL0] = MT2712_MUTEX_MOD_DISP_OVL0, + [DDP_COMPONENT_OVL1] = MT2712_MUTEX_MOD_DISP_OVL1, + [DDP_COMPONENT_PWM0] = MT2712_MUTEX_MOD_DISP_PWM0, + [DDP_COMPONENT_PWM1] = MT2712_MUTEX_MOD_DISP_PWM1, + [DDP_COMPONENT_PWM2] = MT2712_MUTEX_MOD_DISP_PWM2, + [DDP_COMPONENT_RDMA0] = MT2712_MUTEX_MOD_DISP_RDMA0, + [DDP_COMPONENT_RDMA1] = MT2712_MUTEX_MOD_DISP_RDMA1, + [DDP_COMPONENT_RDMA2] = MT2712_MUTEX_MOD_DISP_RDMA2, + [DDP_COMPONENT_UFOE] = MT2712_MUTEX_MOD_DISP_UFOE, + [DDP_COMPONENT_WDMA0] = MT2712_MUTEX_MOD_DISP_WDMA0, + [DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1, +}; + static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = { - [DDP_COMPONENT_AAL] = MT8173_MUTEX_MOD_DISP_AAL, + [DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL, [DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0, [DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1, [DDP_COMPONENT_GAMMA] = MT8173_MUTEX_MOD_DISP_GAMMA, - [DDP_COMPONENT_OD] = MT8173_MUTEX_MOD_DISP_OD, + [DDP_COMPONENT_OD0] = MT8173_MUTEX_MOD_DISP_OD, [DDP_COMPONENT_OVL0] = MT8173_MUTEX_MOD_DISP_OVL0, [DDP_COMPONENT_OVL1] = MT8173_MUTEX_MOD_DISP_OVL1, [DDP_COMPONENT_PWM0] = MT8173_MUTEX_MOD_DISP_PWM0, @@ -139,7 +178,7 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur, } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; value = OVL_MOUT_EN_RDMA; - } else if (cur == DDP_COMPONENT_OD && next == DDP_COMPONENT_RDMA0) { + } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; value = OD_MOUT_EN_RDMA0; } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { @@ -429,6 +468,7 @@ static int mtk_ddp_remove(struct platform_device *pdev) static const struct of_device_id ddp_driver_dt_match[] = { { .compatible = "mediatek,mt2701-disp-mutex", .data = mt2701_mutex_mod}, + { .compatible = "mediatek,mt2712-disp-mutex", .data = mt2712_mutex_mod}, { .compatible = "mediatek,mt8173-disp-mutex", .data = mt8173_mutex_mod}, {}, }; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 4672317e3ad1..86e8c9e5df41 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -218,7 +218,8 @@ struct mtk_ddp_comp_match { }; static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { - [DDP_COMPONENT_AAL] = { MTK_DISP_AAL, 0, &ddp_aal }, + [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal }, + [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal }, [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL }, [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, NULL }, [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, NULL }, @@ -226,10 +227,13 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, NULL }, [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, NULL }, [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma }, - [DDP_COMPONENT_OD] = { MTK_DISP_OD, 0, &ddp_od }, + [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od }, + [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od }, [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, NULL }, [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, NULL }, [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, + [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, + [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL }, [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, NULL }, [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, NULL }, [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, NULL }, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index a2ca90fc403c..b32c4cc8d051 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -146,11 +146,37 @@ static const enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = { DDP_COMPONENT_DPI0, }; +static const enum mtk_ddp_comp_id mt2712_mtk_ddp_main[] = { + DDP_COMPONENT_OVL0, + DDP_COMPONENT_COLOR0, + DDP_COMPONENT_AAL0, + DDP_COMPONENT_OD0, + DDP_COMPONENT_RDMA0, + DDP_COMPONENT_DPI0, + DDP_COMPONENT_PWM0, +}; + +static const enum mtk_ddp_comp_id mt2712_mtk_ddp_ext[] = { + DDP_COMPONENT_OVL1, + DDP_COMPONENT_COLOR1, + DDP_COMPONENT_AAL1, + DDP_COMPONENT_OD1, + DDP_COMPONENT_RDMA1, + DDP_COMPONENT_DPI1, + DDP_COMPONENT_PWM1, +}; + +static const enum mtk_ddp_comp_id mt2712_mtk_ddp_third[] = { + DDP_COMPONENT_RDMA2, + DDP_COMPONENT_DSI2, + DDP_COMPONENT_PWM2, +}; + static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = { DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0, - DDP_COMPONENT_AAL, - DDP_COMPONENT_OD, + DDP_COMPONENT_AAL0, + DDP_COMPONENT_OD0, DDP_COMPONENT_RDMA0, DDP_COMPONENT_UFOE, DDP_COMPONENT_DSI0, @@ -173,6 +199,15 @@ static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { .shadow_register = true, }; +static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { + .main_path = mt2712_mtk_ddp_main, + .main_len = ARRAY_SIZE(mt2712_mtk_ddp_main), + .ext_path = mt2712_mtk_ddp_ext, + .ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext), + .third_path = mt2712_mtk_ddp_third, + .third_len = ARRAY_SIZE(mt2712_mtk_ddp_third), +}; + static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { .main_path = mt8173_mtk_ddp_main, .main_len = ARRAY_SIZE(mt8173_mtk_ddp_main), @@ -374,6 +409,7 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { { .compatible = "mediatek,mt8173-dsi", .data = (void *)MTK_DSI }, { .compatible = "mediatek,mt8173-dpi", .data = (void *)MTK_DPI }, { .compatible = "mediatek,mt2701-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, + { .compatible = "mediatek,mt2712-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt8173-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt2701-disp-pwm", .data = (void *)MTK_DISP_BLS }, { .compatible = "mediatek,mt8173-disp-pwm", .data = (void *)MTK_DISP_PWM }, @@ -552,6 +588,8 @@ static SIMPLE_DEV_PM_OPS(mtk_drm_pm_ops, mtk_drm_sys_suspend, static const struct of_device_id mtk_drm_of_ids[] = { { .compatible = "mediatek,mt2701-mmsys", .data = &mt2701_mmsys_driver_data}, + { .compatible = "mediatek,mt2712-mmsys", + .data = &mt2712_mmsys_driver_data}, { .compatible = "mediatek,mt8173-mmsys", .data = &mt8173_mmsys_driver_data}, { } diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h index c3378c452c0a..e821342bc2d3 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h @@ -17,8 +17,8 @@ #include <linux/io.h> #include "mtk_drm_ddp_comp.h" -#define MAX_CRTC 2 -#define MAX_CONNECTOR 2 +#define MAX_CRTC 3 +#define MAX_CONNECTOR 3 struct device; struct device_node; @@ -33,6 +33,9 @@ struct mtk_mmsys_driver_data { unsigned int main_len; const enum mtk_ddp_comp_id *ext_path; unsigned int ext_len; + enum mtk_ddp_comp_id *third_path; + unsigned int third_len; + bool shadow_register; }; -- 2.12.5 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 66+ messages in thread
* Re: [PATCH v3 7/8] drm/mediatek: Add support for mediatek SOC MT2712 2018-05-25 2:34 ` stu.hsieh (?) @ 2018-05-25 4:51 ` CK Hu -1 siblings, 0 replies; 66+ messages in thread From: CK Hu @ 2018-05-25 4:51 UTC (permalink / raw) To: stu.hsieh Cc: Philipp Zabel, David Airlie, Rob Herring, Mark Rutland, Matthias Brugger, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, srv_heupstream Hi, Stu: I've some inline comment. On Fri, 2018-05-25 at 10:34 +0800, stu.hsieh@mediatek.com wrote: > From: Stu Hsieh <stu.hsieh@mediatek.com> > > This patch add support for the Mediatek MT2712 DISP subsystem. > There are two OVL engine and three disp output in MT2712. > > Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 46 +++++++++++++++++++++++++++-- > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 8 +++-- > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 42 ++++++++++++++++++++++++-- > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 7 +++-- > 4 files changed, 94 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > index 0f568dd853d8..676726249ae0 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > @@ -61,6 +61,24 @@ > #define MT8173_MUTEX_MOD_DISP_PWM1 24 > #define MT8173_MUTEX_MOD_DISP_OD 25 > > +#define MT2712_MUTEX_MOD_DISP_OVL0 11 > +#define MT2712_MUTEX_MOD_DISP_OVL1 12 > +#define MT2712_MUTEX_MOD_DISP_RDMA0 13 > +#define MT2712_MUTEX_MOD_DISP_RDMA1 14 > +#define MT2712_MUTEX_MOD_DISP_RDMA2 15 > +#define MT2712_MUTEX_MOD_DISP_WDMA0 16 > +#define MT2712_MUTEX_MOD_DISP_WDMA1 17 > +#define MT2712_MUTEX_MOD_DISP_COLOR0 18 > +#define MT2712_MUTEX_MOD_DISP_COLOR1 19 > +#define MT2712_MUTEX_MOD_DISP_AAL0 20 > +#define MT2712_MUTEX_MOD_DISP_UFOE 22 > +#define MT2712_MUTEX_MOD_DISP_PWM0 23 > +#define MT2712_MUTEX_MOD_DISP_PWM1 24 > +#define MT2712_MUTEX_MOD_DISP_PWM2 10 > +#define MT2712_MUTEX_MOD_DISP_OD0 25 > +#define MT2712_MUTEX_MOD2_DISP_AAL1 33 > +#define MT2712_MUTEX_MOD2_DISP_OD1 34 I would like this to be in the order by index. > + > #define MT2701_MUTEX_MOD_DISP_OVL 3 > #define MT2701_MUTEX_MOD_DISP_WDMA 6 > #define MT2701_MUTEX_MOD_DISP_COLOR 7 > @@ -75,6 +93,7 @@ > > #define OVL0_MOUT_EN_COLOR0 0x1 > #define OD_MOUT_EN_RDMA0 0x1 > +#define OD1_MOUT_EN_RDMA1 BIT(16) > #define UFOE_MOUT_EN_DSI0 0x1 > #define COLOR0_SEL_IN_OVL0 0x1 > #define OVL1_MOUT_EN_COLOR1 0x1 > @@ -109,12 +128,32 @@ static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = { > [DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA, > }; > > +static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = { > + [DDP_COMPONENT_AAL0] = MT2712_MUTEX_MOD_DISP_AAL0, > + [DDP_COMPONENT_AAL1] = MT2712_MUTEX_MOD2_DISP_AAL1, > + [DDP_COMPONENT_COLOR0] = MT2712_MUTEX_MOD_DISP_COLOR0, > + [DDP_COMPONENT_COLOR1] = MT2712_MUTEX_MOD_DISP_COLOR1, > + [DDP_COMPONENT_OD0] = MT2712_MUTEX_MOD_DISP_OD0, > + [DDP_COMPONENT_OD1] = MT2712_MUTEX_MOD2_DISP_OD1, > + [DDP_COMPONENT_OVL0] = MT2712_MUTEX_MOD_DISP_OVL0, > + [DDP_COMPONENT_OVL1] = MT2712_MUTEX_MOD_DISP_OVL1, > + [DDP_COMPONENT_PWM0] = MT2712_MUTEX_MOD_DISP_PWM0, > + [DDP_COMPONENT_PWM1] = MT2712_MUTEX_MOD_DISP_PWM1, > + [DDP_COMPONENT_PWM2] = MT2712_MUTEX_MOD_DISP_PWM2, > + [DDP_COMPONENT_RDMA0] = MT2712_MUTEX_MOD_DISP_RDMA0, > + [DDP_COMPONENT_RDMA1] = MT2712_MUTEX_MOD_DISP_RDMA1, > + [DDP_COMPONENT_RDMA2] = MT2712_MUTEX_MOD_DISP_RDMA2, > + [DDP_COMPONENT_UFOE] = MT2712_MUTEX_MOD_DISP_UFOE, > + [DDP_COMPONENT_WDMA0] = MT2712_MUTEX_MOD_DISP_WDMA0, > + [DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1, > +}; > + > static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = { > - [DDP_COMPONENT_AAL] = MT8173_MUTEX_MOD_DISP_AAL, > + [DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL, Move this to the patch 'add ddp component AAL1'. > [DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0, > [DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1, > [DDP_COMPONENT_GAMMA] = MT8173_MUTEX_MOD_DISP_GAMMA, > - [DDP_COMPONENT_OD] = MT8173_MUTEX_MOD_DISP_OD, > + [DDP_COMPONENT_OD0] = MT8173_MUTEX_MOD_DISP_OD, Move this to the patch 'add ddp component OD1'. > [DDP_COMPONENT_OVL0] = MT8173_MUTEX_MOD_DISP_OVL0, > [DDP_COMPONENT_OVL1] = MT8173_MUTEX_MOD_DISP_OVL1, > [DDP_COMPONENT_PWM0] = MT8173_MUTEX_MOD_DISP_PWM0, > @@ -139,7 +178,7 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur, > } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { > *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; > value = OVL_MOUT_EN_RDMA; > - } else if (cur == DDP_COMPONENT_OD && next == DDP_COMPONENT_RDMA0) { > + } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { Move this to the patch 'add ddp component OD1'. > *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > value = OD_MOUT_EN_RDMA0; > } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { > @@ -429,6 +468,7 @@ static int mtk_ddp_remove(struct platform_device *pdev) > > static const struct of_device_id ddp_driver_dt_match[] = { > { .compatible = "mediatek,mt2701-disp-mutex", .data = mt2701_mutex_mod}, > + { .compatible = "mediatek,mt2712-disp-mutex", .data = mt2712_mutex_mod}, > { .compatible = "mediatek,mt8173-disp-mutex", .data = mt8173_mutex_mod}, > {}, > }; > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > index 4672317e3ad1..86e8c9e5df41 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > @@ -218,7 +218,8 @@ struct mtk_ddp_comp_match { > }; > > static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { > - [DDP_COMPONENT_AAL] = { MTK_DISP_AAL, 0, &ddp_aal }, > + [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal }, > + [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal }, Move this to the patch 'add ddp component AAL1'. > [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL }, > [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, NULL }, > [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, NULL }, > @@ -226,10 +227,13 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { > [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, NULL }, > [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, NULL }, > [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma }, > - [DDP_COMPONENT_OD] = { MTK_DISP_OD, 0, &ddp_od }, > + [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od }, > + [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od }, Move this to the patch 'add ddp component OD1' > [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, NULL }, > [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, NULL }, > [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, > + [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, Move this to the patch 'add ddp component PWM1' > + [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL }, Move this to the patch 'add ddp component PWM2' > [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, NULL }, > [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, NULL }, > [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, NULL }, > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > index a2ca90fc403c..b32c4cc8d051 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > @@ -146,11 +146,37 @@ static const enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = { > DDP_COMPONENT_DPI0, > }; > > +static const enum mtk_ddp_comp_id mt2712_mtk_ddp_main[] = { > + DDP_COMPONENT_OVL0, > + DDP_COMPONENT_COLOR0, > + DDP_COMPONENT_AAL0, > + DDP_COMPONENT_OD0, > + DDP_COMPONENT_RDMA0, > + DDP_COMPONENT_DPI0, > + DDP_COMPONENT_PWM0, > +}; > + > +static const enum mtk_ddp_comp_id mt2712_mtk_ddp_ext[] = { > + DDP_COMPONENT_OVL1, > + DDP_COMPONENT_COLOR1, > + DDP_COMPONENT_AAL1, > + DDP_COMPONENT_OD1, > + DDP_COMPONENT_RDMA1, > + DDP_COMPONENT_DPI1, > + DDP_COMPONENT_PWM1, > +}; > + > +static const enum mtk_ddp_comp_id mt2712_mtk_ddp_third[] = { > + DDP_COMPONENT_RDMA2, > + DDP_COMPONENT_DSI2, > + DDP_COMPONENT_PWM2, > +}; > + > static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = { > DDP_COMPONENT_OVL0, > DDP_COMPONENT_COLOR0, > - DDP_COMPONENT_AAL, > - DDP_COMPONENT_OD, > + DDP_COMPONENT_AAL0, Move this to the patch 'add ddp component AAL1'. > + DDP_COMPONENT_OD0, Move this to the patch 'add ddp component OD1' > DDP_COMPONENT_RDMA0, > DDP_COMPONENT_UFOE, > DDP_COMPONENT_DSI0, > @@ -173,6 +199,15 @@ static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { > .shadow_register = true, > }; > > +static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { > + .main_path = mt2712_mtk_ddp_main, > + .main_len = ARRAY_SIZE(mt2712_mtk_ddp_main), > + .ext_path = mt2712_mtk_ddp_ext, > + .ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext), > + .third_path = mt2712_mtk_ddp_third, > + .third_len = ARRAY_SIZE(mt2712_mtk_ddp_third), > +}; > + > static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { > .main_path = mt8173_mtk_ddp_main, > .main_len = ARRAY_SIZE(mt8173_mtk_ddp_main), > @@ -374,6 +409,7 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { > { .compatible = "mediatek,mt8173-dsi", .data = (void *)MTK_DSI }, > { .compatible = "mediatek,mt8173-dpi", .data = (void *)MTK_DPI }, > { .compatible = "mediatek,mt2701-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, > + { .compatible = "mediatek,mt2712-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, > { .compatible = "mediatek,mt8173-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, > { .compatible = "mediatek,mt2701-disp-pwm", .data = (void *)MTK_DISP_BLS }, > { .compatible = "mediatek,mt8173-disp-pwm", .data = (void *)MTK_DISP_PWM }, > @@ -552,6 +588,8 @@ static SIMPLE_DEV_PM_OPS(mtk_drm_pm_ops, mtk_drm_sys_suspend, > static const struct of_device_id mtk_drm_of_ids[] = { > { .compatible = "mediatek,mt2701-mmsys", > .data = &mt2701_mmsys_driver_data}, > + { .compatible = "mediatek,mt2712-mmsys", > + .data = &mt2712_mmsys_driver_data}, > { .compatible = "mediatek,mt8173-mmsys", > .data = &mt8173_mmsys_driver_data}, > { } > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h > index c3378c452c0a..e821342bc2d3 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h > @@ -17,8 +17,8 @@ > #include <linux/io.h> > #include "mtk_drm_ddp_comp.h" > > -#define MAX_CRTC 2 > -#define MAX_CONNECTOR 2 > +#define MAX_CRTC 3 > +#define MAX_CONNECTOR 3 > > struct device; > struct device_node; > @@ -33,6 +33,9 @@ struct mtk_mmsys_driver_data { > unsigned int main_len; > const enum mtk_ddp_comp_id *ext_path; > unsigned int ext_len; > + enum mtk_ddp_comp_id *third_path; > + unsigned int third_len; > + Move this to the patch 'add third ddp path'. > bool shadow_register; > }; > Regards, CK ^ permalink raw reply [flat|nested] 66+ messages in thread
* [PATCH v3 7/8] drm/mediatek: Add support for mediatek SOC MT2712 @ 2018-05-25 4:51 ` CK Hu 0 siblings, 0 replies; 66+ messages in thread From: CK Hu @ 2018-05-25 4:51 UTC (permalink / raw) To: linux-arm-kernel Hi, Stu: I've some inline comment. On Fri, 2018-05-25 at 10:34 +0800, stu.hsieh at mediatek.com wrote: > From: Stu Hsieh <stu.hsieh@mediatek.com> > > This patch add support for the Mediatek MT2712 DISP subsystem. > There are two OVL engine and three disp output in MT2712. > > Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 46 +++++++++++++++++++++++++++-- > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 8 +++-- > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 42 ++++++++++++++++++++++++-- > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 7 +++-- > 4 files changed, 94 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > index 0f568dd853d8..676726249ae0 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > @@ -61,6 +61,24 @@ > #define MT8173_MUTEX_MOD_DISP_PWM1 24 > #define MT8173_MUTEX_MOD_DISP_OD 25 > > +#define MT2712_MUTEX_MOD_DISP_OVL0 11 > +#define MT2712_MUTEX_MOD_DISP_OVL1 12 > +#define MT2712_MUTEX_MOD_DISP_RDMA0 13 > +#define MT2712_MUTEX_MOD_DISP_RDMA1 14 > +#define MT2712_MUTEX_MOD_DISP_RDMA2 15 > +#define MT2712_MUTEX_MOD_DISP_WDMA0 16 > +#define MT2712_MUTEX_MOD_DISP_WDMA1 17 > +#define MT2712_MUTEX_MOD_DISP_COLOR0 18 > +#define MT2712_MUTEX_MOD_DISP_COLOR1 19 > +#define MT2712_MUTEX_MOD_DISP_AAL0 20 > +#define MT2712_MUTEX_MOD_DISP_UFOE 22 > +#define MT2712_MUTEX_MOD_DISP_PWM0 23 > +#define MT2712_MUTEX_MOD_DISP_PWM1 24 > +#define MT2712_MUTEX_MOD_DISP_PWM2 10 > +#define MT2712_MUTEX_MOD_DISP_OD0 25 > +#define MT2712_MUTEX_MOD2_DISP_AAL1 33 > +#define MT2712_MUTEX_MOD2_DISP_OD1 34 I would like this to be in the order by index. > + > #define MT2701_MUTEX_MOD_DISP_OVL 3 > #define MT2701_MUTEX_MOD_DISP_WDMA 6 > #define MT2701_MUTEX_MOD_DISP_COLOR 7 > @@ -75,6 +93,7 @@ > > #define OVL0_MOUT_EN_COLOR0 0x1 > #define OD_MOUT_EN_RDMA0 0x1 > +#define OD1_MOUT_EN_RDMA1 BIT(16) > #define UFOE_MOUT_EN_DSI0 0x1 > #define COLOR0_SEL_IN_OVL0 0x1 > #define OVL1_MOUT_EN_COLOR1 0x1 > @@ -109,12 +128,32 @@ static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = { > [DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA, > }; > > +static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = { > + [DDP_COMPONENT_AAL0] = MT2712_MUTEX_MOD_DISP_AAL0, > + [DDP_COMPONENT_AAL1] = MT2712_MUTEX_MOD2_DISP_AAL1, > + [DDP_COMPONENT_COLOR0] = MT2712_MUTEX_MOD_DISP_COLOR0, > + [DDP_COMPONENT_COLOR1] = MT2712_MUTEX_MOD_DISP_COLOR1, > + [DDP_COMPONENT_OD0] = MT2712_MUTEX_MOD_DISP_OD0, > + [DDP_COMPONENT_OD1] = MT2712_MUTEX_MOD2_DISP_OD1, > + [DDP_COMPONENT_OVL0] = MT2712_MUTEX_MOD_DISP_OVL0, > + [DDP_COMPONENT_OVL1] = MT2712_MUTEX_MOD_DISP_OVL1, > + [DDP_COMPONENT_PWM0] = MT2712_MUTEX_MOD_DISP_PWM0, > + [DDP_COMPONENT_PWM1] = MT2712_MUTEX_MOD_DISP_PWM1, > + [DDP_COMPONENT_PWM2] = MT2712_MUTEX_MOD_DISP_PWM2, > + [DDP_COMPONENT_RDMA0] = MT2712_MUTEX_MOD_DISP_RDMA0, > + [DDP_COMPONENT_RDMA1] = MT2712_MUTEX_MOD_DISP_RDMA1, > + [DDP_COMPONENT_RDMA2] = MT2712_MUTEX_MOD_DISP_RDMA2, > + [DDP_COMPONENT_UFOE] = MT2712_MUTEX_MOD_DISP_UFOE, > + [DDP_COMPONENT_WDMA0] = MT2712_MUTEX_MOD_DISP_WDMA0, > + [DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1, > +}; > + > static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = { > - [DDP_COMPONENT_AAL] = MT8173_MUTEX_MOD_DISP_AAL, > + [DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL, Move this to the patch 'add ddp component AAL1'. > [DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0, > [DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1, > [DDP_COMPONENT_GAMMA] = MT8173_MUTEX_MOD_DISP_GAMMA, > - [DDP_COMPONENT_OD] = MT8173_MUTEX_MOD_DISP_OD, > + [DDP_COMPONENT_OD0] = MT8173_MUTEX_MOD_DISP_OD, Move this to the patch 'add ddp component OD1'. > [DDP_COMPONENT_OVL0] = MT8173_MUTEX_MOD_DISP_OVL0, > [DDP_COMPONENT_OVL1] = MT8173_MUTEX_MOD_DISP_OVL1, > [DDP_COMPONENT_PWM0] = MT8173_MUTEX_MOD_DISP_PWM0, > @@ -139,7 +178,7 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur, > } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { > *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; > value = OVL_MOUT_EN_RDMA; > - } else if (cur == DDP_COMPONENT_OD && next == DDP_COMPONENT_RDMA0) { > + } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { Move this to the patch 'add ddp component OD1'. > *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > value = OD_MOUT_EN_RDMA0; > } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { > @@ -429,6 +468,7 @@ static int mtk_ddp_remove(struct platform_device *pdev) > > static const struct of_device_id ddp_driver_dt_match[] = { > { .compatible = "mediatek,mt2701-disp-mutex", .data = mt2701_mutex_mod}, > + { .compatible = "mediatek,mt2712-disp-mutex", .data = mt2712_mutex_mod}, > { .compatible = "mediatek,mt8173-disp-mutex", .data = mt8173_mutex_mod}, > {}, > }; > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > index 4672317e3ad1..86e8c9e5df41 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > @@ -218,7 +218,8 @@ struct mtk_ddp_comp_match { > }; > > static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { > - [DDP_COMPONENT_AAL] = { MTK_DISP_AAL, 0, &ddp_aal }, > + [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal }, > + [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal }, Move this to the patch 'add ddp component AAL1'. > [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL }, > [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, NULL }, > [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, NULL }, > @@ -226,10 +227,13 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { > [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, NULL }, > [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, NULL }, > [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma }, > - [DDP_COMPONENT_OD] = { MTK_DISP_OD, 0, &ddp_od }, > + [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od }, > + [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od }, Move this to the patch 'add ddp component OD1' > [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, NULL }, > [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, NULL }, > [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, > + [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, Move this to the patch 'add ddp component PWM1' > + [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL }, Move this to the patch 'add ddp component PWM2' > [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, NULL }, > [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, NULL }, > [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, NULL }, > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > index a2ca90fc403c..b32c4cc8d051 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > @@ -146,11 +146,37 @@ static const enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = { > DDP_COMPONENT_DPI0, > }; > > +static const enum mtk_ddp_comp_id mt2712_mtk_ddp_main[] = { > + DDP_COMPONENT_OVL0, > + DDP_COMPONENT_COLOR0, > + DDP_COMPONENT_AAL0, > + DDP_COMPONENT_OD0, > + DDP_COMPONENT_RDMA0, > + DDP_COMPONENT_DPI0, > + DDP_COMPONENT_PWM0, > +}; > + > +static const enum mtk_ddp_comp_id mt2712_mtk_ddp_ext[] = { > + DDP_COMPONENT_OVL1, > + DDP_COMPONENT_COLOR1, > + DDP_COMPONENT_AAL1, > + DDP_COMPONENT_OD1, > + DDP_COMPONENT_RDMA1, > + DDP_COMPONENT_DPI1, > + DDP_COMPONENT_PWM1, > +}; > + > +static const enum mtk_ddp_comp_id mt2712_mtk_ddp_third[] = { > + DDP_COMPONENT_RDMA2, > + DDP_COMPONENT_DSI2, > + DDP_COMPONENT_PWM2, > +}; > + > static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = { > DDP_COMPONENT_OVL0, > DDP_COMPONENT_COLOR0, > - DDP_COMPONENT_AAL, > - DDP_COMPONENT_OD, > + DDP_COMPONENT_AAL0, Move this to the patch 'add ddp component AAL1'. > + DDP_COMPONENT_OD0, Move this to the patch 'add ddp component OD1' > DDP_COMPONENT_RDMA0, > DDP_COMPONENT_UFOE, > DDP_COMPONENT_DSI0, > @@ -173,6 +199,15 @@ static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { > .shadow_register = true, > }; > > +static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { > + .main_path = mt2712_mtk_ddp_main, > + .main_len = ARRAY_SIZE(mt2712_mtk_ddp_main), > + .ext_path = mt2712_mtk_ddp_ext, > + .ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext), > + .third_path = mt2712_mtk_ddp_third, > + .third_len = ARRAY_SIZE(mt2712_mtk_ddp_third), > +}; > + > static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { > .main_path = mt8173_mtk_ddp_main, > .main_len = ARRAY_SIZE(mt8173_mtk_ddp_main), > @@ -374,6 +409,7 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { > { .compatible = "mediatek,mt8173-dsi", .data = (void *)MTK_DSI }, > { .compatible = "mediatek,mt8173-dpi", .data = (void *)MTK_DPI }, > { .compatible = "mediatek,mt2701-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, > + { .compatible = "mediatek,mt2712-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, > { .compatible = "mediatek,mt8173-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, > { .compatible = "mediatek,mt2701-disp-pwm", .data = (void *)MTK_DISP_BLS }, > { .compatible = "mediatek,mt8173-disp-pwm", .data = (void *)MTK_DISP_PWM }, > @@ -552,6 +588,8 @@ static SIMPLE_DEV_PM_OPS(mtk_drm_pm_ops, mtk_drm_sys_suspend, > static const struct of_device_id mtk_drm_of_ids[] = { > { .compatible = "mediatek,mt2701-mmsys", > .data = &mt2701_mmsys_driver_data}, > + { .compatible = "mediatek,mt2712-mmsys", > + .data = &mt2712_mmsys_driver_data}, > { .compatible = "mediatek,mt8173-mmsys", > .data = &mt8173_mmsys_driver_data}, > { } > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h > index c3378c452c0a..e821342bc2d3 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h > @@ -17,8 +17,8 @@ > #include <linux/io.h> > #include "mtk_drm_ddp_comp.h" > > -#define MAX_CRTC 2 > -#define MAX_CONNECTOR 2 > +#define MAX_CRTC 3 > +#define MAX_CONNECTOR 3 > > struct device; > struct device_node; > @@ -33,6 +33,9 @@ struct mtk_mmsys_driver_data { > unsigned int main_len; > const enum mtk_ddp_comp_id *ext_path; > unsigned int ext_len; > + enum mtk_ddp_comp_id *third_path; > + unsigned int third_len; > + Move this to the patch 'add third ddp path'. > bool shadow_register; > }; > Regards, CK ^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [PATCH v3 7/8] drm/mediatek: Add support for mediatek SOC MT2712 @ 2018-05-25 4:51 ` CK Hu 0 siblings, 0 replies; 66+ messages in thread From: CK Hu @ 2018-05-25 4:51 UTC (permalink / raw) To: stu.hsieh Cc: Mark Rutland, devicetree, srv_heupstream, David Airlie, linux-kernel, dri-devel, Rob Herring, linux-mediatek, Matthias Brugger, linux-arm-kernel Hi, Stu: I've some inline comment. On Fri, 2018-05-25 at 10:34 +0800, stu.hsieh@mediatek.com wrote: > From: Stu Hsieh <stu.hsieh@mediatek.com> > > This patch add support for the Mediatek MT2712 DISP subsystem. > There are two OVL engine and three disp output in MT2712. > > Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 46 +++++++++++++++++++++++++++-- > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 8 +++-- > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 42 ++++++++++++++++++++++++-- > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 7 +++-- > 4 files changed, 94 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > index 0f568dd853d8..676726249ae0 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > @@ -61,6 +61,24 @@ > #define MT8173_MUTEX_MOD_DISP_PWM1 24 > #define MT8173_MUTEX_MOD_DISP_OD 25 > > +#define MT2712_MUTEX_MOD_DISP_OVL0 11 > +#define MT2712_MUTEX_MOD_DISP_OVL1 12 > +#define MT2712_MUTEX_MOD_DISP_RDMA0 13 > +#define MT2712_MUTEX_MOD_DISP_RDMA1 14 > +#define MT2712_MUTEX_MOD_DISP_RDMA2 15 > +#define MT2712_MUTEX_MOD_DISP_WDMA0 16 > +#define MT2712_MUTEX_MOD_DISP_WDMA1 17 > +#define MT2712_MUTEX_MOD_DISP_COLOR0 18 > +#define MT2712_MUTEX_MOD_DISP_COLOR1 19 > +#define MT2712_MUTEX_MOD_DISP_AAL0 20 > +#define MT2712_MUTEX_MOD_DISP_UFOE 22 > +#define MT2712_MUTEX_MOD_DISP_PWM0 23 > +#define MT2712_MUTEX_MOD_DISP_PWM1 24 > +#define MT2712_MUTEX_MOD_DISP_PWM2 10 > +#define MT2712_MUTEX_MOD_DISP_OD0 25 > +#define MT2712_MUTEX_MOD2_DISP_AAL1 33 > +#define MT2712_MUTEX_MOD2_DISP_OD1 34 I would like this to be in the order by index. > + > #define MT2701_MUTEX_MOD_DISP_OVL 3 > #define MT2701_MUTEX_MOD_DISP_WDMA 6 > #define MT2701_MUTEX_MOD_DISP_COLOR 7 > @@ -75,6 +93,7 @@ > > #define OVL0_MOUT_EN_COLOR0 0x1 > #define OD_MOUT_EN_RDMA0 0x1 > +#define OD1_MOUT_EN_RDMA1 BIT(16) > #define UFOE_MOUT_EN_DSI0 0x1 > #define COLOR0_SEL_IN_OVL0 0x1 > #define OVL1_MOUT_EN_COLOR1 0x1 > @@ -109,12 +128,32 @@ static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = { > [DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA, > }; > > +static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = { > + [DDP_COMPONENT_AAL0] = MT2712_MUTEX_MOD_DISP_AAL0, > + [DDP_COMPONENT_AAL1] = MT2712_MUTEX_MOD2_DISP_AAL1, > + [DDP_COMPONENT_COLOR0] = MT2712_MUTEX_MOD_DISP_COLOR0, > + [DDP_COMPONENT_COLOR1] = MT2712_MUTEX_MOD_DISP_COLOR1, > + [DDP_COMPONENT_OD0] = MT2712_MUTEX_MOD_DISP_OD0, > + [DDP_COMPONENT_OD1] = MT2712_MUTEX_MOD2_DISP_OD1, > + [DDP_COMPONENT_OVL0] = MT2712_MUTEX_MOD_DISP_OVL0, > + [DDP_COMPONENT_OVL1] = MT2712_MUTEX_MOD_DISP_OVL1, > + [DDP_COMPONENT_PWM0] = MT2712_MUTEX_MOD_DISP_PWM0, > + [DDP_COMPONENT_PWM1] = MT2712_MUTEX_MOD_DISP_PWM1, > + [DDP_COMPONENT_PWM2] = MT2712_MUTEX_MOD_DISP_PWM2, > + [DDP_COMPONENT_RDMA0] = MT2712_MUTEX_MOD_DISP_RDMA0, > + [DDP_COMPONENT_RDMA1] = MT2712_MUTEX_MOD_DISP_RDMA1, > + [DDP_COMPONENT_RDMA2] = MT2712_MUTEX_MOD_DISP_RDMA2, > + [DDP_COMPONENT_UFOE] = MT2712_MUTEX_MOD_DISP_UFOE, > + [DDP_COMPONENT_WDMA0] = MT2712_MUTEX_MOD_DISP_WDMA0, > + [DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1, > +}; > + > static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = { > - [DDP_COMPONENT_AAL] = MT8173_MUTEX_MOD_DISP_AAL, > + [DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL, Move this to the patch 'add ddp component AAL1'. > [DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0, > [DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1, > [DDP_COMPONENT_GAMMA] = MT8173_MUTEX_MOD_DISP_GAMMA, > - [DDP_COMPONENT_OD] = MT8173_MUTEX_MOD_DISP_OD, > + [DDP_COMPONENT_OD0] = MT8173_MUTEX_MOD_DISP_OD, Move this to the patch 'add ddp component OD1'. > [DDP_COMPONENT_OVL0] = MT8173_MUTEX_MOD_DISP_OVL0, > [DDP_COMPONENT_OVL1] = MT8173_MUTEX_MOD_DISP_OVL1, > [DDP_COMPONENT_PWM0] = MT8173_MUTEX_MOD_DISP_PWM0, > @@ -139,7 +178,7 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur, > } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { > *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; > value = OVL_MOUT_EN_RDMA; > - } else if (cur == DDP_COMPONENT_OD && next == DDP_COMPONENT_RDMA0) { > + } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { Move this to the patch 'add ddp component OD1'. > *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > value = OD_MOUT_EN_RDMA0; > } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { > @@ -429,6 +468,7 @@ static int mtk_ddp_remove(struct platform_device *pdev) > > static const struct of_device_id ddp_driver_dt_match[] = { > { .compatible = "mediatek,mt2701-disp-mutex", .data = mt2701_mutex_mod}, > + { .compatible = "mediatek,mt2712-disp-mutex", .data = mt2712_mutex_mod}, > { .compatible = "mediatek,mt8173-disp-mutex", .data = mt8173_mutex_mod}, > {}, > }; > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > index 4672317e3ad1..86e8c9e5df41 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > @@ -218,7 +218,8 @@ struct mtk_ddp_comp_match { > }; > > static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { > - [DDP_COMPONENT_AAL] = { MTK_DISP_AAL, 0, &ddp_aal }, > + [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal }, > + [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal }, Move this to the patch 'add ddp component AAL1'. > [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL }, > [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, NULL }, > [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, NULL }, > @@ -226,10 +227,13 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { > [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, NULL }, > [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, NULL }, > [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma }, > - [DDP_COMPONENT_OD] = { MTK_DISP_OD, 0, &ddp_od }, > + [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od }, > + [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od }, Move this to the patch 'add ddp component OD1' > [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, NULL }, > [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, NULL }, > [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, > + [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, Move this to the patch 'add ddp component PWM1' > + [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL }, Move this to the patch 'add ddp component PWM2' > [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, NULL }, > [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, NULL }, > [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, NULL }, > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > index a2ca90fc403c..b32c4cc8d051 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > @@ -146,11 +146,37 @@ static const enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = { > DDP_COMPONENT_DPI0, > }; > > +static const enum mtk_ddp_comp_id mt2712_mtk_ddp_main[] = { > + DDP_COMPONENT_OVL0, > + DDP_COMPONENT_COLOR0, > + DDP_COMPONENT_AAL0, > + DDP_COMPONENT_OD0, > + DDP_COMPONENT_RDMA0, > + DDP_COMPONENT_DPI0, > + DDP_COMPONENT_PWM0, > +}; > + > +static const enum mtk_ddp_comp_id mt2712_mtk_ddp_ext[] = { > + DDP_COMPONENT_OVL1, > + DDP_COMPONENT_COLOR1, > + DDP_COMPONENT_AAL1, > + DDP_COMPONENT_OD1, > + DDP_COMPONENT_RDMA1, > + DDP_COMPONENT_DPI1, > + DDP_COMPONENT_PWM1, > +}; > + > +static const enum mtk_ddp_comp_id mt2712_mtk_ddp_third[] = { > + DDP_COMPONENT_RDMA2, > + DDP_COMPONENT_DSI2, > + DDP_COMPONENT_PWM2, > +}; > + > static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = { > DDP_COMPONENT_OVL0, > DDP_COMPONENT_COLOR0, > - DDP_COMPONENT_AAL, > - DDP_COMPONENT_OD, > + DDP_COMPONENT_AAL0, Move this to the patch 'add ddp component AAL1'. > + DDP_COMPONENT_OD0, Move this to the patch 'add ddp component OD1' > DDP_COMPONENT_RDMA0, > DDP_COMPONENT_UFOE, > DDP_COMPONENT_DSI0, > @@ -173,6 +199,15 @@ static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { > .shadow_register = true, > }; > > +static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { > + .main_path = mt2712_mtk_ddp_main, > + .main_len = ARRAY_SIZE(mt2712_mtk_ddp_main), > + .ext_path = mt2712_mtk_ddp_ext, > + .ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext), > + .third_path = mt2712_mtk_ddp_third, > + .third_len = ARRAY_SIZE(mt2712_mtk_ddp_third), > +}; > + > static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { > .main_path = mt8173_mtk_ddp_main, > .main_len = ARRAY_SIZE(mt8173_mtk_ddp_main), > @@ -374,6 +409,7 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { > { .compatible = "mediatek,mt8173-dsi", .data = (void *)MTK_DSI }, > { .compatible = "mediatek,mt8173-dpi", .data = (void *)MTK_DPI }, > { .compatible = "mediatek,mt2701-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, > + { .compatible = "mediatek,mt2712-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, > { .compatible = "mediatek,mt8173-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, > { .compatible = "mediatek,mt2701-disp-pwm", .data = (void *)MTK_DISP_BLS }, > { .compatible = "mediatek,mt8173-disp-pwm", .data = (void *)MTK_DISP_PWM }, > @@ -552,6 +588,8 @@ static SIMPLE_DEV_PM_OPS(mtk_drm_pm_ops, mtk_drm_sys_suspend, > static const struct of_device_id mtk_drm_of_ids[] = { > { .compatible = "mediatek,mt2701-mmsys", > .data = &mt2701_mmsys_driver_data}, > + { .compatible = "mediatek,mt2712-mmsys", > + .data = &mt2712_mmsys_driver_data}, > { .compatible = "mediatek,mt8173-mmsys", > .data = &mt8173_mmsys_driver_data}, > { } > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h > index c3378c452c0a..e821342bc2d3 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h > @@ -17,8 +17,8 @@ > #include <linux/io.h> > #include "mtk_drm_ddp_comp.h" > > -#define MAX_CRTC 2 > -#define MAX_CONNECTOR 2 > +#define MAX_CRTC 3 > +#define MAX_CONNECTOR 3 > > struct device; > struct device_node; > @@ -33,6 +33,9 @@ struct mtk_mmsys_driver_data { > unsigned int main_len; > const enum mtk_ddp_comp_id *ext_path; > unsigned int ext_len; > + enum mtk_ddp_comp_id *third_path; > + unsigned int third_len; > + Move this to the patch 'add third ddp path'. > bool shadow_register; > }; > Regards, CK _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [PATCH v3 7/8] drm/mediatek: Add support for mediatek SOC MT2712 2018-05-25 4:51 ` CK Hu (?) @ 2018-05-25 9:33 ` Stu Hsieh -1 siblings, 0 replies; 66+ messages in thread From: Stu Hsieh @ 2018-05-25 9:33 UTC (permalink / raw) To: CK Hu Cc: Philipp Zabel, David Airlie, Rob Herring, Mark Rutland, Matthias Brugger, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, srv_heupstream Hi, CK: On Fri, 2018-05-25 at 12:51 +0800, CK Hu wrote: > Hi, Stu: > > I've some inline comment. > > On Fri, 2018-05-25 at 10:34 +0800, stu.hsieh@mediatek.com wrote: > > From: Stu Hsieh <stu.hsieh@mediatek.com> > > > > This patch add support for the Mediatek MT2712 DISP subsystem. > > There are two OVL engine and three disp output in MT2712. > > > > Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> > > --- > > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 46 +++++++++++++++++++++++++++-- > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 8 +++-- > > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 42 ++++++++++++++++++++++++-- > > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 7 +++-- > > 4 files changed, 94 insertions(+), 9 deletions(-) > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > index 0f568dd853d8..676726249ae0 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > @@ -61,6 +61,24 @@ > > #define MT8173_MUTEX_MOD_DISP_PWM1 24 > > #define MT8173_MUTEX_MOD_DISP_OD 25 > > > > +#define MT2712_MUTEX_MOD_DISP_OVL0 11 > > +#define MT2712_MUTEX_MOD_DISP_OVL1 12 > > +#define MT2712_MUTEX_MOD_DISP_RDMA0 13 > > +#define MT2712_MUTEX_MOD_DISP_RDMA1 14 > > +#define MT2712_MUTEX_MOD_DISP_RDMA2 15 > > +#define MT2712_MUTEX_MOD_DISP_WDMA0 16 > > +#define MT2712_MUTEX_MOD_DISP_WDMA1 17 > > +#define MT2712_MUTEX_MOD_DISP_COLOR0 18 > > +#define MT2712_MUTEX_MOD_DISP_COLOR1 19 > > +#define MT2712_MUTEX_MOD_DISP_AAL0 20 > > +#define MT2712_MUTEX_MOD_DISP_UFOE 22 > > +#define MT2712_MUTEX_MOD_DISP_PWM0 23 > > +#define MT2712_MUTEX_MOD_DISP_PWM1 24 > > +#define MT2712_MUTEX_MOD_DISP_PWM2 10 > > +#define MT2712_MUTEX_MOD_DISP_OD0 25 > > +#define MT2712_MUTEX_MOD2_DISP_AAL1 33 > > +#define MT2712_MUTEX_MOD2_DISP_OD1 34 > > I would like this to be in the order by index. OK > > > + > > #define MT2701_MUTEX_MOD_DISP_OVL 3 > > #define MT2701_MUTEX_MOD_DISP_WDMA 6 > > #define MT2701_MUTEX_MOD_DISP_COLOR 7 > > @@ -75,6 +93,7 @@ > > > > #define OVL0_MOUT_EN_COLOR0 0x1 > > #define OD_MOUT_EN_RDMA0 0x1 > > +#define OD1_MOUT_EN_RDMA1 BIT(16) > > #define UFOE_MOUT_EN_DSI0 0x1 > > #define COLOR0_SEL_IN_OVL0 0x1 > > #define OVL1_MOUT_EN_COLOR1 0x1 > > @@ -109,12 +128,32 @@ static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = { > > [DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA, > > }; > > > > +static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = { > > + [DDP_COMPONENT_AAL0] = MT2712_MUTEX_MOD_DISP_AAL0, > > + [DDP_COMPONENT_AAL1] = MT2712_MUTEX_MOD2_DISP_AAL1, > > + [DDP_COMPONENT_COLOR0] = MT2712_MUTEX_MOD_DISP_COLOR0, > > + [DDP_COMPONENT_COLOR1] = MT2712_MUTEX_MOD_DISP_COLOR1, > > + [DDP_COMPONENT_OD0] = MT2712_MUTEX_MOD_DISP_OD0, > > + [DDP_COMPONENT_OD1] = MT2712_MUTEX_MOD2_DISP_OD1, > > + [DDP_COMPONENT_OVL0] = MT2712_MUTEX_MOD_DISP_OVL0, > > + [DDP_COMPONENT_OVL1] = MT2712_MUTEX_MOD_DISP_OVL1, > > + [DDP_COMPONENT_PWM0] = MT2712_MUTEX_MOD_DISP_PWM0, > > + [DDP_COMPONENT_PWM1] = MT2712_MUTEX_MOD_DISP_PWM1, > > + [DDP_COMPONENT_PWM2] = MT2712_MUTEX_MOD_DISP_PWM2, > > + [DDP_COMPONENT_RDMA0] = MT2712_MUTEX_MOD_DISP_RDMA0, > > + [DDP_COMPONENT_RDMA1] = MT2712_MUTEX_MOD_DISP_RDMA1, > > + [DDP_COMPONENT_RDMA2] = MT2712_MUTEX_MOD_DISP_RDMA2, > > + [DDP_COMPONENT_UFOE] = MT2712_MUTEX_MOD_DISP_UFOE, > > + [DDP_COMPONENT_WDMA0] = MT2712_MUTEX_MOD_DISP_WDMA0, > > + [DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1, > > +}; > > + > > static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = { > > - [DDP_COMPONENT_AAL] = MT8173_MUTEX_MOD_DISP_AAL, > > + [DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL, > > Move this to the patch 'add ddp component AAL1'. OK > > > [DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0, > > [DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1, > > [DDP_COMPONENT_GAMMA] = MT8173_MUTEX_MOD_DISP_GAMMA, > > - [DDP_COMPONENT_OD] = MT8173_MUTEX_MOD_DISP_OD, > > + [DDP_COMPONENT_OD0] = MT8173_MUTEX_MOD_DISP_OD, > > Move this to the patch 'add ddp component OD1'. OK > > > [DDP_COMPONENT_OVL0] = MT8173_MUTEX_MOD_DISP_OVL0, > > [DDP_COMPONENT_OVL1] = MT8173_MUTEX_MOD_DISP_OVL1, > > [DDP_COMPONENT_PWM0] = MT8173_MUTEX_MOD_DISP_PWM0, > > @@ -139,7 +178,7 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur, > > } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { > > *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; > > value = OVL_MOUT_EN_RDMA; > > - } else if (cur == DDP_COMPONENT_OD && next == DDP_COMPONENT_RDMA0) { > > + } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { > > Move this to the patch 'add ddp component OD1'. OK > > > *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > > value = OD_MOUT_EN_RDMA0; > > } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { > > @@ -429,6 +468,7 @@ static int mtk_ddp_remove(struct platform_device *pdev) > > > > static const struct of_device_id ddp_driver_dt_match[] = { > > { .compatible = "mediatek,mt2701-disp-mutex", .data = mt2701_mutex_mod}, > > + { .compatible = "mediatek,mt2712-disp-mutex", .data = mt2712_mutex_mod}, > > { .compatible = "mediatek,mt8173-disp-mutex", .data = mt8173_mutex_mod}, > > {}, > > }; > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > index 4672317e3ad1..86e8c9e5df41 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > @@ -218,7 +218,8 @@ struct mtk_ddp_comp_match { > > }; > > > > static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { > > - [DDP_COMPONENT_AAL] = { MTK_DISP_AAL, 0, &ddp_aal }, > > + [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal }, > > + [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal }, > > Move this to the patch 'add ddp component AAL1'. ok > > > [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL }, > > [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, NULL }, > > [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, NULL }, > > @@ -226,10 +227,13 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { > > [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, NULL }, > > [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, NULL }, > > [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma }, > > - [DDP_COMPONENT_OD] = { MTK_DISP_OD, 0, &ddp_od }, > > + [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od }, > > + [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od }, > > Move this to the patch 'add ddp component OD1' ok > > > [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, NULL }, > > [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, NULL }, > > [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, > > + [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, > > Move this to the patch 'add ddp component PWM1' ok, i would create the new patch for 'add ddp component PWM1' > > > + [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL }, > > Move this to the patch 'add ddp component PWM2' ok > > > [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, NULL }, > > [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, NULL }, > > [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, NULL }, > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > > index a2ca90fc403c..b32c4cc8d051 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > > @@ -146,11 +146,37 @@ static const enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = { > > DDP_COMPONENT_DPI0, > > }; > > > > +static const enum mtk_ddp_comp_id mt2712_mtk_ddp_main[] = { > > + DDP_COMPONENT_OVL0, > > + DDP_COMPONENT_COLOR0, > > + DDP_COMPONENT_AAL0, > > + DDP_COMPONENT_OD0, > > + DDP_COMPONENT_RDMA0, > > + DDP_COMPONENT_DPI0, > > + DDP_COMPONENT_PWM0, > > +}; > > + > > +static const enum mtk_ddp_comp_id mt2712_mtk_ddp_ext[] = { > > + DDP_COMPONENT_OVL1, > > + DDP_COMPONENT_COLOR1, > > + DDP_COMPONENT_AAL1, > > + DDP_COMPONENT_OD1, > > + DDP_COMPONENT_RDMA1, > > + DDP_COMPONENT_DPI1, > > + DDP_COMPONENT_PWM1, > > +}; > > + > > +static const enum mtk_ddp_comp_id mt2712_mtk_ddp_third[] = { > > + DDP_COMPONENT_RDMA2, > > + DDP_COMPONENT_DSI2, > > + DDP_COMPONENT_PWM2, > > +}; > > + > > static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = { > > DDP_COMPONENT_OVL0, > > DDP_COMPONENT_COLOR0, > > - DDP_COMPONENT_AAL, > > - DDP_COMPONENT_OD, > > + DDP_COMPONENT_AAL0, > > Move this to the patch 'add ddp component AAL1'. ok > > > + DDP_COMPONENT_OD0, > > Move this to the patch 'add ddp component OD1' ok > > > DDP_COMPONENT_RDMA0, > > DDP_COMPONENT_UFOE, > > DDP_COMPONENT_DSI0, > > @@ -173,6 +199,15 @@ static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { > > .shadow_register = true, > > }; > > > > +static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { > > + .main_path = mt2712_mtk_ddp_main, > > + .main_len = ARRAY_SIZE(mt2712_mtk_ddp_main), > > + .ext_path = mt2712_mtk_ddp_ext, > > + .ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext), > > + .third_path = mt2712_mtk_ddp_third, > > + .third_len = ARRAY_SIZE(mt2712_mtk_ddp_third), > > +}; > > + > > static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { > > .main_path = mt8173_mtk_ddp_main, > > .main_len = ARRAY_SIZE(mt8173_mtk_ddp_main), > > @@ -374,6 +409,7 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { > > { .compatible = "mediatek,mt8173-dsi", .data = (void *)MTK_DSI }, > > { .compatible = "mediatek,mt8173-dpi", .data = (void *)MTK_DPI }, > > { .compatible = "mediatek,mt2701-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, > > + { .compatible = "mediatek,mt2712-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, > > { .compatible = "mediatek,mt8173-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, > > { .compatible = "mediatek,mt2701-disp-pwm", .data = (void *)MTK_DISP_BLS }, > > { .compatible = "mediatek,mt8173-disp-pwm", .data = (void *)MTK_DISP_PWM }, > > @@ -552,6 +588,8 @@ static SIMPLE_DEV_PM_OPS(mtk_drm_pm_ops, mtk_drm_sys_suspend, > > static const struct of_device_id mtk_drm_of_ids[] = { > > { .compatible = "mediatek,mt2701-mmsys", > > .data = &mt2701_mmsys_driver_data}, > > + { .compatible = "mediatek,mt2712-mmsys", > > + .data = &mt2712_mmsys_driver_data}, > > { .compatible = "mediatek,mt8173-mmsys", > > .data = &mt8173_mmsys_driver_data}, > > { } > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h > > index c3378c452c0a..e821342bc2d3 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h > > @@ -17,8 +17,8 @@ > > #include <linux/io.h> > > #include "mtk_drm_ddp_comp.h" > > > > -#define MAX_CRTC 2 > > -#define MAX_CONNECTOR 2 > > +#define MAX_CRTC 3 > > +#define MAX_CONNECTOR 3 > > > > struct device; > > struct device_node; > > @@ -33,6 +33,9 @@ struct mtk_mmsys_driver_data { > > unsigned int main_len; > > const enum mtk_ddp_comp_id *ext_path; > > unsigned int ext_len; > > + enum mtk_ddp_comp_id *third_path; > > + unsigned int third_len; > > + > > Move this to the patch 'add third ddp path'. ok > > > bool shadow_register; > > }; > > > > Regards, > CK > > ^ permalink raw reply [flat|nested] 66+ messages in thread
* [PATCH v3 7/8] drm/mediatek: Add support for mediatek SOC MT2712 @ 2018-05-25 9:33 ` Stu Hsieh 0 siblings, 0 replies; 66+ messages in thread From: Stu Hsieh @ 2018-05-25 9:33 UTC (permalink / raw) To: linux-arm-kernel Hi, CK: On Fri, 2018-05-25 at 12:51 +0800, CK Hu wrote: > Hi, Stu: > > I've some inline comment. > > On Fri, 2018-05-25 at 10:34 +0800, stu.hsieh at mediatek.com wrote: > > From: Stu Hsieh <stu.hsieh@mediatek.com> > > > > This patch add support for the Mediatek MT2712 DISP subsystem. > > There are two OVL engine and three disp output in MT2712. > > > > Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> > > --- > > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 46 +++++++++++++++++++++++++++-- > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 8 +++-- > > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 42 ++++++++++++++++++++++++-- > > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 7 +++-- > > 4 files changed, 94 insertions(+), 9 deletions(-) > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > index 0f568dd853d8..676726249ae0 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > @@ -61,6 +61,24 @@ > > #define MT8173_MUTEX_MOD_DISP_PWM1 24 > > #define MT8173_MUTEX_MOD_DISP_OD 25 > > > > +#define MT2712_MUTEX_MOD_DISP_OVL0 11 > > +#define MT2712_MUTEX_MOD_DISP_OVL1 12 > > +#define MT2712_MUTEX_MOD_DISP_RDMA0 13 > > +#define MT2712_MUTEX_MOD_DISP_RDMA1 14 > > +#define MT2712_MUTEX_MOD_DISP_RDMA2 15 > > +#define MT2712_MUTEX_MOD_DISP_WDMA0 16 > > +#define MT2712_MUTEX_MOD_DISP_WDMA1 17 > > +#define MT2712_MUTEX_MOD_DISP_COLOR0 18 > > +#define MT2712_MUTEX_MOD_DISP_COLOR1 19 > > +#define MT2712_MUTEX_MOD_DISP_AAL0 20 > > +#define MT2712_MUTEX_MOD_DISP_UFOE 22 > > +#define MT2712_MUTEX_MOD_DISP_PWM0 23 > > +#define MT2712_MUTEX_MOD_DISP_PWM1 24 > > +#define MT2712_MUTEX_MOD_DISP_PWM2 10 > > +#define MT2712_MUTEX_MOD_DISP_OD0 25 > > +#define MT2712_MUTEX_MOD2_DISP_AAL1 33 > > +#define MT2712_MUTEX_MOD2_DISP_OD1 34 > > I would like this to be in the order by index. OK > > > + > > #define MT2701_MUTEX_MOD_DISP_OVL 3 > > #define MT2701_MUTEX_MOD_DISP_WDMA 6 > > #define MT2701_MUTEX_MOD_DISP_COLOR 7 > > @@ -75,6 +93,7 @@ > > > > #define OVL0_MOUT_EN_COLOR0 0x1 > > #define OD_MOUT_EN_RDMA0 0x1 > > +#define OD1_MOUT_EN_RDMA1 BIT(16) > > #define UFOE_MOUT_EN_DSI0 0x1 > > #define COLOR0_SEL_IN_OVL0 0x1 > > #define OVL1_MOUT_EN_COLOR1 0x1 > > @@ -109,12 +128,32 @@ static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = { > > [DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA, > > }; > > > > +static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = { > > + [DDP_COMPONENT_AAL0] = MT2712_MUTEX_MOD_DISP_AAL0, > > + [DDP_COMPONENT_AAL1] = MT2712_MUTEX_MOD2_DISP_AAL1, > > + [DDP_COMPONENT_COLOR0] = MT2712_MUTEX_MOD_DISP_COLOR0, > > + [DDP_COMPONENT_COLOR1] = MT2712_MUTEX_MOD_DISP_COLOR1, > > + [DDP_COMPONENT_OD0] = MT2712_MUTEX_MOD_DISP_OD0, > > + [DDP_COMPONENT_OD1] = MT2712_MUTEX_MOD2_DISP_OD1, > > + [DDP_COMPONENT_OVL0] = MT2712_MUTEX_MOD_DISP_OVL0, > > + [DDP_COMPONENT_OVL1] = MT2712_MUTEX_MOD_DISP_OVL1, > > + [DDP_COMPONENT_PWM0] = MT2712_MUTEX_MOD_DISP_PWM0, > > + [DDP_COMPONENT_PWM1] = MT2712_MUTEX_MOD_DISP_PWM1, > > + [DDP_COMPONENT_PWM2] = MT2712_MUTEX_MOD_DISP_PWM2, > > + [DDP_COMPONENT_RDMA0] = MT2712_MUTEX_MOD_DISP_RDMA0, > > + [DDP_COMPONENT_RDMA1] = MT2712_MUTEX_MOD_DISP_RDMA1, > > + [DDP_COMPONENT_RDMA2] = MT2712_MUTEX_MOD_DISP_RDMA2, > > + [DDP_COMPONENT_UFOE] = MT2712_MUTEX_MOD_DISP_UFOE, > > + [DDP_COMPONENT_WDMA0] = MT2712_MUTEX_MOD_DISP_WDMA0, > > + [DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1, > > +}; > > + > > static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = { > > - [DDP_COMPONENT_AAL] = MT8173_MUTEX_MOD_DISP_AAL, > > + [DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL, > > Move this to the patch 'add ddp component AAL1'. OK > > > [DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0, > > [DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1, > > [DDP_COMPONENT_GAMMA] = MT8173_MUTEX_MOD_DISP_GAMMA, > > - [DDP_COMPONENT_OD] = MT8173_MUTEX_MOD_DISP_OD, > > + [DDP_COMPONENT_OD0] = MT8173_MUTEX_MOD_DISP_OD, > > Move this to the patch 'add ddp component OD1'. OK > > > [DDP_COMPONENT_OVL0] = MT8173_MUTEX_MOD_DISP_OVL0, > > [DDP_COMPONENT_OVL1] = MT8173_MUTEX_MOD_DISP_OVL1, > > [DDP_COMPONENT_PWM0] = MT8173_MUTEX_MOD_DISP_PWM0, > > @@ -139,7 +178,7 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur, > > } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { > > *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; > > value = OVL_MOUT_EN_RDMA; > > - } else if (cur == DDP_COMPONENT_OD && next == DDP_COMPONENT_RDMA0) { > > + } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { > > Move this to the patch 'add ddp component OD1'. OK > > > *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > > value = OD_MOUT_EN_RDMA0; > > } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { > > @@ -429,6 +468,7 @@ static int mtk_ddp_remove(struct platform_device *pdev) > > > > static const struct of_device_id ddp_driver_dt_match[] = { > > { .compatible = "mediatek,mt2701-disp-mutex", .data = mt2701_mutex_mod}, > > + { .compatible = "mediatek,mt2712-disp-mutex", .data = mt2712_mutex_mod}, > > { .compatible = "mediatek,mt8173-disp-mutex", .data = mt8173_mutex_mod}, > > {}, > > }; > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > index 4672317e3ad1..86e8c9e5df41 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > @@ -218,7 +218,8 @@ struct mtk_ddp_comp_match { > > }; > > > > static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { > > - [DDP_COMPONENT_AAL] = { MTK_DISP_AAL, 0, &ddp_aal }, > > + [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal }, > > + [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal }, > > Move this to the patch 'add ddp component AAL1'. ok > > > [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL }, > > [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, NULL }, > > [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, NULL }, > > @@ -226,10 +227,13 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { > > [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, NULL }, > > [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, NULL }, > > [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma }, > > - [DDP_COMPONENT_OD] = { MTK_DISP_OD, 0, &ddp_od }, > > + [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od }, > > + [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od }, > > Move this to the patch 'add ddp component OD1' ok > > > [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, NULL }, > > [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, NULL }, > > [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, > > + [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, > > Move this to the patch 'add ddp component PWM1' ok, i would create the new patch for 'add ddp component PWM1' > > > + [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL }, > > Move this to the patch 'add ddp component PWM2' ok > > > [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, NULL }, > > [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, NULL }, > > [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, NULL }, > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > > index a2ca90fc403c..b32c4cc8d051 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > > @@ -146,11 +146,37 @@ static const enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = { > > DDP_COMPONENT_DPI0, > > }; > > > > +static const enum mtk_ddp_comp_id mt2712_mtk_ddp_main[] = { > > + DDP_COMPONENT_OVL0, > > + DDP_COMPONENT_COLOR0, > > + DDP_COMPONENT_AAL0, > > + DDP_COMPONENT_OD0, > > + DDP_COMPONENT_RDMA0, > > + DDP_COMPONENT_DPI0, > > + DDP_COMPONENT_PWM0, > > +}; > > + > > +static const enum mtk_ddp_comp_id mt2712_mtk_ddp_ext[] = { > > + DDP_COMPONENT_OVL1, > > + DDP_COMPONENT_COLOR1, > > + DDP_COMPONENT_AAL1, > > + DDP_COMPONENT_OD1, > > + DDP_COMPONENT_RDMA1, > > + DDP_COMPONENT_DPI1, > > + DDP_COMPONENT_PWM1, > > +}; > > + > > +static const enum mtk_ddp_comp_id mt2712_mtk_ddp_third[] = { > > + DDP_COMPONENT_RDMA2, > > + DDP_COMPONENT_DSI2, > > + DDP_COMPONENT_PWM2, > > +}; > > + > > static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = { > > DDP_COMPONENT_OVL0, > > DDP_COMPONENT_COLOR0, > > - DDP_COMPONENT_AAL, > > - DDP_COMPONENT_OD, > > + DDP_COMPONENT_AAL0, > > Move this to the patch 'add ddp component AAL1'. ok > > > + DDP_COMPONENT_OD0, > > Move this to the patch 'add ddp component OD1' ok > > > DDP_COMPONENT_RDMA0, > > DDP_COMPONENT_UFOE, > > DDP_COMPONENT_DSI0, > > @@ -173,6 +199,15 @@ static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { > > .shadow_register = true, > > }; > > > > +static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { > > + .main_path = mt2712_mtk_ddp_main, > > + .main_len = ARRAY_SIZE(mt2712_mtk_ddp_main), > > + .ext_path = mt2712_mtk_ddp_ext, > > + .ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext), > > + .third_path = mt2712_mtk_ddp_third, > > + .third_len = ARRAY_SIZE(mt2712_mtk_ddp_third), > > +}; > > + > > static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { > > .main_path = mt8173_mtk_ddp_main, > > .main_len = ARRAY_SIZE(mt8173_mtk_ddp_main), > > @@ -374,6 +409,7 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { > > { .compatible = "mediatek,mt8173-dsi", .data = (void *)MTK_DSI }, > > { .compatible = "mediatek,mt8173-dpi", .data = (void *)MTK_DPI }, > > { .compatible = "mediatek,mt2701-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, > > + { .compatible = "mediatek,mt2712-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, > > { .compatible = "mediatek,mt8173-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, > > { .compatible = "mediatek,mt2701-disp-pwm", .data = (void *)MTK_DISP_BLS }, > > { .compatible = "mediatek,mt8173-disp-pwm", .data = (void *)MTK_DISP_PWM }, > > @@ -552,6 +588,8 @@ static SIMPLE_DEV_PM_OPS(mtk_drm_pm_ops, mtk_drm_sys_suspend, > > static const struct of_device_id mtk_drm_of_ids[] = { > > { .compatible = "mediatek,mt2701-mmsys", > > .data = &mt2701_mmsys_driver_data}, > > + { .compatible = "mediatek,mt2712-mmsys", > > + .data = &mt2712_mmsys_driver_data}, > > { .compatible = "mediatek,mt8173-mmsys", > > .data = &mt8173_mmsys_driver_data}, > > { } > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h > > index c3378c452c0a..e821342bc2d3 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h > > @@ -17,8 +17,8 @@ > > #include <linux/io.h> > > #include "mtk_drm_ddp_comp.h" > > > > -#define MAX_CRTC 2 > > -#define MAX_CONNECTOR 2 > > +#define MAX_CRTC 3 > > +#define MAX_CONNECTOR 3 > > > > struct device; > > struct device_node; > > @@ -33,6 +33,9 @@ struct mtk_mmsys_driver_data { > > unsigned int main_len; > > const enum mtk_ddp_comp_id *ext_path; > > unsigned int ext_len; > > + enum mtk_ddp_comp_id *third_path; > > + unsigned int third_len; > > + > > Move this to the patch 'add third ddp path'. ok > > > bool shadow_register; > > }; > > > > Regards, > CK > > ^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [PATCH v3 7/8] drm/mediatek: Add support for mediatek SOC MT2712 @ 2018-05-25 9:33 ` Stu Hsieh 0 siblings, 0 replies; 66+ messages in thread From: Stu Hsieh @ 2018-05-25 9:33 UTC (permalink / raw) To: CK Hu Cc: Mark Rutland, devicetree, srv_heupstream, David Airlie, linux-kernel, dri-devel, Rob Herring, linux-mediatek, Matthias Brugger, linux-arm-kernel Hi, CK: On Fri, 2018-05-25 at 12:51 +0800, CK Hu wrote: > Hi, Stu: > > I've some inline comment. > > On Fri, 2018-05-25 at 10:34 +0800, stu.hsieh@mediatek.com wrote: > > From: Stu Hsieh <stu.hsieh@mediatek.com> > > > > This patch add support for the Mediatek MT2712 DISP subsystem. > > There are two OVL engine and three disp output in MT2712. > > > > Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> > > --- > > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 46 +++++++++++++++++++++++++++-- > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 8 +++-- > > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 42 ++++++++++++++++++++++++-- > > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 7 +++-- > > 4 files changed, 94 insertions(+), 9 deletions(-) > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > index 0f568dd853d8..676726249ae0 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > @@ -61,6 +61,24 @@ > > #define MT8173_MUTEX_MOD_DISP_PWM1 24 > > #define MT8173_MUTEX_MOD_DISP_OD 25 > > > > +#define MT2712_MUTEX_MOD_DISP_OVL0 11 > > +#define MT2712_MUTEX_MOD_DISP_OVL1 12 > > +#define MT2712_MUTEX_MOD_DISP_RDMA0 13 > > +#define MT2712_MUTEX_MOD_DISP_RDMA1 14 > > +#define MT2712_MUTEX_MOD_DISP_RDMA2 15 > > +#define MT2712_MUTEX_MOD_DISP_WDMA0 16 > > +#define MT2712_MUTEX_MOD_DISP_WDMA1 17 > > +#define MT2712_MUTEX_MOD_DISP_COLOR0 18 > > +#define MT2712_MUTEX_MOD_DISP_COLOR1 19 > > +#define MT2712_MUTEX_MOD_DISP_AAL0 20 > > +#define MT2712_MUTEX_MOD_DISP_UFOE 22 > > +#define MT2712_MUTEX_MOD_DISP_PWM0 23 > > +#define MT2712_MUTEX_MOD_DISP_PWM1 24 > > +#define MT2712_MUTEX_MOD_DISP_PWM2 10 > > +#define MT2712_MUTEX_MOD_DISP_OD0 25 > > +#define MT2712_MUTEX_MOD2_DISP_AAL1 33 > > +#define MT2712_MUTEX_MOD2_DISP_OD1 34 > > I would like this to be in the order by index. OK > > > + > > #define MT2701_MUTEX_MOD_DISP_OVL 3 > > #define MT2701_MUTEX_MOD_DISP_WDMA 6 > > #define MT2701_MUTEX_MOD_DISP_COLOR 7 > > @@ -75,6 +93,7 @@ > > > > #define OVL0_MOUT_EN_COLOR0 0x1 > > #define OD_MOUT_EN_RDMA0 0x1 > > +#define OD1_MOUT_EN_RDMA1 BIT(16) > > #define UFOE_MOUT_EN_DSI0 0x1 > > #define COLOR0_SEL_IN_OVL0 0x1 > > #define OVL1_MOUT_EN_COLOR1 0x1 > > @@ -109,12 +128,32 @@ static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = { > > [DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA, > > }; > > > > +static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = { > > + [DDP_COMPONENT_AAL0] = MT2712_MUTEX_MOD_DISP_AAL0, > > + [DDP_COMPONENT_AAL1] = MT2712_MUTEX_MOD2_DISP_AAL1, > > + [DDP_COMPONENT_COLOR0] = MT2712_MUTEX_MOD_DISP_COLOR0, > > + [DDP_COMPONENT_COLOR1] = MT2712_MUTEX_MOD_DISP_COLOR1, > > + [DDP_COMPONENT_OD0] = MT2712_MUTEX_MOD_DISP_OD0, > > + [DDP_COMPONENT_OD1] = MT2712_MUTEX_MOD2_DISP_OD1, > > + [DDP_COMPONENT_OVL0] = MT2712_MUTEX_MOD_DISP_OVL0, > > + [DDP_COMPONENT_OVL1] = MT2712_MUTEX_MOD_DISP_OVL1, > > + [DDP_COMPONENT_PWM0] = MT2712_MUTEX_MOD_DISP_PWM0, > > + [DDP_COMPONENT_PWM1] = MT2712_MUTEX_MOD_DISP_PWM1, > > + [DDP_COMPONENT_PWM2] = MT2712_MUTEX_MOD_DISP_PWM2, > > + [DDP_COMPONENT_RDMA0] = MT2712_MUTEX_MOD_DISP_RDMA0, > > + [DDP_COMPONENT_RDMA1] = MT2712_MUTEX_MOD_DISP_RDMA1, > > + [DDP_COMPONENT_RDMA2] = MT2712_MUTEX_MOD_DISP_RDMA2, > > + [DDP_COMPONENT_UFOE] = MT2712_MUTEX_MOD_DISP_UFOE, > > + [DDP_COMPONENT_WDMA0] = MT2712_MUTEX_MOD_DISP_WDMA0, > > + [DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1, > > +}; > > + > > static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = { > > - [DDP_COMPONENT_AAL] = MT8173_MUTEX_MOD_DISP_AAL, > > + [DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL, > > Move this to the patch 'add ddp component AAL1'. OK > > > [DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0, > > [DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1, > > [DDP_COMPONENT_GAMMA] = MT8173_MUTEX_MOD_DISP_GAMMA, > > - [DDP_COMPONENT_OD] = MT8173_MUTEX_MOD_DISP_OD, > > + [DDP_COMPONENT_OD0] = MT8173_MUTEX_MOD_DISP_OD, > > Move this to the patch 'add ddp component OD1'. OK > > > [DDP_COMPONENT_OVL0] = MT8173_MUTEX_MOD_DISP_OVL0, > > [DDP_COMPONENT_OVL1] = MT8173_MUTEX_MOD_DISP_OVL1, > > [DDP_COMPONENT_PWM0] = MT8173_MUTEX_MOD_DISP_PWM0, > > @@ -139,7 +178,7 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur, > > } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { > > *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; > > value = OVL_MOUT_EN_RDMA; > > - } else if (cur == DDP_COMPONENT_OD && next == DDP_COMPONENT_RDMA0) { > > + } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { > > Move this to the patch 'add ddp component OD1'. OK > > > *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > > value = OD_MOUT_EN_RDMA0; > > } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { > > @@ -429,6 +468,7 @@ static int mtk_ddp_remove(struct platform_device *pdev) > > > > static const struct of_device_id ddp_driver_dt_match[] = { > > { .compatible = "mediatek,mt2701-disp-mutex", .data = mt2701_mutex_mod}, > > + { .compatible = "mediatek,mt2712-disp-mutex", .data = mt2712_mutex_mod}, > > { .compatible = "mediatek,mt8173-disp-mutex", .data = mt8173_mutex_mod}, > > {}, > > }; > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > index 4672317e3ad1..86e8c9e5df41 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > @@ -218,7 +218,8 @@ struct mtk_ddp_comp_match { > > }; > > > > static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { > > - [DDP_COMPONENT_AAL] = { MTK_DISP_AAL, 0, &ddp_aal }, > > + [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal }, > > + [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal }, > > Move this to the patch 'add ddp component AAL1'. ok > > > [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL }, > > [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, NULL }, > > [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, NULL }, > > @@ -226,10 +227,13 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { > > [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, NULL }, > > [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, NULL }, > > [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma }, > > - [DDP_COMPONENT_OD] = { MTK_DISP_OD, 0, &ddp_od }, > > + [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od }, > > + [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od }, > > Move this to the patch 'add ddp component OD1' ok > > > [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, NULL }, > > [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, NULL }, > > [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, > > + [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, > > Move this to the patch 'add ddp component PWM1' ok, i would create the new patch for 'add ddp component PWM1' > > > + [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL }, > > Move this to the patch 'add ddp component PWM2' ok > > > [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, NULL }, > > [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, NULL }, > > [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, NULL }, > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > > index a2ca90fc403c..b32c4cc8d051 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > > @@ -146,11 +146,37 @@ static const enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = { > > DDP_COMPONENT_DPI0, > > }; > > > > +static const enum mtk_ddp_comp_id mt2712_mtk_ddp_main[] = { > > + DDP_COMPONENT_OVL0, > > + DDP_COMPONENT_COLOR0, > > + DDP_COMPONENT_AAL0, > > + DDP_COMPONENT_OD0, > > + DDP_COMPONENT_RDMA0, > > + DDP_COMPONENT_DPI0, > > + DDP_COMPONENT_PWM0, > > +}; > > + > > +static const enum mtk_ddp_comp_id mt2712_mtk_ddp_ext[] = { > > + DDP_COMPONENT_OVL1, > > + DDP_COMPONENT_COLOR1, > > + DDP_COMPONENT_AAL1, > > + DDP_COMPONENT_OD1, > > + DDP_COMPONENT_RDMA1, > > + DDP_COMPONENT_DPI1, > > + DDP_COMPONENT_PWM1, > > +}; > > + > > +static const enum mtk_ddp_comp_id mt2712_mtk_ddp_third[] = { > > + DDP_COMPONENT_RDMA2, > > + DDP_COMPONENT_DSI2, > > + DDP_COMPONENT_PWM2, > > +}; > > + > > static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = { > > DDP_COMPONENT_OVL0, > > DDP_COMPONENT_COLOR0, > > - DDP_COMPONENT_AAL, > > - DDP_COMPONENT_OD, > > + DDP_COMPONENT_AAL0, > > Move this to the patch 'add ddp component AAL1'. ok > > > + DDP_COMPONENT_OD0, > > Move this to the patch 'add ddp component OD1' ok > > > DDP_COMPONENT_RDMA0, > > DDP_COMPONENT_UFOE, > > DDP_COMPONENT_DSI0, > > @@ -173,6 +199,15 @@ static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { > > .shadow_register = true, > > }; > > > > +static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { > > + .main_path = mt2712_mtk_ddp_main, > > + .main_len = ARRAY_SIZE(mt2712_mtk_ddp_main), > > + .ext_path = mt2712_mtk_ddp_ext, > > + .ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext), > > + .third_path = mt2712_mtk_ddp_third, > > + .third_len = ARRAY_SIZE(mt2712_mtk_ddp_third), > > +}; > > + > > static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { > > .main_path = mt8173_mtk_ddp_main, > > .main_len = ARRAY_SIZE(mt8173_mtk_ddp_main), > > @@ -374,6 +409,7 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { > > { .compatible = "mediatek,mt8173-dsi", .data = (void *)MTK_DSI }, > > { .compatible = "mediatek,mt8173-dpi", .data = (void *)MTK_DPI }, > > { .compatible = "mediatek,mt2701-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, > > + { .compatible = "mediatek,mt2712-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, > > { .compatible = "mediatek,mt8173-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, > > { .compatible = "mediatek,mt2701-disp-pwm", .data = (void *)MTK_DISP_BLS }, > > { .compatible = "mediatek,mt8173-disp-pwm", .data = (void *)MTK_DISP_PWM }, > > @@ -552,6 +588,8 @@ static SIMPLE_DEV_PM_OPS(mtk_drm_pm_ops, mtk_drm_sys_suspend, > > static const struct of_device_id mtk_drm_of_ids[] = { > > { .compatible = "mediatek,mt2701-mmsys", > > .data = &mt2701_mmsys_driver_data}, > > + { .compatible = "mediatek,mt2712-mmsys", > > + .data = &mt2712_mmsys_driver_data}, > > { .compatible = "mediatek,mt8173-mmsys", > > .data = &mt8173_mmsys_driver_data}, > > { } > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h > > index c3378c452c0a..e821342bc2d3 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h > > @@ -17,8 +17,8 @@ > > #include <linux/io.h> > > #include "mtk_drm_ddp_comp.h" > > > > -#define MAX_CRTC 2 > > -#define MAX_CONNECTOR 2 > > +#define MAX_CRTC 3 > > +#define MAX_CONNECTOR 3 > > > > struct device; > > struct device_node; > > @@ -33,6 +33,9 @@ struct mtk_mmsys_driver_data { > > unsigned int main_len; > > const enum mtk_ddp_comp_id *ext_path; > > unsigned int ext_len; > > + enum mtk_ddp_comp_id *third_path; > > + unsigned int third_len; > > + > > Move this to the patch 'add third ddp path'. ok > > > bool shadow_register; > > }; > > > > Regards, > CK > > _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [PATCH v3 7/8] drm/mediatek: Add support for mediatek SOC MT2712 2018-05-25 2:34 ` stu.hsieh (?) @ 2018-05-25 16:12 ` kbuild test robot -1 siblings, 0 replies; 66+ messages in thread From: kbuild test robot @ 2018-05-25 16:12 UTC (permalink / raw) To: stu.hsieh Cc: kbuild-all, CK Hu, Philipp Zabel, Mark Rutland, devicetree, srv_heupstream, David Airlie, linux-kernel, dri-devel, Rob Herring, linux-mediatek, Stu Hsieh, Matthias Brugger, linux-arm-kernel [-- Attachment #1: Type: text/plain, Size: 3579 bytes --] Hi Stu, Thank you for the patch! Yet something to improve: [auto build test ERROR on drm/drm-next] [also build test ERROR on v4.17-rc6 next-20180517] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/stu-hsieh-mediatek-com/Add-support-for-mediatek-SOC-MT2712/20180525-211114 base: git://people.freedesktop.org/~airlied/linux.git drm-next config: arm-allmodconfig (attached as .config) compiler: arm-linux-gnueabi-gcc (Debian 7.2.0-11) 7.2.0 reproduce: wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # save the attached .config to linux build tree make.cross ARCH=arm All error/warnings (new ones prefixed by >>): >> drivers/gpu//drm/mediatek/mtk_drm_drv.c:165:2: error: 'DDP_COMPONENT_DPI1' undeclared here (not in a function); did you mean 'DDP_COMPONENT_DSI1'? DDP_COMPONENT_DPI1, ^~~~~~~~~~~~~~~~~~ DDP_COMPONENT_DSI1 >> drivers/gpu//drm/mediatek/mtk_drm_drv.c:171:2: error: 'DDP_COMPONENT_DSI2' undeclared here (not in a function); did you mean 'DDP_COMPONENT_DSI1'? DDP_COMPONENT_DSI2, ^~~~~~~~~~~~~~~~~~ DDP_COMPONENT_DSI1 >> drivers/gpu//drm/mediatek/mtk_drm_drv.c:171:2: error: incompatible types when initializing type 'enum mtk_ddp_comp_id' using type 'const enum mtk_ddp_comp_id *' >> drivers/gpu//drm/mediatek/mtk_drm_drv.c:207:16: warning: initialization discards 'const' qualifier from pointer target type [-Wdiscarded-qualifiers] .third_path = mt2712_mtk_ddp_third, ^~~~~~~~~~~~~~~~~~~~ vim +165 drivers/gpu//drm/mediatek/mtk_drm_drv.c 158 159 static const enum mtk_ddp_comp_id mt2712_mtk_ddp_ext[] = { 160 DDP_COMPONENT_OVL1, 161 DDP_COMPONENT_COLOR1, 162 DDP_COMPONENT_AAL1, 163 DDP_COMPONENT_OD1, 164 DDP_COMPONENT_RDMA1, > 165 DDP_COMPONENT_DPI1, 166 DDP_COMPONENT_PWM1, 167 }; 168 169 static const enum mtk_ddp_comp_id mt2712_mtk_ddp_third[] = { 170 DDP_COMPONENT_RDMA2, > 171 DDP_COMPONENT_DSI2, 172 DDP_COMPONENT_PWM2, 173 }; 174 175 static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = { 176 DDP_COMPONENT_OVL0, 177 DDP_COMPONENT_COLOR0, 178 DDP_COMPONENT_AAL0, 179 DDP_COMPONENT_OD0, 180 DDP_COMPONENT_RDMA0, 181 DDP_COMPONENT_UFOE, 182 DDP_COMPONENT_DSI0, 183 DDP_COMPONENT_PWM0, 184 }; 185 186 static const enum mtk_ddp_comp_id mt8173_mtk_ddp_ext[] = { 187 DDP_COMPONENT_OVL1, 188 DDP_COMPONENT_COLOR1, 189 DDP_COMPONENT_GAMMA, 190 DDP_COMPONENT_RDMA1, 191 DDP_COMPONENT_DPI0, 192 }; 193 194 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { 195 .main_path = mt2701_mtk_ddp_main, 196 .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), 197 .ext_path = mt2701_mtk_ddp_ext, 198 .ext_len = ARRAY_SIZE(mt2701_mtk_ddp_ext), 199 .shadow_register = true, 200 }; 201 202 static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { 203 .main_path = mt2712_mtk_ddp_main, 204 .main_len = ARRAY_SIZE(mt2712_mtk_ddp_main), 205 .ext_path = mt2712_mtk_ddp_ext, 206 .ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext), > 207 .third_path = mt2712_mtk_ddp_third, 208 .third_len = ARRAY_SIZE(mt2712_mtk_ddp_third), 209 }; 210 --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation [-- Attachment #2: .config.gz --] [-- Type: application/gzip, Size: 65211 bytes --] ^ permalink raw reply [flat|nested] 66+ messages in thread
* [PATCH v3 7/8] drm/mediatek: Add support for mediatek SOC MT2712 @ 2018-05-25 16:12 ` kbuild test robot 0 siblings, 0 replies; 66+ messages in thread From: kbuild test robot @ 2018-05-25 16:12 UTC (permalink / raw) To: linux-arm-kernel Hi Stu, Thank you for the patch! Yet something to improve: [auto build test ERROR on drm/drm-next] [also build test ERROR on v4.17-rc6 next-20180517] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/stu-hsieh-mediatek-com/Add-support-for-mediatek-SOC-MT2712/20180525-211114 base: git://people.freedesktop.org/~airlied/linux.git drm-next config: arm-allmodconfig (attached as .config) compiler: arm-linux-gnueabi-gcc (Debian 7.2.0-11) 7.2.0 reproduce: wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # save the attached .config to linux build tree make.cross ARCH=arm All error/warnings (new ones prefixed by >>): >> drivers/gpu//drm/mediatek/mtk_drm_drv.c:165:2: error: 'DDP_COMPONENT_DPI1' undeclared here (not in a function); did you mean 'DDP_COMPONENT_DSI1'? DDP_COMPONENT_DPI1, ^~~~~~~~~~~~~~~~~~ DDP_COMPONENT_DSI1 >> drivers/gpu//drm/mediatek/mtk_drm_drv.c:171:2: error: 'DDP_COMPONENT_DSI2' undeclared here (not in a function); did you mean 'DDP_COMPONENT_DSI1'? DDP_COMPONENT_DSI2, ^~~~~~~~~~~~~~~~~~ DDP_COMPONENT_DSI1 >> drivers/gpu//drm/mediatek/mtk_drm_drv.c:171:2: error: incompatible types when initializing type 'enum mtk_ddp_comp_id' using type 'const enum mtk_ddp_comp_id *' >> drivers/gpu//drm/mediatek/mtk_drm_drv.c:207:16: warning: initialization discards 'const' qualifier from pointer target type [-Wdiscarded-qualifiers] .third_path = mt2712_mtk_ddp_third, ^~~~~~~~~~~~~~~~~~~~ vim +165 drivers/gpu//drm/mediatek/mtk_drm_drv.c 158 159 static const enum mtk_ddp_comp_id mt2712_mtk_ddp_ext[] = { 160 DDP_COMPONENT_OVL1, 161 DDP_COMPONENT_COLOR1, 162 DDP_COMPONENT_AAL1, 163 DDP_COMPONENT_OD1, 164 DDP_COMPONENT_RDMA1, > 165 DDP_COMPONENT_DPI1, 166 DDP_COMPONENT_PWM1, 167 }; 168 169 static const enum mtk_ddp_comp_id mt2712_mtk_ddp_third[] = { 170 DDP_COMPONENT_RDMA2, > 171 DDP_COMPONENT_DSI2, 172 DDP_COMPONENT_PWM2, 173 }; 174 175 static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = { 176 DDP_COMPONENT_OVL0, 177 DDP_COMPONENT_COLOR0, 178 DDP_COMPONENT_AAL0, 179 DDP_COMPONENT_OD0, 180 DDP_COMPONENT_RDMA0, 181 DDP_COMPONENT_UFOE, 182 DDP_COMPONENT_DSI0, 183 DDP_COMPONENT_PWM0, 184 }; 185 186 static const enum mtk_ddp_comp_id mt8173_mtk_ddp_ext[] = { 187 DDP_COMPONENT_OVL1, 188 DDP_COMPONENT_COLOR1, 189 DDP_COMPONENT_GAMMA, 190 DDP_COMPONENT_RDMA1, 191 DDP_COMPONENT_DPI0, 192 }; 193 194 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { 195 .main_path = mt2701_mtk_ddp_main, 196 .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), 197 .ext_path = mt2701_mtk_ddp_ext, 198 .ext_len = ARRAY_SIZE(mt2701_mtk_ddp_ext), 199 .shadow_register = true, 200 }; 201 202 static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { 203 .main_path = mt2712_mtk_ddp_main, 204 .main_len = ARRAY_SIZE(mt2712_mtk_ddp_main), 205 .ext_path = mt2712_mtk_ddp_ext, 206 .ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext), > 207 .third_path = mt2712_mtk_ddp_third, 208 .third_len = ARRAY_SIZE(mt2712_mtk_ddp_third), 209 }; 210 --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation -------------- next part -------------- A non-text attachment was scrubbed... Name: .config.gz Type: application/gzip Size: 65211 bytes Desc: not available URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20180526/893bcab4/attachment-0001.gz> ^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [PATCH v3 7/8] drm/mediatek: Add support for mediatek SOC MT2712 @ 2018-05-25 16:12 ` kbuild test robot 0 siblings, 0 replies; 66+ messages in thread From: kbuild test robot @ 2018-05-25 16:12 UTC (permalink / raw) Cc: kbuild-all, CK Hu, Philipp Zabel, Mark Rutland, devicetree, srv_heupstream, David Airlie, linux-kernel, dri-devel, Rob Herring, linux-mediatek, Stu Hsieh, Matthias Brugger, linux-arm-kernel [-- Attachment #1: Type: text/plain, Size: 3579 bytes --] Hi Stu, Thank you for the patch! Yet something to improve: [auto build test ERROR on drm/drm-next] [also build test ERROR on v4.17-rc6 next-20180517] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/stu-hsieh-mediatek-com/Add-support-for-mediatek-SOC-MT2712/20180525-211114 base: git://people.freedesktop.org/~airlied/linux.git drm-next config: arm-allmodconfig (attached as .config) compiler: arm-linux-gnueabi-gcc (Debian 7.2.0-11) 7.2.0 reproduce: wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # save the attached .config to linux build tree make.cross ARCH=arm All error/warnings (new ones prefixed by >>): >> drivers/gpu//drm/mediatek/mtk_drm_drv.c:165:2: error: 'DDP_COMPONENT_DPI1' undeclared here (not in a function); did you mean 'DDP_COMPONENT_DSI1'? DDP_COMPONENT_DPI1, ^~~~~~~~~~~~~~~~~~ DDP_COMPONENT_DSI1 >> drivers/gpu//drm/mediatek/mtk_drm_drv.c:171:2: error: 'DDP_COMPONENT_DSI2' undeclared here (not in a function); did you mean 'DDP_COMPONENT_DSI1'? DDP_COMPONENT_DSI2, ^~~~~~~~~~~~~~~~~~ DDP_COMPONENT_DSI1 >> drivers/gpu//drm/mediatek/mtk_drm_drv.c:171:2: error: incompatible types when initializing type 'enum mtk_ddp_comp_id' using type 'const enum mtk_ddp_comp_id *' >> drivers/gpu//drm/mediatek/mtk_drm_drv.c:207:16: warning: initialization discards 'const' qualifier from pointer target type [-Wdiscarded-qualifiers] .third_path = mt2712_mtk_ddp_third, ^~~~~~~~~~~~~~~~~~~~ vim +165 drivers/gpu//drm/mediatek/mtk_drm_drv.c 158 159 static const enum mtk_ddp_comp_id mt2712_mtk_ddp_ext[] = { 160 DDP_COMPONENT_OVL1, 161 DDP_COMPONENT_COLOR1, 162 DDP_COMPONENT_AAL1, 163 DDP_COMPONENT_OD1, 164 DDP_COMPONENT_RDMA1, > 165 DDP_COMPONENT_DPI1, 166 DDP_COMPONENT_PWM1, 167 }; 168 169 static const enum mtk_ddp_comp_id mt2712_mtk_ddp_third[] = { 170 DDP_COMPONENT_RDMA2, > 171 DDP_COMPONENT_DSI2, 172 DDP_COMPONENT_PWM2, 173 }; 174 175 static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = { 176 DDP_COMPONENT_OVL0, 177 DDP_COMPONENT_COLOR0, 178 DDP_COMPONENT_AAL0, 179 DDP_COMPONENT_OD0, 180 DDP_COMPONENT_RDMA0, 181 DDP_COMPONENT_UFOE, 182 DDP_COMPONENT_DSI0, 183 DDP_COMPONENT_PWM0, 184 }; 185 186 static const enum mtk_ddp_comp_id mt8173_mtk_ddp_ext[] = { 187 DDP_COMPONENT_OVL1, 188 DDP_COMPONENT_COLOR1, 189 DDP_COMPONENT_GAMMA, 190 DDP_COMPONENT_RDMA1, 191 DDP_COMPONENT_DPI0, 192 }; 193 194 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { 195 .main_path = mt2701_mtk_ddp_main, 196 .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), 197 .ext_path = mt2701_mtk_ddp_ext, 198 .ext_len = ARRAY_SIZE(mt2701_mtk_ddp_ext), 199 .shadow_register = true, 200 }; 201 202 static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { 203 .main_path = mt2712_mtk_ddp_main, 204 .main_len = ARRAY_SIZE(mt2712_mtk_ddp_main), 205 .ext_path = mt2712_mtk_ddp_ext, 206 .ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext), > 207 .third_path = mt2712_mtk_ddp_third, 208 .third_len = ARRAY_SIZE(mt2712_mtk_ddp_third), 209 }; 210 --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation [-- Attachment #2: .config.gz --] [-- Type: application/gzip, Size: 65211 bytes --] ^ permalink raw reply [flat|nested] 66+ messages in thread
* [PATCH v3 8/8] drm/mediatek: add third ddp path 2018-05-25 2:34 ` stu.hsieh (?) @ 2018-05-25 2:34 ` stu.hsieh -1 siblings, 0 replies; 66+ messages in thread From: stu.hsieh @ 2018-05-25 2:34 UTC (permalink / raw) To: CK Hu, Philipp Zabel Cc: David Airlie, Rob Herring, Mark Rutland, Matthias Brugger, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, srv_heupstream, Stu Hsieh From: Stu Hsieh <stu.hsieh@mediatek.com> This patch create third crtc by third ddp path Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> --- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index b32c4cc8d051..3a866e1d6af4 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -267,6 +267,11 @@ static int mtk_drm_kms_init(struct drm_device *drm) if (ret < 0) goto err_component_unbind; + ret = mtk_drm_crtc_create(drm, private->data->third_path, + private->data->third_len); + if (ret < 0) + goto err_component_unbind; + /* Use OVL device for all DMA memory allocations */ np = private->comp_node[private->data->main_path[0]] ?: private->comp_node[private->data->ext_path[0]]; -- 2.12.5 ^ permalink raw reply related [flat|nested] 66+ messages in thread
* [PATCH v3 8/8] drm/mediatek: add third ddp path @ 2018-05-25 2:34 ` stu.hsieh 0 siblings, 0 replies; 66+ messages in thread From: stu.hsieh at mediatek.com @ 2018-05-25 2:34 UTC (permalink / raw) To: linux-arm-kernel From: Stu Hsieh <stu.hsieh@mediatek.com> This patch create third crtc by third ddp path Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> --- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index b32c4cc8d051..3a866e1d6af4 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -267,6 +267,11 @@ static int mtk_drm_kms_init(struct drm_device *drm) if (ret < 0) goto err_component_unbind; + ret = mtk_drm_crtc_create(drm, private->data->third_path, + private->data->third_len); + if (ret < 0) + goto err_component_unbind; + /* Use OVL device for all DMA memory allocations */ np = private->comp_node[private->data->main_path[0]] ?: private->comp_node[private->data->ext_path[0]]; -- 2.12.5 ^ permalink raw reply related [flat|nested] 66+ messages in thread
* [PATCH v3 8/8] drm/mediatek: add third ddp path @ 2018-05-25 2:34 ` stu.hsieh 0 siblings, 0 replies; 66+ messages in thread From: stu.hsieh @ 2018-05-25 2:34 UTC (permalink / raw) To: CK Hu, Philipp Zabel Cc: Mark Rutland, devicetree, srv_heupstream, David Airlie, linux-kernel, dri-devel, Rob Herring, linux-mediatek, Stu Hsieh, Matthias Brugger, linux-arm-kernel From: Stu Hsieh <stu.hsieh@mediatek.com> This patch create third crtc by third ddp path Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> --- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index b32c4cc8d051..3a866e1d6af4 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -267,6 +267,11 @@ static int mtk_drm_kms_init(struct drm_device *drm) if (ret < 0) goto err_component_unbind; + ret = mtk_drm_crtc_create(drm, private->data->third_path, + private->data->third_len); + if (ret < 0) + goto err_component_unbind; + /* Use OVL device for all DMA memory allocations */ np = private->comp_node[private->data->main_path[0]] ?: private->comp_node[private->data->ext_path[0]]; -- 2.12.5 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 66+ messages in thread
* Re: [PATCH v3 8/8] drm/mediatek: add third ddp path 2018-05-25 2:34 ` stu.hsieh (?) @ 2018-05-25 5:00 ` CK Hu -1 siblings, 0 replies; 66+ messages in thread From: CK Hu @ 2018-05-25 5:00 UTC (permalink / raw) To: stu.hsieh Cc: Philipp Zabel, David Airlie, Rob Herring, Mark Rutland, Matthias Brugger, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, srv_heupstream Hi, Stu: On Fri, 2018-05-25 at 10:34 +0800, stu.hsieh@mediatek.com wrote: > From: Stu Hsieh <stu.hsieh@mediatek.com> > > This patch create third crtc by third ddp path > Apply this patch before the patch 'Add support for mediatek SOC MT2712' because this patch is necessary for mt2712. > Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > index b32c4cc8d051..3a866e1d6af4 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > @@ -267,6 +267,11 @@ static int mtk_drm_kms_init(struct drm_device *drm) > if (ret < 0) > goto err_component_unbind; > > + ret = mtk_drm_crtc_create(drm, private->data->third_path, > + private->data->third_len); I think you should prevent doing this for mt8173 and mt2701 because that two SoC has only two ddp path. Regards, CK > + if (ret < 0) > + goto err_component_unbind; > + > /* Use OVL device for all DMA memory allocations */ > np = private->comp_node[private->data->main_path[0]] ?: > private->comp_node[private->data->ext_path[0]]; ^ permalink raw reply [flat|nested] 66+ messages in thread
* [PATCH v3 8/8] drm/mediatek: add third ddp path @ 2018-05-25 5:00 ` CK Hu 0 siblings, 0 replies; 66+ messages in thread From: CK Hu @ 2018-05-25 5:00 UTC (permalink / raw) To: linux-arm-kernel Hi, Stu: On Fri, 2018-05-25 at 10:34 +0800, stu.hsieh at mediatek.com wrote: > From: Stu Hsieh <stu.hsieh@mediatek.com> > > This patch create third crtc by third ddp path > Apply this patch before the patch 'Add support for mediatek SOC MT2712' because this patch is necessary for mt2712. > Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > index b32c4cc8d051..3a866e1d6af4 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > @@ -267,6 +267,11 @@ static int mtk_drm_kms_init(struct drm_device *drm) > if (ret < 0) > goto err_component_unbind; > > + ret = mtk_drm_crtc_create(drm, private->data->third_path, > + private->data->third_len); I think you should prevent doing this for mt8173 and mt2701 because that two SoC has only two ddp path. Regards, CK > + if (ret < 0) > + goto err_component_unbind; > + > /* Use OVL device for all DMA memory allocations */ > np = private->comp_node[private->data->main_path[0]] ?: > private->comp_node[private->data->ext_path[0]]; ^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [PATCH v3 8/8] drm/mediatek: add third ddp path @ 2018-05-25 5:00 ` CK Hu 0 siblings, 0 replies; 66+ messages in thread From: CK Hu @ 2018-05-25 5:00 UTC (permalink / raw) To: stu.hsieh Cc: Philipp Zabel, David Airlie, Rob Herring, Mark Rutland, Matthias Brugger, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, srv_heupstream Hi, Stu: On Fri, 2018-05-25 at 10:34 +0800, stu.hsieh@mediatek.com wrote: > From: Stu Hsieh <stu.hsieh@mediatek.com> > > This patch create third crtc by third ddp path > Apply this patch before the patch 'Add support for mediatek SOC MT2712' because this patch is necessary for mt2712. > Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > index b32c4cc8d051..3a866e1d6af4 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > @@ -267,6 +267,11 @@ static int mtk_drm_kms_init(struct drm_device *drm) > if (ret < 0) > goto err_component_unbind; > > + ret = mtk_drm_crtc_create(drm, private->data->third_path, > + private->data->third_len); I think you should prevent doing this for mt8173 and mt2701 because that two SoC has only two ddp path. Regards, CK > + if (ret < 0) > + goto err_component_unbind; > + > /* Use OVL device for all DMA memory allocations */ > np = private->comp_node[private->data->main_path[0]] ?: > private->comp_node[private->data->ext_path[0]]; ^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [PATCH v3 8/8] drm/mediatek: add third ddp path 2018-05-25 5:00 ` CK Hu (?) @ 2018-05-28 2:26 ` Stu Hsieh -1 siblings, 0 replies; 66+ messages in thread From: Stu Hsieh @ 2018-05-28 2:26 UTC (permalink / raw) To: CK Hu Cc: Philipp Zabel, David Airlie, Rob Herring, Mark Rutland, Matthias Brugger, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, srv_heupstream Hi, CK: I've some idea as below. On Fri, 2018-05-25 at 13:00 +0800, CK Hu wrote: > Hi, Stu: > > On Fri, 2018-05-25 at 10:34 +0800, stu.hsieh@mediatek.com wrote: > > From: Stu Hsieh <stu.hsieh@mediatek.com> > > > > This patch create third crtc by third ddp path > > > > Apply this patch before the patch 'Add support for mediatek SOC MT2712' > because this patch is necessary for mt2712. > > > Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> > > --- > > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 5 +++++ > > 1 file changed, 5 insertions(+) > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > > index b32c4cc8d051..3a866e1d6af4 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > > @@ -267,6 +267,11 @@ static int mtk_drm_kms_init(struct drm_device *drm) > > if (ret < 0) > > goto err_component_unbind; > > > > + ret = mtk_drm_crtc_create(drm, private->data->third_path, > > + private->data->third_len); > > I think you should prevent doing this for mt8173 and mt2701 because that > two SoC has only two ddp path. Now, 8173 and 2701 have only two ddp path, there is a problem on run time. There are three crtc for drm resource, and there is nothing in third crtc. Because 8173 and 2701 have no third ddp, and the third ddp_len is zero. So, I want to add the condition like following in mtk_crtc_create() if (path_len == 0) return 0; Then, the valur ret is zero and it would not create the null third crtc. Regards, Stu > > Regards, > CK > > > + if (ret < 0) > > + goto err_component_unbind; > > + > > /* Use OVL device for all DMA memory allocations */ > > np = private->comp_node[private->data->main_path[0]] ?: > > private->comp_node[private->data->ext_path[0]]; > > ^ permalink raw reply [flat|nested] 66+ messages in thread
* [PATCH v3 8/8] drm/mediatek: add third ddp path @ 2018-05-28 2:26 ` Stu Hsieh 0 siblings, 0 replies; 66+ messages in thread From: Stu Hsieh @ 2018-05-28 2:26 UTC (permalink / raw) To: linux-arm-kernel Hi, CK: I've some idea as below. On Fri, 2018-05-25 at 13:00 +0800, CK Hu wrote: > Hi, Stu: > > On Fri, 2018-05-25 at 10:34 +0800, stu.hsieh at mediatek.com wrote: > > From: Stu Hsieh <stu.hsieh@mediatek.com> > > > > This patch create third crtc by third ddp path > > > > Apply this patch before the patch 'Add support for mediatek SOC MT2712' > because this patch is necessary for mt2712. > > > Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> > > --- > > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 5 +++++ > > 1 file changed, 5 insertions(+) > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > > index b32c4cc8d051..3a866e1d6af4 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > > @@ -267,6 +267,11 @@ static int mtk_drm_kms_init(struct drm_device *drm) > > if (ret < 0) > > goto err_component_unbind; > > > > + ret = mtk_drm_crtc_create(drm, private->data->third_path, > > + private->data->third_len); > > I think you should prevent doing this for mt8173 and mt2701 because that > two SoC has only two ddp path. Now, 8173 and 2701 have only two ddp path, there is a problem on run time. There are three crtc for drm resource, and there is nothing in third crtc. Because 8173 and 2701 have no third ddp, and the third ddp_len is zero. So, I want to add the condition like following in mtk_crtc_create() if (path_len == 0) return 0; Then, the valur ret is zero and it would not create the null third crtc. Regards, Stu > > Regards, > CK > > > + if (ret < 0) > > + goto err_component_unbind; > > + > > /* Use OVL device for all DMA memory allocations */ > > np = private->comp_node[private->data->main_path[0]] ?: > > private->comp_node[private->data->ext_path[0]]; > > ^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [PATCH v3 8/8] drm/mediatek: add third ddp path @ 2018-05-28 2:26 ` Stu Hsieh 0 siblings, 0 replies; 66+ messages in thread From: Stu Hsieh @ 2018-05-28 2:26 UTC (permalink / raw) To: CK Hu Cc: Mark Rutland, devicetree, srv_heupstream, David Airlie, linux-kernel, dri-devel, Rob Herring, linux-mediatek, Matthias Brugger, linux-arm-kernel Hi, CK: I've some idea as below. On Fri, 2018-05-25 at 13:00 +0800, CK Hu wrote: > Hi, Stu: > > On Fri, 2018-05-25 at 10:34 +0800, stu.hsieh@mediatek.com wrote: > > From: Stu Hsieh <stu.hsieh@mediatek.com> > > > > This patch create third crtc by third ddp path > > > > Apply this patch before the patch 'Add support for mediatek SOC MT2712' > because this patch is necessary for mt2712. > > > Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> > > --- > > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 5 +++++ > > 1 file changed, 5 insertions(+) > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > > index b32c4cc8d051..3a866e1d6af4 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > > @@ -267,6 +267,11 @@ static int mtk_drm_kms_init(struct drm_device *drm) > > if (ret < 0) > > goto err_component_unbind; > > > > + ret = mtk_drm_crtc_create(drm, private->data->third_path, > > + private->data->third_len); > > I think you should prevent doing this for mt8173 and mt2701 because that > two SoC has only two ddp path. Now, 8173 and 2701 have only two ddp path, there is a problem on run time. There are three crtc for drm resource, and there is nothing in third crtc. Because 8173 and 2701 have no third ddp, and the third ddp_len is zero. So, I want to add the condition like following in mtk_crtc_create() if (path_len == 0) return 0; Then, the valur ret is zero and it would not create the null third crtc. Regards, Stu > > Regards, > CK > > > + if (ret < 0) > > + goto err_component_unbind; > > + > > /* Use OVL device for all DMA memory allocations */ > > np = private->comp_node[private->data->main_path[0]] ?: > > private->comp_node[private->data->ext_path[0]]; > > _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [PATCH v3 8/8] drm/mediatek: add third ddp path 2018-05-28 2:26 ` Stu Hsieh (?) @ 2018-05-28 2:50 ` CK Hu -1 siblings, 0 replies; 66+ messages in thread From: CK Hu @ 2018-05-28 2:50 UTC (permalink / raw) To: Stu Hsieh Cc: Philipp Zabel, David Airlie, Rob Herring, Mark Rutland, Matthias Brugger, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, srv_heupstream Hi, Stu: On Mon, 2018-05-28 at 10:26 +0800, Stu Hsieh wrote: > Hi, CK: > I've some idea as below. > > On Fri, 2018-05-25 at 13:00 +0800, CK Hu wrote: > > Hi, Stu: > > > > On Fri, 2018-05-25 at 10:34 +0800, stu.hsieh@mediatek.com wrote: > > > From: Stu Hsieh <stu.hsieh@mediatek.com> > > > > > > This patch create third crtc by third ddp path > > > > > > > Apply this patch before the patch 'Add support for mediatek SOC MT2712' > > because this patch is necessary for mt2712. > > > > > Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> > > > --- > > > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 5 +++++ > > > 1 file changed, 5 insertions(+) > > > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > > > index b32c4cc8d051..3a866e1d6af4 100644 > > > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > > > @@ -267,6 +267,11 @@ static int mtk_drm_kms_init(struct drm_device *drm) > > > if (ret < 0) > > > goto err_component_unbind; > > > > > > + ret = mtk_drm_crtc_create(drm, private->data->third_path, > > > + private->data->third_len); > > > > I think you should prevent doing this for mt8173 and mt2701 because that > > two SoC has only two ddp path. > > Now, 8173 and 2701 have only two ddp path, there is a problem on run > time. > There are three crtc for drm resource, and there is nothing in third > crtc. > Because 8173 and 2701 have no third ddp, and the third ddp_len is zero. > So, I want to add the condition like following in mtk_crtc_create() > if (path_len == 0) > return 0; > > Then, the valur ret is zero and it would not create the null third crtc. This sounds good to me. Regards, CK > > > Regards, > Stu > > > > > Regards, > > CK > > > > > + if (ret < 0) > > > + goto err_component_unbind; > > > + > > > /* Use OVL device for all DMA memory allocations */ > > > np = private->comp_node[private->data->main_path[0]] ?: > > > private->comp_node[private->data->ext_path[0]]; > > > > > > ^ permalink raw reply [flat|nested] 66+ messages in thread
* [PATCH v3 8/8] drm/mediatek: add third ddp path @ 2018-05-28 2:50 ` CK Hu 0 siblings, 0 replies; 66+ messages in thread From: CK Hu @ 2018-05-28 2:50 UTC (permalink / raw) To: linux-arm-kernel Hi, Stu: On Mon, 2018-05-28 at 10:26 +0800, Stu Hsieh wrote: > Hi, CK: > I've some idea as below. > > On Fri, 2018-05-25 at 13:00 +0800, CK Hu wrote: > > Hi, Stu: > > > > On Fri, 2018-05-25 at 10:34 +0800, stu.hsieh at mediatek.com wrote: > > > From: Stu Hsieh <stu.hsieh@mediatek.com> > > > > > > This patch create third crtc by third ddp path > > > > > > > Apply this patch before the patch 'Add support for mediatek SOC MT2712' > > because this patch is necessary for mt2712. > > > > > Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> > > > --- > > > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 5 +++++ > > > 1 file changed, 5 insertions(+) > > > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > > > index b32c4cc8d051..3a866e1d6af4 100644 > > > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > > > @@ -267,6 +267,11 @@ static int mtk_drm_kms_init(struct drm_device *drm) > > > if (ret < 0) > > > goto err_component_unbind; > > > > > > + ret = mtk_drm_crtc_create(drm, private->data->third_path, > > > + private->data->third_len); > > > > I think you should prevent doing this for mt8173 and mt2701 because that > > two SoC has only two ddp path. > > Now, 8173 and 2701 have only two ddp path, there is a problem on run > time. > There are three crtc for drm resource, and there is nothing in third > crtc. > Because 8173 and 2701 have no third ddp, and the third ddp_len is zero. > So, I want to add the condition like following in mtk_crtc_create() > if (path_len == 0) > return 0; > > Then, the valur ret is zero and it would not create the null third crtc. This sounds good to me. Regards, CK > > > Regards, > Stu > > > > > Regards, > > CK > > > > > + if (ret < 0) > > > + goto err_component_unbind; > > > + > > > /* Use OVL device for all DMA memory allocations */ > > > np = private->comp_node[private->data->main_path[0]] ?: > > > private->comp_node[private->data->ext_path[0]]; > > > > > > ^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [PATCH v3 8/8] drm/mediatek: add third ddp path @ 2018-05-28 2:50 ` CK Hu 0 siblings, 0 replies; 66+ messages in thread From: CK Hu @ 2018-05-28 2:50 UTC (permalink / raw) To: Stu Hsieh Cc: Mark Rutland, devicetree, srv_heupstream, David Airlie, linux-kernel, dri-devel, Rob Herring, linux-mediatek, Matthias Brugger, linux-arm-kernel Hi, Stu: On Mon, 2018-05-28 at 10:26 +0800, Stu Hsieh wrote: > Hi, CK: > I've some idea as below. > > On Fri, 2018-05-25 at 13:00 +0800, CK Hu wrote: > > Hi, Stu: > > > > On Fri, 2018-05-25 at 10:34 +0800, stu.hsieh@mediatek.com wrote: > > > From: Stu Hsieh <stu.hsieh@mediatek.com> > > > > > > This patch create third crtc by third ddp path > > > > > > > Apply this patch before the patch 'Add support for mediatek SOC MT2712' > > because this patch is necessary for mt2712. > > > > > Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> > > > --- > > > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 5 +++++ > > > 1 file changed, 5 insertions(+) > > > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > > > index b32c4cc8d051..3a866e1d6af4 100644 > > > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > > > @@ -267,6 +267,11 @@ static int mtk_drm_kms_init(struct drm_device *drm) > > > if (ret < 0) > > > goto err_component_unbind; > > > > > > + ret = mtk_drm_crtc_create(drm, private->data->third_path, > > > + private->data->third_len); > > > > I think you should prevent doing this for mt8173 and mt2701 because that > > two SoC has only two ddp path. > > Now, 8173 and 2701 have only two ddp path, there is a problem on run > time. > There are three crtc for drm resource, and there is nothing in third > crtc. > Because 8173 and 2701 have no third ddp, and the third ddp_len is zero. > So, I want to add the condition like following in mtk_crtc_create() > if (path_len == 0) > return 0; > > Then, the valur ret is zero and it would not create the null third crtc. This sounds good to me. Regards, CK > > > Regards, > Stu > > > > > Regards, > > CK > > > > > + if (ret < 0) > > > + goto err_component_unbind; > > > + > > > /* Use OVL device for all DMA memory allocations */ > > > np = private->comp_node[private->data->main_path[0]] ?: > > > private->comp_node[private->data->ext_path[0]]; > > > > > > _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 66+ messages in thread
end of thread, other threads:[~2018-05-28 2:50 UTC | newest] Thread overview: 66+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2018-05-25 2:34 [PATCH v3 0/8] Add support for mediatek SOC MT2712 stu.hsieh 2018-05-25 2:34 ` stu.hsieh at mediatek.com 2018-05-25 2:34 ` stu.hsieh 2018-05-25 2:34 ` [PATCH v3 1/8] drm/mediatek: update dt-bindings for mt2712 stu.hsieh 2018-05-25 2:34 ` stu.hsieh at mediatek.com 2018-05-25 2:34 ` stu.hsieh 2018-05-25 3:18 ` CK Hu 2018-05-25 3:18 ` CK Hu 2018-05-25 3:18 ` CK Hu 2018-05-25 9:20 ` Stu Hsieh 2018-05-25 9:20 ` Stu Hsieh 2018-05-25 9:20 ` Stu Hsieh 2018-05-25 2:34 ` [PATCH v3 2/8] drm/mediatek: support maximum 64 mutex mod stu.hsieh 2018-05-25 2:34 ` stu.hsieh at mediatek.com 2018-05-25 2:34 ` stu.hsieh 2018-05-25 3:24 ` CK Hu 2018-05-25 3:24 ` CK Hu 2018-05-25 3:24 ` CK Hu 2018-05-25 2:34 ` [PATCH v3 3/8] drm/mediatek: add connection from OD1 to RDMA1 stu.hsieh 2018-05-25 2:34 ` stu.hsieh at mediatek.com 2018-05-25 2:34 ` stu.hsieh 2018-05-25 3:26 ` CK Hu 2018-05-25 3:26 ` CK Hu 2018-05-25 3:26 ` CK Hu 2018-05-25 9:36 ` Stu Hsieh 2018-05-25 9:36 ` Stu Hsieh 2018-05-25 9:36 ` Stu Hsieh 2018-05-25 2:34 ` [PATCH v3 4/8] drm/mediatek: add ddp component AAL1 stu.hsieh 2018-05-25 2:34 ` stu.hsieh at mediatek.com 2018-05-25 2:34 ` stu.hsieh 2018-05-25 4:23 ` CK Hu 2018-05-25 4:23 ` CK Hu 2018-05-25 4:23 ` CK Hu 2018-05-25 9:25 ` Stu Hsieh 2018-05-25 9:25 ` Stu Hsieh 2018-05-25 9:25 ` Stu Hsieh 2018-05-25 2:34 ` [PATCH v3 5/8] drm/mediatek: add ddp component OD1 stu.hsieh 2018-05-25 2:34 ` stu.hsieh at mediatek.com 2018-05-25 2:34 ` stu.hsieh 2018-05-25 2:34 ` [PATCH v3 6/8] drm/mediatek: add ddp component PWM2 stu.hsieh 2018-05-25 2:34 ` stu.hsieh at mediatek.com 2018-05-25 2:34 ` stu.hsieh 2018-05-25 2:34 ` [PATCH v3 7/8] drm/mediatek: Add support for mediatek SOC MT2712 stu.hsieh 2018-05-25 2:34 ` stu.hsieh at mediatek.com 2018-05-25 2:34 ` stu.hsieh 2018-05-25 4:51 ` CK Hu 2018-05-25 4:51 ` CK Hu 2018-05-25 4:51 ` CK Hu 2018-05-25 9:33 ` Stu Hsieh 2018-05-25 9:33 ` Stu Hsieh 2018-05-25 9:33 ` Stu Hsieh 2018-05-25 16:12 ` kbuild test robot 2018-05-25 16:12 ` kbuild test robot 2018-05-25 16:12 ` kbuild test robot 2018-05-25 2:34 ` [PATCH v3 8/8] drm/mediatek: add third ddp path stu.hsieh 2018-05-25 2:34 ` stu.hsieh at mediatek.com 2018-05-25 2:34 ` stu.hsieh 2018-05-25 5:00 ` CK Hu 2018-05-25 5:00 ` CK Hu 2018-05-25 5:00 ` CK Hu 2018-05-28 2:26 ` Stu Hsieh 2018-05-28 2:26 ` Stu Hsieh 2018-05-28 2:26 ` Stu Hsieh 2018-05-28 2:50 ` CK Hu 2018-05-28 2:50 ` CK Hu 2018-05-28 2:50 ` CK Hu
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