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From: Shashank Sharma <shashank.sharma@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [REBASE v9 3/8] drm/i915: Add CRTC output format YCBCR 4:4:4
Date: Wed, 30 May 2018 15:47:50 +0530	[thread overview]
Message-ID: <1527675475-18114-4-git-send-email-shashank.sharma@intel.com> (raw)
In-Reply-To: <1527675475-18114-1-git-send-email-shashank.sharma@intel.com>

This patch adds support for YCBCR 4:4:4 CRTC output format.
To do this, this patch extends the existing YCBCR 4:2:0
framework by:
- Adding new parameter in for YCBCR 4:4:4 enum crtc_iutput_format.
- Adding case for YCBCR 4:4:4 in while setting AVI infoframes.
- Adding necessary checks in modeset sequence.

V3: Added this patch in the series
V4: Added r-b from Maarten (for v3)
    Addressed review comment from Ville:
    Do not use (config->output_format > CRTC_OUTPUT_RGB)
V5: Rebase
V6: Rebase and small change, to accommodate changes in patch 2
V7: Fixed checkpatch alignment warnings
V8: Rebase

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
---
 drivers/gpu/drm/i915/intel_color.c   |  3 ++-
 drivers/gpu/drm/i915/intel_display.c | 13 +++++++++----
 drivers/gpu/drm/i915/intel_drv.h     |  1 +
 drivers/gpu/drm/i915/intel_hdmi.c    |  2 ++
 4 files changed, 14 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index bf9d8f6..5127da2 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -149,7 +149,8 @@ static void ilk_load_csc_matrix(struct drm_crtc_state *crtc_state)
 	if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
 		limited_color_range = intel_crtc_state->limited_color_range;
 
-	if (intel_crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
+	if (intel_crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
+	    intel_crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
 		ilk_load_ycbcr_conversion_matrix(intel_crtc);
 		return;
 	} else if (crtc_state->ctm) {
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 5fbd19c..8b5d184 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6552,8 +6552,9 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
 		return -EINVAL;
 	}
 
-	if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
-	    pipe_config->base.ctm) {
+	if ((pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
+	     pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) &&
+	     pipe_config->base.ctm) {
 		/*
 		 * There is only one pipe CSC unit per pipe, and we need that
 		 * for output conversion from RGB->YCBCR. So if CTM is already
@@ -7771,6 +7772,8 @@ static void intel_get_crtc_ycbcr_config(struct intel_crtc *crtc,
 					output = INTEL_OUTPUT_FORMAT_INVALID;
 				else
 					output = INTEL_OUTPUT_FORMAT_YCBCR420;
+			} else {
+				output = INTEL_OUTPUT_FORMAT_YCBCR444;
 			}
 		}
 	}
@@ -8413,11 +8416,13 @@ static void haswell_set_pipemisc(struct drm_crtc *crtc)
 		if (intel_crtc->config->dither)
 			val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
 
-		if (config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
+		if (config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
+		    config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
 			val |= PIPEMISC_OUTPUT_COLORSPACE_YUV;
+
+		if (config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 			val |= PIPEMISC_YUV420_ENABLE |
 			       PIPEMISC_YUV420_MODE_FULL_BLEND;
-		}
 
 		I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
 	}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 35c4dc9..7eb8604 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -713,6 +713,7 @@ enum intel_output_format {
 	INTEL_OUTPUT_FORMAT_INVALID,
 	INTEL_OUTPUT_FORMAT_RGB,
 	INTEL_OUTPUT_FORMAT_YCBCR420,
+	INTEL_OUTPUT_FORMAT_YCBCR444,
 };
 
 struct intel_crtc_state {
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 933f9a2..c741ef5 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -482,6 +482,8 @@ static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
 
 	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 		frame.avi.colorspace = HDMI_COLORSPACE_YUV420;
+	else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
+		frame.avi.colorspace = HDMI_COLORSPACE_YUV444;
 	else
 		frame.avi.colorspace = HDMI_COLORSPACE_RGB;
 
-- 
2.7.4

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  parent reply	other threads:[~2018-05-30 10:10 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-05-30 10:17 [REBASE v9 0/8] YCBCR 4:2:0/4:4:4 output support for LSPCON Shashank Sharma
2018-05-30 10:17 ` [REBASE v9 1/8] drm/i915: Introduce CRTC output format Shashank Sharma
2018-05-30 10:17 ` [REBASE v9 2/8] drm/i915: Add CRTC output format YCBCR 4:2:0 Shashank Sharma
2018-05-30 10:17 ` Shashank Sharma [this message]
2018-05-30 10:17 ` [REBASE v9 4/8] drm/i915: Check LSPCON vendor OUI Shashank Sharma
2018-05-30 10:17 ` [REBASE v9 5/8] drm/i915: Add AVI infoframe support for LSPCON Shashank Sharma
2018-05-30 10:17 ` [REBASE v9 6/8] drm/i915: Write AVI infoframes for MCA LSPCON Shashank Sharma
2018-06-05  9:30   ` [PATCH v9 5/8] drm/i915: Add AVI infoframe support for LSPCON Shashank Sharma
2018-06-05  9:32   ` [PATCH v9 6/8] drm/i915: Write AVI infoframes for MCA LSPCON Shashank Sharma
2018-05-30 10:17 ` [REBASE v9 7/8] drm/i915: Write AVI infoframes for Parade LSPCON Shashank Sharma
2018-05-30 10:17 ` [REBASE v9 8/8] drm/i915: Add YCBCR 4:2:0/4:4:4 support for LSPCON Shashank Sharma
2018-05-30 11:01 ` ✗ Fi.CI.CHECKPATCH: warning for YCBCR 4:2:0/4:4:4 output support for LSPCON (rev8) Patchwork
2018-05-30 11:22 ` ✗ Fi.CI.BAT: failure " Patchwork
2018-06-05 11:02 ` ✗ Fi.CI.CHECKPATCH: warning for YCBCR 4:2:0/4:4:4 output support for LSPCON (rev10) Patchwork
2018-06-05 11:18 ` ✗ Fi.CI.BAT: failure " Patchwork
2018-06-05 13:11 ` ✗ Fi.CI.IGT: " Patchwork

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