* [DPU PATCH v2] drm/msm: make pclk_rate u64 to avoid truncation
@ 2018-05-31 2:12 Abhinav Kumar
2018-06-01 19:37 ` Sean Paul
0 siblings, 1 reply; 2+ messages in thread
From: Abhinav Kumar @ 2018-05-31 2:12 UTC (permalink / raw)
To: dri-devel; +Cc: linux-arm-msm, Abhinav Kumar, hoegsberg, chandanu
Higher values of pclk can exceed 32 bits when multiplied
by a factor.
Make the pclk_rate u64 to accommodate higher pixel clock
rates.
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 13 +++++++++----
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
index b916f46..5a04f2d 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -668,7 +668,8 @@ static int dsi_calc_clk_rate(struct msm_dsi_host *msm_host)
const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
u8 lanes = msm_host->lanes;
u32 bpp = dsi_get_bpp(msm_host->format);
- u32 pclk_rate;
+ u64 pclk_rate;
+ u64 pclk_bpp;
if (!mode) {
pr_err("%s: mode not set\n", __func__);
@@ -676,14 +677,18 @@ static int dsi_calc_clk_rate(struct msm_dsi_host *msm_host)
}
pclk_rate = mode->clock * 1000;
+ pclk_bpp = pclk_rate * bpp;
+
if (lanes > 0) {
- msm_host->byte_clk_rate = (pclk_rate * bpp) / (8 * lanes);
+ do_div(pclk_bpp, (8 * lanes));
} else {
pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__);
- msm_host->byte_clk_rate = (pclk_rate * bpp) / 8;
+ do_div(pclk_bpp, 8);
}
- DBG("pclk=%d, bclk=%d", pclk_rate, msm_host->byte_clk_rate);
+ msm_host->byte_clk_rate = pclk_bpp;
+
+ DBG("pclk=%llu, bclk=%d", pclk_rate, msm_host->byte_clk_rate);
msm_host->esc_clk_rate = clk_get_rate(msm_host->esc_clk);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [DPU PATCH v2] drm/msm: make pclk_rate u64 to avoid truncation
2018-05-31 2:12 [DPU PATCH v2] drm/msm: make pclk_rate u64 to avoid truncation Abhinav Kumar
@ 2018-06-01 19:37 ` Sean Paul
0 siblings, 0 replies; 2+ messages in thread
From: Sean Paul @ 2018-06-01 19:37 UTC (permalink / raw)
To: Abhinav Kumar; +Cc: linux-arm-msm, dri-devel, hoegsberg, chandanu
On Wed, May 30, 2018 at 07:12:52PM -0700, Abhinav Kumar wrote:
> Higher values of pclk can exceed 32 bits when multiplied
> by a factor.
>
> Make the pclk_rate u64 to accommodate higher pixel clock
> rates.
>
> Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Can you please rebase this on "drm/msm/dsi: adjust dsi timing for dual dsi
mode"?
Sean
> ---
> drivers/gpu/drm/msm/dsi/dsi_host.c | 13 +++++++++----
> 1 file changed, 9 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
> index b916f46..5a04f2d 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
> @@ -668,7 +668,8 @@ static int dsi_calc_clk_rate(struct msm_dsi_host *msm_host)
> const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
> u8 lanes = msm_host->lanes;
> u32 bpp = dsi_get_bpp(msm_host->format);
> - u32 pclk_rate;
> + u64 pclk_rate;
> + u64 pclk_bpp;
>
> if (!mode) {
> pr_err("%s: mode not set\n", __func__);
> @@ -676,14 +677,18 @@ static int dsi_calc_clk_rate(struct msm_dsi_host *msm_host)
> }
>
> pclk_rate = mode->clock * 1000;
> + pclk_bpp = pclk_rate * bpp;
> +
> if (lanes > 0) {
> - msm_host->byte_clk_rate = (pclk_rate * bpp) / (8 * lanes);
> + do_div(pclk_bpp, (8 * lanes));
> } else {
> pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__);
> - msm_host->byte_clk_rate = (pclk_rate * bpp) / 8;
> + do_div(pclk_bpp, 8);
> }
>
> - DBG("pclk=%d, bclk=%d", pclk_rate, msm_host->byte_clk_rate);
> + msm_host->byte_clk_rate = pclk_bpp;
> +
> + DBG("pclk=%llu, bclk=%d", pclk_rate, msm_host->byte_clk_rate);
>
> msm_host->esc_clk_rate = clk_get_rate(msm_host->esc_clk);
>
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
--
Sean Paul, Software Engineer, Google / Chromium OS
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
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