[PATCH 1/7] drm/i915: Don't set cursor pipe select bits on g4x+

[PATCH 1/7] drm/i915: Don't set cursor pipe select bits on g4x+

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

G4x cursor control registers still allow us to write to the pipe select
bits even though cursors are supposed to be fixed to a specific pipe.
Bspec tells us that we should only ever write 0 to these bits. Let's
follow that recommendation. On ilk+ the bits become hardwired to 0.

Also looks like ICL repurposes these bits for some other use, so
we had better stop setting them to bogus values there.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index af659d25943b..cccc1126f1d5 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9532,7 +9532,8 @@ static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
 	if (HAS_DDI(dev_priv))
 		cntl |= CURSOR_PIPE_CSC_ENABLE;
 
-	cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
+	if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
+		cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
 
 	switch (plane_state->base.crtc_w) {
 	case 64:
-- 
2.13.6

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[PATCH 2/7] drm/i915: Set the primary plane pipe select bits on gen4

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

i965 and g4x still have the pipe select bits in the plane control
registers, they're just hardcoded to select a specific pipe. However
plane C on i965 can still move between the pipes, thus we should
program the pipe select bits on i965 if we want to expose plane C
some day.

Since there is no harm in programming the bits on any plane on
i965/g4x let's just always set them. This will also make our
pre-computed register value match what the hardware register
would read, should we want to cross check the two.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index cccc1126f1d5..6ffc1d088d7a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3163,7 +3163,7 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
 	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 		dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
 
-	if (INTEL_GEN(dev_priv) < 4)
+	if (INTEL_GEN(dev_priv) < 5)
 		dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
 
 	switch (fb->format->format) {
-- 
2.13.6

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[PATCH 3/7] drm/i915: Have plane->get_hw_state() return the current pipe

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Like we do for encoder let's make the plane->get_hw_state() return
the pipe to which the plane is currently attached. We don't currently
allow planes to move between the pipes, but perhaps one day we will.

In either case this makes the code more uniform and perhaps makes
intel_plane_mapping_ok() slightly more clear.

Note that for i965 and g4x planes A and B still have pipe select bits
but they're hardwired to pipe A and B respectively. This means we can
safely interpret those bits just like on gen2/3. This allows the
same readout code work for plane C (which can still be assigned
to eiter pipe on i965) should we ever expose it.

g4x no longer allows moving the cursor planes between the pipes,
but the pipe select bits can still be set in the register. Thus
we have to ignore those bits. OTOH i965 still allows the cursors
to move between pipes thus we have to trust the bits there.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |  2 +
 drivers/gpu/drm/i915/intel_display.c | 71 ++++++++++++++++++++++++++----------
 drivers/gpu/drm/i915/intel_drv.h     |  4 +-
 drivers/gpu/drm/i915/intel_sprite.c  | 40 ++++++++++++--------
 4 files changed, 79 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 64933fd74cb6..ebb41f279134 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5908,6 +5908,8 @@ enum {
 #define   CURSOR_MODE_128_ARGB_AX ((1 << 5) | CURSOR_MODE_128_32B_AX)
 #define   CURSOR_MODE_256_ARGB_AX ((1 << 5) | CURSOR_MODE_256_32B_AX)
 #define   CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
+#define   MCURSOR_PIPE_SELECT_MASK	(0x3 << 28)
+#define   MCURSOR_PIPE_SELECT_SHIFT	28
 #define   MCURSOR_PIPE_SELECT(pipe)	((pipe) << 28)
 #define   MCURSOR_GAMMA_ENABLE  (1 << 26)
 #define   CURSOR_ROTATE_180	(1<<15)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 6ffc1d088d7a..feae6bd51a44 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1224,7 +1224,10 @@ void assert_pipe(struct drm_i915_private *dev_priv,
 
 static void assert_plane(struct intel_plane *plane, bool state)
 {
-	bool cur_state = plane->get_hw_state(plane);
+	enum pipe pipe;
+	bool cur_state;
+
+	cur_state = plane->get_hw_state(plane, &pipe);
 
 	I915_STATE_WARN(cur_state != state,
 			"%s assertion failure (expected %s, current %s)\n",
@@ -3326,24 +3329,33 @@ static void i9xx_disable_plane(struct intel_plane *plane,
 	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 }
 
-static bool i9xx_plane_get_hw_state(struct intel_plane *plane)
+static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
+				    enum pipe *pipe)
 {
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 	enum intel_display_power_domain power_domain;
 	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
-	enum pipe pipe = plane->pipe;
 	bool ret;
+	u32 val;
 
 	/*
 	 * Not 100% correct for planes that can move between pipes,
 	 * but that's only the case for gen2-4 which don't have any
 	 * display power wells.
 	 */
-	power_domain = POWER_DOMAIN_PIPE(pipe);
+	power_domain = POWER_DOMAIN_PIPE(plane->pipe);
 	if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
 		return false;
 
-	ret = I915_READ(DSPCNTR(i9xx_plane)) & DISPLAY_PLANE_ENABLE;
+	val = I915_READ(DSPCNTR(i9xx_plane));
+
+	ret = val & DISPLAY_PLANE_ENABLE;
+
+	if (INTEL_GEN(dev_priv) >= 5)
+		*pipe = plane->pipe;
+	else
+		*pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
+			DISPPLANE_SEL_PIPE_SHIFT;
 
 	intel_display_power_put(dev_priv, power_domain);
 
@@ -7482,16 +7494,18 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct intel_plane *plane = to_intel_plane(crtc->base.primary);
 	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
-	enum pipe pipe = crtc->pipe;
+	enum pipe pipe;
 	u32 val, base, offset;
 	int fourcc, pixel_format;
 	unsigned int aligned_height;
 	struct drm_framebuffer *fb;
 	struct intel_framebuffer *intel_fb;
 
-	if (!plane->get_hw_state(plane))
+	if (!plane->get_hw_state(plane, &pipe))
 		return;
 
+	WARN_ON(pipe != crtc->pipe);
+
 	intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
 	if (!intel_fb) {
 		DRM_DEBUG_KMS("failed to alloc fb\n");
@@ -8512,16 +8526,18 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct intel_plane *plane = to_intel_plane(crtc->base.primary);
 	enum plane_id plane_id = plane->id;
-	enum pipe pipe = crtc->pipe;
+	enum pipe pipe;
 	u32 val, base, offset, stride_mult, tiling, alpha;
 	int fourcc, pixel_format;
 	unsigned int aligned_height;
 	struct drm_framebuffer *fb;
 	struct intel_framebuffer *intel_fb;
 
-	if (!plane->get_hw_state(plane))
+	if (!plane->get_hw_state(plane, &pipe))
 		return;
 
+	WARN_ON(pipe != crtc->pipe);
+
 	intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
 	if (!intel_fb) {
 		DRM_DEBUG_KMS("failed to alloc fb\n");
@@ -9502,7 +9518,8 @@ static void i845_disable_cursor(struct intel_plane *plane,
 	i845_update_cursor(plane, NULL, NULL);
 }
 
-static bool i845_cursor_get_hw_state(struct intel_plane *plane)
+static bool i845_cursor_get_hw_state(struct intel_plane *plane,
+				     enum pipe *pipe)
 {
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 	enum intel_display_power_domain power_domain;
@@ -9514,6 +9531,8 @@ static bool i845_cursor_get_hw_state(struct intel_plane *plane)
 
 	ret = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
 
+	*pipe = PIPE_A;
+
 	intel_display_power_put(dev_priv, power_domain);
 
 	return ret;
@@ -9713,23 +9732,32 @@ static void i9xx_disable_cursor(struct intel_plane *plane,
 	i9xx_update_cursor(plane, NULL, NULL);
 }
 
-static bool i9xx_cursor_get_hw_state(struct intel_plane *plane)
+static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
+				     enum pipe *pipe)
 {
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 	enum intel_display_power_domain power_domain;
-	enum pipe pipe = plane->pipe;
 	bool ret;
+	u32 val;
 
 	/*
 	 * Not 100% correct for planes that can move between pipes,
 	 * but that's only the case for gen2-3 which don't have any
 	 * display power wells.
 	 */
-	power_domain = POWER_DOMAIN_PIPE(pipe);
+	power_domain = POWER_DOMAIN_PIPE(plane->pipe);
 	if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
 		return false;
 
-	ret = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
+	val = I915_READ(CURCNTR(plane->pipe));
+
+	ret = val & CURSOR_MODE;
+
+	if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
+		*pipe = plane->pipe;
+	else
+		*pipe = (val & MCURSOR_PIPE_SELECT_MASK) >>
+			MCURSOR_PIPE_SELECT_SHIFT;
 
 	intel_display_power_put(dev_priv, power_domain);
 
@@ -14755,12 +14783,12 @@ void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
 static bool intel_plane_mapping_ok(struct intel_crtc *crtc,
 				   struct intel_plane *plane)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
-	u32 val = I915_READ(DSPCNTR(i9xx_plane));
+	enum pipe pipe;
 
-	return (val & DISPLAY_PLANE_ENABLE) == 0 ||
-		(val & DISPPLANE_SEL_PIPE_MASK) == DISPPLANE_SEL_PIPE(crtc->pipe);
+	if (!plane->get_hw_state(plane, &pipe))
+		return true;
+
+	return pipe == crtc->pipe;
 }
 
 static void
@@ -14959,7 +14987,10 @@ static void readout_plane_state(struct intel_crtc *crtc)
 	for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
 		struct intel_plane_state *plane_state =
 			to_intel_plane_state(plane->base.state);
-		bool visible = plane->get_hw_state(plane);
+		enum pipe pipe;
+		bool visible;
+
+		visible = plane->get_hw_state(plane, &pipe);
 
 		intel_set_plane_visible(crtc_state, plane_state, visible);
 	}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 8335d27f4156..d80eae7a69ba 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -946,7 +946,7 @@ struct intel_plane {
 			     const struct intel_plane_state *plane_state);
 	void (*disable_plane)(struct intel_plane *plane,
 			      struct intel_crtc *crtc);
-	bool (*get_hw_state)(struct intel_plane *plane);
+	bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
 	int (*check_plane)(struct intel_plane *plane,
 			   struct intel_crtc_state *crtc_state,
 			   struct intel_plane_state *state);
@@ -2023,7 +2023,7 @@ void skl_update_plane(struct intel_plane *plane,
 		      const struct intel_crtc_state *crtc_state,
 		      const struct intel_plane_state *plane_state);
 void skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc);
-bool skl_plane_get_hw_state(struct intel_plane *plane);
+bool skl_plane_get_hw_state(struct intel_plane *plane, enum pipe *pipe);
 bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
 		       enum pipe pipe, enum plane_id plane_id);
 
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index aea21a9abf6c..86a31535fce3 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -326,19 +326,21 @@ skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
 }
 
 bool
-skl_plane_get_hw_state(struct intel_plane *plane)
+skl_plane_get_hw_state(struct intel_plane *plane,
+		       enum pipe *pipe)
 {
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 	enum intel_display_power_domain power_domain;
 	enum plane_id plane_id = plane->id;
-	enum pipe pipe = plane->pipe;
 	bool ret;
 
-	power_domain = POWER_DOMAIN_PIPE(pipe);
+	power_domain = POWER_DOMAIN_PIPE(plane->pipe);
 	if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
 		return false;
 
-	ret = I915_READ(PLANE_CTL(pipe, plane_id)) & PLANE_CTL_ENABLE;
+	ret = I915_READ(PLANE_CTL(plane->pipe, plane_id)) & PLANE_CTL_ENABLE;
+
+	*pipe = plane->pipe;
 
 	intel_display_power_put(dev_priv, power_domain);
 
@@ -523,19 +525,21 @@ vlv_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
 }
 
 static bool
-vlv_plane_get_hw_state(struct intel_plane *plane)
+vlv_plane_get_hw_state(struct intel_plane *plane,
+		       enum pipe *pipe)
 {
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 	enum intel_display_power_domain power_domain;
 	enum plane_id plane_id = plane->id;
-	enum pipe pipe = plane->pipe;
 	bool ret;
 
-	power_domain = POWER_DOMAIN_PIPE(pipe);
+	power_domain = POWER_DOMAIN_PIPE(plane->pipe);
 	if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
 		return false;
 
-	ret = I915_READ(SPCNTR(pipe, plane_id)) & SP_ENABLE;
+	ret = I915_READ(SPCNTR(plane->pipe, plane_id)) & SP_ENABLE;
+
+	*pipe = plane->pipe;
 
 	intel_display_power_put(dev_priv, power_domain);
 
@@ -683,18 +687,20 @@ ivb_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
 }
 
 static bool
-ivb_plane_get_hw_state(struct intel_plane *plane)
+ivb_plane_get_hw_state(struct intel_plane *plane,
+		       enum pipe *pipe)
 {
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 	enum intel_display_power_domain power_domain;
-	enum pipe pipe = plane->pipe;
 	bool ret;
 
-	power_domain = POWER_DOMAIN_PIPE(pipe);
+	power_domain = POWER_DOMAIN_PIPE(plane->pipe);
 	if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
 		return false;
 
-	ret =  I915_READ(SPRCTL(pipe)) & SPRITE_ENABLE;
+	ret =  I915_READ(SPRCTL(plane->pipe)) & SPRITE_ENABLE;
+
+	*pipe = plane->pipe;
 
 	intel_display_power_put(dev_priv, power_domain);
 
@@ -833,18 +839,20 @@ g4x_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
 }
 
 static bool
-g4x_plane_get_hw_state(struct intel_plane *plane)
+g4x_plane_get_hw_state(struct intel_plane *plane,
+		       enum pipe *pipe)
 {
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 	enum intel_display_power_domain power_domain;
-	enum pipe pipe = plane->pipe;
 	bool ret;
 
-	power_domain = POWER_DOMAIN_PIPE(pipe);
+	power_domain = POWER_DOMAIN_PIPE(plane->pipe);
 	if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
 		return false;
 
-	ret = I915_READ(DVSCNTR(pipe)) & DVS_ENABLE;
+	ret = I915_READ(DVSCNTR(plane->pipe)) & DVS_ENABLE;
+
+	*pipe = plane->pipe;
 
 	intel_display_power_put(dev_priv, power_domain);
 
-- 
2.13.6

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[PATCH 4/7] drm/i915: Clean up cursor defines

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Use MCURSOR_ instead of CURSOR_ as the prefix for the non-845/865
cursor defines consistently, and move the pipe CSC enable bit next
to the other non-845/865 cursor defines.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      | 22 +++++++++++-----------
 drivers/gpu/drm/i915/intel_display.c | 16 ++++++++--------
 2 files changed, 19 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ebb41f279134..dbcb4de92a63 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5891,7 +5891,6 @@ enum {
 #define   CURSOR_GAMMA_ENABLE	0x40000000
 #define   CURSOR_STRIDE_SHIFT	28
 #define   CURSOR_STRIDE(x)	((ffs(x)-9) << CURSOR_STRIDE_SHIFT) /* 256,512,1k,2k */
-#define   CURSOR_PIPE_CSC_ENABLE (1<<24)
 #define   CURSOR_FORMAT_SHIFT	24
 #define   CURSOR_FORMAT_MASK	(0x07 << CURSOR_FORMAT_SHIFT)
 #define   CURSOR_FORMAT_2C	(0x00 << CURSOR_FORMAT_SHIFT)
@@ -5900,20 +5899,21 @@ enum {
 #define   CURSOR_FORMAT_ARGB	(0x04 << CURSOR_FORMAT_SHIFT)
 #define   CURSOR_FORMAT_XRGB	(0x05 << CURSOR_FORMAT_SHIFT)
 /* New style CUR*CNTR flags */
-#define   CURSOR_MODE		0x27
-#define   CURSOR_MODE_DISABLE   0x00
-#define   CURSOR_MODE_128_32B_AX 0x02
-#define   CURSOR_MODE_256_32B_AX 0x03
-#define   CURSOR_MODE_64_32B_AX 0x07
-#define   CURSOR_MODE_128_ARGB_AX ((1 << 5) | CURSOR_MODE_128_32B_AX)
-#define   CURSOR_MODE_256_ARGB_AX ((1 << 5) | CURSOR_MODE_256_32B_AX)
-#define   CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
+#define   MCURSOR_MODE		0x27
+#define   MCURSOR_MODE_DISABLE   0x00
+#define   MCURSOR_MODE_128_32B_AX 0x02
+#define   MCURSOR_MODE_256_32B_AX 0x03
+#define   MCURSOR_MODE_64_32B_AX 0x07
+#define   MCURSOR_MODE_128_ARGB_AX ((1 << 5) | MCURSOR_MODE_128_32B_AX)
+#define   MCURSOR_MODE_256_ARGB_AX ((1 << 5) | MCURSOR_MODE_256_32B_AX)
+#define   MCURSOR_MODE_64_ARGB_AX ((1 << 5) | MCURSOR_MODE_64_32B_AX)
 #define   MCURSOR_PIPE_SELECT_MASK	(0x3 << 28)
 #define   MCURSOR_PIPE_SELECT_SHIFT	28
 #define   MCURSOR_PIPE_SELECT(pipe)	((pipe) << 28)
 #define   MCURSOR_GAMMA_ENABLE  (1 << 26)
-#define   CURSOR_ROTATE_180	(1<<15)
-#define   CURSOR_TRICKLE_FEED_DISABLE	(1 << 14)
+#define   MCURSOR_PIPE_CSC_ENABLE (1<<24)
+#define   MCURSOR_ROTATE_180	(1<<15)
+#define   MCURSOR_TRICKLE_FEED_DISABLE	(1 << 14)
 #define _CURABASE		0x70084
 #define _CURAPOS		0x70088
 #define   CURSOR_POS_MASK       0x007FF
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index feae6bd51a44..0cf02f226fd4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9549,20 +9549,20 @@ static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
 	cntl = MCURSOR_GAMMA_ENABLE;
 
 	if (HAS_DDI(dev_priv))
-		cntl |= CURSOR_PIPE_CSC_ENABLE;
+		cntl |= MCURSOR_PIPE_CSC_ENABLE;
 
 	if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
 		cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
 
 	switch (plane_state->base.crtc_w) {
 	case 64:
-		cntl |= CURSOR_MODE_64_ARGB_AX;
+		cntl |= MCURSOR_MODE_64_ARGB_AX;
 		break;
 	case 128:
-		cntl |= CURSOR_MODE_128_ARGB_AX;
+		cntl |= MCURSOR_MODE_128_ARGB_AX;
 		break;
 	case 256:
-		cntl |= CURSOR_MODE_256_ARGB_AX;
+		cntl |= MCURSOR_MODE_256_ARGB_AX;
 		break;
 	default:
 		MISSING_CASE(plane_state->base.crtc_w);
@@ -9570,7 +9570,7 @@ static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
 	}
 
 	if (plane_state->base.rotation & DRM_MODE_ROTATE_180)
-		cntl |= CURSOR_ROTATE_180;
+		cntl |= MCURSOR_ROTATE_180;
 
 	return cntl;
 }
@@ -9751,7 +9751,7 @@ static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
 
 	val = I915_READ(CURCNTR(plane->pipe));
 
-	ret = val & CURSOR_MODE;
+	ret = val & MCURSOR_MODE;
 
 	if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
 		*pipe = plane->pipe;
@@ -14768,8 +14768,8 @@ void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
 	WARN_ON(I915_READ(DSPCNTR(PLANE_A)) & DISPLAY_PLANE_ENABLE);
 	WARN_ON(I915_READ(DSPCNTR(PLANE_B)) & DISPLAY_PLANE_ENABLE);
 	WARN_ON(I915_READ(DSPCNTR(PLANE_C)) & DISPLAY_PLANE_ENABLE);
-	WARN_ON(I915_READ(CURCNTR(PIPE_A)) & CURSOR_MODE);
-	WARN_ON(I915_READ(CURCNTR(PIPE_B)) & CURSOR_MODE);
+	WARN_ON(I915_READ(CURCNTR(PIPE_A)) & MCURSOR_MODE);
+	WARN_ON(I915_READ(CURCNTR(PIPE_B)) & MCURSOR_MODE);
 
 	I915_WRITE(PIPECONF(pipe), 0);
 	POSTING_READ(PIPECONF(pipe));
-- 
2.13.6

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[PATCH 5/7] drm/i915: Disable trickle feed for SNB/IVB cursors

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We disable trickle feed whenever possible, except for the cursors
on SNB/IVB. Let's try disabling it there too if for no other reason
than consistency.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0cf02f226fd4..ab2402c225c7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9548,6 +9548,9 @@ static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
 
 	cntl = MCURSOR_GAMMA_ENABLE;
 
+	if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
+		cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
+
 	if (HAS_DDI(dev_priv))
 		cntl |= MCURSOR_PIPE_CSC_ENABLE;
 
-- 
2.13.6

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[PATCH 6/7] drm/i915: Drop WaDoubleCursorLP3Latency:ivb

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

WaDoubleCursorLP3Latency was meant for pre-production hardware.
Drop it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0b92ea1dbd40..8eac3895ea9a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2916,10 +2916,6 @@ static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
 	/* ILK cursor LP0 latency is 1300 ns */
 	if (IS_GEN5(dev_priv))
 		wm[0] = 13;
-
-	/* WaDoubleCursorLP3Latency:ivb */
-	if (IS_IVYBRIDGE(dev_priv))
-		wm[3] *= 2;
 }
 
 int ilk_wm_max_level(const struct drm_i915_private *dev_priv)
-- 
2.13.6

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[PATCH 7/7] drm/i915: s/plane/i9xx_plane/

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Call the enum i9xx_plane_id variable i9xx_plane like we do elsewhere.

Cc: Hans de Goede <j.w.r.degoede@gmail.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 51a1d6868b1e..9f378aa2dc5b 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -1665,16 +1665,16 @@ static int intel_dsi_get_panel_orientation(struct intel_connector *connector)
 {
 	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 	int orientation = DRM_MODE_PANEL_ORIENTATION_NORMAL;
-	enum i9xx_plane_id plane;
+	enum i9xx_plane_id i9xx_plane;
 	u32 val;
 
 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 		if (connector->encoder->crtc_mask == BIT(PIPE_B))
-			plane = PLANE_B;
+			i9xx_plane = PLANE_B;
 		else
-			plane = PLANE_A;
+			i9xx_plane = PLANE_A;
 
-		val = I915_READ(DSPCNTR(plane));
+		val = I915_READ(DSPCNTR(i9xx_plane));
 		if (val & DISPPLANE_ROTATE_180)
 			orientation = DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP;
 	}
-- 
2.13.6

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✗ Fi.CI.BAT: failure for series starting with [1/7] drm/i915: Don't set cursor pipe select bits on g4x+

[Patchwork]

== Series Details ==

Series: series starting with [1/7] drm/i915: Don't set cursor pipe select bits on g4x+
URL   : https://patchwork.freedesktop.org/series/37362/
State : failure

== Summary ==

  CHK     include/config/kernel.release
  CHK     include/generated/uapi/linux/version.h
  CHK     include/generated/utsrelease.h
  CHK     include/generated/bounds.h
  CHK     include/generated/timeconst.h
  CHK     include/generated/asm-offsets.h
  CALL    scripts/checksyscalls.sh
  DESCEND  objtool
  CHK     scripts/mod/devicetable-offsets.h
  CHK     include/generated/compile.h
  CHK     kernel/config_data.h
  CC [M]  drivers/gpu/drm/i915/gvt/fb_decoder.o
drivers/gpu/drm/i915/gvt/fb_decoder.c: In function ‘cursor_mode_to_drm’:
drivers/gpu/drm/i915/gvt/fb_decoder.c:306:7: error: ‘CURSOR_MODE_128_ARGB_AX’ undeclared (first use in this function)
  case CURSOR_MODE_128_ARGB_AX:
       ^~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/fb_decoder.c:306:7: note: each undeclared identifier is reported only once for each function it appears in
drivers/gpu/drm/i915/gvt/fb_decoder.c:309:7: error: ‘CURSOR_MODE_256_ARGB_AX’ undeclared (first use in this function)
  case CURSOR_MODE_256_ARGB_AX:
       ^~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/fb_decoder.c:312:7: error: ‘CURSOR_MODE_64_ARGB_AX’ undeclared (first use in this function)
  case CURSOR_MODE_64_ARGB_AX:
       ^~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/fb_decoder.c:315:7: error: ‘CURSOR_MODE_64_32B_AX’ undeclared (first use in this function)
  case CURSOR_MODE_64_32B_AX:
       ^~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/fb_decoder.c: In function ‘intel_vgpu_decode_cursor_plane’:
drivers/gpu/drm/i915/gvt/fb_decoder.c:348:15: error: ‘CURSOR_MODE’ undeclared (first use in this function)
  mode = val & CURSOR_MODE;
               ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/fb_decoder.c:349:28: error: ‘CURSOR_MODE_DISABLE’ undeclared (first use in this function)
  plane->enabled = (mode != CURSOR_MODE_DISABLE);
                            ^~~~~~~~~~~~~~~~~~~
scripts/Makefile.build:316: recipe for target 'drivers/gpu/drm/i915/gvt/fb_decoder.o' failed
make[4]: *** [drivers/gpu/drm/i915/gvt/fb_decoder.o] Error 1
scripts/Makefile.build:575: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:575: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:575: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1018: recipe for target 'drivers' failed
make: *** [drivers] Error 2

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Re: [PATCH 6/7] drm/i915: Drop WaDoubleCursorLP3Latency:ivb

[Mika Kahola]

On Tue, 2018-01-30 at 22:38 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> WaDoubleCursorLP3Latency was meant for pre-production hardware.
> Drop it.
> 
Reviewed-by: Mika Kahola <mika.kahola@intel.com>

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 4 ----
>  1 file changed, 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c
> b/drivers/gpu/drm/i915/intel_pm.c
> index 0b92ea1dbd40..8eac3895ea9a 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2916,10 +2916,6 @@ static void intel_fixup_cur_wm_latency(struct
> drm_i915_private *dev_priv,
>  	/* ILK cursor LP0 latency is 1300 ns */
>  	if (IS_GEN5(dev_priv))
>  		wm[0] = 13;
> -
> -	/* WaDoubleCursorLP3Latency:ivb */
> -	if (IS_IVYBRIDGE(dev_priv))
> -		wm[3] *= 2;
>  }
>  
>  int ilk_wm_max_level(const struct drm_i915_private *dev_priv)
-- 
Mika Kahola - Intel OTC

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[PATCH v2 4/7] drm/i915: Clean up cursor defines

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Use MCURSOR_ instead of CURSOR_ as the prefix for the non-845/865
cursor defines consistently, and move the pipe CSC enable bit next
to the other non-845/865 cursor defines.

v2: Take care of gvt uses as well

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/gvt/fb_decoder.c | 12 ++++++------
 drivers/gpu/drm/i915/i915_reg.h       | 22 +++++++++++-----------
 drivers/gpu/drm/i915/intel_display.c  | 16 ++++++++--------
 3 files changed, 25 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c b/drivers/gpu/drm/i915/gvt/fb_decoder.c
index 6b50fe78dc1b..73c0c2096a62 100644
--- a/drivers/gpu/drm/i915/gvt/fb_decoder.c
+++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c
@@ -303,16 +303,16 @@ static int cursor_mode_to_drm(int mode)
 	int cursor_pixel_formats_index = 4;
 
 	switch (mode) {
-	case CURSOR_MODE_128_ARGB_AX:
+	case MCURSOR_MODE_128_ARGB_AX:
 		cursor_pixel_formats_index = 0;
 		break;
-	case CURSOR_MODE_256_ARGB_AX:
+	case MCURSOR_MODE_256_ARGB_AX:
 		cursor_pixel_formats_index = 1;
 		break;
-	case CURSOR_MODE_64_ARGB_AX:
+	case MCURSOR_MODE_64_ARGB_AX:
 		cursor_pixel_formats_index = 2;
 		break;
-	case CURSOR_MODE_64_32B_AX:
+	case MCURSOR_MODE_64_32B_AX:
 		cursor_pixel_formats_index = 3;
 		break;
 
@@ -345,8 +345,8 @@ int intel_vgpu_decode_cursor_plane(struct intel_vgpu *vgpu,
 		return -ENODEV;
 
 	val = vgpu_vreg_t(vgpu, CURCNTR(pipe));
-	mode = val & CURSOR_MODE;
-	plane->enabled = (mode != CURSOR_MODE_DISABLE);
+	mode = val & MCURSOR_MODE;
+	plane->enabled = (mode != MCURSOR_MODE_DISABLE);
 	if (!plane->enabled)
 		return -ENODEV;
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ebb41f279134..dbcb4de92a63 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5891,7 +5891,6 @@ enum {
 #define   CURSOR_GAMMA_ENABLE	0x40000000
 #define   CURSOR_STRIDE_SHIFT	28
 #define   CURSOR_STRIDE(x)	((ffs(x)-9) << CURSOR_STRIDE_SHIFT) /* 256,512,1k,2k */
-#define   CURSOR_PIPE_CSC_ENABLE (1<<24)
 #define   CURSOR_FORMAT_SHIFT	24
 #define   CURSOR_FORMAT_MASK	(0x07 << CURSOR_FORMAT_SHIFT)
 #define   CURSOR_FORMAT_2C	(0x00 << CURSOR_FORMAT_SHIFT)
@@ -5900,20 +5899,21 @@ enum {
 #define   CURSOR_FORMAT_ARGB	(0x04 << CURSOR_FORMAT_SHIFT)
 #define   CURSOR_FORMAT_XRGB	(0x05 << CURSOR_FORMAT_SHIFT)
 /* New style CUR*CNTR flags */
-#define   CURSOR_MODE		0x27
-#define   CURSOR_MODE_DISABLE   0x00
-#define   CURSOR_MODE_128_32B_AX 0x02
-#define   CURSOR_MODE_256_32B_AX 0x03
-#define   CURSOR_MODE_64_32B_AX 0x07
-#define   CURSOR_MODE_128_ARGB_AX ((1 << 5) | CURSOR_MODE_128_32B_AX)
-#define   CURSOR_MODE_256_ARGB_AX ((1 << 5) | CURSOR_MODE_256_32B_AX)
-#define   CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
+#define   MCURSOR_MODE		0x27
+#define   MCURSOR_MODE_DISABLE   0x00
+#define   MCURSOR_MODE_128_32B_AX 0x02
+#define   MCURSOR_MODE_256_32B_AX 0x03
+#define   MCURSOR_MODE_64_32B_AX 0x07
+#define   MCURSOR_MODE_128_ARGB_AX ((1 << 5) | MCURSOR_MODE_128_32B_AX)
+#define   MCURSOR_MODE_256_ARGB_AX ((1 << 5) | MCURSOR_MODE_256_32B_AX)
+#define   MCURSOR_MODE_64_ARGB_AX ((1 << 5) | MCURSOR_MODE_64_32B_AX)
 #define   MCURSOR_PIPE_SELECT_MASK	(0x3 << 28)
 #define   MCURSOR_PIPE_SELECT_SHIFT	28
 #define   MCURSOR_PIPE_SELECT(pipe)	((pipe) << 28)
 #define   MCURSOR_GAMMA_ENABLE  (1 << 26)
-#define   CURSOR_ROTATE_180	(1<<15)
-#define   CURSOR_TRICKLE_FEED_DISABLE	(1 << 14)
+#define   MCURSOR_PIPE_CSC_ENABLE (1<<24)
+#define   MCURSOR_ROTATE_180	(1<<15)
+#define   MCURSOR_TRICKLE_FEED_DISABLE	(1 << 14)
 #define _CURABASE		0x70084
 #define _CURAPOS		0x70088
 #define   CURSOR_POS_MASK       0x007FF
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index feae6bd51a44..0cf02f226fd4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9549,20 +9549,20 @@ static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
 	cntl = MCURSOR_GAMMA_ENABLE;
 
 	if (HAS_DDI(dev_priv))
-		cntl |= CURSOR_PIPE_CSC_ENABLE;
+		cntl |= MCURSOR_PIPE_CSC_ENABLE;
 
 	if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
 		cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
 
 	switch (plane_state->base.crtc_w) {
 	case 64:
-		cntl |= CURSOR_MODE_64_ARGB_AX;
+		cntl |= MCURSOR_MODE_64_ARGB_AX;
 		break;
 	case 128:
-		cntl |= CURSOR_MODE_128_ARGB_AX;
+		cntl |= MCURSOR_MODE_128_ARGB_AX;
 		break;
 	case 256:
-		cntl |= CURSOR_MODE_256_ARGB_AX;
+		cntl |= MCURSOR_MODE_256_ARGB_AX;
 		break;
 	default:
 		MISSING_CASE(plane_state->base.crtc_w);
@@ -9570,7 +9570,7 @@ static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
 	}
 
 	if (plane_state->base.rotation & DRM_MODE_ROTATE_180)
-		cntl |= CURSOR_ROTATE_180;
+		cntl |= MCURSOR_ROTATE_180;
 
 	return cntl;
 }
@@ -9751,7 +9751,7 @@ static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
 
 	val = I915_READ(CURCNTR(plane->pipe));
 
-	ret = val & CURSOR_MODE;
+	ret = val & MCURSOR_MODE;
 
 	if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
 		*pipe = plane->pipe;
@@ -14768,8 +14768,8 @@ void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
 	WARN_ON(I915_READ(DSPCNTR(PLANE_A)) & DISPLAY_PLANE_ENABLE);
 	WARN_ON(I915_READ(DSPCNTR(PLANE_B)) & DISPLAY_PLANE_ENABLE);
 	WARN_ON(I915_READ(DSPCNTR(PLANE_C)) & DISPLAY_PLANE_ENABLE);
-	WARN_ON(I915_READ(CURCNTR(PIPE_A)) & CURSOR_MODE);
-	WARN_ON(I915_READ(CURCNTR(PIPE_B)) & CURSOR_MODE);
+	WARN_ON(I915_READ(CURCNTR(PIPE_A)) & MCURSOR_MODE);
+	WARN_ON(I915_READ(CURCNTR(PIPE_B)) & MCURSOR_MODE);
 
 	I915_WRITE(PIPECONF(pipe), 0);
 	POSTING_READ(PIPECONF(pipe));
-- 
2.13.6

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✓ Fi.CI.BAT: success for series starting with [1/7] drm/i915: Don't set cursor pipe select bits on g4x+ (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [1/7] drm/i915: Don't set cursor pipe select bits on g4x+ (rev2)
URL   : https://patchwork.freedesktop.org/series/37362/
State : success

== Summary ==

Series 37362v2 series starting with [1/7] drm/i915: Don't set cursor pipe select bits on g4x+
https://patchwork.freedesktop.org/api/1.0/series/37362/revisions/2/mbox/

Test gem_exec_suspend:
        Subgroup basic-s4-devices:
                pass       -> INCOMPLETE (fi-bdw-5557u) fdo#104162
Test kms_pipe_crc_basic:
        Subgroup suspend-read-crc-pipe-b:
                incomplete -> PASS       (fi-snb-2520m) fdo#103713

fdo#104162 https://bugs.freedesktop.org/show_bug.cgi?id=104162
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713

fi-bdw-5557u     total:109  pass:105  dwarn:0   dfail:0   fail:0   skip:3  
fi-bdw-gvtdvm    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:422s
fi-blb-e6850     total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  time:370s
fi-bsw-n3050     total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  time:490s
fi-bwr-2160      total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 time:283s
fi-bxt-dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  time:478s
fi-bxt-j4205     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:487s
fi-byt-j1900     total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  time:471s
fi-byt-n2820     total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  time:454s
fi-cfl-s2        total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:573s
fi-elk-e7500     total:224  pass:168  dwarn:10  dfail:0   fail:0   skip:45 
fi-gdg-551       total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 time:286s
fi-glk-1         total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:514s
fi-hsw-4770      total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:397s
fi-hsw-4770r     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:399s
fi-ilk-650       total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  time:416s
fi-ivb-3520m     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:449s
fi-ivb-3770      total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  time:411s
fi-kbl-7500u     total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  time:463s
fi-kbl-7560u     total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  time:496s
fi-kbl-7567u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:450s
fi-kbl-r         total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:502s
fi-pnv-d510      total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  time:583s
fi-skl-6260u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:438s
fi-skl-6600u     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:509s
fi-skl-6700hq    total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:525s
fi-skl-6700k2    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:494s
fi-skl-6770hq    total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:475s
fi-skl-guc       total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:417s
fi-skl-gvtdvm    total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  time:430s
fi-snb-2520m     total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:522s
fi-snb-2600      total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:403s
Blacklisted hosts:
fi-glk-dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  time:472s

badc0398a06018a07f6f50a1ff5a5fd8a30b9944 drm-tip: 2018y-01m-31d-12h-17m-12s UTC integration manifest
a6b40df641b0 drm/i915: s/plane/i9xx_plane/
309c54212a22 drm/i915: Drop WaDoubleCursorLP3Latency:ivb
ab266dd84d7a drm/i915: Disable trickle feed for SNB/IVB cursors
45da2273b46f drm/i915: Clean up cursor defines
8948a9152607 drm/i915: Have plane->get_hw_state() return the current pipe
db3c2d0815ab drm/i915: Set the primary plane pipe select bits on gen4
45bad81fbb4c drm/i915: Don't set cursor pipe select bits on g4x+

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7839/issues.html
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✓ Fi.CI.IGT: success for series starting with [1/7] drm/i915: Don't set cursor pipe select bits on g4x+ (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [1/7] drm/i915: Don't set cursor pipe select bits on g4x+ (rev2)
URL   : https://patchwork.freedesktop.org/series/37362/
State : success

== Summary ==

Test perf_pmu:
        Subgroup semaphore-wait-bcs0:
                fail       -> PASS       (shard-apl) fdo#104829
Test kms_sysfs_edid_timing:
                pass       -> WARN       (shard-apl) fdo#100047

fdo#104829 https://bugs.freedesktop.org/show_bug.cgi?id=104829
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047

shard-apl        total:2838 pass:1749 dwarn:1   dfail:0   fail:23  skip:1064 time:12633s
shard-hsw        total:2838 pass:1736 dwarn:1   dfail:0   fail:10  skip:1090 time:11990s
shard-snb        total:2838 pass:1330 dwarn:1   dfail:0   fail:10  skip:1497 time:6629s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7839/shards.html
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Re: [PATCH 1/7] drm/i915: Don't set cursor pipe select bits on g4x+

[Mika Kahola]

On Tue, 2018-01-30 at 22:38 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> G4x cursor control registers still allow us to write to the pipe
> select
> bits even though cursors are supposed to be fixed to a specific pipe.
> Bspec tells us that we should only ever write 0 to these bits. Let's
> follow that recommendation. On ilk+ the bits become hardwired to 0.
> 
> Also looks like ICL repurposes these bits for some other use, so
> we had better stop setting them to bogus values there.
> 

Reviewed-by: Mika Kahola <mika.kahola@intel.com>

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index af659d25943b..cccc1126f1d5 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -9532,7 +9532,8 @@ static u32 i9xx_cursor_ctl(const struct
> intel_crtc_state *crtc_state,
>  	if (HAS_DDI(dev_priv))
>  		cntl |= CURSOR_PIPE_CSC_ENABLE;
>  
> -	cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
> +	if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
> +		cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
>  
>  	switch (plane_state->base.crtc_w) {
>  	case 64:
-- 
Mika Kahola - Intel OTC

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Re: [PATCH 2/7] drm/i915: Set the primary plane pipe select bits on gen4

[Mika Kahola]

On Tue, 2018-01-30 at 22:38 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> i965 and g4x still have the pipe select bits in the plane control
> registers, they're just hardcoded to select a specific pipe. However
> plane C on i965 can still move between the pipes, thus we should
> program the pipe select bits on i965 if we want to expose plane C
> some day.
> 
> Since there is no harm in programming the bits on any plane on
> i965/g4x let's just always set them. This will also make our
> pre-computed register value match what the hardware register
> would read, should we want to cross check the two.
> 
Reviewed-by: Mika Kahola <mika.kahola@intel.com>

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index cccc1126f1d5..6ffc1d088d7a 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3163,7 +3163,7 @@ static u32 i9xx_plane_ctl(const struct
> intel_crtc_state *crtc_state,
>  	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
>  		dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
>  
> -	if (INTEL_GEN(dev_priv) < 4)
> +	if (INTEL_GEN(dev_priv) < 5)
>  		dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
>  
>  	switch (fb->format->format) {
-- 
Mika Kahola - Intel OTC

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Re: [PATCH 6/7] drm/i915: Drop WaDoubleCursorLP3Latency:ivb

[Ville Syrjälä]

On Wed, Jan 31, 2018 at 04:10:10PM +0200, Mika Kahola wrote:
> On Tue, 2018-01-30 at 22:38 +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > WaDoubleCursorLP3Latency was meant for pre-production hardware.
> > Drop it.
> > 
> Reviewed-by: Mika Kahola <mika.kahola@intel.com>

Patches 1,2,6 pushed to dinq. Thanks for the review.

> 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c | 4 ----
> >  1 file changed, 4 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index 0b92ea1dbd40..8eac3895ea9a 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -2916,10 +2916,6 @@ static void intel_fixup_cur_wm_latency(struct
> > drm_i915_private *dev_priv,
> >  	/* ILK cursor LP0 latency is 1300 ns */
> >  	if (IS_GEN5(dev_priv))
> >  		wm[0] = 13;
> > -
> > -	/* WaDoubleCursorLP3Latency:ivb */
> > -	if (IS_IVYBRIDGE(dev_priv))
> > -		wm[3] *= 2;
> >  }
> >  
> >  int ilk_wm_max_level(const struct drm_i915_private *dev_priv)
> -- 
> Mika Kahola - Intel OTC

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 3/7] drm/i915: Have plane->get_hw_state() return the current pipe

[Mika Kahola]

On Tue, 2018-01-30 at 22:38 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Like we do for encoder let's make the plane->get_hw_state() return
> the pipe to which the plane is currently attached. We don't currently
> allow planes to move between the pipes, but perhaps one day we will.
> 
> In either case this makes the code more uniform and perhaps makes
> intel_plane_mapping_ok() slightly more clear.
> 
> Note that for i965 and g4x planes A and B still have pipe select bits
> but they're hardwired to pipe A and B respectively. This means we can
> safely interpret those bits just like on gen2/3. This allows the
> same readout code work for plane C (which can still be assigned
> to eiter pipe on i965) should we ever expose it.
> 
> g4x no longer allows moving the cursor planes between the pipes,
> but the pipe select bits can still be set in the register. Thus
> we have to ignore those bits. OTOH i965 still allows the cursors
> to move between pipes thus we have to trust the bits there.
> 
Reviewed-by: Mika Kahola <mika.kahola@intel.com>

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h      |  2 +
>  drivers/gpu/drm/i915/intel_display.c | 71
> ++++++++++++++++++++++++++----------
>  drivers/gpu/drm/i915/intel_drv.h     |  4 +-
>  drivers/gpu/drm/i915/intel_sprite.c  | 40 ++++++++++++--------
>  4 files changed, 79 insertions(+), 38 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 64933fd74cb6..ebb41f279134 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5908,6 +5908,8 @@ enum {
>  #define   CURSOR_MODE_128_ARGB_AX ((1 << 5) |
> CURSOR_MODE_128_32B_AX)
>  #define   CURSOR_MODE_256_ARGB_AX ((1 << 5) |
> CURSOR_MODE_256_32B_AX)
>  #define   CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
> +#define   MCURSOR_PIPE_SELECT_MASK	(0x3 << 28)
> +#define   MCURSOR_PIPE_SELECT_SHIFT	28
>  #define   MCURSOR_PIPE_SELECT(pipe)	((pipe) << 28)
>  #define   MCURSOR_GAMMA_ENABLE  (1 << 26)
>  #define   CURSOR_ROTATE_180	(1<<15)
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 6ffc1d088d7a..feae6bd51a44 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1224,7 +1224,10 @@ void assert_pipe(struct drm_i915_private
> *dev_priv,
>  
>  static void assert_plane(struct intel_plane *plane, bool state)
>  {
> -	bool cur_state = plane->get_hw_state(plane);
> +	enum pipe pipe;
> +	bool cur_state;
> +
> +	cur_state = plane->get_hw_state(plane, &pipe);
>  
>  	I915_STATE_WARN(cur_state != state,
>  			"%s assertion failure (expected %s, current
> %s)\n",
> @@ -3326,24 +3329,33 @@ static void i9xx_disable_plane(struct
> intel_plane *plane,
>  	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
>  }
>  
> -static bool i9xx_plane_get_hw_state(struct intel_plane *plane)
> +static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
> +				    enum pipe *pipe)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(plane-
> >base.dev);
>  	enum intel_display_power_domain power_domain;
>  	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
> -	enum pipe pipe = plane->pipe;
>  	bool ret;
> +	u32 val;
>  
>  	/*
>  	 * Not 100% correct for planes that can move between pipes,
>  	 * but that's only the case for gen2-4 which don't have any
>  	 * display power wells.
>  	 */
> -	power_domain = POWER_DOMAIN_PIPE(pipe);
> +	power_domain = POWER_DOMAIN_PIPE(plane->pipe);
>  	if (!intel_display_power_get_if_enabled(dev_priv,
> power_domain))
>  		return false;
>  
> -	ret = I915_READ(DSPCNTR(i9xx_plane)) & DISPLAY_PLANE_ENABLE;
> +	val = I915_READ(DSPCNTR(i9xx_plane));
> +
> +	ret = val & DISPLAY_PLANE_ENABLE;
> +
> +	if (INTEL_GEN(dev_priv) >= 5)
> +		*pipe = plane->pipe;
> +	else
> +		*pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
> +			DISPPLANE_SEL_PIPE_SHIFT;
>  
>  	intel_display_power_put(dev_priv, power_domain);
>  
> @@ -7482,16 +7494,18 @@ i9xx_get_initial_plane_config(struct
> intel_crtc *crtc,
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  	struct intel_plane *plane = to_intel_plane(crtc-
> >base.primary);
>  	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
> -	enum pipe pipe = crtc->pipe;
> +	enum pipe pipe;
>  	u32 val, base, offset;
>  	int fourcc, pixel_format;
>  	unsigned int aligned_height;
>  	struct drm_framebuffer *fb;
>  	struct intel_framebuffer *intel_fb;
>  
> -	if (!plane->get_hw_state(plane))
> +	if (!plane->get_hw_state(plane, &pipe))
>  		return;
>  
> +	WARN_ON(pipe != crtc->pipe);
> +
>  	intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
>  	if (!intel_fb) {
>  		DRM_DEBUG_KMS("failed to alloc fb\n");
> @@ -8512,16 +8526,18 @@ skylake_get_initial_plane_config(struct
> intel_crtc *crtc,
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  	struct intel_plane *plane = to_intel_plane(crtc-
> >base.primary);
>  	enum plane_id plane_id = plane->id;
> -	enum pipe pipe = crtc->pipe;
> +	enum pipe pipe;
>  	u32 val, base, offset, stride_mult, tiling, alpha;
>  	int fourcc, pixel_format;
>  	unsigned int aligned_height;
>  	struct drm_framebuffer *fb;
>  	struct intel_framebuffer *intel_fb;
>  
> -	if (!plane->get_hw_state(plane))
> +	if (!plane->get_hw_state(plane, &pipe))
>  		return;
>  
> +	WARN_ON(pipe != crtc->pipe);
> +
>  	intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
>  	if (!intel_fb) {
>  		DRM_DEBUG_KMS("failed to alloc fb\n");
> @@ -9502,7 +9518,8 @@ static void i845_disable_cursor(struct
> intel_plane *plane,
>  	i845_update_cursor(plane, NULL, NULL);
>  }
>  
> -static bool i845_cursor_get_hw_state(struct intel_plane *plane)
> +static bool i845_cursor_get_hw_state(struct intel_plane *plane,
> +				     enum pipe *pipe)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(plane-
> >base.dev);
>  	enum intel_display_power_domain power_domain;
> @@ -9514,6 +9531,8 @@ static bool i845_cursor_get_hw_state(struct
> intel_plane *plane)
>  
>  	ret = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
>  
> +	*pipe = PIPE_A;
> +
>  	intel_display_power_put(dev_priv, power_domain);
>  
>  	return ret;
> @@ -9713,23 +9732,32 @@ static void i9xx_disable_cursor(struct
> intel_plane *plane,
>  	i9xx_update_cursor(plane, NULL, NULL);
>  }
>  
> -static bool i9xx_cursor_get_hw_state(struct intel_plane *plane)
> +static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
> +				     enum pipe *pipe)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(plane-
> >base.dev);
>  	enum intel_display_power_domain power_domain;
> -	enum pipe pipe = plane->pipe;
>  	bool ret;
> +	u32 val;
>  
>  	/*
>  	 * Not 100% correct for planes that can move between pipes,
>  	 * but that's only the case for gen2-3 which don't have any
>  	 * display power wells.
>  	 */
> -	power_domain = POWER_DOMAIN_PIPE(pipe);
> +	power_domain = POWER_DOMAIN_PIPE(plane->pipe);
>  	if (!intel_display_power_get_if_enabled(dev_priv,
> power_domain))
>  		return false;
>  
> -	ret = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
> +	val = I915_READ(CURCNTR(plane->pipe));
> +
> +	ret = val & CURSOR_MODE;
> +
> +	if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
> +		*pipe = plane->pipe;
> +	else
> +		*pipe = (val & MCURSOR_PIPE_SELECT_MASK) >>
> +			MCURSOR_PIPE_SELECT_SHIFT;
>  
>  	intel_display_power_put(dev_priv, power_domain);
>  
> @@ -14755,12 +14783,12 @@ void i830_disable_pipe(struct
> drm_i915_private *dev_priv, enum pipe pipe)
>  static bool intel_plane_mapping_ok(struct intel_crtc *crtc,
>  				   struct intel_plane *plane)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> -	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
> -	u32 val = I915_READ(DSPCNTR(i9xx_plane));
> +	enum pipe pipe;
>  
> -	return (val & DISPLAY_PLANE_ENABLE) == 0 ||
> -		(val & DISPPLANE_SEL_PIPE_MASK) ==
> DISPPLANE_SEL_PIPE(crtc->pipe);
> +	if (!plane->get_hw_state(plane, &pipe))
> +		return true;
> +
> +	return pipe == crtc->pipe;
>  }
>  
>  static void
> @@ -14959,7 +14987,10 @@ static void readout_plane_state(struct
> intel_crtc *crtc)
>  	for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
>  		struct intel_plane_state *plane_state =
>  			to_intel_plane_state(plane->base.state);
> -		bool visible = plane->get_hw_state(plane);
> +		enum pipe pipe;
> +		bool visible;
> +
> +		visible = plane->get_hw_state(plane, &pipe);
>  
>  		intel_set_plane_visible(crtc_state, plane_state,
> visible);
>  	}
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 8335d27f4156..d80eae7a69ba 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -946,7 +946,7 @@ struct intel_plane {
>  			     const struct intel_plane_state
> *plane_state);
>  	void (*disable_plane)(struct intel_plane *plane,
>  			      struct intel_crtc *crtc);
> -	bool (*get_hw_state)(struct intel_plane *plane);
> +	bool (*get_hw_state)(struct intel_plane *plane, enum pipe
> *pipe);
>  	int (*check_plane)(struct intel_plane *plane,
>  			   struct intel_crtc_state *crtc_state,
>  			   struct intel_plane_state *state);
> @@ -2023,7 +2023,7 @@ void skl_update_plane(struct intel_plane
> *plane,
>  		      const struct intel_crtc_state *crtc_state,
>  		      const struct intel_plane_state *plane_state);
>  void skl_disable_plane(struct intel_plane *plane, struct intel_crtc
> *crtc);
> -bool skl_plane_get_hw_state(struct intel_plane *plane);
> +bool skl_plane_get_hw_state(struct intel_plane *plane, enum pipe
> *pipe);
>  bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
>  		       enum pipe pipe, enum plane_id plane_id);
>  
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> b/drivers/gpu/drm/i915/intel_sprite.c
> index aea21a9abf6c..86a31535fce3 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -326,19 +326,21 @@ skl_disable_plane(struct intel_plane *plane,
> struct intel_crtc *crtc)
>  }
>  
>  bool
> -skl_plane_get_hw_state(struct intel_plane *plane)
> +skl_plane_get_hw_state(struct intel_plane *plane,
> +		       enum pipe *pipe)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(plane-
> >base.dev);
>  	enum intel_display_power_domain power_domain;
>  	enum plane_id plane_id = plane->id;
> -	enum pipe pipe = plane->pipe;
>  	bool ret;
>  
> -	power_domain = POWER_DOMAIN_PIPE(pipe);
> +	power_domain = POWER_DOMAIN_PIPE(plane->pipe);
>  	if (!intel_display_power_get_if_enabled(dev_priv,
> power_domain))
>  		return false;
>  
> -	ret = I915_READ(PLANE_CTL(pipe, plane_id)) &
> PLANE_CTL_ENABLE;
> +	ret = I915_READ(PLANE_CTL(plane->pipe, plane_id)) &
> PLANE_CTL_ENABLE;
> +
> +	*pipe = plane->pipe;
>  
>  	intel_display_power_put(dev_priv, power_domain);
>  
> @@ -523,19 +525,21 @@ vlv_disable_plane(struct intel_plane *plane,
> struct intel_crtc *crtc)
>  }
>  
>  static bool
> -vlv_plane_get_hw_state(struct intel_plane *plane)
> +vlv_plane_get_hw_state(struct intel_plane *plane,
> +		       enum pipe *pipe)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(plane-
> >base.dev);
>  	enum intel_display_power_domain power_domain;
>  	enum plane_id plane_id = plane->id;
> -	enum pipe pipe = plane->pipe;
>  	bool ret;
>  
> -	power_domain = POWER_DOMAIN_PIPE(pipe);
> +	power_domain = POWER_DOMAIN_PIPE(plane->pipe);
>  	if (!intel_display_power_get_if_enabled(dev_priv,
> power_domain))
>  		return false;
>  
> -	ret = I915_READ(SPCNTR(pipe, plane_id)) & SP_ENABLE;
> +	ret = I915_READ(SPCNTR(plane->pipe, plane_id)) & SP_ENABLE;
> +
> +	*pipe = plane->pipe;
>  
>  	intel_display_power_put(dev_priv, power_domain);
>  
> @@ -683,18 +687,20 @@ ivb_disable_plane(struct intel_plane *plane,
> struct intel_crtc *crtc)
>  }
>  
>  static bool
> -ivb_plane_get_hw_state(struct intel_plane *plane)
> +ivb_plane_get_hw_state(struct intel_plane *plane,
> +		       enum pipe *pipe)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(plane-
> >base.dev);
>  	enum intel_display_power_domain power_domain;
> -	enum pipe pipe = plane->pipe;
>  	bool ret;
>  
> -	power_domain = POWER_DOMAIN_PIPE(pipe);
> +	power_domain = POWER_DOMAIN_PIPE(plane->pipe);
>  	if (!intel_display_power_get_if_enabled(dev_priv,
> power_domain))
>  		return false;
>  
> -	ret =  I915_READ(SPRCTL(pipe)) & SPRITE_ENABLE;
> +	ret =  I915_READ(SPRCTL(plane->pipe)) & SPRITE_ENABLE;
> +
> +	*pipe = plane->pipe;
>  
>  	intel_display_power_put(dev_priv, power_domain);
>  
> @@ -833,18 +839,20 @@ g4x_disable_plane(struct intel_plane *plane,
> struct intel_crtc *crtc)
>  }
>  
>  static bool
> -g4x_plane_get_hw_state(struct intel_plane *plane)
> +g4x_plane_get_hw_state(struct intel_plane *plane,
> +		       enum pipe *pipe)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(plane-
> >base.dev);
>  	enum intel_display_power_domain power_domain;
> -	enum pipe pipe = plane->pipe;
>  	bool ret;
>  
> -	power_domain = POWER_DOMAIN_PIPE(pipe);
> +	power_domain = POWER_DOMAIN_PIPE(plane->pipe);
>  	if (!intel_display_power_get_if_enabled(dev_priv,
> power_domain))
>  		return false;
>  
> -	ret = I915_READ(DVSCNTR(pipe)) & DVS_ENABLE;
> +	ret = I915_READ(DVSCNTR(plane->pipe)) & DVS_ENABLE;
> +
> +	*pipe = plane->pipe;
>  
>  	intel_display_power_put(dev_priv, power_domain);
>  
-- 
Mika Kahola - Intel OTC

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Re: [PATCH v2 4/7] drm/i915: Clean up cursor defines

[Mika Kahola]

On Wed, 2018-01-31 at 16:37 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Use MCURSOR_ instead of CURSOR_ as the prefix for the non-845/865
> cursor defines consistently, and move the pipe CSC enable bit next
> to the other non-845/865 cursor defines.
> 
> v2: Take care of gvt uses as well
> 
Reviewed-by: Mika Kahola <mika.kahola@intel.com>

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/gvt/fb_decoder.c | 12 ++++++------
>  drivers/gpu/drm/i915/i915_reg.h       | 22 +++++++++++-----------
>  drivers/gpu/drm/i915/intel_display.c  | 16 ++++++++--------
>  3 files changed, 25 insertions(+), 25 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c
> b/drivers/gpu/drm/i915/gvt/fb_decoder.c
> index 6b50fe78dc1b..73c0c2096a62 100644
> --- a/drivers/gpu/drm/i915/gvt/fb_decoder.c
> +++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c
> @@ -303,16 +303,16 @@ static int cursor_mode_to_drm(int mode)
>  	int cursor_pixel_formats_index = 4;
>  
>  	switch (mode) {
> -	case CURSOR_MODE_128_ARGB_AX:
> +	case MCURSOR_MODE_128_ARGB_AX:
>  		cursor_pixel_formats_index = 0;
>  		break;
> -	case CURSOR_MODE_256_ARGB_AX:
> +	case MCURSOR_MODE_256_ARGB_AX:
>  		cursor_pixel_formats_index = 1;
>  		break;
> -	case CURSOR_MODE_64_ARGB_AX:
> +	case MCURSOR_MODE_64_ARGB_AX:
>  		cursor_pixel_formats_index = 2;
>  		break;
> -	case CURSOR_MODE_64_32B_AX:
> +	case MCURSOR_MODE_64_32B_AX:
>  		cursor_pixel_formats_index = 3;
>  		break;
>  
> @@ -345,8 +345,8 @@ int intel_vgpu_decode_cursor_plane(struct
> intel_vgpu *vgpu,
>  		return -ENODEV;
>  
>  	val = vgpu_vreg_t(vgpu, CURCNTR(pipe));
> -	mode = val & CURSOR_MODE;
> -	plane->enabled = (mode != CURSOR_MODE_DISABLE);
> +	mode = val & MCURSOR_MODE;
> +	plane->enabled = (mode != MCURSOR_MODE_DISABLE);
>  	if (!plane->enabled)
>  		return -ENODEV;
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index ebb41f279134..dbcb4de92a63 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5891,7 +5891,6 @@ enum {
>  #define   CURSOR_GAMMA_ENABLE	0x40000000
>  #define   CURSOR_STRIDE_SHIFT	28
>  #define   CURSOR_STRIDE(x)	((ffs(x)-9) <<
> CURSOR_STRIDE_SHIFT) /* 256,512,1k,2k */
> -#define   CURSOR_PIPE_CSC_ENABLE (1<<24)
>  #define   CURSOR_FORMAT_SHIFT	24
>  #define   CURSOR_FORMAT_MASK	(0x07 << CURSOR_FORMAT_SHIFT)
>  #define   CURSOR_FORMAT_2C	(0x00 << CURSOR_FORMAT_SHIFT)
> @@ -5900,20 +5899,21 @@ enum {
>  #define   CURSOR_FORMAT_ARGB	(0x04 << CURSOR_FORMAT_SHIFT)
>  #define   CURSOR_FORMAT_XRGB	(0x05 << CURSOR_FORMAT_SHIFT)
>  /* New style CUR*CNTR flags */
> -#define   CURSOR_MODE		0x27
> -#define   CURSOR_MODE_DISABLE   0x00
> -#define   CURSOR_MODE_128_32B_AX 0x02
> -#define   CURSOR_MODE_256_32B_AX 0x03
> -#define   CURSOR_MODE_64_32B_AX 0x07
> -#define   CURSOR_MODE_128_ARGB_AX ((1 << 5) |
> CURSOR_MODE_128_32B_AX)
> -#define   CURSOR_MODE_256_ARGB_AX ((1 << 5) |
> CURSOR_MODE_256_32B_AX)
> -#define   CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
> +#define   MCURSOR_MODE		0x27
> +#define   MCURSOR_MODE_DISABLE   0x00
> +#define   MCURSOR_MODE_128_32B_AX 0x02
> +#define   MCURSOR_MODE_256_32B_AX 0x03
> +#define   MCURSOR_MODE_64_32B_AX 0x07
> +#define   MCURSOR_MODE_128_ARGB_AX ((1 << 5) |
> MCURSOR_MODE_128_32B_AX)
> +#define   MCURSOR_MODE_256_ARGB_AX ((1 << 5) |
> MCURSOR_MODE_256_32B_AX)
> +#define   MCURSOR_MODE_64_ARGB_AX ((1 << 5) |
> MCURSOR_MODE_64_32B_AX)
>  #define   MCURSOR_PIPE_SELECT_MASK	(0x3 << 28)
>  #define   MCURSOR_PIPE_SELECT_SHIFT	28
>  #define   MCURSOR_PIPE_SELECT(pipe)	((pipe) << 28)
>  #define   MCURSOR_GAMMA_ENABLE  (1 << 26)
> -#define   CURSOR_ROTATE_180	(1<<15)
> -#define   CURSOR_TRICKLE_FEED_DISABLE	(1 << 14)
> +#define   MCURSOR_PIPE_CSC_ENABLE (1<<24)
> +#define   MCURSOR_ROTATE_180	(1<<15)
> +#define   MCURSOR_TRICKLE_FEED_DISABLE	(1 << 14)
>  #define _CURABASE		0x70084
>  #define _CURAPOS		0x70088
>  #define   CURSOR_POS_MASK       0x007FF
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index feae6bd51a44..0cf02f226fd4 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -9549,20 +9549,20 @@ static u32 i9xx_cursor_ctl(const struct
> intel_crtc_state *crtc_state,
>  	cntl = MCURSOR_GAMMA_ENABLE;
>  
>  	if (HAS_DDI(dev_priv))
> -		cntl |= CURSOR_PIPE_CSC_ENABLE;
> +		cntl |= MCURSOR_PIPE_CSC_ENABLE;
>  
>  	if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
>  		cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
>  
>  	switch (plane_state->base.crtc_w) {
>  	case 64:
> -		cntl |= CURSOR_MODE_64_ARGB_AX;
> +		cntl |= MCURSOR_MODE_64_ARGB_AX;
>  		break;
>  	case 128:
> -		cntl |= CURSOR_MODE_128_ARGB_AX;
> +		cntl |= MCURSOR_MODE_128_ARGB_AX;
>  		break;
>  	case 256:
> -		cntl |= CURSOR_MODE_256_ARGB_AX;
> +		cntl |= MCURSOR_MODE_256_ARGB_AX;
>  		break;
>  	default:
>  		MISSING_CASE(plane_state->base.crtc_w);
> @@ -9570,7 +9570,7 @@ static u32 i9xx_cursor_ctl(const struct
> intel_crtc_state *crtc_state,
>  	}
>  
>  	if (plane_state->base.rotation & DRM_MODE_ROTATE_180)
> -		cntl |= CURSOR_ROTATE_180;
> +		cntl |= MCURSOR_ROTATE_180;
>  
>  	return cntl;
>  }
> @@ -9751,7 +9751,7 @@ static bool i9xx_cursor_get_hw_state(struct
> intel_plane *plane,
>  
>  	val = I915_READ(CURCNTR(plane->pipe));
>  
> -	ret = val & CURSOR_MODE;
> +	ret = val & MCURSOR_MODE;
>  
>  	if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
>  		*pipe = plane->pipe;
> @@ -14768,8 +14768,8 @@ void i830_disable_pipe(struct
> drm_i915_private *dev_priv, enum pipe pipe)
>  	WARN_ON(I915_READ(DSPCNTR(PLANE_A)) & DISPLAY_PLANE_ENABLE);
>  	WARN_ON(I915_READ(DSPCNTR(PLANE_B)) & DISPLAY_PLANE_ENABLE);
>  	WARN_ON(I915_READ(DSPCNTR(PLANE_C)) & DISPLAY_PLANE_ENABLE);
> -	WARN_ON(I915_READ(CURCNTR(PIPE_A)) & CURSOR_MODE);
> -	WARN_ON(I915_READ(CURCNTR(PIPE_B)) & CURSOR_MODE);
> +	WARN_ON(I915_READ(CURCNTR(PIPE_A)) & MCURSOR_MODE);
> +	WARN_ON(I915_READ(CURCNTR(PIPE_B)) & MCURSOR_MODE);
>  
>  	I915_WRITE(PIPECONF(pipe), 0);
>  	POSTING_READ(PIPECONF(pipe));
-- 
Mika Kahola - Intel OTC

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Re: [PATCH 5/7] drm/i915: Disable trickle feed for SNB/IVB cursors

[Mika Kahola]

On Tue, 2018-01-30 at 22:38 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> We disable trickle feed whenever possible, except for the cursors
> on SNB/IVB. Let's try disabling it there too if for no other reason
> than consistency.
> 
Reviewed-by: Mika Kahola <mika.kahola@intel.com>

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 0cf02f226fd4..ab2402c225c7 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -9548,6 +9548,9 @@ static u32 i9xx_cursor_ctl(const struct
> intel_crtc_state *crtc_state,
>  
>  	cntl = MCURSOR_GAMMA_ENABLE;
>  
> +	if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
> +		cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
> +
>  	if (HAS_DDI(dev_priv))
>  		cntl |= MCURSOR_PIPE_CSC_ENABLE;
>  
-- 
Mika Kahola - Intel OTC

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Re: [PATCH 7/7] drm/i915: s/plane/i9xx_plane/

[Mika Kahola]

On Tue, 2018-01-30 at 22:38 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Call the enum i9xx_plane_id variable i9xx_plane like we do elsewhere.
> 
> Cc: Hans de Goede <j.w.r.degoede@gmail.com>

Reviewed-by: Mika Kahola <mika.kahola@intel.com>

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dsi.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c
> b/drivers/gpu/drm/i915/intel_dsi.c
> index 51a1d6868b1e..9f378aa2dc5b 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -1665,16 +1665,16 @@ static int
> intel_dsi_get_panel_orientation(struct intel_connector *connector)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(connector-
> >base.dev);
>  	int orientation = DRM_MODE_PANEL_ORIENTATION_NORMAL;
> -	enum i9xx_plane_id plane;
> +	enum i9xx_plane_id i9xx_plane;
>  	u32 val;
>  
>  	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
>  		if (connector->encoder->crtc_mask == BIT(PIPE_B))
> -			plane = PLANE_B;
> +			i9xx_plane = PLANE_B;
>  		else
> -			plane = PLANE_A;
> +			i9xx_plane = PLANE_A;
>  
> -		val = I915_READ(DSPCNTR(plane));
> +		val = I915_READ(DSPCNTR(i9xx_plane));
>  		if (val & DISPPLANE_ROTATE_180)
>  			orientation =
> DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP;
>  	}
-- 
Mika Kahola - Intel OTC

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Re: [PATCH 7/7] drm/i915: s/plane/i9xx_plane/

[Ville Syrjälä]

On Fri, Jun 01, 2018 at 01:29:12PM +0300, Mika Kahola wrote:
> On Tue, 2018-01-30 at 22:38 +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Call the enum i9xx_plane_id variable i9xx_plane like we do elsewhere.
> > 
> > Cc: Hans de Goede <j.w.r.degoede@gmail.com>
> 
> Reviewed-by: Mika Kahola <mika.kahola@intel.com>

Thanks. Remainder of the series pushed.

> 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_dsi.c | 8 ++++----
> >  1 file changed, 4 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_dsi.c
> > b/drivers/gpu/drm/i915/intel_dsi.c
> > index 51a1d6868b1e..9f378aa2dc5b 100644
> > --- a/drivers/gpu/drm/i915/intel_dsi.c
> > +++ b/drivers/gpu/drm/i915/intel_dsi.c
> > @@ -1665,16 +1665,16 @@ static int
> > intel_dsi_get_panel_orientation(struct intel_connector *connector)
> >  {
> >  	struct drm_i915_private *dev_priv = to_i915(connector-
> > >base.dev);
> >  	int orientation = DRM_MODE_PANEL_ORIENTATION_NORMAL;
> > -	enum i9xx_plane_id plane;
> > +	enum i9xx_plane_id i9xx_plane;
> >  	u32 val;
> >  
> >  	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> >  		if (connector->encoder->crtc_mask == BIT(PIPE_B))
> > -			plane = PLANE_B;
> > +			i9xx_plane = PLANE_B;
> >  		else
> > -			plane = PLANE_A;
> > +			i9xx_plane = PLANE_A;
> >  
> > -		val = I915_READ(DSPCNTR(plane));
> > +		val = I915_READ(DSPCNTR(i9xx_plane));
> >  		if (val & DISPPLANE_ROTATE_180)
> >  			orientation =
> > DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP;
> >  	}
> -- 
> Mika Kahola - Intel OTC

-- 
Ville Syrjälä
Intel
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