* [PATCH 1/4] clk: imx6q: remove clks_init_on array @ 2018-06-03 3:00 ` Anson Huang 0 siblings, 0 replies; 28+ messages in thread From: Anson Huang @ 2018-06-03 3:00 UTC (permalink / raw) To: shawnguo, kernel, fabio.estevam, mturquette, sboyd Cc: Linux-imx, linux-arm-kernel, linux-clk, linux-kernel Clock framework will enable those clocks registered with CLK_IS_CRITICAL flag, so no need to have clks_init_on array during clock initialization now. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> --- drivers/clk/imx/clk-imx6q.c | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-) diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c index b9ea703..8754c61 100644 --- a/drivers/clk/imx/clk-imx6q.c +++ b/drivers/clk/imx/clk-imx6q.c @@ -96,12 +96,6 @@ static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", }; static struct clk *clk[IMX6QDL_CLK_END]; static struct clk_onecell_data clk_data; -static unsigned int const clks_init_on[] __initconst = { - IMX6QDL_CLK_MMDC_CH0_AXI, - IMX6QDL_CLK_ROM, - IMX6QDL_CLK_ARM, -}; - static struct clk_div_table clk_enet_ref_table[] = { { .val = 0, .div = 20, }, { .val = 1, .div = 10, }, @@ -417,7 +411,6 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) { struct device_node *np; void __iomem *anatop_base, *base; - int i; int ret; clk[IMX6QDL_CLK_DUMMY] = imx_clk_fixed("dummy", 0); @@ -794,7 +787,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk[IMX6QDL_CLK_MLB] = imx_clk_gate2("mlb", "mlb_podf", base + 0x74, 18); else clk[IMX6QDL_CLK_MLB] = imx_clk_gate2("mlb", "axi", base + 0x74, 18); - clk[IMX6QDL_CLK_MMDC_CH0_AXI] = imx_clk_gate2("mmdc_ch0_axi", "mmdc_ch0_axi_podf", base + 0x74, 20); + clk[IMX6QDL_CLK_MMDC_CH0_AXI] = imx_clk_gate2_flags("mmdc_ch0_axi", "mmdc_ch0_axi_podf", base + 0x74, 20, CLK_IS_CRITICAL); clk[IMX6QDL_CLK_MMDC_CH1_AXI] = imx_clk_gate2("mmdc_ch1_axi", "mmdc_ch1_axi_podf", base + 0x74, 22); clk[IMX6QDL_CLK_OCRAM] = imx_clk_gate2("ocram", "ahb", base + 0x74, 28); clk[IMX6QDL_CLK_OPENVG_AXI] = imx_clk_gate2("openvg_axi", "axi", base + 0x74, 30); @@ -808,7 +801,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk[IMX6QDL_CLK_GPMI_BCH] = imx_clk_gate2("gpmi_bch", "usdhc4", base + 0x78, 26); clk[IMX6QDL_CLK_GPMI_IO] = imx_clk_gate2("gpmi_io", "enfc", base + 0x78, 28); clk[IMX6QDL_CLK_GPMI_APB] = imx_clk_gate2("gpmi_apb", "usdhc3", base + 0x78, 30); - clk[IMX6QDL_CLK_ROM] = imx_clk_gate2("rom", "ahb", base + 0x7c, 0); + clk[IMX6QDL_CLK_ROM] = imx_clk_gate2_flags("rom", "ahb", base + 0x7c, 0, CLK_IS_CRITICAL); clk[IMX6QDL_CLK_SATA] = imx_clk_gate2("sata", "ahb", base + 0x7c, 4); clk[IMX6QDL_CLK_SDMA] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6); clk[IMX6QDL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12); @@ -878,9 +871,6 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) */ clk_set_parent(clk[IMX6QDL_CLK_ENFC_SEL], clk[IMX6QDL_CLK_PLL2_PFD2_396M]); - for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) - clk_prepare_enable(clk[clks_init_on[i]]); - if (IS_ENABLED(CONFIG_USB_MXS_PHY)) { clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY1_GATE]); clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY2_GATE]); -- 2.7.4 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 1/4] clk: imx6q: remove clks_init_on array @ 2018-06-03 3:00 ` Anson Huang 0 siblings, 0 replies; 28+ messages in thread From: Anson Huang @ 2018-06-03 3:00 UTC (permalink / raw) To: linux-arm-kernel Clock framework will enable those clocks registered with CLK_IS_CRITICAL flag, so no need to have clks_init_on array during clock initialization now. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> --- drivers/clk/imx/clk-imx6q.c | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-) diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c index b9ea703..8754c61 100644 --- a/drivers/clk/imx/clk-imx6q.c +++ b/drivers/clk/imx/clk-imx6q.c @@ -96,12 +96,6 @@ static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", }; static struct clk *clk[IMX6QDL_CLK_END]; static struct clk_onecell_data clk_data; -static unsigned int const clks_init_on[] __initconst = { - IMX6QDL_CLK_MMDC_CH0_AXI, - IMX6QDL_CLK_ROM, - IMX6QDL_CLK_ARM, -}; - static struct clk_div_table clk_enet_ref_table[] = { { .val = 0, .div = 20, }, { .val = 1, .div = 10, }, @@ -417,7 +411,6 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) { struct device_node *np; void __iomem *anatop_base, *base; - int i; int ret; clk[IMX6QDL_CLK_DUMMY] = imx_clk_fixed("dummy", 0); @@ -794,7 +787,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk[IMX6QDL_CLK_MLB] = imx_clk_gate2("mlb", "mlb_podf", base + 0x74, 18); else clk[IMX6QDL_CLK_MLB] = imx_clk_gate2("mlb", "axi", base + 0x74, 18); - clk[IMX6QDL_CLK_MMDC_CH0_AXI] = imx_clk_gate2("mmdc_ch0_axi", "mmdc_ch0_axi_podf", base + 0x74, 20); + clk[IMX6QDL_CLK_MMDC_CH0_AXI] = imx_clk_gate2_flags("mmdc_ch0_axi", "mmdc_ch0_axi_podf", base + 0x74, 20, CLK_IS_CRITICAL); clk[IMX6QDL_CLK_MMDC_CH1_AXI] = imx_clk_gate2("mmdc_ch1_axi", "mmdc_ch1_axi_podf", base + 0x74, 22); clk[IMX6QDL_CLK_OCRAM] = imx_clk_gate2("ocram", "ahb", base + 0x74, 28); clk[IMX6QDL_CLK_OPENVG_AXI] = imx_clk_gate2("openvg_axi", "axi", base + 0x74, 30); @@ -808,7 +801,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk[IMX6QDL_CLK_GPMI_BCH] = imx_clk_gate2("gpmi_bch", "usdhc4", base + 0x78, 26); clk[IMX6QDL_CLK_GPMI_IO] = imx_clk_gate2("gpmi_io", "enfc", base + 0x78, 28); clk[IMX6QDL_CLK_GPMI_APB] = imx_clk_gate2("gpmi_apb", "usdhc3", base + 0x78, 30); - clk[IMX6QDL_CLK_ROM] = imx_clk_gate2("rom", "ahb", base + 0x7c, 0); + clk[IMX6QDL_CLK_ROM] = imx_clk_gate2_flags("rom", "ahb", base + 0x7c, 0, CLK_IS_CRITICAL); clk[IMX6QDL_CLK_SATA] = imx_clk_gate2("sata", "ahb", base + 0x7c, 4); clk[IMX6QDL_CLK_SDMA] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6); clk[IMX6QDL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12); @@ -878,9 +871,6 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) */ clk_set_parent(clk[IMX6QDL_CLK_ENFC_SEL], clk[IMX6QDL_CLK_PLL2_PFD2_396M]); - for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) - clk_prepare_enable(clk[clks_init_on[i]]); - if (IS_ENABLED(CONFIG_USB_MXS_PHY)) { clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY1_GATE]); clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY2_GATE]); -- 2.7.4 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 2/4] clk: imx6sl: remove clks_init_on array 2018-06-03 3:00 ` Anson Huang @ 2018-06-03 3:00 ` Anson Huang -1 siblings, 0 replies; 28+ messages in thread From: Anson Huang @ 2018-06-03 3:00 UTC (permalink / raw) To: shawnguo, kernel, fabio.estevam, mturquette, sboyd Cc: Linux-imx, linux-arm-kernel, linux-clk, linux-kernel Clock framework will enable those clocks registered with CLK_IS_CRITICAL flag, so no need to have clks_init_on array during clock initialization now. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> --- drivers/clk/imx/clk-imx6sl.c | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/drivers/clk/imx/clk-imx6sl.c b/drivers/clk/imx/clk-imx6sl.c index 66b1dd1..eb6bcbf 100644 --- a/drivers/clk/imx/clk-imx6sl.c +++ b/drivers/clk/imx/clk-imx6sl.c @@ -104,10 +104,6 @@ static struct clk_onecell_data clk_data; static void __iomem *ccm_base; static void __iomem *anatop_base; -static const u32 clks_init_on[] __initconst = { - IMX6SL_CLK_IPG, IMX6SL_CLK_ARM, IMX6SL_CLK_MMDC_ROOT, -}; - /* * ERR005311 CCM: After exit from WAIT mode, unwanted interrupt(s) taken * during WAIT mode entry process could cause cache memory @@ -195,7 +191,6 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) { struct device_node *np; void __iomem *base; - int i; int ret; clks[IMX6SL_CLK_DUMMY] = imx_clk_fixed("dummy", 0); @@ -426,13 +421,6 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) pr_warn("%s: failed to set AHB clock rate %d!\n", __func__, ret); - /* - * Make sure those always on clocks are enabled to maintain the correct - * usecount and enabling/disabling of parent PLLs. - */ - for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) - clk_prepare_enable(clks[clks_init_on[i]]); - if (IS_ENABLED(CONFIG_USB_MXS_PHY)) { clk_prepare_enable(clks[IMX6SL_CLK_USBPHY1_GATE]); clk_prepare_enable(clks[IMX6SL_CLK_USBPHY2_GATE]); -- 2.7.4 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 2/4] clk: imx6sl: remove clks_init_on array @ 2018-06-03 3:00 ` Anson Huang 0 siblings, 0 replies; 28+ messages in thread From: Anson Huang @ 2018-06-03 3:00 UTC (permalink / raw) To: linux-arm-kernel Clock framework will enable those clocks registered with CLK_IS_CRITICAL flag, so no need to have clks_init_on array during clock initialization now. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> --- drivers/clk/imx/clk-imx6sl.c | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/drivers/clk/imx/clk-imx6sl.c b/drivers/clk/imx/clk-imx6sl.c index 66b1dd1..eb6bcbf 100644 --- a/drivers/clk/imx/clk-imx6sl.c +++ b/drivers/clk/imx/clk-imx6sl.c @@ -104,10 +104,6 @@ static struct clk_onecell_data clk_data; static void __iomem *ccm_base; static void __iomem *anatop_base; -static const u32 clks_init_on[] __initconst = { - IMX6SL_CLK_IPG, IMX6SL_CLK_ARM, IMX6SL_CLK_MMDC_ROOT, -}; - /* * ERR005311 CCM: After exit from WAIT mode, unwanted interrupt(s) taken * during WAIT mode entry process could cause cache memory @@ -195,7 +191,6 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) { struct device_node *np; void __iomem *base; - int i; int ret; clks[IMX6SL_CLK_DUMMY] = imx_clk_fixed("dummy", 0); @@ -426,13 +421,6 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) pr_warn("%s: failed to set AHB clock rate %d!\n", __func__, ret); - /* - * Make sure those always on clocks are enabled to maintain the correct - * usecount and enabling/disabling of parent PLLs. - */ - for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) - clk_prepare_enable(clks[clks_init_on[i]]); - if (IS_ENABLED(CONFIG_USB_MXS_PHY)) { clk_prepare_enable(clks[IMX6SL_CLK_USBPHY1_GATE]); clk_prepare_enable(clks[IMX6SL_CLK_USBPHY2_GATE]); -- 2.7.4 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* Re: [PATCH 2/4] clk: imx6sl: remove clks_init_on array 2018-06-03 3:00 ` Anson Huang @ 2018-06-03 12:17 ` Fabio Estevam -1 siblings, 0 replies; 28+ messages in thread From: Fabio Estevam @ 2018-06-03 12:17 UTC (permalink / raw) To: Anson Huang Cc: Shawn Guo, Sascha Hauer, Fabio Estevam, Michael Turquette, Stephen Boyd, NXP Linux Team, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE, linux-clk, linux-kernel Hi Anson, On Sun, Jun 3, 2018 at 12:00 AM, Anson Huang <Anson.Huang@nxp.com> wrote: > Clock framework will enable those clocks registered > with CLK_IS_CRITICAL flag, so no need to have > clks_init_on array during clock initialization now. > > Signed-off-by: Anson Huang <Anson.Huang@nxp.com> > --- > drivers/clk/imx/clk-imx6sl.c | 12 ------------ > 1 file changed, 12 deletions(-) > > diff --git a/drivers/clk/imx/clk-imx6sl.c b/drivers/clk/imx/clk-imx6sl.c > index 66b1dd1..eb6bcbf 100644 > --- a/drivers/clk/imx/clk-imx6sl.c > +++ b/drivers/clk/imx/clk-imx6sl.c > @@ -104,10 +104,6 @@ static struct clk_onecell_data clk_data; > static void __iomem *ccm_base; > static void __iomem *anatop_base; > > -static const u32 clks_init_on[] __initconst = { > - IMX6SL_CLK_IPG, IMX6SL_CLK_ARM, IMX6SL_CLK_MMDC_ROOT, > -}; It looks like you missed to pass the CLK_IS_CRITICAL flag to these clocks. ^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 2/4] clk: imx6sl: remove clks_init_on array @ 2018-06-03 12:17 ` Fabio Estevam 0 siblings, 0 replies; 28+ messages in thread From: Fabio Estevam @ 2018-06-03 12:17 UTC (permalink / raw) To: linux-arm-kernel Hi Anson, On Sun, Jun 3, 2018 at 12:00 AM, Anson Huang <Anson.Huang@nxp.com> wrote: > Clock framework will enable those clocks registered > with CLK_IS_CRITICAL flag, so no need to have > clks_init_on array during clock initialization now. > > Signed-off-by: Anson Huang <Anson.Huang@nxp.com> > --- > drivers/clk/imx/clk-imx6sl.c | 12 ------------ > 1 file changed, 12 deletions(-) > > diff --git a/drivers/clk/imx/clk-imx6sl.c b/drivers/clk/imx/clk-imx6sl.c > index 66b1dd1..eb6bcbf 100644 > --- a/drivers/clk/imx/clk-imx6sl.c > +++ b/drivers/clk/imx/clk-imx6sl.c > @@ -104,10 +104,6 @@ static struct clk_onecell_data clk_data; > static void __iomem *ccm_base; > static void __iomem *anatop_base; > > -static const u32 clks_init_on[] __initconst = { > - IMX6SL_CLK_IPG, IMX6SL_CLK_ARM, IMX6SL_CLK_MMDC_ROOT, > -}; It looks like you missed to pass the CLK_IS_CRITICAL flag to these clocks. ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 2/4] clk: imx6sl: remove clks_init_on array 2018-06-03 12:17 ` Fabio Estevam (?) @ 2018-06-03 12:45 ` Anson Huang -1 siblings, 0 replies; 28+ messages in thread From: Anson Huang @ 2018-06-03 12:45 UTC (permalink / raw) To: Fabio Estevam Cc: Shawn Guo, Sascha Hauer, Fabio Estevam, Michael Turquette, Stephen Boyd, dl-linux-imx, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE, linux-clk, linux-kernel Hi, Fabio >From Anson's iPhone 6 > 在 2018年6月3日，20:17，Fabio Estevam <festevam@gmail.com> 写道： > > Hi Anson, > >> On Sun, Jun 3, 2018 at 12:00 AM, Anson Huang <Anson.Huang@nxp.com> wrote: >> Clock framework will enable those clocks registered >> with CLK_IS_CRITICAL flag, so no need to have >> clks_init_on array during clock initialization now. >> >> Signed-off-by: Anson Huang <Anson.Huang@nxp.com> >> --- >> drivers/clk/imx/clk-imx6sl.c | 12 ------------ >> 1 file changed, 12 deletions(-) >> >> diff --git a/drivers/clk/imx/clk-imx6sl.c b/drivers/clk/imx/clk-imx6sl.c >> index 66b1dd1..eb6bcbf 100644 >> --- a/drivers/clk/imx/clk-imx6sl.c >> +++ b/drivers/clk/imx/clk-imx6sl.c >> @@ -104,10 +104,6 @@ static struct clk_onecell_data clk_data; >> static void __iomem *ccm_base; >> static void __iomem *anatop_base; >> >> -static const u32 clks_init_on[] __initconst = { >> - IMX6SL_CLK_IPG, IMX6SL_CLK_ARM, IMX6SL_CLK_MMDC_ROOT, >> -}; > > It looks like you missed to pass the CLK_IS_CRITICAL flag to these clocks. The ARM and mmdc root are busy divider, the CLK_IS_CRITICAL flag is included by default when busy divider is registered. IPG’parent is AHB which is also a busy divider. And IPG itself has no gate, no need to add flag. Anson. ^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 2/4] clk: imx6sl: remove clks_init_on array @ 2018-06-03 12:45 ` Anson Huang 0 siblings, 0 replies; 28+ messages in thread From: Anson Huang @ 2018-06-03 12:45 UTC (permalink / raw) To: linux-arm-kernel Hi, Fabio >From Anson's iPhone 6 > ? 2018?6?3??20:17?Fabio Estevam <festevam@gmail.com> ??? > > Hi Anson, > >> On Sun, Jun 3, 2018 at 12:00 AM, Anson Huang <Anson.Huang@nxp.com> wrote: >> Clock framework will enable those clocks registered >> with CLK_IS_CRITICAL flag, so no need to have >> clks_init_on array during clock initialization now. >> >> Signed-off-by: Anson Huang <Anson.Huang@nxp.com> >> --- >> drivers/clk/imx/clk-imx6sl.c | 12 ------------ >> 1 file changed, 12 deletions(-) >> >> diff --git a/drivers/clk/imx/clk-imx6sl.c b/drivers/clk/imx/clk-imx6sl.c >> index 66b1dd1..eb6bcbf 100644 >> --- a/drivers/clk/imx/clk-imx6sl.c >> +++ b/drivers/clk/imx/clk-imx6sl.c >> @@ -104,10 +104,6 @@ static struct clk_onecell_data clk_data; >> static void __iomem *ccm_base; >> static void __iomem *anatop_base; >> >> -static const u32 clks_init_on[] __initconst = { >> - IMX6SL_CLK_IPG, IMX6SL_CLK_ARM, IMX6SL_CLK_MMDC_ROOT, >> -}; > > It looks like you missed to pass the CLK_IS_CRITICAL flag to these clocks. The ARM and mmdc root are busy divider, the CLK_IS_CRITICAL flag is included by default when busy divider is registered. IPG?parent is AHB which is also a busy divider. And IPG itself has no gate, no need to add flag. Anson. ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 2/4] clk: imx6sl: remove clks_init_on array @ 2018-06-03 12:45 ` Anson Huang 0 siblings, 0 replies; 28+ messages in thread From: Anson Huang @ 2018-06-03 12:45 UTC (permalink / raw) To: Fabio Estevam Cc: Shawn Guo, Sascha Hauer, Fabio Estevam, Michael Turquette, Stephen Boyd, dl-linux-imx, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE, linux-clk, linux-kernel SGksIEZhYmlvDQoNCkZyb20gQW5zb24ncyBpUGhvbmUgNg0KDQoNCj4g5ZyoIDIwMTjlubQ25pyI M+aXpe+8jDIwOjE377yMRmFiaW8gRXN0ZXZhbSA8ZmVzdGV2YW1AZ21haWwuY29tPiDlhpnpgZPv vJoNCj4gDQo+IEhpIEFuc29uLA0KPiANCj4+IE9uIFN1biwgSnVuIDMsIDIwMTggYXQgMTI6MDAg QU0sIEFuc29uIEh1YW5nIDxBbnNvbi5IdWFuZ0BueHAuY29tPiB3cm90ZToNCj4+IENsb2NrIGZy YW1ld29yayB3aWxsIGVuYWJsZSB0aG9zZSBjbG9ja3MgcmVnaXN0ZXJlZA0KPj4gd2l0aCBDTEtf SVNfQ1JJVElDQUwgZmxhZywgc28gbm8gbmVlZCB0byBoYXZlDQo+PiBjbGtzX2luaXRfb24gYXJy YXkgZHVyaW5nIGNsb2NrIGluaXRpYWxpemF0aW9uIG5vdy4NCj4+IA0KPj4gU2lnbmVkLW9mZi1i eTogQW5zb24gSHVhbmcgPEFuc29uLkh1YW5nQG54cC5jb20+DQo+PiAtLS0NCj4+IGRyaXZlcnMv Y2xrL2lteC9jbGstaW14NnNsLmMgfCAxMiAtLS0tLS0tLS0tLS0NCj4+IDEgZmlsZSBjaGFuZ2Vk LCAxMiBkZWxldGlvbnMoLSkNCj4+IA0KPj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvY2xrL2lteC9j bGstaW14NnNsLmMgYi9kcml2ZXJzL2Nsay9pbXgvY2xrLWlteDZzbC5jDQo+PiBpbmRleCA2NmIx ZGQxLi5lYjZiY2JmIDEwMDY0NA0KPj4gLS0tIGEvZHJpdmVycy9jbGsvaW14L2Nsay1pbXg2c2wu Yw0KPj4gKysrIGIvZHJpdmVycy9jbGsvaW14L2Nsay1pbXg2c2wuYw0KPj4gQEAgLTEwNCwxMCAr MTA0LDYgQEAgc3RhdGljIHN0cnVjdCBjbGtfb25lY2VsbF9kYXRhIGNsa19kYXRhOw0KPj4gc3Rh dGljIHZvaWQgX19pb21lbSAqY2NtX2Jhc2U7DQo+PiBzdGF0aWMgdm9pZCBfX2lvbWVtICphbmF0 b3BfYmFzZTsNCj4+IA0KPj4gLXN0YXRpYyBjb25zdCB1MzIgY2xrc19pbml0X29uW10gX19pbml0 Y29uc3QgPSB7DQo+PiAtICAgICAgIElNWDZTTF9DTEtfSVBHLCBJTVg2U0xfQ0xLX0FSTSwgSU1Y NlNMX0NMS19NTURDX1JPT1QsDQo+PiAtfTsNCj4gDQo+IEl0IGxvb2tzIGxpa2UgeW91IG1pc3Nl ZCB0byBwYXNzIHRoZSBDTEtfSVNfQ1JJVElDQUwgZmxhZyB0byB0aGVzZSBjbG9ja3MuDQoNClRo ZSBBUk0gYW5kIG1tZGMgcm9vdCBhcmUgYnVzeSBkaXZpZGVyLCB0aGUgQ0xLX0lTX0NSSVRJQ0FM IGZsYWcgaXMgaW5jbHVkZWQgYnkgZGVmYXVsdCB3aGVuIGJ1c3kgZGl2aWRlciBpcyByZWdpc3Rl cmVkLiBJUEfigJlwYXJlbnQgaXMgQUhCIHdoaWNoIGlzIGFsc28gYSBidXN5IGRpdmlkZXIuIEFu ZCBJUEcgaXRzZWxmIGhhcyBubyBnYXRlLCBubyBuZWVkIHRvIGFkZCBmbGFnLg0KDQpBbnNvbi4= ^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 3/4] clk: imx6sx: remove clks_init_on array 2018-06-03 3:00 ` Anson Huang @ 2018-06-03 3:00 ` Anson Huang -1 siblings, 0 replies; 28+ messages in thread From: Anson Huang @ 2018-06-03 3:00 UTC (permalink / raw) To: shawnguo, kernel, fabio.estevam, mturquette, sboyd Cc: Linux-imx, linux-arm-kernel, linux-clk, linux-kernel Clock framework will enable those clocks registered with CLK_IS_CRITICAL flag, so no need to have clks_init_on array during clock initialization now. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> --- drivers/clk/imx/clk-imx6sx.c | 40 ++++++++++++++-------------------------- 1 file changed, 14 insertions(+), 26 deletions(-) diff --git a/drivers/clk/imx/clk-imx6sx.c b/drivers/clk/imx/clk-imx6sx.c index 10c771b..aed4391 100644 --- a/drivers/clk/imx/clk-imx6sx.c +++ b/drivers/clk/imx/clk-imx6sx.c @@ -92,14 +92,6 @@ static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", }; static struct clk *clks[IMX6SX_CLK_CLK_END]; static struct clk_onecell_data clk_data; -static int const clks_init_on[] __initconst = { - IMX6SX_CLK_AIPS_TZ1, IMX6SX_CLK_AIPS_TZ2, IMX6SX_CLK_AIPS_TZ3, - IMX6SX_CLK_IPMUX1, IMX6SX_CLK_IPMUX2, IMX6SX_CLK_IPMUX3, - IMX6SX_CLK_WAKEUP, IMX6SX_CLK_MMDC_P0_FAST, IMX6SX_CLK_MMDC_P0_IPG, - IMX6SX_CLK_ROM, IMX6SX_CLK_ARM, IMX6SX_CLK_IPG, IMX6SX_CLK_OCRAM, - IMX6SX_CLK_PER2_MAIN, IMX6SX_CLK_PERCLK, IMX6SX_CLK_TZASC1, -}; - static const struct clk_div_table clk_enet_ref_table[] = { { .val = 0, .div = 20, }, { .val = 1, .div = 10, }, @@ -142,7 +134,6 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) { struct device_node *np; void __iomem *base; - int i; clks[IMX6SX_CLK_DUMMY] = imx_clk_fixed("dummy", 0); @@ -332,7 +323,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) clks[IMX6SX_CLK_QSPI1_PODF] = imx_clk_divider("qspi1_podf", "qspi1_sel", base + 0x1c, 26, 3); clks[IMX6SX_CLK_EIM_SLOW_PODF] = imx_clk_divider("eim_slow_podf", "eim_slow_sel", base + 0x1c, 23, 3); clks[IMX6SX_CLK_LCDIF2_PODF] = imx_clk_divider("lcdif2_podf", "lcdif2_pred", base + 0x1c, 20, 3); - clks[IMX6SX_CLK_PERCLK] = imx_clk_divider("perclk", "perclk_sel", base + 0x1c, 0, 6); + clks[IMX6SX_CLK_PERCLK] = imx_clk_divider_flags("perclk", "perclk_sel", base + 0x1c, 0, 6, CLK_IS_CRITICAL); clks[IMX6SX_CLK_VID_PODF] = imx_clk_divider("vid_podf", "vid_sel", base + 0x20, 24, 2); clks[IMX6SX_CLK_CAN_PODF] = imx_clk_divider("can_podf", "can_sel", base + 0x20, 2, 6); clks[IMX6SX_CLK_USDHC4_PODF] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3); @@ -380,8 +371,8 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) /* name parent_name reg shift */ /* CCGR0 */ - clks[IMX6SX_CLK_AIPS_TZ1] = imx_clk_gate2("aips_tz1", "ahb", base + 0x68, 0); - clks[IMX6SX_CLK_AIPS_TZ2] = imx_clk_gate2("aips_tz2", "ahb", base + 0x68, 2); + clks[IMX6SX_CLK_AIPS_TZ1] = imx_clk_gate2_flags("aips_tz1", "ahb", base + 0x68, 0, CLK_IS_CRITICAL); + clks[IMX6SX_CLK_AIPS_TZ2] = imx_clk_gate2_flags("aips_tz2", "ahb", base + 0x68, 2, CLK_IS_CRITICAL); clks[IMX6SX_CLK_APBH_DMA] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4); clks[IMX6SX_CLK_ASRC_MEM] = imx_clk_gate2_shared("asrc_mem", "ahb", base + 0x68, 6, &share_count_asrc); clks[IMX6SX_CLK_ASRC_IPG] = imx_clk_gate2_shared("asrc_ipg", "ahb", base + 0x68, 6, &share_count_asrc); @@ -394,7 +385,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) clks[IMX6SX_CLK_CAN2_SERIAL] = imx_clk_gate2("can2_serial", "can_podf", base + 0x68, 20); clks[IMX6SX_CLK_DCIC1] = imx_clk_gate2("dcic1", "display_podf", base + 0x68, 24); clks[IMX6SX_CLK_DCIC2] = imx_clk_gate2("dcic2", "display_podf", base + 0x68, 26); - clks[IMX6SX_CLK_AIPS_TZ3] = imx_clk_gate2("aips_tz3", "ahb", base + 0x68, 30); + clks[IMX6SX_CLK_AIPS_TZ3] = imx_clk_gate2_flags("aips_tz3", "ahb", base + 0x68, 30, CLK_IS_CRITICAL); /* CCGR1 */ clks[IMX6SX_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_podf", base + 0x6c, 0); @@ -407,7 +398,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) clks[IMX6SX_CLK_ESAI_EXTAL] = imx_clk_gate2_shared("esai_extal", "esai_podf", base + 0x6c, 16, &share_count_esai); clks[IMX6SX_CLK_ESAI_IPG] = imx_clk_gate2_shared("esai_ipg", "ahb", base + 0x6c, 16, &share_count_esai); clks[IMX6SX_CLK_ESAI_MEM] = imx_clk_gate2_shared("esai_mem", "ahb", base + 0x6c, 16, &share_count_esai); - clks[IMX6SX_CLK_WAKEUP] = imx_clk_gate2("wakeup", "ipg", base + 0x6c, 18); + clks[IMX6SX_CLK_WAKEUP] = imx_clk_gate2_flags("wakeup", "ipg", base + 0x6c, 18, CLK_IS_CRITICAL); clks[IMX6SX_CLK_GPT_BUS] = imx_clk_gate2("gpt_bus", "perclk", base + 0x6c, 20); clks[IMX6SX_CLK_GPT_SERIAL] = imx_clk_gate2("gpt_serial", "perclk", base + 0x6c, 22); clks[IMX6SX_CLK_GPU] = imx_clk_gate2("gpu", "gpu_core_podf", base + 0x6c, 26); @@ -420,10 +411,10 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) clks[IMX6SX_CLK_I2C3] = imx_clk_gate2("i2c3", "perclk", base + 0x70, 10); clks[IMX6SX_CLK_OCOTP] = imx_clk_gate2("ocotp", "ipg", base + 0x70, 12); clks[IMX6SX_CLK_IOMUXC] = imx_clk_gate2("iomuxc", "lcdif1_podf", base + 0x70, 14); - clks[IMX6SX_CLK_IPMUX1] = imx_clk_gate2("ipmux1", "ahb", base + 0x70, 16); - clks[IMX6SX_CLK_IPMUX2] = imx_clk_gate2("ipmux2", "ahb", base + 0x70, 18); - clks[IMX6SX_CLK_IPMUX3] = imx_clk_gate2("ipmux3", "ahb", base + 0x70, 20); - clks[IMX6SX_CLK_TZASC1] = imx_clk_gate2("tzasc1", "mmdc_podf", base + 0x70, 22); + clks[IMX6SX_CLK_IPMUX1] = imx_clk_gate2_flags("ipmux1", "ahb", base + 0x70, 16, CLK_IS_CRITICAL); + clks[IMX6SX_CLK_IPMUX2] = imx_clk_gate2_flags("ipmux2", "ahb", base + 0x70, 18, CLK_IS_CRITICAL); + clks[IMX6SX_CLK_IPMUX3] = imx_clk_gate2_flags("ipmux3", "ahb", base + 0x70, 20, CLK_IS_CRITICAL); + clks[IMX6SX_CLK_TZASC1] = imx_clk_gate2_flags("tzasc1", "mmdc_podf", base + 0x70, 22, CLK_IS_CRITICAL); clks[IMX6SX_CLK_LCDIF_APB] = imx_clk_gate2("lcdif_apb", "display_podf", base + 0x70, 28); clks[IMX6SX_CLK_PXP_AXI] = imx_clk_gate2("pxp_axi", "display_podf", base + 0x70, 30); @@ -437,15 +428,15 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) clks[IMX6SX_CLK_LDB_DI0] = imx_clk_gate2("ldb_di0", "ldb_di0_div_sel", base + 0x74, 12); clks[IMX6SX_CLK_QSPI1] = imx_clk_gate2("qspi1", "qspi1_podf", base + 0x74, 14); clks[IMX6SX_CLK_MLB] = imx_clk_gate2("mlb", "ahb", base + 0x74, 18); - clks[IMX6SX_CLK_MMDC_P0_FAST] = imx_clk_gate2("mmdc_p0_fast", "mmdc_podf", base + 0x74, 20); - clks[IMX6SX_CLK_MMDC_P0_IPG] = imx_clk_gate2("mmdc_p0_ipg", "ipg", base + 0x74, 24); - clks[IMX6SX_CLK_OCRAM] = imx_clk_gate2("ocram", "ocram_podf", base + 0x74, 28); + clks[IMX6SX_CLK_MMDC_P0_FAST] = imx_clk_gate2_flags("mmdc_p0_fast", "mmdc_podf", base + 0x74, 20, CLK_IS_CRITICAL); + clks[IMX6SX_CLK_MMDC_P0_IPG] = imx_clk_gate2_flags("mmdc_p0_ipg", "ipg", base + 0x74, 24, CLK_IS_CRITICAL); + clks[IMX6SX_CLK_OCRAM] = imx_clk_gate2_flags("ocram", "ocram_podf", base + 0x74, 28, CLK_IS_CRITICAL); /* CCGR4 */ clks[IMX6SX_CLK_PCIE_AXI] = imx_clk_gate2("pcie_axi", "display_podf", base + 0x78, 0); clks[IMX6SX_CLK_QSPI2] = imx_clk_gate2("qspi2", "qspi2_podf", base + 0x78, 10); clks[IMX6SX_CLK_PER1_BCH] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12); - clks[IMX6SX_CLK_PER2_MAIN] = imx_clk_gate2("per2_main", "ahb", base + 0x78, 14); + clks[IMX6SX_CLK_PER2_MAIN] = imx_clk_gate2_flags("per2_main", "ahb", base + 0x78, 14, CLK_IS_CRITICAL); clks[IMX6SX_CLK_PWM1] = imx_clk_gate2("pwm1", "perclk", base + 0x78, 16); clks[IMX6SX_CLK_PWM2] = imx_clk_gate2("pwm2", "perclk", base + 0x78, 18); clks[IMX6SX_CLK_PWM3] = imx_clk_gate2("pwm3", "perclk", base + 0x78, 20); @@ -456,7 +447,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) clks[IMX6SX_CLK_GPMI_APB] = imx_clk_gate2("gpmi_apb", "usdhc3", base + 0x78, 30); /* CCGR5 */ - clks[IMX6SX_CLK_ROM] = imx_clk_gate2("rom", "ahb", base + 0x7c, 0); + clks[IMX6SX_CLK_ROM] = imx_clk_gate2_flags("rom", "ahb", base + 0x7c, 0, CLK_IS_CRITICAL); clks[IMX6SX_CLK_SDMA] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6); clks[IMX6SX_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12); clks[IMX6SX_CLK_AUDIO] = imx_clk_gate2_shared("audio", "audio_podf", base + 0x7c, 14, &share_count_audio); @@ -502,9 +493,6 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) clk_data.clk_num = ARRAY_SIZE(clks); of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); - for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) - clk_prepare_enable(clks[clks_init_on[i]]); - if (IS_ENABLED(CONFIG_USB_MXS_PHY)) { clk_prepare_enable(clks[IMX6SX_CLK_USBPHY1_GATE]); clk_prepare_enable(clks[IMX6SX_CLK_USBPHY2_GATE]); -- 2.7.4 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 3/4] clk: imx6sx: remove clks_init_on array @ 2018-06-03 3:00 ` Anson Huang 0 siblings, 0 replies; 28+ messages in thread From: Anson Huang @ 2018-06-03 3:00 UTC (permalink / raw) To: linux-arm-kernel Clock framework will enable those clocks registered with CLK_IS_CRITICAL flag, so no need to have clks_init_on array during clock initialization now. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> --- drivers/clk/imx/clk-imx6sx.c | 40 ++++++++++++++-------------------------- 1 file changed, 14 insertions(+), 26 deletions(-) diff --git a/drivers/clk/imx/clk-imx6sx.c b/drivers/clk/imx/clk-imx6sx.c index 10c771b..aed4391 100644 --- a/drivers/clk/imx/clk-imx6sx.c +++ b/drivers/clk/imx/clk-imx6sx.c @@ -92,14 +92,6 @@ static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", }; static struct clk *clks[IMX6SX_CLK_CLK_END]; static struct clk_onecell_data clk_data; -static int const clks_init_on[] __initconst = { - IMX6SX_CLK_AIPS_TZ1, IMX6SX_CLK_AIPS_TZ2, IMX6SX_CLK_AIPS_TZ3, - IMX6SX_CLK_IPMUX1, IMX6SX_CLK_IPMUX2, IMX6SX_CLK_IPMUX3, - IMX6SX_CLK_WAKEUP, IMX6SX_CLK_MMDC_P0_FAST, IMX6SX_CLK_MMDC_P0_IPG, - IMX6SX_CLK_ROM, IMX6SX_CLK_ARM, IMX6SX_CLK_IPG, IMX6SX_CLK_OCRAM, - IMX6SX_CLK_PER2_MAIN, IMX6SX_CLK_PERCLK, IMX6SX_CLK_TZASC1, -}; - static const struct clk_div_table clk_enet_ref_table[] = { { .val = 0, .div = 20, }, { .val = 1, .div = 10, }, @@ -142,7 +134,6 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) { struct device_node *np; void __iomem *base; - int i; clks[IMX6SX_CLK_DUMMY] = imx_clk_fixed("dummy", 0); @@ -332,7 +323,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) clks[IMX6SX_CLK_QSPI1_PODF] = imx_clk_divider("qspi1_podf", "qspi1_sel", base + 0x1c, 26, 3); clks[IMX6SX_CLK_EIM_SLOW_PODF] = imx_clk_divider("eim_slow_podf", "eim_slow_sel", base + 0x1c, 23, 3); clks[IMX6SX_CLK_LCDIF2_PODF] = imx_clk_divider("lcdif2_podf", "lcdif2_pred", base + 0x1c, 20, 3); - clks[IMX6SX_CLK_PERCLK] = imx_clk_divider("perclk", "perclk_sel", base + 0x1c, 0, 6); + clks[IMX6SX_CLK_PERCLK] = imx_clk_divider_flags("perclk", "perclk_sel", base + 0x1c, 0, 6, CLK_IS_CRITICAL); clks[IMX6SX_CLK_VID_PODF] = imx_clk_divider("vid_podf", "vid_sel", base + 0x20, 24, 2); clks[IMX6SX_CLK_CAN_PODF] = imx_clk_divider("can_podf", "can_sel", base + 0x20, 2, 6); clks[IMX6SX_CLK_USDHC4_PODF] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3); @@ -380,8 +371,8 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) /* name parent_name reg shift */ /* CCGR0 */ - clks[IMX6SX_CLK_AIPS_TZ1] = imx_clk_gate2("aips_tz1", "ahb", base + 0x68, 0); - clks[IMX6SX_CLK_AIPS_TZ2] = imx_clk_gate2("aips_tz2", "ahb", base + 0x68, 2); + clks[IMX6SX_CLK_AIPS_TZ1] = imx_clk_gate2_flags("aips_tz1", "ahb", base + 0x68, 0, CLK_IS_CRITICAL); + clks[IMX6SX_CLK_AIPS_TZ2] = imx_clk_gate2_flags("aips_tz2", "ahb", base + 0x68, 2, CLK_IS_CRITICAL); clks[IMX6SX_CLK_APBH_DMA] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4); clks[IMX6SX_CLK_ASRC_MEM] = imx_clk_gate2_shared("asrc_mem", "ahb", base + 0x68, 6, &share_count_asrc); clks[IMX6SX_CLK_ASRC_IPG] = imx_clk_gate2_shared("asrc_ipg", "ahb", base + 0x68, 6, &share_count_asrc); @@ -394,7 +385,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) clks[IMX6SX_CLK_CAN2_SERIAL] = imx_clk_gate2("can2_serial", "can_podf", base + 0x68, 20); clks[IMX6SX_CLK_DCIC1] = imx_clk_gate2("dcic1", "display_podf", base + 0x68, 24); clks[IMX6SX_CLK_DCIC2] = imx_clk_gate2("dcic2", "display_podf", base + 0x68, 26); - clks[IMX6SX_CLK_AIPS_TZ3] = imx_clk_gate2("aips_tz3", "ahb", base + 0x68, 30); + clks[IMX6SX_CLK_AIPS_TZ3] = imx_clk_gate2_flags("aips_tz3", "ahb", base + 0x68, 30, CLK_IS_CRITICAL); /* CCGR1 */ clks[IMX6SX_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_podf", base + 0x6c, 0); @@ -407,7 +398,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) clks[IMX6SX_CLK_ESAI_EXTAL] = imx_clk_gate2_shared("esai_extal", "esai_podf", base + 0x6c, 16, &share_count_esai); clks[IMX6SX_CLK_ESAI_IPG] = imx_clk_gate2_shared("esai_ipg", "ahb", base + 0x6c, 16, &share_count_esai); clks[IMX6SX_CLK_ESAI_MEM] = imx_clk_gate2_shared("esai_mem", "ahb", base + 0x6c, 16, &share_count_esai); - clks[IMX6SX_CLK_WAKEUP] = imx_clk_gate2("wakeup", "ipg", base + 0x6c, 18); + clks[IMX6SX_CLK_WAKEUP] = imx_clk_gate2_flags("wakeup", "ipg", base + 0x6c, 18, CLK_IS_CRITICAL); clks[IMX6SX_CLK_GPT_BUS] = imx_clk_gate2("gpt_bus", "perclk", base + 0x6c, 20); clks[IMX6SX_CLK_GPT_SERIAL] = imx_clk_gate2("gpt_serial", "perclk", base + 0x6c, 22); clks[IMX6SX_CLK_GPU] = imx_clk_gate2("gpu", "gpu_core_podf", base + 0x6c, 26); @@ -420,10 +411,10 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) clks[IMX6SX_CLK_I2C3] = imx_clk_gate2("i2c3", "perclk", base + 0x70, 10); clks[IMX6SX_CLK_OCOTP] = imx_clk_gate2("ocotp", "ipg", base + 0x70, 12); clks[IMX6SX_CLK_IOMUXC] = imx_clk_gate2("iomuxc", "lcdif1_podf", base + 0x70, 14); - clks[IMX6SX_CLK_IPMUX1] = imx_clk_gate2("ipmux1", "ahb", base + 0x70, 16); - clks[IMX6SX_CLK_IPMUX2] = imx_clk_gate2("ipmux2", "ahb", base + 0x70, 18); - clks[IMX6SX_CLK_IPMUX3] = imx_clk_gate2("ipmux3", "ahb", base + 0x70, 20); - clks[IMX6SX_CLK_TZASC1] = imx_clk_gate2("tzasc1", "mmdc_podf", base + 0x70, 22); + clks[IMX6SX_CLK_IPMUX1] = imx_clk_gate2_flags("ipmux1", "ahb", base + 0x70, 16, CLK_IS_CRITICAL); + clks[IMX6SX_CLK_IPMUX2] = imx_clk_gate2_flags("ipmux2", "ahb", base + 0x70, 18, CLK_IS_CRITICAL); + clks[IMX6SX_CLK_IPMUX3] = imx_clk_gate2_flags("ipmux3", "ahb", base + 0x70, 20, CLK_IS_CRITICAL); + clks[IMX6SX_CLK_TZASC1] = imx_clk_gate2_flags("tzasc1", "mmdc_podf", base + 0x70, 22, CLK_IS_CRITICAL); clks[IMX6SX_CLK_LCDIF_APB] = imx_clk_gate2("lcdif_apb", "display_podf", base + 0x70, 28); clks[IMX6SX_CLK_PXP_AXI] = imx_clk_gate2("pxp_axi", "display_podf", base + 0x70, 30); @@ -437,15 +428,15 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) clks[IMX6SX_CLK_LDB_DI0] = imx_clk_gate2("ldb_di0", "ldb_di0_div_sel", base + 0x74, 12); clks[IMX6SX_CLK_QSPI1] = imx_clk_gate2("qspi1", "qspi1_podf", base + 0x74, 14); clks[IMX6SX_CLK_MLB] = imx_clk_gate2("mlb", "ahb", base + 0x74, 18); - clks[IMX6SX_CLK_MMDC_P0_FAST] = imx_clk_gate2("mmdc_p0_fast", "mmdc_podf", base + 0x74, 20); - clks[IMX6SX_CLK_MMDC_P0_IPG] = imx_clk_gate2("mmdc_p0_ipg", "ipg", base + 0x74, 24); - clks[IMX6SX_CLK_OCRAM] = imx_clk_gate2("ocram", "ocram_podf", base + 0x74, 28); + clks[IMX6SX_CLK_MMDC_P0_FAST] = imx_clk_gate2_flags("mmdc_p0_fast", "mmdc_podf", base + 0x74, 20, CLK_IS_CRITICAL); + clks[IMX6SX_CLK_MMDC_P0_IPG] = imx_clk_gate2_flags("mmdc_p0_ipg", "ipg", base + 0x74, 24, CLK_IS_CRITICAL); + clks[IMX6SX_CLK_OCRAM] = imx_clk_gate2_flags("ocram", "ocram_podf", base + 0x74, 28, CLK_IS_CRITICAL); /* CCGR4 */ clks[IMX6SX_CLK_PCIE_AXI] = imx_clk_gate2("pcie_axi", "display_podf", base + 0x78, 0); clks[IMX6SX_CLK_QSPI2] = imx_clk_gate2("qspi2", "qspi2_podf", base + 0x78, 10); clks[IMX6SX_CLK_PER1_BCH] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12); - clks[IMX6SX_CLK_PER2_MAIN] = imx_clk_gate2("per2_main", "ahb", base + 0x78, 14); + clks[IMX6SX_CLK_PER2_MAIN] = imx_clk_gate2_flags("per2_main", "ahb", base + 0x78, 14, CLK_IS_CRITICAL); clks[IMX6SX_CLK_PWM1] = imx_clk_gate2("pwm1", "perclk", base + 0x78, 16); clks[IMX6SX_CLK_PWM2] = imx_clk_gate2("pwm2", "perclk", base + 0x78, 18); clks[IMX6SX_CLK_PWM3] = imx_clk_gate2("pwm3", "perclk", base + 0x78, 20); @@ -456,7 +447,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) clks[IMX6SX_CLK_GPMI_APB] = imx_clk_gate2("gpmi_apb", "usdhc3", base + 0x78, 30); /* CCGR5 */ - clks[IMX6SX_CLK_ROM] = imx_clk_gate2("rom", "ahb", base + 0x7c, 0); + clks[IMX6SX_CLK_ROM] = imx_clk_gate2_flags("rom", "ahb", base + 0x7c, 0, CLK_IS_CRITICAL); clks[IMX6SX_CLK_SDMA] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6); clks[IMX6SX_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12); clks[IMX6SX_CLK_AUDIO] = imx_clk_gate2_shared("audio", "audio_podf", base + 0x7c, 14, &share_count_audio); @@ -502,9 +493,6 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) clk_data.clk_num = ARRAY_SIZE(clks); of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); - for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) - clk_prepare_enable(clks[clks_init_on[i]]); - if (IS_ENABLED(CONFIG_USB_MXS_PHY)) { clk_prepare_enable(clks[IMX6SX_CLK_USBPHY1_GATE]); clk_prepare_enable(clks[IMX6SX_CLK_USBPHY2_GATE]); -- 2.7.4 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* Re: [PATCH 3/4] clk: imx6sx: remove clks_init_on array 2018-06-03 3:00 ` Anson Huang @ 2018-06-03 12:52 ` Fabio Estevam -1 siblings, 0 replies; 28+ messages in thread From: Fabio Estevam @ 2018-06-03 12:52 UTC (permalink / raw) To: Anson Huang Cc: Shawn Guo, Sascha Hauer, Fabio Estevam, Michael Turquette, Stephen Boyd, NXP Linux Team, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE, linux-clk, linux-kernel On Sun, Jun 3, 2018 at 12:00 AM, Anson Huang <Anson.Huang@nxp.com> wrote: > Clock framework will enable those clocks registered > with CLK_IS_CRITICAL flag, so no need to have > clks_init_on array during clock initialization now. > > Signed-off-by: Anson Huang <Anson.Huang@nxp.com> > --- > drivers/clk/imx/clk-imx6sx.c | 40 ++++++++++++++-------------------------- > 1 file changed, 14 insertions(+), 26 deletions(-) > > diff --git a/drivers/clk/imx/clk-imx6sx.c b/drivers/clk/imx/clk-imx6sx.c > index 10c771b..aed4391 100644 > --- a/drivers/clk/imx/clk-imx6sx.c > +++ b/drivers/clk/imx/clk-imx6sx.c > @@ -92,14 +92,6 @@ static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", }; > static struct clk *clks[IMX6SX_CLK_CLK_END]; > static struct clk_onecell_data clk_data; > > -static int const clks_init_on[] __initconst = { > - IMX6SX_CLK_AIPS_TZ1, IMX6SX_CLK_AIPS_TZ2, IMX6SX_CLK_AIPS_TZ3, > - IMX6SX_CLK_IPMUX1, IMX6SX_CLK_IPMUX2, IMX6SX_CLK_IPMUX3, > - IMX6SX_CLK_WAKEUP, IMX6SX_CLK_MMDC_P0_FAST, IMX6SX_CLK_MMDC_P0_IPG, > - IMX6SX_CLK_ROM, IMX6SX_CLK_ARM, IMX6SX_CLK_IPG, IMX6SX_CLK_OCRAM, > - IMX6SX_CLK_PER2_MAIN, IMX6SX_CLK_PERCLK, IMX6SX_CLK_TZASC1, > -}; MX6SX_CLK_ARM and IMX6SX_CLK_IPG did not have the CLK_IS_CRITICAL flag. Is this on purpose? ^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 3/4] clk: imx6sx: remove clks_init_on array @ 2018-06-03 12:52 ` Fabio Estevam 0 siblings, 0 replies; 28+ messages in thread From: Fabio Estevam @ 2018-06-03 12:52 UTC (permalink / raw) To: linux-arm-kernel On Sun, Jun 3, 2018 at 12:00 AM, Anson Huang <Anson.Huang@nxp.com> wrote: > Clock framework will enable those clocks registered > with CLK_IS_CRITICAL flag, so no need to have > clks_init_on array during clock initialization now. > > Signed-off-by: Anson Huang <Anson.Huang@nxp.com> > --- > drivers/clk/imx/clk-imx6sx.c | 40 ++++++++++++++-------------------------- > 1 file changed, 14 insertions(+), 26 deletions(-) > > diff --git a/drivers/clk/imx/clk-imx6sx.c b/drivers/clk/imx/clk-imx6sx.c > index 10c771b..aed4391 100644 > --- a/drivers/clk/imx/clk-imx6sx.c > +++ b/drivers/clk/imx/clk-imx6sx.c > @@ -92,14 +92,6 @@ static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", }; > static struct clk *clks[IMX6SX_CLK_CLK_END]; > static struct clk_onecell_data clk_data; > > -static int const clks_init_on[] __initconst = { > - IMX6SX_CLK_AIPS_TZ1, IMX6SX_CLK_AIPS_TZ2, IMX6SX_CLK_AIPS_TZ3, > - IMX6SX_CLK_IPMUX1, IMX6SX_CLK_IPMUX2, IMX6SX_CLK_IPMUX3, > - IMX6SX_CLK_WAKEUP, IMX6SX_CLK_MMDC_P0_FAST, IMX6SX_CLK_MMDC_P0_IPG, > - IMX6SX_CLK_ROM, IMX6SX_CLK_ARM, IMX6SX_CLK_IPG, IMX6SX_CLK_OCRAM, > - IMX6SX_CLK_PER2_MAIN, IMX6SX_CLK_PERCLK, IMX6SX_CLK_TZASC1, > -}; MX6SX_CLK_ARM and IMX6SX_CLK_IPG did not have the CLK_IS_CRITICAL flag. Is this on purpose? ^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 4/4] clk: imx6ul: remove clks_init_on array 2018-06-03 3:00 ` Anson Huang @ 2018-06-03 3:00 ` Anson Huang -1 siblings, 0 replies; 28+ messages in thread From: Anson Huang @ 2018-06-03 3:00 UTC (permalink / raw) To: shawnguo, kernel, fabio.estevam, mturquette, sboyd Cc: Linux-imx, linux-arm-kernel, linux-clk, linux-kernel Clock framework will enable those clocks registered with CLK_IS_CRITICAL flag, so no need to have clks_init_on array during clock initialization now. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> --- This patch is based on "[V2,1/2] clk: imx6ul: add GPIO clock gates". drivers/clk/imx/clk-imx6ul.c | 23 ++++++----------------- 1 file changed, 6 insertions(+), 17 deletions(-) diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c index 3ea2d97..d3f7f4d 100644 --- a/drivers/clk/imx/clk-imx6ul.c +++ b/drivers/clk/imx/clk-imx6ul.c @@ -79,12 +79,6 @@ static const char *cko_sels[] = { "cko1", "cko2", }; static struct clk *clks[IMX6UL_CLK_END]; static struct clk_onecell_data clk_data; -static int const clks_init_on[] __initconst = { - IMX6UL_CLK_AIPSTZ1, IMX6UL_CLK_AIPSTZ2, - IMX6UL_CLK_AXI, IMX6UL_CLK_ARM, IMX6UL_CLK_ROM, - IMX6UL_CLK_MMDC_P0_FAST, IMX6UL_CLK_MMDC_P0_IPG, -}; - static const struct clk_div_table clk_enet_ref_table[] = { { .val = 0, .div = 20, }, { .val = 1, .div = 10, }, @@ -129,7 +123,6 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) { struct device_node *np; void __iomem *base; - int i; clks[IMX6UL_CLK_DUMMY] = imx_clk_fixed("dummy", 0); @@ -336,8 +329,8 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) clks[IMX6UL_CLK_AHB] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1); /* CCGR0 */ - clks[IMX6UL_CLK_AIPSTZ1] = imx_clk_gate2("aips_tz1", "ahb", base + 0x68, 0); - clks[IMX6UL_CLK_AIPSTZ2] = imx_clk_gate2("aips_tz2", "ahb", base + 0x68, 2); + clks[IMX6UL_CLK_AIPSTZ1] = imx_clk_gate2_flags("aips_tz1", "ahb", base + 0x68, 0, CLK_IS_CRITICAL); + clks[IMX6UL_CLK_AIPSTZ2] = imx_clk_gate2_flags("aips_tz2", "ahb", base + 0x68, 2, CLK_IS_CRITICAL); clks[IMX6UL_CLK_APBHDMA] = imx_clk_gate2("apbh_dma", "bch_podf", base + 0x68, 4); clks[IMX6UL_CLK_ASRC_IPG] = imx_clk_gate2_shared("asrc_ipg", "ahb", base + 0x68, 6, &share_count_asrc); clks[IMX6UL_CLK_ASRC_MEM] = imx_clk_gate2_shared("asrc_mem", "ahb", base + 0x68, 6, &share_count_asrc); @@ -412,9 +405,9 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) clks[IMX6UL_CLK_GPIO4] = imx_clk_gate2("gpio4", "ipg", base + 0x74, 12); clks[IMX6UL_CLK_QSPI] = imx_clk_gate2("qspi1", "qspi1_podf", base + 0x74, 14); clks[IMX6UL_CLK_WDOG1] = imx_clk_gate2("wdog1", "ipg", base + 0x74, 16); - clks[IMX6UL_CLK_MMDC_P0_FAST] = imx_clk_gate("mmdc_p0_fast", "mmdc_podf", base + 0x74, 20); - clks[IMX6UL_CLK_MMDC_P0_IPG] = imx_clk_gate2("mmdc_p0_ipg", "ipg", base + 0x74, 24); - clks[IMX6UL_CLK_AXI] = imx_clk_gate("axi", "axi_podf", base + 0x74, 28); + clks[IMX6UL_CLK_MMDC_P0_FAST] = imx_clk_gate_flags("mmdc_p0_fast", "mmdc_podf", base + 0x74, 20, CLK_IS_CRITICAL); + clks[IMX6UL_CLK_MMDC_P0_IPG] = imx_clk_gate2_flags("mmdc_p0_ipg", "ipg", base + 0x74, 24, CLK_IS_CRITICAL); + clks[IMX6UL_CLK_AXI] = imx_clk_gate_flags("axi", "axi_podf", base + 0x74, 28, CLK_IS_CRITICAL); /* CCGR4 */ clks[IMX6UL_CLK_PER_BCH] = imx_clk_gate2("per_bch", "bch_podf", base + 0x78, 12); @@ -428,7 +421,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) clks[IMX6UL_CLK_GPMI_APB] = imx_clk_gate2("gpmi_apb", "bch_podf", base + 0x78, 30); /* CCGR5 */ - clks[IMX6UL_CLK_ROM] = imx_clk_gate2("rom", "ahb", base + 0x7c, 0); + clks[IMX6UL_CLK_ROM] = imx_clk_gate2_flags("rom", "ahb", base + 0x7c, 0, CLK_IS_CRITICAL); clks[IMX6UL_CLK_SDMA] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6); clks[IMX6UL_CLK_KPP] = imx_clk_gate2("kpp", "ipg", base + 0x7c, 8); clks[IMX6UL_CLK_WDOG2] = imx_clk_gate2("wdog2", "ipg", base + 0x7c, 10); @@ -502,10 +495,6 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) clk_set_rate(clks[IMX6UL_CLK_ENET2_REF], 50000000); clk_set_rate(clks[IMX6UL_CLK_CSI], 24000000); - /* keep all the clks on just for bringup */ - for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) - clk_prepare_enable(clks[clks_init_on[i]]); - if (clk_on_imx6ull()) clk_prepare_enable(clks[IMX6UL_CLK_AIPSTZ3]); -- 2.7.4 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 4/4] clk: imx6ul: remove clks_init_on array @ 2018-06-03 3:00 ` Anson Huang 0 siblings, 0 replies; 28+ messages in thread From: Anson Huang @ 2018-06-03 3:00 UTC (permalink / raw) To: linux-arm-kernel Clock framework will enable those clocks registered with CLK_IS_CRITICAL flag, so no need to have clks_init_on array during clock initialization now. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> --- This patch is based on "[V2,1/2] clk: imx6ul: add GPIO clock gates". drivers/clk/imx/clk-imx6ul.c | 23 ++++++----------------- 1 file changed, 6 insertions(+), 17 deletions(-) diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c index 3ea2d97..d3f7f4d 100644 --- a/drivers/clk/imx/clk-imx6ul.c +++ b/drivers/clk/imx/clk-imx6ul.c @@ -79,12 +79,6 @@ static const char *cko_sels[] = { "cko1", "cko2", }; static struct clk *clks[IMX6UL_CLK_END]; static struct clk_onecell_data clk_data; -static int const clks_init_on[] __initconst = { - IMX6UL_CLK_AIPSTZ1, IMX6UL_CLK_AIPSTZ2, - IMX6UL_CLK_AXI, IMX6UL_CLK_ARM, IMX6UL_CLK_ROM, - IMX6UL_CLK_MMDC_P0_FAST, IMX6UL_CLK_MMDC_P0_IPG, -}; - static const struct clk_div_table clk_enet_ref_table[] = { { .val = 0, .div = 20, }, { .val = 1, .div = 10, }, @@ -129,7 +123,6 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) { struct device_node *np; void __iomem *base; - int i; clks[IMX6UL_CLK_DUMMY] = imx_clk_fixed("dummy", 0); @@ -336,8 +329,8 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) clks[IMX6UL_CLK_AHB] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1); /* CCGR0 */ - clks[IMX6UL_CLK_AIPSTZ1] = imx_clk_gate2("aips_tz1", "ahb", base + 0x68, 0); - clks[IMX6UL_CLK_AIPSTZ2] = imx_clk_gate2("aips_tz2", "ahb", base + 0x68, 2); + clks[IMX6UL_CLK_AIPSTZ1] = imx_clk_gate2_flags("aips_tz1", "ahb", base + 0x68, 0, CLK_IS_CRITICAL); + clks[IMX6UL_CLK_AIPSTZ2] = imx_clk_gate2_flags("aips_tz2", "ahb", base + 0x68, 2, CLK_IS_CRITICAL); clks[IMX6UL_CLK_APBHDMA] = imx_clk_gate2("apbh_dma", "bch_podf", base + 0x68, 4); clks[IMX6UL_CLK_ASRC_IPG] = imx_clk_gate2_shared("asrc_ipg", "ahb", base + 0x68, 6, &share_count_asrc); clks[IMX6UL_CLK_ASRC_MEM] = imx_clk_gate2_shared("asrc_mem", "ahb", base + 0x68, 6, &share_count_asrc); @@ -412,9 +405,9 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) clks[IMX6UL_CLK_GPIO4] = imx_clk_gate2("gpio4", "ipg", base + 0x74, 12); clks[IMX6UL_CLK_QSPI] = imx_clk_gate2("qspi1", "qspi1_podf", base + 0x74, 14); clks[IMX6UL_CLK_WDOG1] = imx_clk_gate2("wdog1", "ipg", base + 0x74, 16); - clks[IMX6UL_CLK_MMDC_P0_FAST] = imx_clk_gate("mmdc_p0_fast", "mmdc_podf", base + 0x74, 20); - clks[IMX6UL_CLK_MMDC_P0_IPG] = imx_clk_gate2("mmdc_p0_ipg", "ipg", base + 0x74, 24); - clks[IMX6UL_CLK_AXI] = imx_clk_gate("axi", "axi_podf", base + 0x74, 28); + clks[IMX6UL_CLK_MMDC_P0_FAST] = imx_clk_gate_flags("mmdc_p0_fast", "mmdc_podf", base + 0x74, 20, CLK_IS_CRITICAL); + clks[IMX6UL_CLK_MMDC_P0_IPG] = imx_clk_gate2_flags("mmdc_p0_ipg", "ipg", base + 0x74, 24, CLK_IS_CRITICAL); + clks[IMX6UL_CLK_AXI] = imx_clk_gate_flags("axi", "axi_podf", base + 0x74, 28, CLK_IS_CRITICAL); /* CCGR4 */ clks[IMX6UL_CLK_PER_BCH] = imx_clk_gate2("per_bch", "bch_podf", base + 0x78, 12); @@ -428,7 +421,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) clks[IMX6UL_CLK_GPMI_APB] = imx_clk_gate2("gpmi_apb", "bch_podf", base + 0x78, 30); /* CCGR5 */ - clks[IMX6UL_CLK_ROM] = imx_clk_gate2("rom", "ahb", base + 0x7c, 0); + clks[IMX6UL_CLK_ROM] = imx_clk_gate2_flags("rom", "ahb", base + 0x7c, 0, CLK_IS_CRITICAL); clks[IMX6UL_CLK_SDMA] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6); clks[IMX6UL_CLK_KPP] = imx_clk_gate2("kpp", "ipg", base + 0x7c, 8); clks[IMX6UL_CLK_WDOG2] = imx_clk_gate2("wdog2", "ipg", base + 0x7c, 10); @@ -502,10 +495,6 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) clk_set_rate(clks[IMX6UL_CLK_ENET2_REF], 50000000); clk_set_rate(clks[IMX6UL_CLK_CSI], 24000000); - /* keep all the clks on just for bringup */ - for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) - clk_prepare_enable(clks[clks_init_on[i]]); - if (clk_on_imx6ull()) clk_prepare_enable(clks[IMX6UL_CLK_AIPSTZ3]); -- 2.7.4 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* RE: [PATCH 4/4] clk: imx6ul: remove clks_init_on array 2018-06-03 3:00 ` Anson Huang (?) @ 2018-06-25 3:15 ` Anson Huang -1 siblings, 0 replies; 28+ messages in thread From: Anson Huang @ 2018-06-25 3:15 UTC (permalink / raw) To: shawnguo, kernel, Fabio Estevam, mturquette, sboyd Cc: dl-linux-imx, linux-arm-kernel, linux-clk, linux-kernel Gentle Ping... Anson Huang Best Regards! > -----Original Message----- > From: Anson Huang > Sent: Sunday, June 3, 2018 11:01 AM > To: shawnguo@kernel.org; kernel@pengutronix.de; Fabio Estevam > <fabio.estevam@nxp.com>; mturquette@baylibre.com; sboyd@kernel.org > Cc: dl-linux-imx <linux-imx@nxp.com>; linux-arm-kernel@lists.infradead.org; > linux-clk@vger.kernel.org; linux-kernel@vger.kernel.org > Subject: [PATCH 4/4] clk: imx6ul: remove clks_init_on array > > Clock framework will enable those clocks registered with CLK_IS_CRITICAL flag, > so no need to have clks_init_on array during clock initialization now. > > Signed-off-by: Anson Huang <Anson.Huang@nxp.com> > --- > This patch is based on "[V2,1/2] clk: imx6ul: add GPIO clock gates". > drivers/clk/imx/clk-imx6ul.c | 23 ++++++----------------- > 1 file changed, 6 insertions(+), 17 deletions(-) > > diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c index > 3ea2d97..d3f7f4d 100644 > --- a/drivers/clk/imx/clk-imx6ul.c > +++ b/drivers/clk/imx/clk-imx6ul.c > @@ -79,12 +79,6 @@ static const char *cko_sels[] = { "cko1", "cko2", }; > static struct clk *clks[IMX6UL_CLK_END]; static struct clk_onecell_data > clk_data; > > -static int const clks_init_on[] __initconst = { > - IMX6UL_CLK_AIPSTZ1, IMX6UL_CLK_AIPSTZ2, > - IMX6UL_CLK_AXI, IMX6UL_CLK_ARM, IMX6UL_CLK_ROM, > - IMX6UL_CLK_MMDC_P0_FAST, IMX6UL_CLK_MMDC_P0_IPG, > -}; > - > static const struct clk_div_table clk_enet_ref_table[] = { > { .val = 0, .div = 20, }, > { .val = 1, .div = 10, }, > @@ -129,7 +123,6 @@ static void __init imx6ul_clocks_init(struct > device_node *ccm_node) { > struct device_node *np; > void __iomem *base; > - int i; > > clks[IMX6UL_CLK_DUMMY] = imx_clk_fixed("dummy", 0); > > @@ -336,8 +329,8 @@ static void __init imx6ul_clocks_init(struct > device_node *ccm_node) > clks[IMX6UL_CLK_AHB] = imx_clk_busy_divider("ahb", > "periph", base + 0x14, 10, 3, base + 0x48, 1); > > /* CCGR0 */ > - clks[IMX6UL_CLK_AIPSTZ1] = imx_clk_gate2("aips_tz1", "ahb", > base + 0x68, 0); > - clks[IMX6UL_CLK_AIPSTZ2] = imx_clk_gate2("aips_tz2", "ahb", > base + 0x68, 2); > + clks[IMX6UL_CLK_AIPSTZ1] = imx_clk_gate2_flags("aips_tz1", "ahb", > base + 0x68, 0, CLK_IS_CRITICAL); > + clks[IMX6UL_CLK_AIPSTZ2] = imx_clk_gate2_flags("aips_tz2", "ahb", > base + 0x68, 2, CLK_IS_CRITICAL); > clks[IMX6UL_CLK_APBHDMA] = imx_clk_gate2("apbh_dma", > "bch_podf", base + 0x68, 4); > clks[IMX6UL_CLK_ASRC_IPG] = imx_clk_gate2_shared("asrc_ipg", > "ahb", base + 0x68, 6, &share_count_asrc); > clks[IMX6UL_CLK_ASRC_MEM] = imx_clk_gate2_shared("asrc_mem", > "ahb", base + 0x68, 6, &share_count_asrc); > @@ -412,9 +405,9 @@ static void __init imx6ul_clocks_init(struct > device_node *ccm_node) > clks[IMX6UL_CLK_GPIO4] = imx_clk_gate2("gpio4", "ipg", > base + 0x74, 12); > clks[IMX6UL_CLK_QSPI] = imx_clk_gate2("qspi1", "qspi1_podf", > base + 0x74, 14); > clks[IMX6UL_CLK_WDOG1] = imx_clk_gate2("wdog1", "ipg", > base + 0x74, 16); > - clks[IMX6UL_CLK_MMDC_P0_FAST] = imx_clk_gate("mmdc_p0_fast", > "mmdc_podf", base + 0x74, 20); > - clks[IMX6UL_CLK_MMDC_P0_IPG] = imx_clk_gate2("mmdc_p0_ipg", > "ipg", base + 0x74, 24); > - clks[IMX6UL_CLK_AXI] = imx_clk_gate("axi", "axi_podf", base > + 0x74, 28); > + clks[IMX6UL_CLK_MMDC_P0_FAST] = > imx_clk_gate_flags("mmdc_p0_fast", "mmdc_podf", base + 0x74, 20, > CLK_IS_CRITICAL); > + clks[IMX6UL_CLK_MMDC_P0_IPG] = > imx_clk_gate2_flags("mmdc_p0_ipg", "ipg", base + 0x74, 24, > CLK_IS_CRITICAL); > + clks[IMX6UL_CLK_AXI] = imx_clk_gate_flags("axi", "axi_podf", > base + 0x74, 28, CLK_IS_CRITICAL); > > /* CCGR4 */ > clks[IMX6UL_CLK_PER_BCH] = imx_clk_gate2("per_bch", "bch_podf", > base + 0x78, 12); > @@ -428,7 +421,7 @@ static void __init imx6ul_clocks_init(struct > device_node *ccm_node) > clks[IMX6UL_CLK_GPMI_APB] = imx_clk_gate2("gpmi_apb", > "bch_podf", base + 0x78, 30); > > /* CCGR5 */ > - clks[IMX6UL_CLK_ROM] = imx_clk_gate2("rom", "ahb", > base + 0x7c, 0); > + clks[IMX6UL_CLK_ROM] = imx_clk_gate2_flags("rom", "ahb", > base + 0x7c, 0, CLK_IS_CRITICAL); > clks[IMX6UL_CLK_SDMA] = imx_clk_gate2("sdma", > "ahb", base + 0x7c, 6); > clks[IMX6UL_CLK_KPP] = imx_clk_gate2("kpp", "ipg", > base + 0x7c, 8); > clks[IMX6UL_CLK_WDOG2] = imx_clk_gate2("wdog2", "ipg", > base + 0x7c, 10); > @@ -502,10 +495,6 @@ static void __init imx6ul_clocks_init(struct > device_node *ccm_node) > clk_set_rate(clks[IMX6UL_CLK_ENET2_REF], 50000000); > clk_set_rate(clks[IMX6UL_CLK_CSI], 24000000); > > - /* keep all the clks on just for bringup */ > - for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) > - clk_prepare_enable(clks[clks_init_on[i]]); > - > if (clk_on_imx6ull()) > clk_prepare_enable(clks[IMX6UL_CLK_AIPSTZ3]); > > -- > 2.7.4 ^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 4/4] clk: imx6ul: remove clks_init_on array @ 2018-06-25 3:15 ` Anson Huang 0 siblings, 0 replies; 28+ messages in thread From: Anson Huang @ 2018-06-25 3:15 UTC (permalink / raw) To: linux-arm-kernel Gentle Ping... Anson Huang Best Regards! > -----Original Message----- > From: Anson Huang > Sent: Sunday, June 3, 2018 11:01 AM > To: shawnguo at kernel.org; kernel at pengutronix.de; Fabio Estevam > <fabio.estevam@nxp.com>; mturquette at baylibre.com; sboyd at kernel.org > Cc: dl-linux-imx <linux-imx@nxp.com>; linux-arm-kernel at lists.infradead.org; > linux-clk at vger.kernel.org; linux-kernel at vger.kernel.org > Subject: [PATCH 4/4] clk: imx6ul: remove clks_init_on array > > Clock framework will enable those clocks registered with CLK_IS_CRITICAL flag, > so no need to have clks_init_on array during clock initialization now. > > Signed-off-by: Anson Huang <Anson.Huang@nxp.com> > --- > This patch is based on "[V2,1/2] clk: imx6ul: add GPIO clock gates". > drivers/clk/imx/clk-imx6ul.c | 23 ++++++----------------- > 1 file changed, 6 insertions(+), 17 deletions(-) > > diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c index > 3ea2d97..d3f7f4d 100644 > --- a/drivers/clk/imx/clk-imx6ul.c > +++ b/drivers/clk/imx/clk-imx6ul.c > @@ -79,12 +79,6 @@ static const char *cko_sels[] = { "cko1", "cko2", }; > static struct clk *clks[IMX6UL_CLK_END]; static struct clk_onecell_data > clk_data; > > -static int const clks_init_on[] __initconst = { > - IMX6UL_CLK_AIPSTZ1, IMX6UL_CLK_AIPSTZ2, > - IMX6UL_CLK_AXI, IMX6UL_CLK_ARM, IMX6UL_CLK_ROM, > - IMX6UL_CLK_MMDC_P0_FAST, IMX6UL_CLK_MMDC_P0_IPG, > -}; > - > static const struct clk_div_table clk_enet_ref_table[] = { > { .val = 0, .div = 20, }, > { .val = 1, .div = 10, }, > @@ -129,7 +123,6 @@ static void __init imx6ul_clocks_init(struct > device_node *ccm_node) { > struct device_node *np; > void __iomem *base; > - int i; > > clks[IMX6UL_CLK_DUMMY] = imx_clk_fixed("dummy", 0); > > @@ -336,8 +329,8 @@ static void __init imx6ul_clocks_init(struct > device_node *ccm_node) > clks[IMX6UL_CLK_AHB] = imx_clk_busy_divider("ahb", > "periph", base + 0x14, 10, 3, base + 0x48, 1); > > /* CCGR0 */ > - clks[IMX6UL_CLK_AIPSTZ1] = imx_clk_gate2("aips_tz1", "ahb", > base + 0x68, 0); > - clks[IMX6UL_CLK_AIPSTZ2] = imx_clk_gate2("aips_tz2", "ahb", > base + 0x68, 2); > + clks[IMX6UL_CLK_AIPSTZ1] = imx_clk_gate2_flags("aips_tz1", "ahb", > base + 0x68, 0, CLK_IS_CRITICAL); > + clks[IMX6UL_CLK_AIPSTZ2] = imx_clk_gate2_flags("aips_tz2", "ahb", > base + 0x68, 2, CLK_IS_CRITICAL); > clks[IMX6UL_CLK_APBHDMA] = imx_clk_gate2("apbh_dma", > "bch_podf", base + 0x68, 4); > clks[IMX6UL_CLK_ASRC_IPG] = imx_clk_gate2_shared("asrc_ipg", > "ahb", base + 0x68, 6, &share_count_asrc); > clks[IMX6UL_CLK_ASRC_MEM] = imx_clk_gate2_shared("asrc_mem", > "ahb", base + 0x68, 6, &share_count_asrc); > @@ -412,9 +405,9 @@ static void __init imx6ul_clocks_init(struct > device_node *ccm_node) > clks[IMX6UL_CLK_GPIO4] = imx_clk_gate2("gpio4", "ipg", > base + 0x74, 12); > clks[IMX6UL_CLK_QSPI] = imx_clk_gate2("qspi1", "qspi1_podf", > base + 0x74, 14); > clks[IMX6UL_CLK_WDOG1] = imx_clk_gate2("wdog1", "ipg", > base + 0x74, 16); > - clks[IMX6UL_CLK_MMDC_P0_FAST] = imx_clk_gate("mmdc_p0_fast", > "mmdc_podf", base + 0x74, 20); > - clks[IMX6UL_CLK_MMDC_P0_IPG] = imx_clk_gate2("mmdc_p0_ipg", > "ipg", base + 0x74, 24); > - clks[IMX6UL_CLK_AXI] = imx_clk_gate("axi", "axi_podf", base > + 0x74, 28); > + clks[IMX6UL_CLK_MMDC_P0_FAST] = > imx_clk_gate_flags("mmdc_p0_fast", "mmdc_podf", base + 0x74, 20, > CLK_IS_CRITICAL); > + clks[IMX6UL_CLK_MMDC_P0_IPG] = > imx_clk_gate2_flags("mmdc_p0_ipg", "ipg", base + 0x74, 24, > CLK_IS_CRITICAL); > + clks[IMX6UL_CLK_AXI] = imx_clk_gate_flags("axi", "axi_podf", > base + 0x74, 28, CLK_IS_CRITICAL); > > /* CCGR4 */ > clks[IMX6UL_CLK_PER_BCH] = imx_clk_gate2("per_bch", "bch_podf", > base + 0x78, 12); > @@ -428,7 +421,7 @@ static void __init imx6ul_clocks_init(struct > device_node *ccm_node) > clks[IMX6UL_CLK_GPMI_APB] = imx_clk_gate2("gpmi_apb", > "bch_podf", base + 0x78, 30); > > /* CCGR5 */ > - clks[IMX6UL_CLK_ROM] = imx_clk_gate2("rom", "ahb", > base + 0x7c, 0); > + clks[IMX6UL_CLK_ROM] = imx_clk_gate2_flags("rom", "ahb", > base + 0x7c, 0, CLK_IS_CRITICAL); > clks[IMX6UL_CLK_SDMA] = imx_clk_gate2("sdma", > "ahb", base + 0x7c, 6); > clks[IMX6UL_CLK_KPP] = imx_clk_gate2("kpp", "ipg", > base + 0x7c, 8); > clks[IMX6UL_CLK_WDOG2] = imx_clk_gate2("wdog2", "ipg", > base + 0x7c, 10); > @@ -502,10 +495,6 @@ static void __init imx6ul_clocks_init(struct > device_node *ccm_node) > clk_set_rate(clks[IMX6UL_CLK_ENET2_REF], 50000000); > clk_set_rate(clks[IMX6UL_CLK_CSI], 24000000); > > - /* keep all the clks on just for bringup */ > - for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) > - clk_prepare_enable(clks[clks_init_on[i]]); > - > if (clk_on_imx6ull()) > clk_prepare_enable(clks[IMX6UL_CLK_AIPSTZ3]); > > -- > 2.7.4 ^ permalink raw reply [flat|nested] 28+ messages in thread
* RE: [PATCH 4/4] clk: imx6ul: remove clks_init_on array @ 2018-06-25 3:15 ` Anson Huang 0 siblings, 0 replies; 28+ messages in thread From: Anson Huang @ 2018-06-25 3:15 UTC (permalink / raw) To: shawnguo, kernel, Fabio Estevam, mturquette, sboyd Cc: dl-linux-imx, linux-arm-kernel, linux-clk, linux-kernel Gentle Ping... Anson Huang Best Regards! > -----Original Message----- > From: Anson Huang > Sent: Sunday, June 3, 2018 11:01 AM > To: shawnguo@kernel.org; kernel@pengutronix.de; Fabio Estevam > <fabio.estevam@nxp.com>; mturquette@baylibre.com; sboyd@kernel.org > Cc: dl-linux-imx <linux-imx@nxp.com>; linux-arm-kernel@lists.infradead.or= g; > linux-clk@vger.kernel.org; linux-kernel@vger.kernel.org > Subject: [PATCH 4/4] clk: imx6ul: remove clks_init_on array >=20 > Clock framework will enable those clocks registered with CLK_IS_CRITICAL = flag, > so no need to have clks_init_on array during clock initialization now. >=20 > Signed-off-by: Anson Huang <Anson.Huang@nxp.com> > --- > This patch is based on "[V2,1/2] clk: imx6ul: add GPIO clock gates". > drivers/clk/imx/clk-imx6ul.c | 23 ++++++----------------- > 1 file changed, 6 insertions(+), 17 deletions(-) >=20 > diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c = index > 3ea2d97..d3f7f4d 100644 > --- a/drivers/clk/imx/clk-imx6ul.c > +++ b/drivers/clk/imx/clk-imx6ul.c > @@ -79,12 +79,6 @@ static const char *cko_sels[] =3D { "cko1", "cko2", }; > static struct clk *clks[IMX6UL_CLK_END]; static struct clk_onecell_data > clk_data; >=20 > -static int const clks_init_on[] __initconst =3D { > - IMX6UL_CLK_AIPSTZ1, IMX6UL_CLK_AIPSTZ2, > - IMX6UL_CLK_AXI, IMX6UL_CLK_ARM, IMX6UL_CLK_ROM, > - IMX6UL_CLK_MMDC_P0_FAST, IMX6UL_CLK_MMDC_P0_IPG, > -}; > - > static const struct clk_div_table clk_enet_ref_table[] =3D { > { .val =3D 0, .div =3D 20, }, > { .val =3D 1, .div =3D 10, }, > @@ -129,7 +123,6 @@ static void __init imx6ul_clocks_init(struct > device_node *ccm_node) { > struct device_node *np; > void __iomem *base; > - int i; >=20 > clks[IMX6UL_CLK_DUMMY] =3D imx_clk_fixed("dummy", 0); >=20 > @@ -336,8 +329,8 @@ static void __init imx6ul_clocks_init(struct > device_node *ccm_node) > clks[IMX6UL_CLK_AHB] =3D imx_clk_busy_divider("ahb", > "periph", base + 0x14, 10, 3, base + 0x48, 1); >=20 > /* CCGR0 */ > - clks[IMX6UL_CLK_AIPSTZ1] =3D imx_clk_gate2("aips_tz1", "ahb", > base + 0x68, 0); > - clks[IMX6UL_CLK_AIPSTZ2] =3D imx_clk_gate2("aips_tz2", "ahb", > base + 0x68, 2); > + clks[IMX6UL_CLK_AIPSTZ1] =3D imx_clk_gate2_flags("aips_tz1", "ahb", > base + 0x68, 0, CLK_IS_CRITICAL); > + clks[IMX6UL_CLK_AIPSTZ2] =3D imx_clk_gate2_flags("aips_tz2", "ahb", > base + 0x68, 2, CLK_IS_CRITICAL); > clks[IMX6UL_CLK_APBHDMA] =3D imx_clk_gate2("apbh_dma", > "bch_podf", base + 0x68, 4); > clks[IMX6UL_CLK_ASRC_IPG] =3D imx_clk_gate2_shared("asrc_ipg", > "ahb", base + 0x68, 6, &share_count_asrc); > clks[IMX6UL_CLK_ASRC_MEM] =3D imx_clk_gate2_shared("asrc_mem", > "ahb", base + 0x68, 6, &share_count_asrc); > @@ -412,9 +405,9 @@ static void __init imx6ul_clocks_init(struct > device_node *ccm_node) > clks[IMX6UL_CLK_GPIO4] =3D imx_clk_gate2("gpio4", "ipg", > base + 0x74, 12); > clks[IMX6UL_CLK_QSPI] =3D imx_clk_gate2("qspi1", "qspi1_podf", > base + 0x74, 14); > clks[IMX6UL_CLK_WDOG1] =3D imx_clk_gate2("wdog1", "ipg", > base + 0x74, 16); > - clks[IMX6UL_CLK_MMDC_P0_FAST] =3D imx_clk_gate("mmdc_p0_fast", > "mmdc_podf", base + 0x74, 20); > - clks[IMX6UL_CLK_MMDC_P0_IPG] =3D imx_clk_gate2("mmdc_p0_ipg", > "ipg", base + 0x74, 24); > - clks[IMX6UL_CLK_AXI] =3D imx_clk_gate("axi", "axi_podf", base > + 0x74, 28); > + clks[IMX6UL_CLK_MMDC_P0_FAST] =3D > imx_clk_gate_flags("mmdc_p0_fast", "mmdc_podf", base + 0x74, 20, > CLK_IS_CRITICAL); > + clks[IMX6UL_CLK_MMDC_P0_IPG] =3D > imx_clk_gate2_flags("mmdc_p0_ipg", "ipg", base + 0x74, 24, > CLK_IS_CRITICAL); > + clks[IMX6UL_CLK_AXI] =3D imx_clk_gate_flags("axi", "axi_podf", > base + 0x74, 28, CLK_IS_CRITICAL); >=20 > /* CCGR4 */ > clks[IMX6UL_CLK_PER_BCH] =3D imx_clk_gate2("per_bch", "bch_podf", > base + 0x78, 12); > @@ -428,7 +421,7 @@ static void __init imx6ul_clocks_init(struct > device_node *ccm_node) > clks[IMX6UL_CLK_GPMI_APB] =3D imx_clk_gate2("gpmi_apb", > "bch_podf", base + 0x78, 30); >=20 > /* CCGR5 */ > - clks[IMX6UL_CLK_ROM] =3D imx_clk_gate2("rom", "ahb", > base + 0x7c, 0); > + clks[IMX6UL_CLK_ROM] =3D imx_clk_gate2_flags("rom", "ahb", > base + 0x7c, 0, CLK_IS_CRITICAL); > clks[IMX6UL_CLK_SDMA] =3D imx_clk_gate2("sdma", > "ahb", base + 0x7c, 6); > clks[IMX6UL_CLK_KPP] =3D imx_clk_gate2("kpp", "ipg", > base + 0x7c, 8); > clks[IMX6UL_CLK_WDOG2] =3D imx_clk_gate2("wdog2", "ipg", > base + 0x7c, 10); > @@ -502,10 +495,6 @@ static void __init imx6ul_clocks_init(struct > device_node *ccm_node) > clk_set_rate(clks[IMX6UL_CLK_ENET2_REF], 50000000); > clk_set_rate(clks[IMX6UL_CLK_CSI], 24000000); >=20 > - /* keep all the clks on just for bringup */ > - for (i =3D 0; i < ARRAY_SIZE(clks_init_on); i++) > - clk_prepare_enable(clks[clks_init_on[i]]); > - > if (clk_on_imx6ull()) > clk_prepare_enable(clks[IMX6UL_CLK_AIPSTZ3]); >=20 > -- > 2.7.4 ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 1/4] clk: imx6q: remove clks_init_on array 2018-06-03 3:00 ` Anson Huang @ 2018-06-03 12:44 ` Fabio Estevam -1 siblings, 0 replies; 28+ messages in thread From: Fabio Estevam @ 2018-06-03 12:44 UTC (permalink / raw) To: Anson Huang Cc: Shawn Guo, Sascha Hauer, Fabio Estevam, Michael Turquette, Stephen Boyd, NXP Linux Team, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE, linux-clk, linux-kernel On Sun, Jun 3, 2018 at 12:00 AM, Anson Huang <Anson.Huang@nxp.com> wrote: > Clock framework will enable those clocks registered > with CLK_IS_CRITICAL flag, so no need to have > clks_init_on array during clock initialization now. > > Signed-off-by: Anson Huang <Anson.Huang@nxp.com> > --- > drivers/clk/imx/clk-imx6q.c | 14 ++------------ > 1 file changed, 2 insertions(+), 12 deletions(-) > > diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c > index b9ea703..8754c61 100644 > --- a/drivers/clk/imx/clk-imx6q.c > +++ b/drivers/clk/imx/clk-imx6q.c > @@ -96,12 +96,6 @@ static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", }; > static struct clk *clk[IMX6QDL_CLK_END]; > static struct clk_onecell_data clk_data; > > -static unsigned int const clks_init_on[] __initconst = { > - IMX6QDL_CLK_MMDC_CH0_AXI, > - IMX6QDL_CLK_ROM, > - IMX6QDL_CLK_ARM, IMX6QDL_CLK_ARM does not have the CLK_IS_CRITICAL flag. Is this intended? If so, please mention in the commit log. ^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 1/4] clk: imx6q: remove clks_init_on array @ 2018-06-03 12:44 ` Fabio Estevam 0 siblings, 0 replies; 28+ messages in thread From: Fabio Estevam @ 2018-06-03 12:44 UTC (permalink / raw) To: linux-arm-kernel On Sun, Jun 3, 2018 at 12:00 AM, Anson Huang <Anson.Huang@nxp.com> wrote: > Clock framework will enable those clocks registered > with CLK_IS_CRITICAL flag, so no need to have > clks_init_on array during clock initialization now. > > Signed-off-by: Anson Huang <Anson.Huang@nxp.com> > --- > drivers/clk/imx/clk-imx6q.c | 14 ++------------ > 1 file changed, 2 insertions(+), 12 deletions(-) > > diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c > index b9ea703..8754c61 100644 > --- a/drivers/clk/imx/clk-imx6q.c > +++ b/drivers/clk/imx/clk-imx6q.c > @@ -96,12 +96,6 @@ static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", }; > static struct clk *clk[IMX6QDL_CLK_END]; > static struct clk_onecell_data clk_data; > > -static unsigned int const clks_init_on[] __initconst = { > - IMX6QDL_CLK_MMDC_CH0_AXI, > - IMX6QDL_CLK_ROM, > - IMX6QDL_CLK_ARM, IMX6QDL_CLK_ARM does not have the CLK_IS_CRITICAL flag. Is this intended? If so, please mention in the commit log. ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 1/4] clk: imx6q: remove clks_init_on array 2018-06-03 12:44 ` Fabio Estevam (?) @ 2018-06-03 12:48 ` Anson Huang -1 siblings, 0 replies; 28+ messages in thread From: Anson Huang @ 2018-06-03 12:48 UTC (permalink / raw) To: Fabio Estevam Cc: Shawn Guo, Sascha Hauer, Fabio Estevam, Michael Turquette, Stephen Boyd, dl-linux-imx, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE, linux-clk, linux-kernel Hi, Fabio >From Anson's iPhone 6 > 在 2018年6月3日，20:44，Fabio Estevam <festevam@gmail.com> 写道： > >> On Sun, Jun 3, 2018 at 12:00 AM, Anson Huang <Anson.Huang@nxp.com> wrote: >> Clock framework will enable those clocks registered >> with CLK_IS_CRITICAL flag, so no need to have >> clks_init_on array during clock initialization now. >> >> Signed-off-by: Anson Huang <Anson.Huang@nxp.com> >> --- >> drivers/clk/imx/clk-imx6q.c | 14 ++------------ >> 1 file changed, 2 insertions(+), 12 deletions(-) >> >> diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c >> index b9ea703..8754c61 100644 >> --- a/drivers/clk/imx/clk-imx6q.c >> +++ b/drivers/clk/imx/clk-imx6q.c >> @@ -96,12 +96,6 @@ static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", }; >> static struct clk *clk[IMX6QDL_CLK_END]; >> static struct clk_onecell_data clk_data; >> >> -static unsigned int const clks_init_on[] __initconst = { >> - IMX6QDL_CLK_MMDC_CH0_AXI, >> - IMX6QDL_CLK_ROM, >> - IMX6QDL_CLK_ARM, > > IMX6QDL_CLK_ARM does not have the CLK_IS_CRITICAL flag. > > Is this intended? If so, please mention in the commit log. As I explain in previous mail, busy divider clk type already include the flag when registered. Anson. ^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 1/4] clk: imx6q: remove clks_init_on array @ 2018-06-03 12:48 ` Anson Huang 0 siblings, 0 replies; 28+ messages in thread From: Anson Huang @ 2018-06-03 12:48 UTC (permalink / raw) To: linux-arm-kernel Hi, Fabio >From Anson's iPhone 6 > ? 2018?6?3??20:44?Fabio Estevam <festevam@gmail.com> ??? > >> On Sun, Jun 3, 2018 at 12:00 AM, Anson Huang <Anson.Huang@nxp.com> wrote: >> Clock framework will enable those clocks registered >> with CLK_IS_CRITICAL flag, so no need to have >> clks_init_on array during clock initialization now. >> >> Signed-off-by: Anson Huang <Anson.Huang@nxp.com> >> --- >> drivers/clk/imx/clk-imx6q.c | 14 ++------------ >> 1 file changed, 2 insertions(+), 12 deletions(-) >> >> diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c >> index b9ea703..8754c61 100644 >> --- a/drivers/clk/imx/clk-imx6q.c >> +++ b/drivers/clk/imx/clk-imx6q.c >> @@ -96,12 +96,6 @@ static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", }; >> static struct clk *clk[IMX6QDL_CLK_END]; >> static struct clk_onecell_data clk_data; >> >> -static unsigned int const clks_init_on[] __initconst = { >> - IMX6QDL_CLK_MMDC_CH0_AXI, >> - IMX6QDL_CLK_ROM, >> - IMX6QDL_CLK_ARM, > > IMX6QDL_CLK_ARM does not have the CLK_IS_CRITICAL flag. > > Is this intended? If so, please mention in the commit log. As I explain in previous mail, busy divider clk type already include the flag when registered. Anson. ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 1/4] clk: imx6q: remove clks_init_on array @ 2018-06-03 12:48 ` Anson Huang 0 siblings, 0 replies; 28+ messages in thread From: Anson Huang @ 2018-06-03 12:48 UTC (permalink / raw) To: Fabio Estevam Cc: Shawn Guo, Sascha Hauer, Fabio Estevam, Michael Turquette, Stephen Boyd, dl-linux-imx, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE, linux-clk, linux-kernel SGksIEZhYmlvDQoNCkZyb20gQW5zb24ncyBpUGhvbmUgNg0KDQoNCj4g5ZyoIDIwMTjlubQ25pyI M+aXpe+8jDIwOjQ077yMRmFiaW8gRXN0ZXZhbSA8ZmVzdGV2YW1AZ21haWwuY29tPiDlhpnpgZPv vJoNCj4gDQo+PiBPbiBTdW4sIEp1biAzLCAyMDE4IGF0IDEyOjAwIEFNLCBBbnNvbiBIdWFuZyA8 QW5zb24uSHVhbmdAbnhwLmNvbT4gd3JvdGU6DQo+PiBDbG9jayBmcmFtZXdvcmsgd2lsbCBlbmFi bGUgdGhvc2UgY2xvY2tzIHJlZ2lzdGVyZWQNCj4+IHdpdGggQ0xLX0lTX0NSSVRJQ0FMIGZsYWcs IHNvIG5vIG5lZWQgdG8gaGF2ZQ0KPj4gY2xrc19pbml0X29uIGFycmF5IGR1cmluZyBjbG9jayBp bml0aWFsaXphdGlvbiBub3cuDQo+PiANCj4+IFNpZ25lZC1vZmYtYnk6IEFuc29uIEh1YW5nIDxB bnNvbi5IdWFuZ0BueHAuY29tPg0KPj4gLS0tDQo+PiBkcml2ZXJzL2Nsay9pbXgvY2xrLWlteDZx LmMgfCAxNCArKy0tLS0tLS0tLS0tLQ0KPj4gMSBmaWxlIGNoYW5nZWQsIDIgaW5zZXJ0aW9ucygr KSwgMTIgZGVsZXRpb25zKC0pDQo+PiANCj4+IGRpZmYgLS1naXQgYS9kcml2ZXJzL2Nsay9pbXgv Y2xrLWlteDZxLmMgYi9kcml2ZXJzL2Nsay9pbXgvY2xrLWlteDZxLmMNCj4+IGluZGV4IGI5ZWE3 MDMuLjg3NTRjNjEgMTAwNjQ0DQo+PiAtLS0gYS9kcml2ZXJzL2Nsay9pbXgvY2xrLWlteDZxLmMN Cj4+ICsrKyBiL2RyaXZlcnMvY2xrL2lteC9jbGstaW14NnEuYw0KPj4gQEAgLTk2LDEyICs5Niw2 IEBAIHN0YXRpYyBjb25zdCBjaGFyICpwbGw3X2J5cGFzc19zZWxzW10gPSB7ICJwbGw3IiwgInBs bDdfYnlwYXNzX3NyYyIsIH07DQo+PiBzdGF0aWMgc3RydWN0IGNsayAqY2xrW0lNWDZRRExfQ0xL X0VORF07DQo+PiBzdGF0aWMgc3RydWN0IGNsa19vbmVjZWxsX2RhdGEgY2xrX2RhdGE7DQo+PiAN Cj4+IC1zdGF0aWMgdW5zaWduZWQgaW50IGNvbnN0IGNsa3NfaW5pdF9vbltdIF9faW5pdGNvbnN0 ID0gew0KPj4gLSAgICAgICBJTVg2UURMX0NMS19NTURDX0NIMF9BWEksDQo+PiAtICAgICAgIElN WDZRRExfQ0xLX1JPTSwNCj4+IC0gICAgICAgSU1YNlFETF9DTEtfQVJNLA0KPiANCj4gSU1YNlFE TF9DTEtfQVJNIGRvZXMgbm90IGhhdmUgdGhlIENMS19JU19DUklUSUNBTCBmbGFnLg0KPiANCj4g SXMgdGhpcyBpbnRlbmRlZD8gSWYgc28sIHBsZWFzZSBtZW50aW9uIGluIHRoZSBjb21taXQgbG9n Lg0KDQpBcyBJIGV4cGxhaW4gaW4gcHJldmlvdXMgbWFpbCwgYnVzeSBkaXZpZGVyIGNsayB0eXBl IGFscmVhZHkgaW5jbHVkZSB0aGUgZmxhZyB3aGVuIHJlZ2lzdGVyZWQuDQoNCkFuc29uLg== ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 1/4] clk: imx6q: remove clks_init_on array 2018-06-03 12:48 ` Anson Huang @ 2018-06-03 12:54 ` Fabio Estevam -1 siblings, 0 replies; 28+ messages in thread From: Fabio Estevam @ 2018-06-03 12:54 UTC (permalink / raw) To: Anson Huang Cc: Shawn Guo, Sascha Hauer, Fabio Estevam, Michael Turquette, Stephen Boyd, dl-linux-imx, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE, linux-clk, linux-kernel Hi Anson, On Sun, Jun 3, 2018 at 9:48 AM, Anson Huang <anson.huang@nxp.com> wrote: > As I explain in previous mail, busy divider clk type already include the flag when registered. Ok, then please add this information in the commit log to make the review process easier. ^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 1/4] clk: imx6q: remove clks_init_on array @ 2018-06-03 12:54 ` Fabio Estevam 0 siblings, 0 replies; 28+ messages in thread From: Fabio Estevam @ 2018-06-03 12:54 UTC (permalink / raw) To: linux-arm-kernel Hi Anson, On Sun, Jun 3, 2018 at 9:48 AM, Anson Huang <anson.huang@nxp.com> wrote: > As I explain in previous mail, busy divider clk type already include the flag when registered. Ok, then please add this information in the commit log to make the review process easier. ^ permalink raw reply [flat|nested] 28+ messages in thread
* RE: [PATCH 1/4] clk: imx6q: remove clks_init_on array 2018-06-03 12:54 ` Fabio Estevam (?) @ 2018-06-04 1:11 ` Anson Huang -1 siblings, 0 replies; 28+ messages in thread From: Anson Huang @ 2018-06-04 1:11 UTC (permalink / raw) To: Fabio Estevam Cc: Shawn Guo, Sascha Hauer, Fabio Estevam, Michael Turquette, Stephen Boyd, dl-linux-imx, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE, linux-clk, linux-kernel Hi, Fabio Anson Huang Best Regards! > -----Original Message----- > From: Fabio Estevam [mailto:festevam@gmail.com] > Sent: Sunday, June 3, 2018 8:54 PM > To: Anson Huang <anson.huang@nxp.com> > Cc: Shawn Guo <shawnguo@kernel.org>; Sascha Hauer > <kernel@pengutronix.de>; Fabio Estevam <fabio.estevam@nxp.com>; Michael > Turquette <mturquette@baylibre.com>; Stephen Boyd <sboyd@kernel.org>; > dl-linux-imx <linux-imx@nxp.com>; moderated list:ARM/FREESCALE IMX / MXC > ARM ARCHITECTURE <linux-arm-kernel@lists.infradead.org>; linux-clk > <linux-clk@vger.kernel.org>; linux-kernel <linux-kernel@vger.kernel.org> > Subject: Re: [PATCH 1/4] clk: imx6q: remove clks_init_on array > > Hi Anson, > > On Sun, Jun 3, 2018 at 9:48 AM, Anson Huang <anson.huang@nxp.com> > wrote: > > > As I explain in previous mail, busy divider clk type already include the flag > when registered. > > Ok, then please add this information in the commit log to make the review > process easier. Thanks for the comments, I improved the commit log in V2 patch set. Anson. ^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 1/4] clk: imx6q: remove clks_init_on array @ 2018-06-04 1:11 ` Anson Huang 0 siblings, 0 replies; 28+ messages in thread From: Anson Huang @ 2018-06-04 1:11 UTC (permalink / raw) To: linux-arm-kernel Hi, Fabio Anson Huang Best Regards! > -----Original Message----- > From: Fabio Estevam [mailto:festevam at gmail.com] > Sent: Sunday, June 3, 2018 8:54 PM > To: Anson Huang <anson.huang@nxp.com> > Cc: Shawn Guo <shawnguo@kernel.org>; Sascha Hauer > <kernel@pengutronix.de>; Fabio Estevam <fabio.estevam@nxp.com>; Michael > Turquette <mturquette@baylibre.com>; Stephen Boyd <sboyd@kernel.org>; > dl-linux-imx <linux-imx@nxp.com>; moderated list:ARM/FREESCALE IMX / MXC > ARM ARCHITECTURE <linux-arm-kernel@lists.infradead.org>; linux-clk > <linux-clk@vger.kernel.org>; linux-kernel <linux-kernel@vger.kernel.org> > Subject: Re: [PATCH 1/4] clk: imx6q: remove clks_init_on array > > Hi Anson, > > On Sun, Jun 3, 2018 at 9:48 AM, Anson Huang <anson.huang@nxp.com> > wrote: > > > As I explain in previous mail, busy divider clk type already include the flag > when registered. > > Ok, then please add this information in the commit log to make the review > process easier. Thanks for the comments, I improved the commit log in V2 patch set. Anson. ^ permalink raw reply [flat|nested] 28+ messages in thread
* RE: [PATCH 1/4] clk: imx6q: remove clks_init_on array @ 2018-06-04 1:11 ` Anson Huang 0 siblings, 0 replies; 28+ messages in thread From: Anson Huang @ 2018-06-04 1:11 UTC (permalink / raw) To: Fabio Estevam Cc: Shawn Guo, Sascha Hauer, Fabio Estevam, Michael Turquette, Stephen Boyd, dl-linux-imx, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE, linux-clk, linux-kernel SGksIEZhYmlvDQoNCkFuc29uIEh1YW5nDQpCZXN0IFJlZ2FyZHMhDQoNCg0KPiAtLS0tLU9yaWdp bmFsIE1lc3NhZ2UtLS0tLQ0KPiBGcm9tOiBGYWJpbyBFc3RldmFtIFttYWlsdG86ZmVzdGV2YW1A Z21haWwuY29tXQ0KPiBTZW50OiBTdW5kYXksIEp1bmUgMywgMjAxOCA4OjU0IFBNDQo+IFRvOiBB bnNvbiBIdWFuZyA8YW5zb24uaHVhbmdAbnhwLmNvbT4NCj4gQ2M6IFNoYXduIEd1byA8c2hhd25n dW9Aa2VybmVsLm9yZz47IFNhc2NoYSBIYXVlcg0KPiA8a2VybmVsQHBlbmd1dHJvbml4LmRlPjsg RmFiaW8gRXN0ZXZhbSA8ZmFiaW8uZXN0ZXZhbUBueHAuY29tPjsgTWljaGFlbA0KPiBUdXJxdWV0 dGUgPG10dXJxdWV0dGVAYmF5bGlicmUuY29tPjsgU3RlcGhlbiBCb3lkIDxzYm95ZEBrZXJuZWwu b3JnPjsNCj4gZGwtbGludXgtaW14IDxsaW51eC1pbXhAbnhwLmNvbT47IG1vZGVyYXRlZCBsaXN0 OkFSTS9GUkVFU0NBTEUgSU1YIC8gTVhDDQo+IEFSTSBBUkNISVRFQ1RVUkUgPGxpbnV4LWFybS1r ZXJuZWxAbGlzdHMuaW5mcmFkZWFkLm9yZz47IGxpbnV4LWNsaw0KPiA8bGludXgtY2xrQHZnZXIu a2VybmVsLm9yZz47IGxpbnV4LWtlcm5lbCA8bGludXgta2VybmVsQHZnZXIua2VybmVsLm9yZz4N Cj4gU3ViamVjdDogUmU6IFtQQVRDSCAxLzRdIGNsazogaW14NnE6IHJlbW92ZSBjbGtzX2luaXRf b24gYXJyYXkNCj4gDQo+IEhpIEFuc29uLA0KPiANCj4gT24gU3VuLCBKdW4gMywgMjAxOCBhdCA5 OjQ4IEFNLCBBbnNvbiBIdWFuZyA8YW5zb24uaHVhbmdAbnhwLmNvbT4NCj4gd3JvdGU6DQo+IA0K PiA+IEFzIEkgZXhwbGFpbiBpbiBwcmV2aW91cyBtYWlsLCBidXN5IGRpdmlkZXIgY2xrIHR5cGUg YWxyZWFkeSBpbmNsdWRlIHRoZSBmbGFnDQo+IHdoZW4gcmVnaXN0ZXJlZC4NCj4gDQo+IE9rLCB0 aGVuIHBsZWFzZSBhZGQgdGhpcyBpbmZvcm1hdGlvbiBpbiB0aGUgY29tbWl0IGxvZyB0byBtYWtl IHRoZSByZXZpZXcNCj4gcHJvY2VzcyBlYXNpZXIuDQogDQpUaGFua3MgZm9yIHRoZSBjb21tZW50 cywgSSBpbXByb3ZlZCB0aGUgY29tbWl0IGxvZyBpbiBWMiBwYXRjaCBzZXQuDQoNCkFuc29uLg0K DQo= ^ permalink raw reply [flat|nested] 28+ messages in thread
end of thread, other threads:[~2018-06-25 3:15 UTC | newest] Thread overview: 28+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2018-06-03 3:00 [PATCH 1/4] clk: imx6q: remove clks_init_on array Anson Huang 2018-06-03 3:00 ` Anson Huang 2018-06-03 3:00 ` [PATCH 2/4] clk: imx6sl: " Anson Huang 2018-06-03 3:00 ` Anson Huang 2018-06-03 12:17 ` Fabio Estevam 2018-06-03 12:17 ` Fabio Estevam 2018-06-03 12:45 ` Anson Huang 2018-06-03 12:45 ` Anson Huang 2018-06-03 12:45 ` Anson Huang 2018-06-03 3:00 ` [PATCH 3/4] clk: imx6sx: " Anson Huang 2018-06-03 3:00 ` Anson Huang 2018-06-03 12:52 ` Fabio Estevam 2018-06-03 12:52 ` Fabio Estevam 2018-06-03 3:00 ` [PATCH 4/4] clk: imx6ul: " Anson Huang 2018-06-03 3:00 ` Anson Huang 2018-06-25 3:15 ` Anson Huang 2018-06-25 3:15 ` Anson Huang 2018-06-25 3:15 ` Anson Huang 2018-06-03 12:44 ` [PATCH 1/4] clk: imx6q: " Fabio Estevam 2018-06-03 12:44 ` Fabio Estevam 2018-06-03 12:48 ` Anson Huang 2018-06-03 12:48 ` Anson Huang 2018-06-03 12:48 ` Anson Huang 2018-06-03 12:54 ` Fabio Estevam 2018-06-03 12:54 ` Fabio Estevam 2018-06-04 1:11 ` Anson Huang 2018-06-04 1:11 ` Anson Huang 2018-06-04 1:11 ` Anson Huang
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