* [Qemu-devel] [PATCH v2 0/3] aspeed: introduce the APB clock settings
@ 2018-06-22 7:56 Cédric Le Goater
2018-06-22 7:56 ` [Qemu-devel] [PATCH v2 1/3] aspeed/scu: introduce clock frequencies Cédric Le Goater
` (4 more replies)
0 siblings, 5 replies; 11+ messages in thread
From: Cédric Le Goater @ 2018-06-22 7:56 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, Peter Maydell, Joel Stanley, Andrew Jeffery,
Cédric Le Goater
Hello,
The Aspeed SoC clocks are driven by an input source clock which can
have different frequencies : 24MHz or 25MHz, and also, on the Aspeed
AST2400 SoC, 48MHz. The H-PLL (CPU) clock is defined from a calculation
using parameters in the H-PLL Parameter register or from a predefined
set of frequencies if the setting is strapped by hardware (Aspeed
AST2400 SoC). The other clocks of the SoC are then defined from the
H-PLL using dividers.
We first introduce the APB clock because it drives the timer model.
This fixes a slowdown issue on the palmetto machine (AST2400) when
running Linux. The latest Linux versions take into account more
precisely the SoC settings for the clocks and the APB freq is set to
48MHz but modeled at 24MHz by QEMU.
Thanks,
C.
Changes since v1:
- fixed AST2400 HPLL calculation when CLKIN is 25MHz
Cédric Le Goater (3):
aspeed/scu: introduce clock frequencies
aspeed: initialize the SCU controller first
aspeed/timer: use the APB frequency from the SCU
include/hw/misc/aspeed_scu.h | 70 ++++++++++++++++++++++++--
include/hw/timer/aspeed_timer.h | 4 ++
hw/arm/aspeed_soc.c | 42 ++++++++--------
hw/misc/aspeed_scu.c | 106 ++++++++++++++++++++++++++++++++++++++++
hw/timer/aspeed_timer.c | 19 +++++--
5 files changed, 213 insertions(+), 28 deletions(-)
--
2.13.6
^ permalink raw reply [flat|nested] 11+ messages in thread
* [Qemu-devel] [PATCH v2 1/3] aspeed/scu: introduce clock frequencies
2018-06-22 7:56 [Qemu-devel] [PATCH v2 0/3] aspeed: introduce the APB clock settings Cédric Le Goater
@ 2018-06-22 7:56 ` Cédric Le Goater
2018-06-25 0:54 ` Andrew Jeffery
2018-06-22 7:56 ` [Qemu-devel] [PATCH v2 2/3] aspeed: initialize the SCU controller first Cédric Le Goater
` (3 subsequent siblings)
4 siblings, 1 reply; 11+ messages in thread
From: Cédric Le Goater @ 2018-06-22 7:56 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, Peter Maydell, Joel Stanley, Andrew Jeffery,
Cédric Le Goater
All Aspeed SoC clocks are driven by an input source clock which can
have different frequencies : 24MHz or 25MHz, and also, on the Aspeed
AST2400 SoC, 48MHz. The H-PLL (CPU) clock is defined from a
calculation using parameters in the H-PLL Parameter register or from a
predefined set of frequencies if the setting is strapped by hardware
(Aspeed AST2400 SoC). The other clocks of the SoC are then defined
from the H-PLL using dividers.
We introduce first the APB clock because it should be used to drive
the Aspeed timer model.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/misc/aspeed_scu.h | 70 ++++++++++++++++++++++++++--
hw/misc/aspeed_scu.c | 106 +++++++++++++++++++++++++++++++++++++++++++
2 files changed, 172 insertions(+), 4 deletions(-)
diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h
index d70cc0aeca61..f662c38188f4 100644
--- a/include/hw/misc/aspeed_scu.h
+++ b/include/hw/misc/aspeed_scu.h
@@ -30,6 +30,10 @@ typedef struct AspeedSCUState {
uint32_t hw_strap1;
uint32_t hw_strap2;
uint32_t hw_prot_key;
+
+ uint32_t clkin;
+ uint32_t hpll;
+ uint32_t apb_freq;
} AspeedSCUState;
#define AST2400_A0_SILICON_REV 0x02000303U
@@ -58,7 +62,64 @@ extern bool is_supported_silicon_rev(uint32_t silicon_rev);
* 1. 2012/12/29 Ryan Chen Create
*/
-/* Hardware Strapping Register definition (for Aspeed AST2400 SOC)
+/* SCU08 Clock Selection Register
+ *
+ * 31 Enable Video Engine clock dynamic slow down
+ * 30:28 Video Engine clock slow down setting
+ * 27 2D Engine GCLK clock source selection
+ * 26 2D Engine GCLK clock throttling enable
+ * 25:23 APB PCLK divider selection
+ * 22:20 LPC Host LHCLK divider selection
+ * 19 LPC Host LHCLK clock generation/output enable control
+ * 18:16 MAC AHB bus clock divider selection
+ * 15 SD/SDIO clock running enable
+ * 14:12 SD/SDIO divider selection
+ * 11 Reserved
+ * 10:8 Video port output clock delay control bit
+ * 7 ARM CPU/AHB clock slow down enable
+ * 6:4 ARM CPU/AHB clock slow down setting
+ * 3:2 ECLK clock source selection
+ * 1 CPU/AHB clock slow down idle timer
+ * 0 CPU/AHB clock dynamic slow down enable (defined in bit[6:4])
+ */
+#define SCU_CLK_GET_PCLK_DIV(x) (((x) >> 23) & 0x7)
+
+/* SCU24 H-PLL Parameter Register (for Aspeed AST2400 SOC)
+ *
+ * 18 H-PLL parameter selection
+ * 0: Select H-PLL by strapping resistors
+ * 1: Select H-PLL by the programmed registers (SCU24[17:0])
+ * 17 Enable H-PLL bypass mode
+ * 16 Turn off H-PLL
+ * 10:5 H-PLL Numerator
+ * 4 H-PLL Output Divider
+ * 3:0 H-PLL Denumerator
+ *
+ * (Output frequency) = 24MHz * (2-OD) * [(Numerator+2) / (Denumerator+1)]
+ */
+
+#define SCU_AST2400_H_PLL_PROGRAMMED (0x1 << 18)
+#define SCU_AST2400_H_PLL_BYPASS_EN (0x1 << 17)
+#define SCU_AST2400_H_PLL_OFF (0x1 << 16)
+
+/* SCU24 H-PLL Parameter Register (for Aspeed AST2500 SOC)
+ *
+ * 21 Enable H-PLL reset
+ * 20 Enable H-PLL bypass mode
+ * 19 Turn off H-PLL
+ * 18:13 H-PLL Post Divider
+ * 12:5 H-PLL Numerator (M)
+ * 4:0 H-PLL Denumerator (N)
+ *
+ * (Output frequency) = CLKIN(24MHz) * [(M+1) / (N+1)] / (P+1)
+ *
+ * The default frequency is 792Mhz when CLKIN = 24MHz
+ */
+
+#define SCU_H_PLL_BYPASS_EN (0x1 << 20)
+#define SCU_H_PLL_OFF (0x1 << 19)
+
+/* SCU70 Hardware Strapping Register definition (for Aspeed AST2400 SOC)
*
* 31:29 Software defined strapping registers
* 28:27 DRAM size setting (for VGA driver use)
@@ -107,12 +168,13 @@ extern bool is_supported_silicon_rev(uint32_t silicon_rev);
#define SCU_AST2400_HW_STRAP_GET_CLK_SOURCE(x) (((((x) >> 23) & 0x1) << 1) \
| (((x) >> 18) & 0x1))
#define SCU_AST2400_HW_STRAP_CLK_SOURCE_MASK ((0x1 << 23) | (0x1 << 18))
-#define AST2400_CLK_25M_IN (0x1 << 23)
+#define SCU_HW_STRAP_CLK_25M_IN (0x1 << 23)
#define AST2400_CLK_24M_IN 0
#define AST2400_CLK_48M_IN 1
#define AST2400_CLK_25M_IN_24M_USB_CKI 2
#define AST2400_CLK_25M_IN_48M_USB_CKI 3
+#define SCU_HW_STRAP_CLK_48M_IN (0x1 << 18)
#define SCU_HW_STRAP_2ND_BOOT_WDT (0x1 << 17)
#define SCU_HW_STRAP_SUPER_IO_CONFIG (0x1 << 16)
#define SCU_HW_STRAP_VGA_CLASS_CODE (0x1 << 15)
@@ -160,8 +222,8 @@ extern bool is_supported_silicon_rev(uint32_t silicon_rev);
#define AST2400_DIS_BOOT 3
/*
- * Hardware strapping register definition (for Aspeed AST2500 SoC and
- * higher)
+ * SCU70 Hardware strapping register definition (for Aspeed AST2500
+ * SoC and higher)
*
* 31 Enable SPI Flash Strap Auto Fetch Mode
* 30 Enable GPIO Strap Mode
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index 59315010db9a..59333b50abdd 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -168,6 +168,27 @@ static uint32_t aspeed_scu_get_random(void)
return num;
}
+static void aspeed_scu_set_apb_freq(AspeedSCUState *s)
+{
+ uint32_t apb_divider;
+
+ switch (s->silicon_rev) {
+ case AST2400_A0_SILICON_REV:
+ case AST2400_A1_SILICON_REV:
+ apb_divider = 2;
+ break;
+ case AST2500_A0_SILICON_REV:
+ case AST2500_A1_SILICON_REV:
+ apb_divider = 4;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ s->apb_freq = s->hpll / (SCU_CLK_GET_PCLK_DIV(s->regs[CLK_SEL]) + 1)
+ / apb_divider;
+}
+
static uint64_t aspeed_scu_read(void *opaque, hwaddr offset, unsigned size)
{
AspeedSCUState *s = ASPEED_SCU(opaque);
@@ -222,6 +243,10 @@ static void aspeed_scu_write(void *opaque, hwaddr offset, uint64_t data,
case PROT_KEY:
s->regs[reg] = (data == ASPEED_SCU_PROT_KEY) ? 1 : 0;
return;
+ case CLK_SEL:
+ s->regs[reg] = data;
+ aspeed_scu_set_apb_freq(s);
+ break;
case FREQ_CNTR_EVAL:
case VGA_SCRATCH1 ... VGA_SCRATCH8:
@@ -247,19 +272,93 @@ static const MemoryRegionOps aspeed_scu_ops = {
.valid.unaligned = false,
};
+static uint32_t aspeed_scu_get_clkin(AspeedSCUState *s)
+{
+ if (s->hw_strap1 & SCU_HW_STRAP_CLK_25M_IN) {
+ return 25000000;
+ } else if (s->hw_strap1 & SCU_HW_STRAP_CLK_48M_IN) {
+ return 48000000;
+ } else {
+ return 24000000;
+ }
+}
+
+/*
+ * Strapped frequencies for the AST2400 in MHz. They depend on the
+ * clkin frequency.
+ */
+static const uint32_t hpll_ast2400_freqs[][4] = {
+ { 384, 360, 336, 408 }, /* 24MHz or 48MHz */
+ { 400, 375, 350, 425 }, /* 25MHz */
+};
+
+static uint32_t aspeed_scu_calc_hpll_ast2400(AspeedSCUState *s)
+{
+ uint32_t hpll_reg = s->regs[HPLL_PARAM];
+ uint8_t freq_select;
+ bool clk_25m_in;
+
+ if (hpll_reg & SCU_AST2400_H_PLL_OFF) {
+ return 0;
+ }
+
+ if (hpll_reg & SCU_AST2400_H_PLL_PROGRAMMED) {
+ uint32_t multiplier = 1;
+
+ if (!(hpll_reg & SCU_AST2400_H_PLL_BYPASS_EN)) {
+ uint32_t n = (hpll_reg >> 5) & 0x3f;
+ uint32_t od = (hpll_reg >> 4) & 0x1;
+ uint32_t d = hpll_reg & 0xf;
+
+ multiplier = (2 - od) * ((n + 2) / (d + 1));
+ }
+
+ return s->clkin * multiplier;
+ }
+
+ /* HW strapping */
+ clk_25m_in = !!(s->hw_strap1 & SCU_HW_STRAP_CLK_25M_IN);
+ freq_select = SCU_AST2400_HW_STRAP_GET_H_PLL_CLK(s->hw_strap1);
+
+ return hpll_ast2400_freqs[clk_25m_in][freq_select] * 1000000;
+}
+
+static uint32_t aspeed_scu_calc_hpll_ast2500(AspeedSCUState *s)
+{
+ uint32_t hpll_reg = s->regs[HPLL_PARAM];
+ uint32_t multiplier = 1;
+
+ if (hpll_reg & SCU_H_PLL_OFF) {
+ return 0;
+ }
+
+ if (!(hpll_reg & SCU_H_PLL_BYPASS_EN)) {
+ uint32_t p = (hpll_reg >> 13) & 0x3f;
+ uint32_t m = (hpll_reg >> 5) & 0xff;
+ uint32_t n = hpll_reg & 0x1f;
+
+ multiplier = ((m + 1) / (n + 1)) / (p + 1);
+ }
+
+ return s->clkin * multiplier;
+}
+
static void aspeed_scu_reset(DeviceState *dev)
{
AspeedSCUState *s = ASPEED_SCU(dev);
const uint32_t *reset;
+ uint32_t (*calc_hpll)(AspeedSCUState *s);
switch (s->silicon_rev) {
case AST2400_A0_SILICON_REV:
case AST2400_A1_SILICON_REV:
reset = ast2400_a0_resets;
+ calc_hpll = aspeed_scu_calc_hpll_ast2400;
break;
case AST2500_A0_SILICON_REV:
case AST2500_A1_SILICON_REV:
reset = ast2500_a1_resets;
+ calc_hpll = aspeed_scu_calc_hpll_ast2500;
break;
default:
g_assert_not_reached();
@@ -270,6 +369,13 @@ static void aspeed_scu_reset(DeviceState *dev)
s->regs[HW_STRAP1] = s->hw_strap1;
s->regs[HW_STRAP2] = s->hw_strap2;
s->regs[PROT_KEY] = s->hw_prot_key;
+
+ /*
+ * All registers are set. Now compute the frequencies of the main clocks
+ */
+ s->clkin = aspeed_scu_get_clkin(s);
+ s->hpll = calc_hpll(s);
+ aspeed_scu_set_apb_freq(s);
}
static uint32_t aspeed_silicon_revs[] = {
--
2.13.6
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Qemu-devel] [PATCH v2 2/3] aspeed: initialize the SCU controller first
2018-06-22 7:56 [Qemu-devel] [PATCH v2 0/3] aspeed: introduce the APB clock settings Cédric Le Goater
2018-06-22 7:56 ` [Qemu-devel] [PATCH v2 1/3] aspeed/scu: introduce clock frequencies Cédric Le Goater
@ 2018-06-22 7:56 ` Cédric Le Goater
2018-06-25 0:54 ` Andrew Jeffery
2018-06-22 7:57 ` [Qemu-devel] [PATCH v2 3/3] aspeed/timer: use the APB frequency from the SCU Cédric Le Goater
` (2 subsequent siblings)
4 siblings, 1 reply; 11+ messages in thread
From: Cédric Le Goater @ 2018-06-22 7:56 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, Peter Maydell, Joel Stanley, Andrew Jeffery,
Cédric Le Goater
The System Control Unit should be initialized first as it drives all
the configuration of the SoC and other device models.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
---
hw/arm/aspeed_soc.c | 40 ++++++++++++++++++++--------------------
1 file changed, 20 insertions(+), 20 deletions(-)
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index 1955a892f4a4..7cc05ee27ea4 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -109,18 +109,6 @@ static void aspeed_soc_init(Object *obj)
object_initialize(&s->cpu, sizeof(s->cpu), sc->info->cpu_type);
object_property_add_child(obj, "cpu", OBJECT(&s->cpu), NULL);
- object_initialize(&s->vic, sizeof(s->vic), TYPE_ASPEED_VIC);
- object_property_add_child(obj, "vic", OBJECT(&s->vic), NULL);
- qdev_set_parent_bus(DEVICE(&s->vic), sysbus_get_default());
-
- object_initialize(&s->timerctrl, sizeof(s->timerctrl), TYPE_ASPEED_TIMER);
- object_property_add_child(obj, "timerctrl", OBJECT(&s->timerctrl), NULL);
- qdev_set_parent_bus(DEVICE(&s->timerctrl), sysbus_get_default());
-
- object_initialize(&s->i2c, sizeof(s->i2c), TYPE_ASPEED_I2C);
- object_property_add_child(obj, "i2c", OBJECT(&s->i2c), NULL);
- qdev_set_parent_bus(DEVICE(&s->i2c), sysbus_get_default());
-
object_initialize(&s->scu, sizeof(s->scu), TYPE_ASPEED_SCU);
object_property_add_child(obj, "scu", OBJECT(&s->scu), NULL);
qdev_set_parent_bus(DEVICE(&s->scu), sysbus_get_default());
@@ -133,6 +121,18 @@ static void aspeed_soc_init(Object *obj)
object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
"hw-prot-key", &error_abort);
+ object_initialize(&s->vic, sizeof(s->vic), TYPE_ASPEED_VIC);
+ object_property_add_child(obj, "vic", OBJECT(&s->vic), NULL);
+ qdev_set_parent_bus(DEVICE(&s->vic), sysbus_get_default());
+
+ object_initialize(&s->timerctrl, sizeof(s->timerctrl), TYPE_ASPEED_TIMER);
+ object_property_add_child(obj, "timerctrl", OBJECT(&s->timerctrl), NULL);
+ qdev_set_parent_bus(DEVICE(&s->timerctrl), sysbus_get_default());
+
+ object_initialize(&s->i2c, sizeof(s->i2c), TYPE_ASPEED_I2C);
+ object_property_add_child(obj, "i2c", OBJECT(&s->i2c), NULL);
+ qdev_set_parent_bus(DEVICE(&s->i2c), sysbus_get_default());
+
object_initialize(&s->fmc, sizeof(s->fmc), sc->info->fmc_typename);
object_property_add_child(obj, "fmc", OBJECT(&s->fmc), NULL);
qdev_set_parent_bus(DEVICE(&s->fmc), sysbus_get_default());
@@ -195,6 +195,14 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
memory_region_add_subregion(get_system_memory(), ASPEED_SOC_SRAM_BASE,
&s->sram);
+ /* SCU */
+ object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, ASPEED_SOC_SCU_BASE);
+
/* VIC */
object_property_set_bool(OBJECT(&s->vic), true, "realized", &err);
if (err) {
@@ -219,14 +227,6 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
}
- /* SCU */
- object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
- if (err) {
- error_propagate(errp, err);
- return;
- }
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, ASPEED_SOC_SCU_BASE);
-
/* UART - attach an 8250 to the IO space as our UART5 */
if (serial_hd(0)) {
qemu_irq uart5 = qdev_get_gpio_in(DEVICE(&s->vic), uart_irqs[4]);
--
2.13.6
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Qemu-devel] [PATCH v2 3/3] aspeed/timer: use the APB frequency from the SCU
2018-06-22 7:56 [Qemu-devel] [PATCH v2 0/3] aspeed: introduce the APB clock settings Cédric Le Goater
2018-06-22 7:56 ` [Qemu-devel] [PATCH v2 1/3] aspeed/scu: introduce clock frequencies Cédric Le Goater
2018-06-22 7:56 ` [Qemu-devel] [PATCH v2 2/3] aspeed: initialize the SCU controller first Cédric Le Goater
@ 2018-06-22 7:57 ` Cédric Le Goater
2018-06-25 0:59 ` Andrew Jeffery
2018-08-31 8:34 ` Thomas Huth
2018-06-22 11:14 ` [Qemu-devel] [PATCH v2 0/3] aspeed: introduce the APB clock settings no-reply
2018-06-26 16:05 ` Peter Maydell
4 siblings, 2 replies; 11+ messages in thread
From: Cédric Le Goater @ 2018-06-22 7:57 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, Peter Maydell, Joel Stanley, Andrew Jeffery,
Cédric Le Goater
The timer controller can be driven by either an external 1MHz clock or
by the APB clock. Today, the model makes the assumption that the APB
frequency is always set to 24MHz but this is incorrect.
The AST2400 SoC on the palmetto machines uses a 48MHz input clock
source and the APB can be set to 48MHz. The consequence is a general
system slowdown. The QEMU machines using the AST2500 SoC do not seem
impacted today because the APB frequency is still set to 24MHz.
We fix the timer frequency for all SoCs by linking the Timer model to
the SCU model. The APB frequency driving the timers is now the one
configured for the SoC.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
---
include/hw/timer/aspeed_timer.h | 4 ++++
hw/arm/aspeed_soc.c | 2 ++
hw/timer/aspeed_timer.c | 19 +++++++++++++++----
3 files changed, 21 insertions(+), 4 deletions(-)
diff --git a/include/hw/timer/aspeed_timer.h b/include/hw/timer/aspeed_timer.h
index bd6c1a7f9609..040a08873432 100644
--- a/include/hw/timer/aspeed_timer.h
+++ b/include/hw/timer/aspeed_timer.h
@@ -24,6 +24,8 @@
#include "qemu/timer.h"
+typedef struct AspeedSCUState AspeedSCUState;
+
#define ASPEED_TIMER(obj) \
OBJECT_CHECK(AspeedTimerCtrlState, (obj), TYPE_ASPEED_TIMER);
#define TYPE_ASPEED_TIMER "aspeed.timer"
@@ -55,6 +57,8 @@ typedef struct AspeedTimerCtrlState {
uint32_t ctrl;
uint32_t ctrl2;
AspeedTimer timers[ASPEED_TIMER_NR_TIMERS];
+
+ AspeedSCUState *scu;
} AspeedTimerCtrlState;
#endif /* ASPEED_TIMER_H */
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index 7cc05ee27ea4..e68911af0f90 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -127,6 +127,8 @@ static void aspeed_soc_init(Object *obj)
object_initialize(&s->timerctrl, sizeof(s->timerctrl), TYPE_ASPEED_TIMER);
object_property_add_child(obj, "timerctrl", OBJECT(&s->timerctrl), NULL);
+ object_property_add_const_link(OBJECT(&s->timerctrl), "scu",
+ OBJECT(&s->scu), &error_abort);
qdev_set_parent_bus(DEVICE(&s->timerctrl), sysbus_get_default());
object_initialize(&s->i2c, sizeof(s->i2c), TYPE_ASPEED_I2C);
diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c
index 1e31e22b6f1f..5e3f51b66b43 100644
--- a/hw/timer/aspeed_timer.c
+++ b/hw/timer/aspeed_timer.c
@@ -10,8 +10,10 @@
*/
#include "qemu/osdep.h"
+#include "qapi/error.h"
#include "hw/sysbus.h"
#include "hw/timer/aspeed_timer.h"
+#include "hw/misc/aspeed_scu.h"
#include "qemu-common.h"
#include "qemu/bitops.h"
#include "qemu/timer.h"
@@ -26,7 +28,6 @@
#define TIMER_CLOCK_USE_EXT true
#define TIMER_CLOCK_EXT_HZ 1000000
#define TIMER_CLOCK_USE_APB false
-#define TIMER_CLOCK_APB_HZ 24000000
#define TIMER_REG_STATUS 0
#define TIMER_REG_RELOAD 1
@@ -80,11 +81,11 @@ static inline bool timer_external_clock(AspeedTimer *t)
return timer_ctrl_status(t, op_external_clock);
}
-static uint32_t clock_rates[] = { TIMER_CLOCK_APB_HZ, TIMER_CLOCK_EXT_HZ };
-
static inline uint32_t calculate_rate(struct AspeedTimer *t)
{
- return clock_rates[timer_external_clock(t)];
+ AspeedTimerCtrlState *s = timer_to_ctrl(t);
+
+ return timer_external_clock(t) ? TIMER_CLOCK_EXT_HZ : s->scu->apb_freq;
}
static inline uint32_t calculate_ticks(struct AspeedTimer *t, uint64_t now_ns)
@@ -449,6 +450,16 @@ static void aspeed_timer_realize(DeviceState *dev, Error **errp)
int i;
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
AspeedTimerCtrlState *s = ASPEED_TIMER(dev);
+ Object *obj;
+ Error *err = NULL;
+
+ obj = object_property_get_link(OBJECT(dev), "scu", &err);
+ if (!obj) {
+ error_propagate(errp, err);
+ error_prepend(errp, "required link 'scu' not found: ");
+ return;
+ }
+ s->scu = ASPEED_SCU(obj);
for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
aspeed_init_one_timer(s, i);
--
2.13.6
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [Qemu-devel] [PATCH v2 0/3] aspeed: introduce the APB clock settings
2018-06-22 7:56 [Qemu-devel] [PATCH v2 0/3] aspeed: introduce the APB clock settings Cédric Le Goater
` (2 preceding siblings ...)
2018-06-22 7:57 ` [Qemu-devel] [PATCH v2 3/3] aspeed/timer: use the APB frequency from the SCU Cédric Le Goater
@ 2018-06-22 11:14 ` no-reply
2018-06-26 16:05 ` Peter Maydell
4 siblings, 0 replies; 11+ messages in thread
From: no-reply @ 2018-06-22 11:14 UTC (permalink / raw)
To: clg; +Cc: famz, qemu-devel, andrew, peter.maydell, qemu-arm, joel
Hi,
This series failed docker-mingw@fedora build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
Type: series
Message-id: 20180622075700.5923-1-clg@kaod.org
Subject: [Qemu-devel] [PATCH v2 0/3] aspeed: introduce the APB clock settings
=== TEST SCRIPT BEGIN ===
#!/bin/bash
set -e
git submodule update --init dtc
# Let docker tests dump environment info
export SHOW_ENV=1
export J=8
time make docker-test-mingw@fedora
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
33836a7315..de44c04442 master -> master
Switched to a new branch 'test'
f88089e372 aspeed/timer: use the APB frequency from the SCU
885a96dc9b aspeed: initialize the SCU controller first
1518b02694 aspeed/scu: introduce clock frequencies
=== OUTPUT BEGIN ===
Submodule 'dtc' (git://git.qemu-project.org/dtc.git) registered for path 'dtc'
Cloning into '/var/tmp/patchew-tester-tmp-6_su1war/src/dtc'...
Submodule path 'dtc': checked out 'e54388015af1fb4bf04d0bca99caba1074d9cc42'
BUILD fedora
make[1]: Entering directory '/var/tmp/patchew-tester-tmp-6_su1war/src'
GEN /var/tmp/patchew-tester-tmp-6_su1war/src/docker-src.2018-06-22-07.12.36.16942/qemu.tar
Cloning into '/var/tmp/patchew-tester-tmp-6_su1war/src/docker-src.2018-06-22-07.12.36.16942/qemu.tar.vroot'...
done.
Checking out files: 18% (1135/6275)
Checking out files: 19% (1193/6275)
Checking out files: 20% (1255/6275)
Checking out files: 21% (1318/6275)
Checking out files: 22% (1381/6275)
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Checking out files: 24% (1506/6275)
Checking out files: 25% (1569/6275)
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Checking out files: 27% (1695/6275)
Checking out files: 28% (1757/6275)
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Checking out files: 30% (1883/6275)
Checking out files: 31% (1946/6275)
Checking out files: 32% (2008/6275)
Checking out files: 33% (2071/6275)
Checking out files: 34% (2134/6275)
Checking out files: 35% (2197/6275)
Checking out files: 36% (2259/6275)
Checking out files: 37% (2322/6275)
Checking out files: 38% (2385/6275)
Checking out files: 39% (2448/6275)
Checking out files: 40% (2510/6275)
Checking out files: 41% (2573/6275)
Checking out files: 42% (2636/6275)
Checking out files: 43% (2699/6275)
Checking out files: 44% (2761/6275)
Checking out files: 45% (2824/6275)
Checking out files: 46% (2887/6275)
Checking out files: 47% (2950/6275)
Checking out files: 48% (3012/6275)
Checking out files: 49% (3075/6275)
Checking out files: 50% (3138/6275)
Checking out files: 51% (3201/6275)
Checking out files: 52% (3263/6275)
Checking out files: 53% (3326/6275)
Checking out files: 54% (3389/6275)
Checking out files: 55% (3452/6275)
Checking out files: 56% (3514/6275)
Checking out files: 57% (3577/6275)
Checking out files: 58% (3640/6275)
Checking out files: 59% (3703/6275)
Checking out files: 60% (3765/6275)
Checking out files: 61% (3828/6275)
Checking out files: 62% (3891/6275)
Checking out files: 63% (3954/6275)
Checking out files: 64% (4016/6275)
Checking out files: 65% (4079/6275)
Checking out files: 66% (4142/6275)
Checking out files: 67% (4205/6275)
Checking out files: 68% (4267/6275)
Checking out files: 69% (4330/6275)
Checking out files: 70% (4393/6275)
Checking out files: 71% (4456/6275)
Checking out files: 72% (4518/6275)
Checking out files: 73% (4581/6275)
Checking out files: 74% (4644/6275)
Checking out files: 75% (4707/6275)
Checking out files: 76% (4769/6275)
Checking out files: 77% (4832/6275)
Checking out files: 78% (4895/6275)
Checking out files: 79% (4958/6275)
Checking out files: 80% (5020/6275)
Checking out files: 81% (5083/6275)
Checking out files: 82% (5146/6275)
Checking out files: 83% (5209/6275)
Checking out files: 84% (5271/6275)
Checking out files: 85% (5334/6275)
Checking out files: 86% (5397/6275)
Checking out files: 87% (5460/6275)
Checking out files: 88% (5522/6275)
Checking out files: 89% (5585/6275)
Checking out files: 90% (5648/6275)
Checking out files: 91% (5711/6275)
Checking out files: 92% (5773/6275)
Checking out files: 93% (5836/6275)
Checking out files: 94% (5899/6275)
Checking out files: 95% (5962/6275)
Checking out files: 96% (6024/6275)
Checking out files: 97% (6087/6275)
Checking out files: 98% (6150/6275)
Checking out files: 99% (6213/6275)
Checking out files: 100% (6275/6275)
Checking out files: 100% (6275/6275), done.
Your branch is up-to-date with 'origin/test'.
Submodule 'dtc' (git://git.qemu-project.org/dtc.git) registered for path 'dtc'
Cloning into '/var/tmp/patchew-tester-tmp-6_su1war/src/docker-src.2018-06-22-07.12.36.16942/qemu.tar.vroot/dtc'...
Submodule path 'dtc': checked out 'e54388015af1fb4bf04d0bca99caba1074d9cc42'
Submodule 'ui/keycodemapdb' (git://git.qemu.org/keycodemapdb.git) registered for path 'ui/keycodemapdb'
Cloning into '/var/tmp/patchew-tester-tmp-6_su1war/src/docker-src.2018-06-22-07.12.36.16942/qemu.tar.vroot/ui/keycodemapdb'...
Submodule path 'ui/keycodemapdb': checked out '6b3d716e2b6472eb7189d3220552280ef3d832ce'
COPY RUNNER
RUN test-mingw in qemu:fedora
Packages installed:
SDL2-devel-2.0.8-5.fc28.x86_64
bc-1.07.1-5.fc28.x86_64
bison-3.0.4-9.fc28.x86_64
bluez-libs-devel-5.49-3.fc28.x86_64
brlapi-devel-0.6.7-12.fc28.x86_64
bzip2-1.0.6-26.fc28.x86_64
bzip2-devel-1.0.6-26.fc28.x86_64
ccache-3.4.2-2.fc28.x86_64
clang-6.0.0-5.fc28.x86_64
device-mapper-multipath-devel-0.7.4-2.git07e7bd5.fc28.x86_64
findutils-4.6.0-19.fc28.x86_64
flex-2.6.1-7.fc28.x86_64
gcc-8.1.1-1.fc28.x86_64
gcc-c++-8.1.1-1.fc28.x86_64
gettext-0.19.8.1-14.fc28.x86_64
git-2.17.1-2.fc28.x86_64
glib2-devel-2.56.1-3.fc28.x86_64
glusterfs-api-devel-4.0.2-1.fc28.x86_64
gnutls-devel-3.6.2-1.fc28.x86_64
gtk3-devel-3.22.30-1.fc28.x86_64
hostname-3.20-3.fc28.x86_64
libaio-devel-0.3.110-11.fc28.x86_64
libasan-8.1.1-1.fc28.x86_64
libattr-devel-2.4.47-23.fc28.x86_64
libcap-devel-2.25-9.fc28.x86_64
libcap-ng-devel-0.7.9-1.fc28.x86_64
libcurl-devel-7.59.0-3.fc28.x86_64
libfdt-devel-1.4.6-4.fc28.x86_64
libpng-devel-1.6.34-3.fc28.x86_64
librbd-devel-12.2.5-1.fc28.x86_64
libssh2-devel-1.8.0-7.fc28.x86_64
libubsan-8.1.1-1.fc28.x86_64
libusbx-devel-1.0.21-6.fc28.x86_64
libxml2-devel-2.9.7-4.fc28.x86_64
llvm-6.0.0-11.fc28.x86_64
lzo-devel-2.08-12.fc28.x86_64
make-4.2.1-6.fc28.x86_64
mingw32-SDL2-2.0.5-3.fc27.noarch
mingw32-bzip2-1.0.6-9.fc27.noarch
mingw32-curl-7.57.0-1.fc28.noarch
mingw32-glib2-2.54.1-1.fc28.noarch
mingw32-gmp-6.1.2-2.fc27.noarch
mingw32-gnutls-3.5.13-2.fc27.noarch
mingw32-gtk3-3.22.16-1.fc27.noarch
mingw32-libjpeg-turbo-1.5.1-3.fc27.noarch
mingw32-libpng-1.6.29-2.fc27.noarch
mingw32-libssh2-1.8.0-3.fc27.noarch
mingw32-libtasn1-4.13-1.fc28.noarch
mingw32-nettle-3.3-3.fc27.noarch
mingw32-pixman-0.34.0-3.fc27.noarch
mingw32-pkg-config-0.28-9.fc27.x86_64
mingw64-SDL2-2.0.5-3.fc27.noarch
mingw64-bzip2-1.0.6-9.fc27.noarch
mingw64-curl-7.57.0-1.fc28.noarch
mingw64-glib2-2.54.1-1.fc28.noarch
mingw64-gmp-6.1.2-2.fc27.noarch
mingw64-gnutls-3.5.13-2.fc27.noarch
mingw64-gtk3-3.22.16-1.fc27.noarch
mingw64-libjpeg-turbo-1.5.1-3.fc27.noarch
mingw64-libpng-1.6.29-2.fc27.noarch
mingw64-libssh2-1.8.0-3.fc27.noarch
mingw64-libtasn1-4.13-1.fc28.noarch
mingw64-nettle-3.3-3.fc27.noarch
mingw64-pixman-0.34.0-3.fc27.noarch
mingw64-pkg-config-0.28-9.fc27.x86_64
ncurses-devel-6.1-5.20180224.fc28.x86_64
nettle-devel-3.4-2.fc28.x86_64
nss-devel-3.36.1-1.1.fc28.x86_64
numactl-devel-2.0.11-8.fc28.x86_64
package PyYAML is not installed
package libjpeg-devel is not installed
perl-5.26.2-411.fc28.x86_64
pixman-devel-0.34.0-8.fc28.x86_64
python3-3.6.5-1.fc28.x86_64
snappy-devel-1.1.7-5.fc28.x86_64
sparse-0.5.2-1.fc28.x86_64
spice-server-devel-0.14.0-4.fc28.x86_64
systemtap-sdt-devel-3.2-11.fc28.x86_64
tar-1.30-3.fc28.x86_64
usbredir-devel-0.7.1-7.fc28.x86_64
virglrenderer-devel-0.6.0-4.20170210git76b3da97b.fc28.x86_64
vte3-devel-0.36.5-6.fc28.x86_64
which-2.21-8.fc28.x86_64
xen-devel-4.10.1-3.fc28.x86_64
zlib-devel-1.2.11-8.fc28.x86_64
Environment variables:
TARGET_LIST=
PACKAGES=ccache gettext git tar PyYAML sparse flex bison python3 bzip2 hostname gcc gcc-c++ llvm clang make perl which bc findutils glib2-devel libaio-devel pixman-devel zlib-devel libfdt-devel libasan libubsan bluez-libs-devel brlapi-devel bzip2-devel device-mapper-multipath-devel glusterfs-api-devel gnutls-devel gtk3-devel libattr-devel libcap-devel libcap-ng-devel libcurl-devel libjpeg-devel libpng-devel librbd-devel libssh2-devel libusbx-devel libxml2-devel lzo-devel ncurses-devel nettle-devel nss-devel numactl-devel SDL2-devel snappy-devel spice-server-devel systemtap-sdt-devel usbredir-devel virglrenderer-devel vte3-devel xen-devel mingw32-pixman mingw32-glib2 mingw32-gmp mingw32-SDL2 mingw32-pkg-config mingw32-gtk3 mingw32-gnutls mingw32-nettle mingw32-libtasn1 mingw32-libjpeg-turbo mingw32-libpng mingw32-curl mingw32-libssh2 mingw32-bzip2 mingw64-pixman mingw64-glib2 mingw64-gmp mingw64-SDL2 mingw64-pkg-config mingw64-gtk3 mingw64-gnutls mingw64-nettle mingw64-libtasn1 mingw64-libjpeg-turbo mingw64-libpng mingw64-curl mingw64-libssh2 mingw64-bzip2
J=8
V=
HOSTNAME=0d332f77ae3f
DEBUG=
SHOW_ENV=1
PWD=/
HOME=/root
CCACHE_DIR=/var/tmp/ccache
DISTTAG=f28container
QEMU_CONFIGURE_OPTS=--python=/usr/bin/python3
FGC=f28
TEST_DIR=/tmp/qemu-test
SHLVL=1
FEATURES=mingw clang pyyaml asan dtc
PATH=/usr/lib/ccache:/usr/lib64/ccache:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin
MAKEFLAGS= -j8
EXTRA_CONFIGURE_OPTS=
_=/usr/bin/env
Configure options:
--enable-werror --target-list=x86_64-softmmu,aarch64-softmmu --prefix=/tmp/qemu-test/install --python=/usr/bin/python3 --cross-prefix=x86_64-w64-mingw32- --enable-trace-backends=simple --enable-gnutls --enable-nettle --enable-curl --enable-vnc --enable-bzip2 --enable-guest-agent --with-sdlabi=2.0 --with-gtkabi=3.0
Install prefix /tmp/qemu-test/install
BIOS directory /tmp/qemu-test/install
firmware path /tmp/qemu-test/install/share/qemu-firmware
binary directory /tmp/qemu-test/install
library directory /tmp/qemu-test/install/lib
module directory /tmp/qemu-test/install/lib
libexec directory /tmp/qemu-test/install/libexec
include directory /tmp/qemu-test/install/include
config directory /tmp/qemu-test/install
local state directory queried at runtime
Windows SDK no
Source path /tmp/qemu-test/src
GIT binary git
GIT submodules
C compiler x86_64-w64-mingw32-gcc
Host C compiler cc
C++ compiler x86_64-w64-mingw32-g++
Objective-C compiler clang
ARFLAGS rv
CFLAGS -O2 -U_FORTIFY_SOURCE -D_FORTIFY_SOURCE=2 -g
QEMU_CFLAGS -I/usr/x86_64-w64-mingw32/sys-root/mingw/include/pixman-1 -I$(SRC_PATH)/dtc/libfdt -Werror -DHAS_LIBSSH2_SFTP_FSYNC -mms-bitfields -I/usr/x86_64-w64-mingw32/sys-root/mingw/include/glib-2.0 -I/usr/x86_64-w64-mingw32/sys-root/mingw/lib/glib-2.0/include -I/usr/x86_64-w64-mingw32/sys-root/mingw/include -m64 -mcx16 -mthreads -D__USE_MINGW_ANSI_STDIO=1 -DWIN32_LEAN_AND_MEAN -DWINVER=0x501 -D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE -Wstrict-prototypes -Wredundant-decls -Wall -Wundef -Wwrite-strings -Wmissing-prototypes -fno-strict-aliasing -fno-common -fwrapv -Wexpansion-to-defined -Wendif-labels -Wno-shift-negative-value -Wno-missing-include-dirs -Wempty-body -Wnested-externs -Wformat-security -Wformat-y2k -Winit-self -Wignored-qualifiers -Wold-style-declaration -Wold-style-definition -Wtype-limits -fstack-protector-strong -I/usr/x86_64-w64-mingw32/sys-root/mingw/include -I/usr/x86_64-w64-mingw32/sys-root/mingw/include/p11-kit-1 -I/usr/x86_64-w64-mingw32/sys-root/mingw/include -I/usr/x86_64-w64-mingw32/sys-root/mingw/include -I/usr/x86_64-w64-mingw32/sys-root/mingw/include/libpng16
LDFLAGS -Wl,--nxcompat -Wl,--no-seh -Wl,--dynamicbase -Wl,--warn-common -m64 -g
QEMU_LDFLAGS -L$(BUILD_DIR)/dtc/libfdt
make make
install install
python /usr/bin/python3 -B
smbd /usr/sbin/smbd
module support no
host CPU x86_64
host big endian no
target list x86_64-softmmu aarch64-softmmu
gprof enabled no
sparse enabled no
strip binaries yes
profiler no
static build no
SDL support yes (2.0.5)
GTK support yes (3.22.16)
GTK GL support no
VTE support no
TLS priority NORMAL
GNUTLS support yes
GNUTLS rnd yes
libgcrypt no
libgcrypt kdf no
nettle yes (3.3)
nettle kdf yes
libtasn1 yes
curses support no
virgl support no
curl support yes
mingw32 support yes
Audio drivers dsound
Block whitelist (rw)
Block whitelist (ro)
VirtFS support no
Multipath support no
VNC support yes
VNC SASL support no
VNC JPEG support yes
VNC PNG support yes
xen support no
brlapi support no
bluez support no
Documentation no
PIE no
vde support no
netmap support no
Linux AIO support no
ATTR/XATTR support no
Install blobs yes
KVM support no
HAX support yes
HVF support no
WHPX support no
TCG support yes
TCG debug enabled no
TCG interpreter no
malloc trim support no
RDMA support no
fdt support git
membarrier no
preadv support no
fdatasync no
madvise no
posix_madvise no
posix_memalign no
libcap-ng support no
vhost-net support no
vhost-crypto support no
vhost-scsi support no
vhost-vsock support no
vhost-user support no
Trace backends simple
Trace output file trace-<pid>
spice support no
rbd support no
xfsctl support no
smartcard support no
libusb no
usb net redir no
OpenGL support no
OpenGL dmabufs no
libiscsi support no
libnfs support no
build guest agent yes
QGA VSS support no
QGA w32 disk info yes
QGA MSI support no
seccomp support no
coroutine backend win32
coroutine pool yes
debug stack usage no
crypto afalg no
GlusterFS support no
gcov gcov
gcov enabled no
TPM support yes
libssh2 support yes
TPM passthrough no
TPM emulator no
QOM debugging yes
Live block migration yes
lzo support no
snappy support no
bzip2 support yes
NUMA host support no
libxml2 no
tcmalloc support no
jemalloc support no
avx2 optimization yes
replication support yes
VxHS block device no
capstone no
docker no
NOTE: cross-compilers enabled: 'x86_64-w64-mingw32-gcc'
GEN x86_64-softmmu/config-devices.mak.tmp
GEN aarch64-softmmu/config-devices.mak.tmp
GEN qemu-options.def
GEN config-host.h
GEN qapi-gen
GEN trace/generated-helpers-wrappers.h
GEN trace/generated-tcg-tracers.h
GEN trace/generated-helpers.h
GEN trace/generated-helpers.c
GEN aarch64-softmmu/config-devices.mak
GEN module_block.h
GEN x86_64-softmmu/config-devices.mak
GEN ui/input-keymap-atset1-to-qcode.c
GEN ui/input-keymap-qcode-to-atset1.c
GEN ui/input-keymap-qcode-to-atset2.c
GEN ui/input-keymap-linux-to-qcode.c
GEN ui/input-keymap-qcode-to-atset3.c
GEN ui/input-keymap-qcode-to-linux.c
GEN ui/input-keymap-qcode-to-qnum.c
GEN ui/input-keymap-qcode-to-sun.c
GEN ui/input-keymap-qnum-to-qcode.c
GEN ui/input-keymap-usb-to-qcode.c
GEN ui/input-keymap-win32-to-qcode.c
GEN ui/input-keymap-x11-to-qcode.c
GEN ui/input-keymap-xorgevdev-to-qcode.c
GEN ui/input-keymap-xorgkbd-to-qcode.c
GEN ui/input-keymap-xorgxquartz-to-qcode.c
GEN ui/input-keymap-xorgxwin-to-qcode.c
GEN ui/input-keymap-osx-to-qcode.c
GEN tests/test-qapi-gen
GEN trace-root.h
GEN accel/kvm/trace.h
GEN accel/tcg/trace.h
GEN audio/trace.h
GEN block/trace.h
GEN chardev/trace.h
GEN crypto/trace.h
GEN hw/9pfs/trace.h
GEN hw/acpi/trace.h
GEN hw/alpha/trace.h
GEN hw/arm/trace.h
GEN hw/audio/trace.h
GEN hw/block/trace.h
GEN hw/block/dataplane/trace.h
GEN hw/char/trace.h
GEN hw/display/trace.h
GEN hw/dma/trace.h
GEN hw/hppa/trace.h
GEN hw/i2c/trace.h
GEN hw/i386/trace.h
GEN hw/i386/xen/trace.h
GEN hw/ide/trace.h
GEN hw/input/trace.h
GEN hw/intc/trace.h
GEN hw/isa/trace.h
GEN hw/mem/trace.h
GEN hw/misc/trace.h
GEN hw/misc/macio/trace.h
GEN hw/net/trace.h
GEN hw/nvram/trace.h
GEN hw/pci/trace.h
GEN hw/pci-host/trace.h
GEN hw/ppc/trace.h
GEN hw/rdma/trace.h
GEN hw/rdma/vmw/trace.h
GEN hw/s390x/trace.h
GEN hw/scsi/trace.h
GEN hw/sd/trace.h
GEN hw/sparc/trace.h
GEN hw/sparc64/trace.h
GEN hw/timer/trace.h
GEN hw/tpm/trace.h
GEN hw/usb/trace.h
GEN hw/vfio/trace.h
GEN hw/virtio/trace.h
GEN hw/xen/trace.h
GEN io/trace.h
GEN linux-user/trace.h
GEN migration/trace.h
GEN nbd/trace.h
GEN net/trace.h
GEN qapi/trace.h
GEN qom/trace.h
GEN scsi/trace.h
GEN target/arm/trace.h
GEN target/i386/trace.h
GEN target/mips/trace.h
GEN target/ppc/trace.h
GEN target/s390x/trace.h
GEN target/sparc/trace.h
GEN ui/trace.h
GEN util/trace.h
GEN trace-root.c
GEN accel/kvm/trace.c
GEN accel/tcg/trace.c
GEN audio/trace.c
GEN block/trace.c
GEN chardev/trace.c
GEN crypto/trace.c
GEN hw/9pfs/trace.c
GEN hw/acpi/trace.c
GEN hw/alpha/trace.c
GEN hw/arm/trace.c
GEN hw/audio/trace.c
GEN hw/block/trace.c
GEN hw/block/dataplane/trace.c
GEN hw/char/trace.c
GEN hw/display/trace.c
GEN hw/dma/trace.c
GEN hw/hppa/trace.c
GEN hw/i2c/trace.c
GEN hw/i386/trace.c
GEN hw/i386/xen/trace.c
GEN hw/ide/trace.c
GEN hw/input/trace.c
GEN hw/intc/trace.c
GEN hw/isa/trace.c
GEN hw/mem/trace.c
GEN hw/misc/trace.c
GEN hw/misc/macio/trace.c
GEN hw/net/trace.c
GEN hw/nvram/trace.c
GEN hw/pci/trace.c
GEN hw/pci-host/trace.c
GEN hw/ppc/trace.c
GEN hw/rdma/trace.c
GEN hw/rdma/vmw/trace.c
GEN hw/s390x/trace.c
GEN hw/scsi/trace.c
GEN hw/sd/trace.c
GEN hw/sparc/trace.c
GEN hw/sparc64/trace.c
GEN hw/timer/trace.c
GEN hw/tpm/trace.c
GEN hw/usb/trace.c
GEN hw/vfio/trace.c
GEN hw/virtio/trace.c
GEN hw/xen/trace.c
GEN io/trace.c
GEN linux-user/trace.c
GEN migration/trace.c
GEN nbd/trace.c
GEN net/trace.c
GEN qapi/trace.c
GEN qom/trace.c
GEN scsi/trace.c
GEN target/arm/trace.c
GEN target/i386/trace.c
GEN target/mips/trace.c
GEN target/ppc/trace.c
GEN target/s390x/trace.c
GEN target/sparc/trace.c
GEN ui/trace.c
GEN config-all-devices.mak
GEN util/trace.c
DEP /tmp/qemu-test/src/dtc/tests/dumptrees.c
DEP /tmp/qemu-test/src/dtc/tests/trees.S
DEP /tmp/qemu-test/src/dtc/tests/testutils.c
DEP /tmp/qemu-test/src/dtc/tests/value-labels.c
DEP /tmp/qemu-test/src/dtc/tests/asm_tree_dump.c
DEP /tmp/qemu-test/src/dtc/tests/truncated_property.c
DEP /tmp/qemu-test/src/dtc/tests/check_path.c
DEP /tmp/qemu-test/src/dtc/tests/overlay_bad_fixup.c
DEP /tmp/qemu-test/src/dtc/tests/overlay.c
DEP /tmp/qemu-test/src/dtc/tests/subnode_iterate.c
DEP /tmp/qemu-test/src/dtc/tests/property_iterate.c
DEP /tmp/qemu-test/src/dtc/tests/integer-expressions.c
DEP /tmp/qemu-test/src/dtc/tests/utilfdt_test.c
DEP /tmp/qemu-test/src/dtc/tests/path_offset_aliases.c
DEP /tmp/qemu-test/src/dtc/tests/add_subnode_with_nops.c
DEP /tmp/qemu-test/src/dtc/tests/dtbs_equal_unordered.c
DEP /tmp/qemu-test/src/dtc/tests/dtb_reverse.c
DEP /tmp/qemu-test/src/dtc/tests/dtbs_equal_ordered.c
DEP /tmp/qemu-test/src/dtc/tests/extra-terminating-null.c
DEP /tmp/qemu-test/src/dtc/tests/incbin.c
DEP /tmp/qemu-test/src/dtc/tests/boot-cpuid.c
DEP /tmp/qemu-test/src/dtc/tests/phandle_format.c
DEP /tmp/qemu-test/src/dtc/tests/path-references.c
DEP /tmp/qemu-test/src/dtc/tests/references.c
DEP /tmp/qemu-test/src/dtc/tests/string_escapes.c
DEP /tmp/qemu-test/src/dtc/tests/propname_escapes.c
DEP /tmp/qemu-test/src/dtc/tests/appendprop2.c
DEP /tmp/qemu-test/src/dtc/tests/appendprop1.c
DEP /tmp/qemu-test/src/dtc/tests/del_node.c
DEP /tmp/qemu-test/src/dtc/tests/del_property.c
DEP /tmp/qemu-test/src/dtc/tests/setprop.c
DEP /tmp/qemu-test/src/dtc/tests/set_name.c
DEP /tmp/qemu-test/src/dtc/tests/rw_tree1.c
DEP /tmp/qemu-test/src/dtc/tests/open_pack.c
DEP /tmp/qemu-test/src/dtc/tests/nopulate.c
DEP /tmp/qemu-test/src/dtc/tests/mangle-layout.c
DEP /tmp/qemu-test/src/dtc/tests/move_and_save.c
DEP /tmp/qemu-test/src/dtc/tests/sw_tree1.c
DEP /tmp/qemu-test/src/dtc/tests/nop_node.c
DEP /tmp/qemu-test/src/dtc/tests/nop_property.c
DEP /tmp/qemu-test/src/dtc/tests/setprop_inplace.c
DEP /tmp/qemu-test/src/dtc/tests/stringlist.c
DEP /tmp/qemu-test/src/dtc/tests/addr_size_cells.c
DEP /tmp/qemu-test/src/dtc/tests/notfound.c
DEP /tmp/qemu-test/src/dtc/tests/sized_cells.c
DEP /tmp/qemu-test/src/dtc/tests/char_literal.c
DEP /tmp/qemu-test/src/dtc/tests/get_alias.c
DEP /tmp/qemu-test/src/dtc/tests/node_offset_by_compatible.c
DEP /tmp/qemu-test/src/dtc/tests/node_check_compatible.c
DEP /tmp/qemu-test/src/dtc/tests/node_offset_by_phandle.c
DEP /tmp/qemu-test/src/dtc/tests/node_offset_by_prop_value.c
DEP /tmp/qemu-test/src/dtc/tests/parent_offset.c
DEP /tmp/qemu-test/src/dtc/tests/supernode_atdepth_offset.c
DEP /tmp/qemu-test/src/dtc/tests/get_path.c
DEP /tmp/qemu-test/src/dtc/tests/get_phandle.c
DEP /tmp/qemu-test/src/dtc/tests/getprop.c
DEP /tmp/qemu-test/src/dtc/tests/get_name.c
DEP /tmp/qemu-test/src/dtc/tests/path_offset.c
DEP /tmp/qemu-test/src/dtc/tests/subnode_offset.c
DEP /tmp/qemu-test/src/dtc/tests/find_property.c
DEP /tmp/qemu-test/src/dtc/tests/root_node.c
DEP /tmp/qemu-test/src/dtc/tests/get_mem_rsv.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_addresses.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_empty_tree.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_overlay.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_strerror.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_rw.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_sw.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_wip.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_ro.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt.c
DEP /tmp/qemu-test/src/dtc/util.c
DEP /tmp/qemu-test/src/dtc/fdtoverlay.c
DEP /tmp/qemu-test/src/dtc/fdtget.c
DEP /tmp/qemu-test/src/dtc/fdtput.c
DEP /tmp/qemu-test/src/dtc/fdtdump.c
DEP /tmp/qemu-test/src/dtc/srcpos.c
LEX convert-dtsv0-lexer.lex.c
BISON dtc-parser.tab.c
DEP /tmp/qemu-test/src/dtc/treesource.c
LEX dtc-lexer.lex.c
DEP /tmp/qemu-test/src/dtc/livetree.c
DEP /tmp/qemu-test/src/dtc/fstree.c
DEP /tmp/qemu-test/src/dtc/flattree.c
DEP /tmp/qemu-test/src/dtc/dtc.c
DEP /tmp/qemu-test/src/dtc/data.c
DEP /tmp/qemu-test/src/dtc/checks.c
DEP convert-dtsv0-lexer.lex.c
DEP dtc-parser.tab.c
DEP dtc-lexer.lex.c
CHK version_gen.h
UPD version_gen.h
DEP /tmp/qemu-test/src/dtc/util.c
CC libfdt/fdt.o
CC libfdt/fdt_ro.o
CC libfdt/fdt_strerror.o
CC libfdt/fdt_wip.o
CC libfdt/fdt_sw.o
CC libfdt/fdt_empty_tree.o
CC libfdt/fdt_addresses.o
CC libfdt/fdt_rw.o
CC libfdt/fdt_overlay.o
AR libfdt/libfdt.a
x86_64-w64-mingw32-ar: creating libfdt/libfdt.a
a - libfdt/fdt.o
a - libfdt/fdt_ro.o
a - libfdt/fdt_wip.o
a - libfdt/fdt_sw.o
a - libfdt/fdt_rw.o
a - libfdt/fdt_strerror.o
a - libfdt/fdt_empty_tree.o
a - libfdt/fdt_addresses.o
a - libfdt/fdt_overlay.o
RC version.o
GEN qga/qapi-generated/qapi-gen
CC qapi/qapi-builtin-types.o
CC qapi/qapi-types.o
CC qapi/qapi-types-common.o
CC qapi/qapi-types-block-core.o
CC qapi/qapi-types-crypto.o
CC qapi/qapi-types-char.o
CC qapi/qapi-types-block.o
CC qapi/qapi-types-introspect.o
CC qapi/qapi-types-job.o
CC qapi/qapi-types-migration.o
CC qapi/qapi-types-misc.o
CC qapi/qapi-types-net.o
CC qapi/qapi-types-rocker.o
CC qapi/qapi-types-run-state.o
CC qapi/qapi-types-sockets.o
CC qapi/qapi-types-tpm.o
CC qapi/qapi-types-trace.o
CC qapi/qapi-types-transaction.o
CC qapi/qapi-types-ui.o
CC qapi/qapi-visit.o
CC qapi/qapi-builtin-visit.o
CC qapi/qapi-visit-block-core.o
CC qapi/qapi-visit-block.o
CC qapi/qapi-visit-char.o
CC qapi/qapi-visit-common.o
CC qapi/qapi-visit-crypto.o
CC qapi/qapi-visit-job.o
CC qapi/qapi-visit-introspect.o
CC qapi/qapi-visit-migration.o
CC qapi/qapi-visit-misc.o
CC qapi/qapi-visit-net.o
CC qapi/qapi-visit-rocker.o
CC qapi/qapi-visit-run-state.o
CC qapi/qapi-visit-sockets.o
CC qapi/qapi-visit-tpm.o
CC qapi/qapi-visit-trace.o
CC qapi/qapi-visit-transaction.o
CC qapi/qapi-visit-ui.o
CC qapi/qapi-events.o
CC qapi/qapi-events-block-core.o
CC qapi/qapi-events-block.o
CC qapi/qapi-events-char.o
CC qapi/qapi-events-common.o
CC qapi/qapi-events-crypto.o
CC qapi/qapi-events-introspect.o
CC qapi/qapi-events-job.o
CC qapi/qapi-events-migration.o
CC qapi/qapi-events-misc.o
CC qapi/qapi-events-net.o
CC qapi/qapi-events-rocker.o
CC qapi/qapi-events-run-state.o
CC qapi/qapi-events-sockets.o
CC qapi/qapi-events-tpm.o
CC qapi/qapi-events-trace.o
CC qapi/qapi-events-transaction.o
CC qapi/qapi-events-ui.o
CC qapi/qapi-introspect.o
CC qapi/qapi-visit-core.o
CC qapi/qapi-dealloc-visitor.o
CC qapi/qobject-input-visitor.o
CC qapi/qobject-output-visitor.o
CC qapi/qmp-registry.o
CC qapi/qmp-dispatch.o
CC qapi/string-input-visitor.o
CC qapi/opts-visitor.o
CC qapi/string-output-visitor.o
CC qapi/qapi-clone-visitor.o
CC qapi/qmp-event.o
CC qapi/qapi-util.o
CC qobject/qnull.o
CC qobject/qnum.o
CC qobject/qstring.o
CC qobject/qdict.o
CC qobject/qlist.o
CC qobject/qbool.o
CC qobject/qlit.o
CC qobject/qjson.o
CC qobject/qobject.o
CC qobject/json-lexer.o
CC qobject/json-streamer.o
CC qobject/json-parser.o
CC qobject/block-qdict.o
CC trace/simple.o
CC trace/control.o
CC util/osdep.o
CC trace/qmp.o
CC util/cutils.o
CC util/unicode.o
CC util/qemu-timer-common.o
CC util/bufferiszero.o
CC util/lockcnt.o
CC util/aiocb.o
CC util/async.o
CC util/aio-wait.o
CC util/thread-pool.o
CC util/qemu-timer.o
CC util/main-loop.o
CC util/iohandler.o
CC util/aio-win32.o
CC util/qemu-thread-win32.o
CC util/event_notifier-win32.o
CC util/oslib-win32.o
CC util/envlist.o
CC util/path.o
CC util/module.o
CC util/host-utils.o
CC util/bitops.o
CC util/bitmap.o
CC util/hbitmap.o
CC util/fifo8.o
CC util/acl.o
CC util/cacheinfo.o
CC util/error.o
CC util/qemu-error.o
CC util/id.o
CC util/iov.o
CC util/qemu-config.o
CC util/qemu-sockets.o
CC util/uri.o
CC util/notify.o
CC util/qemu-option.o
CC util/qemu-progress.o
CC util/keyval.o
CC util/hexdump.o
CC util/crc32c.o
CC util/uuid.o
CC util/getauxval.o
CC util/throttle.o
CC util/readline.o
CC util/rcu.o
CC util/qemu-coroutine.o
CC util/qemu-coroutine-lock.o
CC util/qemu-coroutine-io.o
CC util/qemu-coroutine-sleep.o
CC util/coroutine-win32.o
CC util/buffer.o
CC util/timed-average.o
CC util/base64.o
CC util/log.o
CC util/pagesize.o
CC util/qdist.o
CC util/qht.o
CC util/range.o
CC util/systemd.o
CC util/stats64.o
CC util/iova-tree.o
CC trace-root.o
CC accel/kvm/trace.o
CC accel/tcg/trace.o
CC audio/trace.o
CC chardev/trace.o
CC block/trace.o
CC crypto/trace.o
CC hw/9pfs/trace.o
CC hw/acpi/trace.o
CC hw/alpha/trace.o
CC hw/arm/trace.o
CC hw/audio/trace.o
CC hw/block/dataplane/trace.o
CC hw/block/trace.o
CC hw/char/trace.o
CC hw/dma/trace.o
CC hw/display/trace.o
CC hw/hppa/trace.o
CC hw/i2c/trace.o
CC hw/i386/trace.o
CC hw/i386/xen/trace.o
CC hw/ide/trace.o
CC hw/intc/trace.o
CC hw/input/trace.o
CC hw/isa/trace.o
CC hw/mem/trace.o
CC hw/misc/trace.o
CC hw/misc/macio/trace.o
CC hw/net/trace.o
CC hw/nvram/trace.o
CC hw/pci/trace.o
CC hw/ppc/trace.o
CC hw/pci-host/trace.o
CC hw/rdma/trace.o
CC hw/s390x/trace.o
CC hw/rdma/vmw/trace.o
CC hw/scsi/trace.o
CC hw/sd/trace.o
CC hw/sparc64/trace.o
CC hw/sparc/trace.o
CC hw/tpm/trace.o
CC hw/timer/trace.o
CC hw/usb/trace.o
CC hw/vfio/trace.o
CC hw/virtio/trace.o
CC hw/xen/trace.o
CC linux-user/trace.o
CC io/trace.o
CC nbd/trace.o
CC net/trace.o
CC migration/trace.o
CC qapi/trace.o
CC qom/trace.o
CC scsi/trace.o
CC target/arm/trace.o
CC target/i386/trace.o
CC target/mips/trace.o
CC target/ppc/trace.o
CC target/s390x/trace.o
CC target/sparc/trace.o
CC ui/trace.o
CC util/trace.o
CC crypto/pbkdf-stub.o
CC stubs/arch-query-cpu-model-expansion.o
CC stubs/arch-query-cpu-def.o
CC stubs/arch-query-cpu-model-comparison.o
CC stubs/arch-query-cpu-model-baseline.o
CC stubs/bdrv-next-monitor-owned.o
CC stubs/blk-commit-all.o
CC stubs/blockdev-close-all-bdrv-states.o
CC stubs/clock-warp.o
CC stubs/cpu-get-clock.o
CC stubs/cpu-get-icount.o
CC stubs/dump.o
CC stubs/error-printf.o
CC stubs/gdbstub.o
CC stubs/fdset.o
CC stubs/get-vm-name.o
CC stubs/iothread-lock.o
CC stubs/iothread.o
CC stubs/is-daemonized.o
CC stubs/machine-init-done.o
CC stubs/migr-blocker.o
CC stubs/change-state-handler.o
CC stubs/monitor.o
CC stubs/qtest.o
CC stubs/notify-event.o
CC stubs/replay.o
CC stubs/runstate-check.o
CC stubs/set-fd-handler.o
CC stubs/slirp.o
CC stubs/tpm.o
CC stubs/sysbus.o
CC stubs/trace-control.o
CC stubs/uuid.o
CC stubs/vm-stop.o
CC stubs/vmstate.o
CC stubs/fd-register.o
CC stubs/target-monitor-defs.o
CC stubs/qmp_memory_device.o
CC stubs/target-get-monitor-def.o
CC stubs/pc_madt_cpu_entry.o
CC stubs/vmgenid.o
CC stubs/xen-common.o
CC stubs/xen-hvm.o
CC stubs/pci-host-piix.o
CC stubs/ram-block.o
GEN qemu-img-cmds.h
CC block.o
CC blockjob.o
CC job.o
CC qemu-io-cmds.o
CC replication.o
CC block/raw-format.o
CC block/qcow.o
CC block/vmdk.o
CC block/vdi.o
CC block/cloop.o
CC block/bochs.o
CC block/vpc.o
CC block/vvfat.o
CC block/qcow2.o
CC block/qcow2-refcount.o
CC block/dmg.o
CC block/qcow2-cluster.o
CC block/qcow2-snapshot.o
CC block/qcow2-cache.o
CC block/qcow2-bitmap.o
CC block/qed.o
CC block/qed-l2-cache.o
CC block/qed-table.o
CC block/qed-cluster.o
CC block/qed-check.o
CC block/vhdx.o
CC block/vhdx-log.o
CC block/vhdx-endian.o
CC block/quorum.o
CC block/parallels.o
CC block/blkdebug.o
CC block/blkverify.o
CC block/block-backend.o
CC block/snapshot.o
CC block/blkreplay.o
CC block/qapi.o
CC block/file-win32.o
CC block/win32-aio.o
CC block/mirror.o
CC block/null.o
CC block/commit.o
CC block/io.o
CC block/create.o
CC block/nbd.o
CC block/throttle-groups.o
CC block/nbd-client.o
CC block/sheepdog.o
CC block/accounting.o
CC block/dirty-bitmap.o
CC block/write-threshold.o
CC block/backup.o
CC block/replication.o
CC block/throttle.o
CC block/copy-on-read.o
CC block/crypto.o
CC nbd/server.o
CC nbd/client.o
CC nbd/common.o
CC scsi/utils.o
CC block/curl.o
CC block/ssh.o
CC block/dmg-bz2.o
CC crypto/init.o
CC crypto/hash.o
CC crypto/hash-nettle.o
CC crypto/hmac.o
CC crypto/hmac-nettle.o
CC crypto/aes.o
CC crypto/desrfb.o
CC crypto/cipher.o
CC crypto/tlscreds.o
CC crypto/tlscredsanon.o
CC crypto/tlscredsx509.o
CC crypto/tlssession.o
CC crypto/pbkdf.o
CC crypto/secret.o
CC crypto/random-gnutls.o
CC crypto/pbkdf-nettle.o
CC crypto/ivgen.o
CC crypto/ivgen-plain.o
CC crypto/ivgen-essiv.o
CC crypto/ivgen-plain64.o
CC crypto/afsplit.o
CC crypto/xts.o
CC crypto/block.o
CC crypto/block-qcow.o
CC crypto/block-luks.o
CC io/channel-buffer.o
CC io/channel-file.o
CC io/channel-socket.o
CC io/channel-command.o
CC io/channel.o
CC io/channel-tls.o
CC io/channel-watch.o
CC io/channel-websock.o
CC io/channel-util.o
CC io/dns-resolver.o
CC io/net-listener.o
CC qom/object.o
CC io/task.o
CC qom/container.o
CC qom/qom-qobject.o
CC qom/object_interfaces.o
CC qemu-io.o
CC blockdev.o
CC blockdev-nbd.o
CC bootdevice.o
CC iothread.o
CC job-qmp.o
CC qdev-monitor.o
CC device-hotplug.o
CC os-win32.o
CC bt-host.o
CC dma-helpers.o
CC bt-vhci.o
CC vl.o
CC tpm.o
CC device_tree.o
CC qapi/qapi-commands.o
CC qapi/qapi-commands-block-core.o
CC qapi/qapi-commands-block.o
CC qapi/qapi-commands-common.o
CC qapi/qapi-commands-char.o
CC qapi/qapi-commands-crypto.o
CC qapi/qapi-commands-introspect.o
CC qapi/qapi-commands-job.o
CC qapi/qapi-commands-migration.o
CC qapi/qapi-commands-misc.o
CC qapi/qapi-commands-net.o
CC qapi/qapi-commands-rocker.o
CC qapi/qapi-commands-run-state.o
CC qapi/qapi-commands-sockets.o
CC qapi/qapi-commands-tpm.o
CC qapi/qapi-commands-trace.o
CC qapi/qapi-commands-transaction.o
CC qapi/qapi-commands-ui.o
CC qmp.o
CC hmp.o
CC cpus-common.o
CC audio/audio.o
CC audio/noaudio.o
CC audio/wavaudio.o
CC audio/mixeng.o
CC audio/dsoundaudio.o
CC audio/audio_win_int.o
CC audio/wavcapture.o
CC backends/rng.o
CC backends/rng-egd.o
CC backends/tpm.o
CC backends/hostmem.o
CC backends/hostmem-ram.o
CC backends/cryptodev.o
CC backends/cryptodev-builtin.o
CC backends/cryptodev-vhost.o
CC block/stream.o
CC chardev/msmouse.o
CC chardev/wctablet.o
CC chardev/testdev.o
CC disas/arm.o
CXX disas/arm-a64.o
/tmp/qemu-test/src/nbd/server.c: In function 'nbd_trip':
/tmp/qemu-test/src/nbd/server.c:1980:19: error: 'end' may be used uninitialized in this function [-Werror=maybe-uninitialized]
*length = end - offset;
~~~~^~~~~~~~
/tmp/qemu-test/src/nbd/server.c:1940:30: note: 'end' was declared here
uint64_t begin = offset, end;
^~~
cc1: all warnings being treated as errors
make: *** [/tmp/qemu-test/src/rules.mak:69: nbd/server.o] Error 1
make: *** Waiting for unfinished jobs....
Traceback (most recent call last):
File "./tests/docker/docker.py", line 526, in <module>
sys.exit(main())
File "./tests/docker/docker.py", line 523, in main
return args.cmdobj.run(args, argv)
File "./tests/docker/docker.py", line 279, in run
return Docker().run(argv, args.keep, quiet=args.quiet)
File "./tests/docker/docker.py", line 247, in run
quiet=quiet)
File "./tests/docker/docker.py", line 154, in _do_check
return subprocess.check_call(self._command + cmd, **kwargs)
File "/usr/lib64/python2.7/subprocess.py", line 186, in check_call
raise CalledProcessError(retcode, cmd)
subprocess.CalledProcessError: Command '['docker', 'run', '--label', 'com.qemu.instance.uuid=35834706760d11e89ed652540069c830', '-u', '0', '--security-opt', 'seccomp=unconfined', '--rm', '--net=none', '-e', 'TARGET_LIST=', '-e', 'EXTRA_CONFIGURE_OPTS=', '-e', 'V=', '-e', 'J=8', '-e', 'DEBUG=', '-e', 'SHOW_ENV=1', '-e', 'CCACHE_DIR=/var/tmp/ccache', '-v', '/root/.cache/qemu-docker-ccache:/var/tmp/ccache:z', '-v', '/var/tmp/patchew-tester-tmp-6_su1war/src/docker-src.2018-06-22-07.12.36.16942:/var/tmp/qemu:z,ro', 'qemu:fedora', '/var/tmp/qemu/run', 'test-mingw']' returned non-zero exit status 2
make[1]: *** [tests/docker/Makefile.include:164: docker-run] Error 1
make[1]: Leaving directory '/var/tmp/patchew-tester-tmp-6_su1war/src'
make: *** [tests/docker/Makefile.include:198: docker-run-test-mingw@fedora] Error 2
real 1m40.749s
user 0m4.592s
sys 0m3.653s
=== OUTPUT END ===
Test command exited with code: 2
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Qemu-devel] [PATCH v2 1/3] aspeed/scu: introduce clock frequencies
2018-06-22 7:56 ` [Qemu-devel] [PATCH v2 1/3] aspeed/scu: introduce clock frequencies Cédric Le Goater
@ 2018-06-25 0:54 ` Andrew Jeffery
0 siblings, 0 replies; 11+ messages in thread
From: Andrew Jeffery @ 2018-06-25 0:54 UTC (permalink / raw)
To: Cédric Le Goater, qemu-devel; +Cc: qemu-arm, Peter Maydell, Joel Stanley
On Fri, 22 Jun 2018, at 17:26, Cédric Le Goater wrote:
> All Aspeed SoC clocks are driven by an input source clock which can
> have different frequencies : 24MHz or 25MHz, and also, on the Aspeed
> AST2400 SoC, 48MHz. The H-PLL (CPU) clock is defined from a
> calculation using parameters in the H-PLL Parameter register or from a
> predefined set of frequencies if the setting is strapped by hardware
> (Aspeed AST2400 SoC). The other clocks of the SoC are then defined
> from the H-PLL using dividers.
>
> We introduce first the APB clock because it should be used to drive
> the Aspeed timer model.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
> ---
> include/hw/misc/aspeed_scu.h | 70 ++++++++++++++++++++++++++--
> hw/misc/aspeed_scu.c | 106 +++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 172 insertions(+), 4 deletions(-)
>
> diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h
> index d70cc0aeca61..f662c38188f4 100644
> --- a/include/hw/misc/aspeed_scu.h
> +++ b/include/hw/misc/aspeed_scu.h
> @@ -30,6 +30,10 @@ typedef struct AspeedSCUState {
> uint32_t hw_strap1;
> uint32_t hw_strap2;
> uint32_t hw_prot_key;
> +
> + uint32_t clkin;
> + uint32_t hpll;
> + uint32_t apb_freq;
> } AspeedSCUState;
>
> #define AST2400_A0_SILICON_REV 0x02000303U
> @@ -58,7 +62,64 @@ extern bool is_supported_silicon_rev(uint32_t silicon_rev);
> * 1. 2012/12/29 Ryan Chen Create
> */
>
> -/* Hardware Strapping Register definition (for Aspeed AST2400 SOC)
> +/* SCU08 Clock Selection Register
> + *
> + * 31 Enable Video Engine clock dynamic slow down
> + * 30:28 Video Engine clock slow down setting
> + * 27 2D Engine GCLK clock source selection
> + * 26 2D Engine GCLK clock throttling enable
> + * 25:23 APB PCLK divider selection
> + * 22:20 LPC Host LHCLK divider selection
> + * 19 LPC Host LHCLK clock generation/output enable control
> + * 18:16 MAC AHB bus clock divider selection
> + * 15 SD/SDIO clock running enable
> + * 14:12 SD/SDIO divider selection
> + * 11 Reserved
> + * 10:8 Video port output clock delay control bit
> + * 7 ARM CPU/AHB clock slow down enable
> + * 6:4 ARM CPU/AHB clock slow down setting
> + * 3:2 ECLK clock source selection
> + * 1 CPU/AHB clock slow down idle timer
> + * 0 CPU/AHB clock dynamic slow down enable (defined in bit[6:4])
> + */
> +#define SCU_CLK_GET_PCLK_DIV(x) (((x) >> 23) & 0x7)
> +
> +/* SCU24 H-PLL Parameter Register (for Aspeed AST2400 SOC)
> + *
> + * 18 H-PLL parameter selection
> + * 0: Select H-PLL by strapping resistors
> + * 1: Select H-PLL by the programmed registers (SCU24[17:0])
> + * 17 Enable H-PLL bypass mode
> + * 16 Turn off H-PLL
> + * 10:5 H-PLL Numerator
> + * 4 H-PLL Output Divider
> + * 3:0 H-PLL Denumerator
> + *
> + * (Output frequency) = 24MHz * (2-OD) * [(Numerator+2) / (Denumerator
> +1)]
> + */
> +
> +#define SCU_AST2400_H_PLL_PROGRAMMED (0x1 << 18)
> +#define SCU_AST2400_H_PLL_BYPASS_EN (0x1 << 17)
> +#define SCU_AST2400_H_PLL_OFF (0x1 << 16)
> +
> +/* SCU24 H-PLL Parameter Register (for Aspeed AST2500 SOC)
> + *
> + * 21 Enable H-PLL reset
> + * 20 Enable H-PLL bypass mode
> + * 19 Turn off H-PLL
> + * 18:13 H-PLL Post Divider
> + * 12:5 H-PLL Numerator (M)
> + * 4:0 H-PLL Denumerator (N)
> + *
> + * (Output frequency) = CLKIN(24MHz) * [(M+1) / (N+1)] / (P+1)
> + *
> + * The default frequency is 792Mhz when CLKIN = 24MHz
> + */
> +
> +#define SCU_H_PLL_BYPASS_EN (0x1 << 20)
> +#define SCU_H_PLL_OFF (0x1 << 19)
> +
> +/* SCU70 Hardware Strapping Register definition (for Aspeed AST2400
> SOC)
> *
> * 31:29 Software defined strapping registers
> * 28:27 DRAM size setting (for VGA driver use)
> @@ -107,12 +168,13 @@ extern bool is_supported_silicon_rev(uint32_t
> silicon_rev);
> #define SCU_AST2400_HW_STRAP_GET_CLK_SOURCE(x) (((((x) >> 23) &
> 0x1) << 1) \
> | (((x) >> 18) &
> 0x1))
> #define SCU_AST2400_HW_STRAP_CLK_SOURCE_MASK ((0x1 << 23) | (0x1
> << 18))
> -#define AST2400_CLK_25M_IN (0x1 << 23)
> +#define SCU_HW_STRAP_CLK_25M_IN (0x1 << 23)
> #define AST2400_CLK_24M_IN 0
> #define AST2400_CLK_48M_IN 1
> #define AST2400_CLK_25M_IN_24M_USB_CKI 2
> #define AST2400_CLK_25M_IN_48M_USB_CKI 3
>
> +#define SCU_HW_STRAP_CLK_48M_IN (0x1 << 18)
> #define SCU_HW_STRAP_2ND_BOOT_WDT (0x1 << 17)
> #define SCU_HW_STRAP_SUPER_IO_CONFIG (0x1 << 16)
> #define SCU_HW_STRAP_VGA_CLASS_CODE (0x1 << 15)
> @@ -160,8 +222,8 @@ extern bool is_supported_silicon_rev(uint32_t silicon_rev);
> #define AST2400_DIS_BOOT 3
>
> /*
> - * Hardware strapping register definition (for Aspeed AST2500 SoC and
> - * higher)
> + * SCU70 Hardware strapping register definition (for Aspeed AST2500
> + * SoC and higher)
> *
> * 31 Enable SPI Flash Strap Auto Fetch Mode
> * 30 Enable GPIO Strap Mode
> diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
> index 59315010db9a..59333b50abdd 100644
> --- a/hw/misc/aspeed_scu.c
> +++ b/hw/misc/aspeed_scu.c
> @@ -168,6 +168,27 @@ static uint32_t aspeed_scu_get_random(void)
> return num;
> }
>
> +static void aspeed_scu_set_apb_freq(AspeedSCUState *s)
> +{
> + uint32_t apb_divider;
> +
> + switch (s->silicon_rev) {
> + case AST2400_A0_SILICON_REV:
> + case AST2400_A1_SILICON_REV:
> + apb_divider = 2;
> + break;
> + case AST2500_A0_SILICON_REV:
> + case AST2500_A1_SILICON_REV:
> + apb_divider = 4;
> + break;
> + default:
> + g_assert_not_reached();
> + }
> +
> + s->apb_freq = s->hpll / (SCU_CLK_GET_PCLK_DIV(s->regs[CLK_SEL]) +
> 1)
> + / apb_divider;
> +}
> +
> static uint64_t aspeed_scu_read(void *opaque, hwaddr offset, unsigned
> size)
> {
> AspeedSCUState *s = ASPEED_SCU(opaque);
> @@ -222,6 +243,10 @@ static void aspeed_scu_write(void *opaque, hwaddr
> offset, uint64_t data,
> case PROT_KEY:
> s->regs[reg] = (data == ASPEED_SCU_PROT_KEY) ? 1 : 0;
> return;
> + case CLK_SEL:
> + s->regs[reg] = data;
> + aspeed_scu_set_apb_freq(s);
> + break;
>
> case FREQ_CNTR_EVAL:
> case VGA_SCRATCH1 ... VGA_SCRATCH8:
> @@ -247,19 +272,93 @@ static const MemoryRegionOps aspeed_scu_ops = {
> .valid.unaligned = false,
> };
>
> +static uint32_t aspeed_scu_get_clkin(AspeedSCUState *s)
> +{
> + if (s->hw_strap1 & SCU_HW_STRAP_CLK_25M_IN) {
> + return 25000000;
> + } else if (s->hw_strap1 & SCU_HW_STRAP_CLK_48M_IN) {
> + return 48000000;
> + } else {
> + return 24000000;
> + }
> +}
> +
> +/*
> + * Strapped frequencies for the AST2400 in MHz. They depend on the
> + * clkin frequency.
> + */
> +static const uint32_t hpll_ast2400_freqs[][4] = {
> + { 384, 360, 336, 408 }, /* 24MHz or 48MHz */
> + { 400, 375, 350, 425 }, /* 25MHz */
> +};
> +
> +static uint32_t aspeed_scu_calc_hpll_ast2400(AspeedSCUState *s)
> +{
> + uint32_t hpll_reg = s->regs[HPLL_PARAM];
> + uint8_t freq_select;
> + bool clk_25m_in;
> +
> + if (hpll_reg & SCU_AST2400_H_PLL_OFF) {
> + return 0;
> + }
> +
> + if (hpll_reg & SCU_AST2400_H_PLL_PROGRAMMED) {
> + uint32_t multiplier = 1;
> +
> + if (!(hpll_reg & SCU_AST2400_H_PLL_BYPASS_EN)) {
> + uint32_t n = (hpll_reg >> 5) & 0x3f;
> + uint32_t od = (hpll_reg >> 4) & 0x1;
> + uint32_t d = hpll_reg & 0xf;
> +
> + multiplier = (2 - od) * ((n + 2) / (d + 1));
> + }
> +
> + return s->clkin * multiplier;
> + }
> +
> + /* HW strapping */
> + clk_25m_in = !!(s->hw_strap1 & SCU_HW_STRAP_CLK_25M_IN);
> + freq_select = SCU_AST2400_HW_STRAP_GET_H_PLL_CLK(s->hw_strap1);
> +
> + return hpll_ast2400_freqs[clk_25m_in][freq_select] * 1000000;
> +}
> +
> +static uint32_t aspeed_scu_calc_hpll_ast2500(AspeedSCUState *s)
> +{
> + uint32_t hpll_reg = s->regs[HPLL_PARAM];
> + uint32_t multiplier = 1;
> +
> + if (hpll_reg & SCU_H_PLL_OFF) {
> + return 0;
> + }
> +
> + if (!(hpll_reg & SCU_H_PLL_BYPASS_EN)) {
> + uint32_t p = (hpll_reg >> 13) & 0x3f;
> + uint32_t m = (hpll_reg >> 5) & 0xff;
> + uint32_t n = hpll_reg & 0x1f;
> +
> + multiplier = ((m + 1) / (n + 1)) / (p + 1);
> + }
> +
> + return s->clkin * multiplier;
> +}
> +
> static void aspeed_scu_reset(DeviceState *dev)
> {
> AspeedSCUState *s = ASPEED_SCU(dev);
> const uint32_t *reset;
> + uint32_t (*calc_hpll)(AspeedSCUState *s);
>
> switch (s->silicon_rev) {
> case AST2400_A0_SILICON_REV:
> case AST2400_A1_SILICON_REV:
> reset = ast2400_a0_resets;
> + calc_hpll = aspeed_scu_calc_hpll_ast2400;
> break;
> case AST2500_A0_SILICON_REV:
> case AST2500_A1_SILICON_REV:
> reset = ast2500_a1_resets;
> + calc_hpll = aspeed_scu_calc_hpll_ast2500;
> break;
> default:
> g_assert_not_reached();
> @@ -270,6 +369,13 @@ static void aspeed_scu_reset(DeviceState *dev)
> s->regs[HW_STRAP1] = s->hw_strap1;
> s->regs[HW_STRAP2] = s->hw_strap2;
> s->regs[PROT_KEY] = s->hw_prot_key;
> +
> + /*
> + * All registers are set. Now compute the frequencies of the main clocks
> + */
> + s->clkin = aspeed_scu_get_clkin(s);
> + s->hpll = calc_hpll(s);
> + aspeed_scu_set_apb_freq(s);
> }
>
> static uint32_t aspeed_silicon_revs[] = {
> --
> 2.13.6
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Qemu-devel] [PATCH v2 2/3] aspeed: initialize the SCU controller first
2018-06-22 7:56 ` [Qemu-devel] [PATCH v2 2/3] aspeed: initialize the SCU controller first Cédric Le Goater
@ 2018-06-25 0:54 ` Andrew Jeffery
0 siblings, 0 replies; 11+ messages in thread
From: Andrew Jeffery @ 2018-06-25 0:54 UTC (permalink / raw)
To: Cédric Le Goater, qemu-devel; +Cc: qemu-arm, Peter Maydell, Joel Stanley
On Fri, 22 Jun 2018, at 17:26, Cédric Le Goater wrote:
> The System Control Unit should be initialized first as it drives all
> the configuration of the SoC and other device models.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> Reviewed-by: Joel Stanley <joel@jms.id.au>
Acked-by: Andrew Jeffery <andrew@aj.id.au>
> ---
> hw/arm/aspeed_soc.c | 40 ++++++++++++++++++++--------------------
> 1 file changed, 20 insertions(+), 20 deletions(-)
>
> diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
> index 1955a892f4a4..7cc05ee27ea4 100644
> --- a/hw/arm/aspeed_soc.c
> +++ b/hw/arm/aspeed_soc.c
> @@ -109,18 +109,6 @@ static void aspeed_soc_init(Object *obj)
> object_initialize(&s->cpu, sizeof(s->cpu), sc->info->cpu_type);
> object_property_add_child(obj, "cpu", OBJECT(&s->cpu), NULL);
>
> - object_initialize(&s->vic, sizeof(s->vic), TYPE_ASPEED_VIC);
> - object_property_add_child(obj, "vic", OBJECT(&s->vic), NULL);
> - qdev_set_parent_bus(DEVICE(&s->vic), sysbus_get_default());
> -
> - object_initialize(&s->timerctrl, sizeof(s->timerctrl), TYPE_ASPEED_TIMER);
> - object_property_add_child(obj, "timerctrl", OBJECT(&s->timerctrl), NULL);
> - qdev_set_parent_bus(DEVICE(&s->timerctrl), sysbus_get_default());
> -
> - object_initialize(&s->i2c, sizeof(s->i2c), TYPE_ASPEED_I2C);
> - object_property_add_child(obj, "i2c", OBJECT(&s->i2c), NULL);
> - qdev_set_parent_bus(DEVICE(&s->i2c), sysbus_get_default());
> -
> object_initialize(&s->scu, sizeof(s->scu), TYPE_ASPEED_SCU);
> object_property_add_child(obj, "scu", OBJECT(&s->scu), NULL);
> qdev_set_parent_bus(DEVICE(&s->scu), sysbus_get_default());
> @@ -133,6 +121,18 @@ static void aspeed_soc_init(Object *obj)
> object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
> "hw-prot-key", &error_abort);
>
> + object_initialize(&s->vic, sizeof(s->vic), TYPE_ASPEED_VIC);
> + object_property_add_child(obj, "vic", OBJECT(&s->vic), NULL);
> + qdev_set_parent_bus(DEVICE(&s->vic), sysbus_get_default());
> +
> + object_initialize(&s->timerctrl, sizeof(s->timerctrl),
> TYPE_ASPEED_TIMER);
> + object_property_add_child(obj, "timerctrl", OBJECT(&s->timerctrl),
> NULL);
> + qdev_set_parent_bus(DEVICE(&s->timerctrl), sysbus_get_default());
> +
> + object_initialize(&s->i2c, sizeof(s->i2c), TYPE_ASPEED_I2C);
> + object_property_add_child(obj, "i2c", OBJECT(&s->i2c), NULL);
> + qdev_set_parent_bus(DEVICE(&s->i2c), sysbus_get_default());
> +
> object_initialize(&s->fmc, sizeof(s->fmc), sc->info->fmc_typename);
> object_property_add_child(obj, "fmc", OBJECT(&s->fmc), NULL);
> qdev_set_parent_bus(DEVICE(&s->fmc), sysbus_get_default());
> @@ -195,6 +195,14 @@ static void aspeed_soc_realize(DeviceState *dev,
> Error **errp)
> memory_region_add_subregion(get_system_memory(),
> ASPEED_SOC_SRAM_BASE,
> &s->sram);
>
> + /* SCU */
> + object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
> + if (err) {
> + error_propagate(errp, err);
> + return;
> + }
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, ASPEED_SOC_SCU_BASE);
> +
> /* VIC */
> object_property_set_bool(OBJECT(&s->vic), true, "realized", &err);
> if (err) {
> @@ -219,14 +227,6 @@ static void aspeed_soc_realize(DeviceState *dev,
> Error **errp)
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
> }
>
> - /* SCU */
> - object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
> - if (err) {
> - error_propagate(errp, err);
> - return;
> - }
> - sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, ASPEED_SOC_SCU_BASE);
> -
> /* UART - attach an 8250 to the IO space as our UART5 */
> if (serial_hd(0)) {
> qemu_irq uart5 = qdev_get_gpio_in(DEVICE(&s->vic), uart_irqs[4]);
> --
> 2.13.6
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Qemu-devel] [PATCH v2 3/3] aspeed/timer: use the APB frequency from the SCU
2018-06-22 7:57 ` [Qemu-devel] [PATCH v2 3/3] aspeed/timer: use the APB frequency from the SCU Cédric Le Goater
@ 2018-06-25 0:59 ` Andrew Jeffery
2018-08-31 8:34 ` Thomas Huth
1 sibling, 0 replies; 11+ messages in thread
From: Andrew Jeffery @ 2018-06-25 0:59 UTC (permalink / raw)
To: Cédric Le Goater, qemu-devel; +Cc: qemu-arm, Peter Maydell, Joel Stanley
On Fri, 22 Jun 2018, at 17:27, Cédric Le Goater wrote:
> The timer controller can be driven by either an external 1MHz clock or
> by the APB clock. Today, the model makes the assumption that the APB
> frequency is always set to 24MHz but this is incorrect.
>
> The AST2400 SoC on the palmetto machines uses a 48MHz input clock
> source and the APB can be set to 48MHz. The consequence is a general
> system slowdown. The QEMU machines using the AST2500 SoC do not seem
> impacted today because the APB frequency is still set to 24MHz.
>
> We fix the timer frequency for all SoCs by linking the Timer model to
> the SCU model. The APB frequency driving the timers is now the one
> configured for the SoC.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
> ---
> include/hw/timer/aspeed_timer.h | 4 ++++
> hw/arm/aspeed_soc.c | 2 ++
> hw/timer/aspeed_timer.c | 19 +++++++++++++++----
> 3 files changed, 21 insertions(+), 4 deletions(-)
>
> diff --git a/include/hw/timer/aspeed_timer.h b/include/hw/timer/aspeed_timer.h
> index bd6c1a7f9609..040a08873432 100644
> --- a/include/hw/timer/aspeed_timer.h
> +++ b/include/hw/timer/aspeed_timer.h
> @@ -24,6 +24,8 @@
>
> #include "qemu/timer.h"
>
> +typedef struct AspeedSCUState AspeedSCUState;
> +
> #define ASPEED_TIMER(obj) \
> OBJECT_CHECK(AspeedTimerCtrlState, (obj), TYPE_ASPEED_TIMER);
> #define TYPE_ASPEED_TIMER "aspeed.timer"
> @@ -55,6 +57,8 @@ typedef struct AspeedTimerCtrlState {
> uint32_t ctrl;
> uint32_t ctrl2;
> AspeedTimer timers[ASPEED_TIMER_NR_TIMERS];
> +
> + AspeedSCUState *scu;
> } AspeedTimerCtrlState;
>
> #endif /* ASPEED_TIMER_H */
> diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
> index 7cc05ee27ea4..e68911af0f90 100644
> --- a/hw/arm/aspeed_soc.c
> +++ b/hw/arm/aspeed_soc.c
> @@ -127,6 +127,8 @@ static void aspeed_soc_init(Object *obj)
>
> object_initialize(&s->timerctrl, sizeof(s->timerctrl), TYPE_ASPEED_TIMER);
> object_property_add_child(obj, "timerctrl", OBJECT(&s->timerctrl), NULL);
> + object_property_add_const_link(OBJECT(&s->timerctrl), "scu",
> + OBJECT(&s->scu), &error_abort);
> qdev_set_parent_bus(DEVICE(&s->timerctrl), sysbus_get_default());
>
> object_initialize(&s->i2c, sizeof(s->i2c), TYPE_ASPEED_I2C);
> diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c
> index 1e31e22b6f1f..5e3f51b66b43 100644
> --- a/hw/timer/aspeed_timer.c
> +++ b/hw/timer/aspeed_timer.c
> @@ -10,8 +10,10 @@
> */
>
> #include "qemu/osdep.h"
> +#include "qapi/error.h"
> #include "hw/sysbus.h"
> #include "hw/timer/aspeed_timer.h"
> +#include "hw/misc/aspeed_scu.h"
> #include "qemu-common.h"
> #include "qemu/bitops.h"
> #include "qemu/timer.h"
> @@ -26,7 +28,6 @@
> #define TIMER_CLOCK_USE_EXT true
> #define TIMER_CLOCK_EXT_HZ 1000000
> #define TIMER_CLOCK_USE_APB false
> -#define TIMER_CLOCK_APB_HZ 24000000
>
> #define TIMER_REG_STATUS 0
> #define TIMER_REG_RELOAD 1
> @@ -80,11 +81,11 @@ static inline bool timer_external_clock(AspeedTimer *t)
> return timer_ctrl_status(t, op_external_clock);
> }
>
> -static uint32_t clock_rates[] = { TIMER_CLOCK_APB_HZ, TIMER_CLOCK_EXT_HZ };
> -
> static inline uint32_t calculate_rate(struct AspeedTimer *t)
> {
> - return clock_rates[timer_external_clock(t)];
> + AspeedTimerCtrlState *s = timer_to_ctrl(t);
> +
> + return timer_external_clock(t) ? TIMER_CLOCK_EXT_HZ : s->scu->apb_freq;
> }
>
> static inline uint32_t calculate_ticks(struct AspeedTimer *t, uint64_t
> now_ns)
> @@ -449,6 +450,16 @@ static void aspeed_timer_realize(DeviceState *dev,
> Error **errp)
> int i;
> SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
> AspeedTimerCtrlState *s = ASPEED_TIMER(dev);
> + Object *obj;
> + Error *err = NULL;
> +
> + obj = object_property_get_link(OBJECT(dev), "scu", &err);
> + if (!obj) {
> + error_propagate(errp, err);
> + error_prepend(errp, "required link 'scu' not found: ");
> + return;
> + }
> + s->scu = ASPEED_SCU(obj);
>
> for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
> aspeed_init_one_timer(s, i);
> --
> 2.13.6
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Qemu-devel] [PATCH v2 0/3] aspeed: introduce the APB clock settings
2018-06-22 7:56 [Qemu-devel] [PATCH v2 0/3] aspeed: introduce the APB clock settings Cédric Le Goater
` (3 preceding siblings ...)
2018-06-22 11:14 ` [Qemu-devel] [PATCH v2 0/3] aspeed: introduce the APB clock settings no-reply
@ 2018-06-26 16:05 ` Peter Maydell
4 siblings, 0 replies; 11+ messages in thread
From: Peter Maydell @ 2018-06-26 16:05 UTC (permalink / raw)
To: Cédric Le Goater
Cc: QEMU Developers, qemu-arm, Joel Stanley, Andrew Jeffery
On 22 June 2018 at 08:56, Cédric Le Goater <clg@kaod.org> wrote:
> Hello,
>
> The Aspeed SoC clocks are driven by an input source clock which can
> have different frequencies : 24MHz or 25MHz, and also, on the Aspeed
> AST2400 SoC, 48MHz. The H-PLL (CPU) clock is defined from a calculation
> using parameters in the H-PLL Parameter register or from a predefined
> set of frequencies if the setting is strapped by hardware (Aspeed
> AST2400 SoC). The other clocks of the SoC are then defined from the
> H-PLL using dividers.
>
> We first introduce the APB clock because it drives the timer model.
> This fixes a slowdown issue on the palmetto machine (AST2400) when
> running Linux. The latest Linux versions take into account more
> precisely the SoC settings for the clocks and the APB freq is set to
> 48MHz but modeled at 24MHz by QEMU.
>
> Thanks,
>
Applied to target-arm.next, thanks.
-- PMM
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Qemu-devel] [PATCH v2 3/3] aspeed/timer: use the APB frequency from the SCU
2018-06-22 7:57 ` [Qemu-devel] [PATCH v2 3/3] aspeed/timer: use the APB frequency from the SCU Cédric Le Goater
2018-06-25 0:59 ` Andrew Jeffery
@ 2018-08-31 8:34 ` Thomas Huth
2018-08-31 8:55 ` Cédric Le Goater
1 sibling, 1 reply; 11+ messages in thread
From: Thomas Huth @ 2018-08-31 8:34 UTC (permalink / raw)
To: Cédric Le Goater, qemu-devel, Peter Maydell
Cc: Andrew Jeffery, qemu-arm, Joel Stanley, Markus Armbruster
On 2018-06-22 09:57, Cédric Le Goater wrote:
> The timer controller can be driven by either an external 1MHz clock or
> by the APB clock. Today, the model makes the assumption that the APB
> frequency is always set to 24MHz but this is incorrect.
>
> The AST2400 SoC on the palmetto machines uses a 48MHz input clock
> source and the APB can be set to 48MHz. The consequence is a general
> system slowdown. The QEMU machines using the AST2500 SoC do not seem
> impacted today because the APB frequency is still set to 24MHz.
>
> We fix the timer frequency for all SoCs by linking the Timer model to
> the SCU model. The APB frequency driving the timers is now the one
> configured for the SoC.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> Reviewed-by: Joel Stanley <joel@jms.id.au>
> ---
> include/hw/timer/aspeed_timer.h | 4 ++++
> hw/arm/aspeed_soc.c | 2 ++
> hw/timer/aspeed_timer.c | 19 +++++++++++++++----
> 3 files changed, 21 insertions(+), 4 deletions(-)
>
> diff --git a/include/hw/timer/aspeed_timer.h b/include/hw/timer/aspeed_timer.h
> index bd6c1a7f9609..040a08873432 100644
> --- a/include/hw/timer/aspeed_timer.h
> +++ b/include/hw/timer/aspeed_timer.h
> @@ -24,6 +24,8 @@
>
> #include "qemu/timer.h"
>
> +typedef struct AspeedSCUState AspeedSCUState;
> +
> #define ASPEED_TIMER(obj) \
> OBJECT_CHECK(AspeedTimerCtrlState, (obj), TYPE_ASPEED_TIMER);
> #define TYPE_ASPEED_TIMER "aspeed.timer"
> @@ -55,6 +57,8 @@ typedef struct AspeedTimerCtrlState {
> uint32_t ctrl;
> uint32_t ctrl2;
> AspeedTimer timers[ASPEED_TIMER_NR_TIMERS];
> +
> + AspeedSCUState *scu;
> } AspeedTimerCtrlState;
This patch breaks compiling with clang 3.4.2 for me:
In file included from /home/thuth/devel/qemu/hw/timer/aspeed_timer.c:16:
/home/thuth/devel/qemu/include/hw/misc/aspeed_scu.h:37:3: error:
redefinition of typedef 'AspeedSCUState' is a C11 feature
[-Werror,-Wtypedef-redefinition]
} AspeedSCUState;
^
/home/thuth/devel/qemu/include/hw/timer/aspeed_timer.h:27:31: note:
previous definition is here
typedef struct AspeedSCUState AspeedSCUState;
^
I think you should not re-typedef here. Either include the right header,
or use include/qemu/typedefs.h.
Thomas
PS: Did I already mention that I really dislike the typedeffing in QEMU?
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Qemu-devel] [PATCH v2 3/3] aspeed/timer: use the APB frequency from the SCU
2018-08-31 8:34 ` Thomas Huth
@ 2018-08-31 8:55 ` Cédric Le Goater
0 siblings, 0 replies; 11+ messages in thread
From: Cédric Le Goater @ 2018-08-31 8:55 UTC (permalink / raw)
To: Thomas Huth, qemu-devel, Peter Maydell
Cc: Andrew Jeffery, qemu-arm, Joel Stanley, Markus Armbruster
On 08/31/2018 10:34 AM, Thomas Huth wrote:
> On 2018-06-22 09:57, Cédric Le Goater wrote:
>> The timer controller can be driven by either an external 1MHz clock or
>> by the APB clock. Today, the model makes the assumption that the APB
>> frequency is always set to 24MHz but this is incorrect.
>>
>> The AST2400 SoC on the palmetto machines uses a 48MHz input clock
>> source and the APB can be set to 48MHz. The consequence is a general
>> system slowdown. The QEMU machines using the AST2500 SoC do not seem
>> impacted today because the APB frequency is still set to 24MHz.
>>
>> We fix the timer frequency for all SoCs by linking the Timer model to
>> the SCU model. The APB frequency driving the timers is now the one
>> configured for the SoC.
>>
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>> Reviewed-by: Joel Stanley <joel@jms.id.au>
>> ---
>> include/hw/timer/aspeed_timer.h | 4 ++++
>> hw/arm/aspeed_soc.c | 2 ++
>> hw/timer/aspeed_timer.c | 19 +++++++++++++++----
>> 3 files changed, 21 insertions(+), 4 deletions(-)
>>
>> diff --git a/include/hw/timer/aspeed_timer.h b/include/hw/timer/aspeed_timer.h
>> index bd6c1a7f9609..040a08873432 100644
>> --- a/include/hw/timer/aspeed_timer.h
>> +++ b/include/hw/timer/aspeed_timer.h
>> @@ -24,6 +24,8 @@
>>
>> #include "qemu/timer.h"
>>
>> +typedef struct AspeedSCUState AspeedSCUState;
>> +
>> #define ASPEED_TIMER(obj) \
>> OBJECT_CHECK(AspeedTimerCtrlState, (obj), TYPE_ASPEED_TIMER);
>> #define TYPE_ASPEED_TIMER "aspeed.timer"
>> @@ -55,6 +57,8 @@ typedef struct AspeedTimerCtrlState {
>> uint32_t ctrl;
>> uint32_t ctrl2;
>> AspeedTimer timers[ASPEED_TIMER_NR_TIMERS];
>> +
>> + AspeedSCUState *scu;
>> } AspeedTimerCtrlState;
>
> This patch breaks compiling with clang 3.4.2 for me:
>
> In file included from /home/thuth/devel/qemu/hw/timer/aspeed_timer.c:16:
> /home/thuth/devel/qemu/include/hw/misc/aspeed_scu.h:37:3: error:
> redefinition of typedef 'AspeedSCUState' is a C11 feature
> [-Werror,-Wtypedef-redefinition]
> } AspeedSCUState;
> ^
> /home/thuth/devel/qemu/include/hw/timer/aspeed_timer.h:27:31: note:
> previous definition is here
> typedef struct AspeedSCUState AspeedSCUState;
Ah. Bummer. I will just include the file then.
>
> I think you should not re-typedef here. Either include the right header,
> or use include/qemu/typedefs.h.
I didn't know this file existed. I am not sure to like this method.
> Thomas
>
>
> PS: Did I already mention that I really dislike the typedeffing in QEMU?
>
It's a bit painful I agree.
Thanks,
C.
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2018-08-31 8:55 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-06-22 7:56 [Qemu-devel] [PATCH v2 0/3] aspeed: introduce the APB clock settings Cédric Le Goater
2018-06-22 7:56 ` [Qemu-devel] [PATCH v2 1/3] aspeed/scu: introduce clock frequencies Cédric Le Goater
2018-06-25 0:54 ` Andrew Jeffery
2018-06-22 7:56 ` [Qemu-devel] [PATCH v2 2/3] aspeed: initialize the SCU controller first Cédric Le Goater
2018-06-25 0:54 ` Andrew Jeffery
2018-06-22 7:57 ` [Qemu-devel] [PATCH v2 3/3] aspeed/timer: use the APB frequency from the SCU Cédric Le Goater
2018-06-25 0:59 ` Andrew Jeffery
2018-08-31 8:34 ` Thomas Huth
2018-08-31 8:55 ` Cédric Le Goater
2018-06-22 11:14 ` [Qemu-devel] [PATCH v2 0/3] aspeed: introduce the APB clock settings no-reply
2018-06-26 16:05 ` Peter Maydell
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