[PATCH v2 00/20] ICELAKE DSI DRIVER

[PATCH v2 00/20] ICELAKE DSI DRIVER

[Madhav Chauhan]

From ICELAKE platform onwards, new MIPI DSI IP controller is integrated to
GPU/Display Engine and same could be extended for future Intel platforms as well.
DSI IP controller supports MIPI DSI 1.3 and DPHY 1.2 specification.

So, a new DSI driver has been added inside I915.

Given below patches are the part of new DSI driver which implements BSPEC
sequence till transcoder configuration. Rest of the patches (~45) will be
published to GITHUB and will share the GITHUB link so that complete
implementation can be looked at by reviewers.

v2: Addressed review comments from Jani N for Patches 1-6 and rebase for some
other few patches.

Madhav Chauhan (20):
  drm/i915/icl: Define register for DSI PLL
  drm/i915/icl: Program DSI Escape clock Divider
  drm/i915/icl: Define DSI mode ctl register
  drm/i915/icl: Enable DSI IO power
  drm/i915/icl: Define PORT_CL_DW_10 register
  drm/i915/icl: Power down unused DSI lanes
  drm/i915/icl: Define AUX lane registers for Port A/B
  drm/i915/icl: Configure lane sequencing of combo phy transmitter
  drm/i915/icl: DSI vswing programming sequence
  drm/i915/icl: Enable DDI Buffer
  drm/i915/icl: Define T_INIT_MASTER registers
  drm/i915/icl: Program T_INIT_MASTER registers
  drm/i915/icl: Define data/clock lanes dphy timing registers
  drm/i915/icl: Program DSI clock and data lane timing params
  drm/i915/icl: Define TA_TIMING_PARAM registers
  drm/i915/icl: Program TA_TIMING_PARAM registers
  drm/i915/icl: Get DSI transcoder for a given port
  drm/i915/icl: Add macros for MMIO of DSI transcoder registers
  drm/i915/icl: Define TRANS_DSI_FUNC_CONF register
  drm/i915/icl: Configure DSI transcoders

 drivers/gpu/drm/i915/Makefile        |   1 +
 drivers/gpu/drm/i915/i915_reg.h      | 178 ++++++++++++++
 drivers/gpu/drm/i915/intel_display.h |   6 +-
 drivers/gpu/drm/i915/intel_dsi.h     |   7 +
 drivers/gpu/drm/i915/intel_dsi_new.c | 451 +++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_dsi_vbt.c | 202 +++++++++++-----
 6 files changed, 787 insertions(+), 58 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_dsi_new.c

-- 
2.7.4

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[PATCH v2 01/20] drm/i915/icl: Define register for DSI PLL

[Madhav Chauhan]

This patch adds the new registers and corresponding bit definitions
which will be used for programming/enable DSI PLL.

v2: Review comments from Jani N
    - Fix spaces while defining ICL_ESC_CLK_DIV_MASK
    - Define shift and mask for bitfields.

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c30cfcd..d414940 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9522,6 +9522,21 @@ enum skl_power_gate {
 #define MIPIO_TXESC_CLK_DIV2			_MMIO(0x160008)
 #define  GLK_TX_ESC_CLK_DIV2_MASK			0x3FF
 
+#define _ICL_DSI_ESC_CLK_DIV0		0x6b090
+#define _ICL_DSI_ESC_CLK_DIV1		0x6b890
+#define ICL_DSI_ESC_CLK_DIV(port)	_MMIO_PORT((port),	\
+							_ICL_DSI_ESC_CLK_DIV0, \
+							_ICL_DSI_ESC_CLK_DIV1)
+#define _ICL_DPHY_ESC_CLK_DIV0		0x162190
+#define _ICL_DPHY_ESC_CLK_DIV1		0x6C190
+#define ICL_DPHY_ESC_CLK_DIV(port)	_MMIO_PORT((port),	\
+						_ICL_DPHY_ESC_CLK_DIV0, \
+						_ICL_DPHY_ESC_CLK_DIV1)
+#define  ICL_BYTE_CLK_PER_ESC_CLK_MASK		(0x1f << 16)
+#define  ICL_BYTE_CLK_PER_ESC_CLK_SHIFT	16
+#define  ICL_ESC_CLK_DIV_MASK			0x1ff
+#define  ICL_ESC_CLK_DIV_SHIFT			0
+
 /* Gen4+ Timestamp and Pipe Frame time stamp registers */
 #define GEN4_TIMESTAMP		_MMIO(0x2358)
 #define ILK_TIMESTAMP_HI	_MMIO(0x70070)
-- 
2.7.4

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[PATCH v2 02/20] drm/i915/icl: Program DSI Escape clock Divider

[Madhav Chauhan]

Escape Clock is used for LP communication across the DSI
Link. To achieve the constant frequency of the escape clock
from the variable DPLL frequency output, a variable divider(M)
is needed. This patch programs the same.

v2: (Jani N) Don't end line with "(".

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/Makefile        |  1 +
 drivers/gpu/drm/i915/i915_reg.h      |  1 +
 drivers/gpu/drm/i915/intel_dsi_new.c | 64 ++++++++++++++++++++++++++++++++++++
 3 files changed, 66 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/intel_dsi_new.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 4c6adae..a5f60c8 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -142,6 +142,7 @@ i915-y += dvo_ch7017.o \
 	  intel_dp_mst.o \
 	  intel_dp.o \
 	  intel_dsi.o \
+	  intel_dsi_new.o \
 	  intel_dsi_dcs_backlight.o \
 	  intel_dsi_pll.o \
 	  intel_dsi_vbt.o \
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d414940..414579f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9536,6 +9536,7 @@ enum skl_power_gate {
 #define  ICL_BYTE_CLK_PER_ESC_CLK_SHIFT	16
 #define  ICL_ESC_CLK_DIV_MASK			0x1ff
 #define  ICL_ESC_CLK_DIV_SHIFT			0
+#define DSI_MAX_ESC_CLK			20000		/* in KHz */
 
 /* Gen4+ Timestamp and Pipe Frame time stamp registers */
 #define GEN4_TIMESTAMP		_MMIO(0x2358)
diff --git a/drivers/gpu/drm/i915/intel_dsi_new.c b/drivers/gpu/drm/i915/intel_dsi_new.c
new file mode 100644
index 0000000..a890b36
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_dsi_new.c
@@ -0,0 +1,64 @@
+/*
+ * Copyright © 2018 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *   Madhav Chauhan <madhav.chauhan@intel.com>
+ *   Jani Nikula <jani.nikula@intel.com>
+ */
+
+#include "intel_dsi.h"
+
+static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	enum port port;
+	u32 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
+	u32 afe_clk_khz; /* 8X Clock */
+	u32 esc_clk_div_m;
+
+	afe_clk_khz = DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp,
+					intel_dsi->lane_count);
+
+	esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK);
+
+	for_each_dsi_port(port, intel_dsi->ports) {
+		I915_WRITE(ICL_DSI_ESC_CLK_DIV(port),
+				esc_clk_div_m & ICL_ESC_CLK_DIV_MASK);
+		POSTING_READ(ICL_DSI_ESC_CLK_DIV(port));
+	}
+
+	for_each_dsi_port(port, intel_dsi->ports) {
+		I915_WRITE(ICL_DPHY_ESC_CLK_DIV(port),
+				esc_clk_div_m & ICL_ESC_CLK_DIV_MASK);
+		POSTING_READ(ICL_DPHY_ESC_CLK_DIV(port));
+	}
+}
+
+static void __attribute__((unused))
+gen11_dsi_pre_enable(struct intel_encoder *encoder,
+		const struct intel_crtc_state *pipe_config,
+		const struct drm_connector_state *conn_state)
+{
+	/* step3: enable DSI PLL */
+	gen11_dsi_program_esc_clk_div(encoder);
+}
-- 
2.7.4

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[PATCH v2 03/20] drm/i915/icl: Define DSI mode ctl register

[Madhav Chauhan]

This patch defines DSI IO mode control register and it's bits
used while enabling IO power for DSI.

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 414579f..dfd603c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9672,6 +9672,14 @@ enum skl_power_gate {
 #define _BXT_MIPIC_PORT_CTRL				0x6B8C0
 #define BXT_MIPI_PORT_CTRL(tc)	_MMIO_MIPI(tc, _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL)
 
+/* ICL DSI MODE control */
+#define _ICL_DSI_IO_MODECTL_0				0x6B094
+#define _ICL_DSI_IO_MODECTL_1				0x6B894
+#define ICL_DSI_IO_MODECTL(port)	_MMIO_PORT(port,	\
+						    _ICL_DSI_IO_MODECTL_0, \
+						    _ICL_DSI_IO_MODECTL_1)
+#define  COMBO_PHY_MODE_DSI				(1 << 0)
+
 #define BXT_P_DSI_REGULATOR_CFG			_MMIO(0x160020)
 #define  STAP_SELECT					(1 << 0)
 
-- 
2.7.4

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[PATCH v2 04/20] drm/i915/icl: Enable DSI IO power

[Madhav Chauhan]

This patch configures mode of operation for DSI
and enable DDI IO power by configuring power well.

v2: Use for_each_dsi_port() for power get (Jani N)

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_new.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dsi_new.c b/drivers/gpu/drm/i915/intel_dsi_new.c
index a890b36..64f97c7 100644
--- a/drivers/gpu/drm/i915/intel_dsi_new.c
+++ b/drivers/gpu/drm/i915/intel_dsi_new.c
@@ -54,11 +54,34 @@ static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder)
 	}
 }
 
+static void gen11_dsi_enable_io_power(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	enum port port;
+	u32 tmp;
+
+	for_each_dsi_port(port, intel_dsi->ports) {
+		tmp = I915_READ(ICL_DSI_IO_MODECTL(port));
+		tmp |= COMBO_PHY_MODE_DSI;
+		I915_WRITE(ICL_DSI_IO_MODECTL(port), tmp);
+	}
+
+	for_each_dsi_port(port, intel_dsi->ports) {
+		intel_display_power_get(dev_priv, port == PORT_A ?
+					POWER_DOMAIN_PORT_DDI_A_IO :
+					POWER_DOMAIN_PORT_DDI_B_IO);
+	}
+}
+
 static void __attribute__((unused))
 gen11_dsi_pre_enable(struct intel_encoder *encoder,
 		const struct intel_crtc_state *pipe_config,
 		const struct drm_connector_state *conn_state)
 {
+	/* step2: enable IO power */
+	gen11_dsi_enable_io_power(encoder);
+
 	/* step3: enable DSI PLL */
 	gen11_dsi_program_esc_clk_div(encoder);
 }
-- 
2.7.4

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[PATCH v2 05/20] drm/i915/icl: Define PORT_CL_DW_10 register

[Madhav Chauhan]

This register used to power down individual lanes for
DDI/DSI ports. Bitfields to power up/down various
combinations of lanes are also added in this patch.

v2: Review comments from Jani N
    - Use override instead of "override" for bitfields
    - Define mask for override bitfield
    - Define PWR_DOWN_LN* macros shifted in place

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index dfd603c..3fa8f02 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1704,6 +1704,26 @@ enum i915_power_well_id {
 #define ICL_PORT_CL_DW5(port)	_MMIO_PORT(port, _ICL_PORT_CL_DW5_A, \
 						 _ICL_PORT_CL_DW5_B)
 
+#define _CNL_PORT_CL_DW10_A		0x162028
+#define _ICL_PORT_CL_DW10_B		0x6c028
+#define ICL_PORT_CL_DW10(port)		_MMIO_PORT(port,	\
+						   _CNL_PORT_CL_DW10_A, \
+						   _ICL_PORT_CL_DW10_B)
+#define  PG_SEQ_DELAY_OVERRIDE_MASK	(3 << 25)
+#define  PG_SEQ_DELAY_OVERRIDE_SHIFT	25
+#define  PG_SEQ_DELAY_OVERRIDE_ENABLE	(1 << 24)
+#define  PWR_UP_ALL_LANES		(0x0 << 4)
+#define  PWR_DOWN_LN_3_2_1		(0xe << 4)
+#define  PWR_DOWN_LN_3_2		(0xc << 4)
+#define  PWR_DOWN_LN_3			(0x8 << 4)
+#define  PWR_DOWN_LN_2_1_0		(0x7 << 4)
+#define  PWR_DOWN_LN_1_0		(0x3 << 4)
+#define  PWR_DOWN_LN_1			(0x2 << 4)
+#define  PWR_DOWN_LN_3_1		(0xa << 4)
+#define  PWR_DOWN_LN_3_1_0		(0xb << 4)
+#define  PWR_DOWN_LN_MASK		(0xf0 << 4)
+#define  PWR_DOWN_LN_SHIFT		4
+
 #define _PORT_CL1CM_DW9_A		0x162024
 #define _PORT_CL1CM_DW9_BC		0x6C024
 #define   IREF0RC_OFFSET_SHIFT		8
-- 
2.7.4

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[PATCH v2 06/20] drm/i915/icl: Power down unused DSI lanes

[Madhav Chauhan]

To save power, unused lanes should be powered
down using the bitfield of PORT_CL_DW10.

v2: Review comments from Jani N
    - Put default label next to case 4
    - Include the shifts in the macros

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_new.c | 40 ++++++++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dsi_new.c b/drivers/gpu/drm/i915/intel_dsi_new.c
index 64f97c7..9262e3f 100644
--- a/drivers/gpu/drm/i915/intel_dsi_new.c
+++ b/drivers/gpu/drm/i915/intel_dsi_new.c
@@ -74,6 +74,43 @@ static void gen11_dsi_enable_io_power(struct intel_encoder *encoder)
 	}
 }
 
+static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	enum port port;
+	u32 tmp;
+	u32 lane_mask;
+
+	switch (intel_dsi->lane_count) {
+	case 1:
+		lane_mask = PWR_DOWN_LN_3_1_0;
+		break;
+	case 2:
+		lane_mask = PWR_DOWN_LN_3_1;
+		break;
+	case 3:
+		lane_mask = PWR_DOWN_LN_3;
+		break;
+	case 4:
+	default:
+		lane_mask = PWR_UP_ALL_LANES;
+		break;
+	}
+
+	for_each_dsi_port(port, intel_dsi->ports) {
+		tmp = I915_READ(ICL_PORT_CL_DW10(port));
+		tmp &= ~PWR_DOWN_LN_MASK;
+		I915_WRITE(ICL_PORT_CL_DW10(port), tmp | lane_mask);
+	}
+}
+
+static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
+{
+	/* step 4a: power up all lanes of the DDI used by DSI */
+	gen11_dsi_power_up_lanes(encoder);
+}
+
 static void __attribute__((unused))
 gen11_dsi_pre_enable(struct intel_encoder *encoder,
 		const struct intel_crtc_state *pipe_config,
@@ -84,4 +121,7 @@ gen11_dsi_pre_enable(struct intel_encoder *encoder,
 
 	/* step3: enable DSI PLL */
 	gen11_dsi_program_esc_clk_div(encoder);
+
+	/* step4: enable DSI port and DPHY */
+	gen11_dsi_enable_port_and_phy(encoder);
 }
-- 
2.7.4

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[PATCH v2 07/20] drm/i915/icl: Define AUX lane registers for Port A/B

[Madhav Chauhan]

This patch defines AUX lane registers for PORT_PCS_DW1,
PORT_TX_DW2, PORT_TX_DW4, PORT_TX_DW5 used during
dsi enabling.

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3fa8f02..d3ce1a9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1780,16 +1780,21 @@ enum i915_power_well_id {
 						    _CNL_PORT_PCS_DW1_LN0_D, \
 						    _CNL_PORT_PCS_DW1_LN0_AE, \
 						    _CNL_PORT_PCS_DW1_LN0_F))
+
 #define _ICL_PORT_PCS_DW1_GRP_A		0x162604
 #define _ICL_PORT_PCS_DW1_GRP_B		0x6C604
 #define _ICL_PORT_PCS_DW1_LN0_A		0x162804
 #define _ICL_PORT_PCS_DW1_LN0_B		0x6C804
+#define _ICL_PORT_PCS_DW1_AUX_B		0x6c304
 #define ICL_PORT_PCS_DW1_GRP(port)	_MMIO_PORT(port,\
 						   _ICL_PORT_PCS_DW1_GRP_A, \
 						   _ICL_PORT_PCS_DW1_GRP_B)
 #define ICL_PORT_PCS_DW1_LN0(port)	_MMIO_PORT(port, \
 						   _ICL_PORT_PCS_DW1_LN0_A, \
 						   _ICL_PORT_PCS_DW1_LN0_B)
+#define ICL_PORT_PCS_DW1_AUX(port)	_MMIO_PORT(port, \
+						   _CNL_PORT_PCS_DW1_GRP_AE, \
+						   _ICL_PORT_PCS_DW1_AUX_B)
 #define   COMMON_KEEPER_EN		(1 << 26)
 
 /* CNL Port TX registers */
@@ -1826,16 +1831,23 @@ enum i915_power_well_id {
 #define _ICL_PORT_TX_DW2_GRP_B		0x6C688
 #define _ICL_PORT_TX_DW2_LN0_A		0x162888
 #define _ICL_PORT_TX_DW2_LN0_B		0x6C888
+#define _ICL_PORT_TX_DW2_AUX_A		0x162388
+#define _ICL_PORT_TX_DW2_AUX_B		0x6c388
 #define ICL_PORT_TX_DW2_GRP(port)	_MMIO_PORT(port, \
 						   _ICL_PORT_TX_DW2_GRP_A, \
 						   _ICL_PORT_TX_DW2_GRP_B)
 #define ICL_PORT_TX_DW2_LN0(port)	_MMIO_PORT(port, \
 						   _ICL_PORT_TX_DW2_LN0_A, \
 						   _ICL_PORT_TX_DW2_LN0_B)
+#define ICL_PORT_TX_DW2_AUX(port)	_MMIO_PORT(port, \
+						   _ICL_PORT_TX_DW2_AUX_A, \
+						   _ICL_PORT_TX_DW2_AUX_B)
 #define   SWING_SEL_UPPER(x)		(((x) >> 3) << 15)
 #define   SWING_SEL_UPPER_MASK		(1 << 15)
 #define   SWING_SEL_LOWER(x)		(((x) & 0x7) << 11)
 #define   SWING_SEL_LOWER_MASK		(0x7 << 11)
+#define  FRC_LATENCY_OPTIM_MASK	(0x7 << 8)
+#define  FRC_LATENCY_OPTIM_VAL(x)	((x) << 8)
 #define   RCOMP_SCALAR(x)		((x) << 0)
 #define   RCOMP_SCALAR_MASK		(0xFF << 0)
 
@@ -1851,6 +1863,8 @@ enum i915_power_well_id {
 #define _ICL_PORT_TX_DW4_LN0_A		0x162890
 #define _ICL_PORT_TX_DW4_LN1_A		0x162990
 #define _ICL_PORT_TX_DW4_LN0_B		0x6C890
+#define _ICL_PORT_TX_DW4_AUX_A		0x162390
+#define _ICL_PORT_TX_DW4_AUX_B		0x6c390
 #define ICL_PORT_TX_DW4_GRP(port)	_MMIO_PORT(port, \
 						   _ICL_PORT_TX_DW4_GRP_A, \
 						   _ICL_PORT_TX_DW4_GRP_B)
@@ -1859,6 +1873,9 @@ enum i915_power_well_id {
 						   _ICL_PORT_TX_DW4_LN0_B) + \
 					     ((ln) * (_ICL_PORT_TX_DW4_LN1_A - \
 						      _ICL_PORT_TX_DW4_LN0_A)))
+#define ICL_PORT_TX_DW4_AUX(port)	_MMIO_PORT(port, \
+						   _ICL_PORT_TX_DW4_AUX_A, \
+						   _ICL_PORT_TX_DW4_AUX_B)
 #define   LOADGEN_SELECT		(1 << 31)
 #define   POST_CURSOR_1(x)		((x) << 12)
 #define   POST_CURSOR_1_MASK		(0x3F << 12)
@@ -1873,12 +1890,17 @@ enum i915_power_well_id {
 #define _ICL_PORT_TX_DW5_GRP_B		0x6C694
 #define _ICL_PORT_TX_DW5_LN0_A		0x162894
 #define _ICL_PORT_TX_DW5_LN0_B		0x6C894
+#define _ICL_PORT_TX_DW5_AUX_A		0x162394
+#define _ICL_PORT_TX_DW5_AUX_B		0x6c394
 #define ICL_PORT_TX_DW5_GRP(port)	_MMIO_PORT(port, \
 						   _ICL_PORT_TX_DW5_GRP_A, \
 						   _ICL_PORT_TX_DW5_GRP_B)
 #define ICL_PORT_TX_DW5_LN0(port)	_MMIO_PORT(port, \
 						   _ICL_PORT_TX_DW5_LN0_A, \
 						   _ICL_PORT_TX_DW5_LN0_B)
+#define ICL_PORT_TX_DW5_AUX(port)	_MMIO_PORT(port, \
+						   _ICL_PORT_TX_DW5_AUX_A, \
+						   _ICL_PORT_TX_DW5_AUX_B)
 #define   TX_TRAINING_EN		(1 << 31)
 #define   TAP2_DISABLE			(1 << 30)
 #define   TAP3_DISABLE			(1 << 29)
-- 
2.7.4

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[PATCH v2 08/20] drm/i915/icl: Configure lane sequencing of combo phy transmitter

[Madhav Chauhan]

This patch set the loadgen select and latency optimization for
aux and transmit lanes of combo phy transmitters. It will be
used for MIPI DSI HS operations.

v2: Rebase

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_new.c | 38 ++++++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dsi_new.c b/drivers/gpu/drm/i915/intel_dsi_new.c
index 9262e3f..3192450 100644
--- a/drivers/gpu/drm/i915/intel_dsi_new.c
+++ b/drivers/gpu/drm/i915/intel_dsi_new.c
@@ -105,10 +105,48 @@ static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder)
 	}
 }
 
+static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	enum port port;
+	u32 tmp;
+	int lane;
+
+	/* Step 4b(i) set loadgen select for transmit and aux lanes */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		tmp = I915_READ(ICL_PORT_TX_DW4_AUX(port));
+		tmp &= ~LOADGEN_SELECT;
+		I915_WRITE(ICL_PORT_TX_DW4_AUX(port), tmp);
+		for (lane = 0; lane <= 3; lane++) {
+			tmp = I915_READ(ICL_PORT_TX_DW4_LN(port, lane));
+			tmp &= ~LOADGEN_SELECT;
+			if (lane != 2)
+				tmp |= LOADGEN_SELECT;
+			I915_WRITE(ICL_PORT_TX_DW4_LN(port, lane), tmp);
+		}
+	}
+
+	/* Step 4b(ii) set latency optimization for transmit and aux lanes */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		tmp = I915_READ(ICL_PORT_TX_DW2_AUX(port));
+		tmp &= ~FRC_LATENCY_OPTIM_MASK;
+		tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
+		I915_WRITE(ICL_PORT_TX_DW2_AUX(port), tmp);
+		tmp = I915_READ(ICL_PORT_TX_DW2_LN0(port));
+		tmp &= ~FRC_LATENCY_OPTIM_MASK;
+		tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
+		I915_WRITE(ICL_PORT_TX_DW2_GRP(port), tmp);
+	}
+}
+
 static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
 {
 	/* step 4a: power up all lanes of the DDI used by DSI */
 	gen11_dsi_power_up_lanes(encoder);
+
+	/* step 4b: configure lane sequencing of the Combo-PHY transmitters */
+	gen11_dsi_config_phy_lanes_sequence(encoder);
 }
 
 static void __attribute__((unused))
-- 
2.7.4

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[PATCH v2 09/20] drm/i915/icl: DSI vswing programming sequence

[Madhav Chauhan]

This patch setup voltage swing before enabling
combo PHY DDI (shared with DSI).
Note that DSI voltage swing programming is for
high speed data buffers. HW automatically handles
the voltage swing for the low power data buffers.

v2: Rebase

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_new.c | 114 +++++++++++++++++++++++++++++++++++
 1 file changed, 114 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dsi_new.c b/drivers/gpu/drm/i915/intel_dsi_new.c
index 3192450..45420f2 100644
--- a/drivers/gpu/drm/i915/intel_dsi_new.c
+++ b/drivers/gpu/drm/i915/intel_dsi_new.c
@@ -27,6 +27,65 @@
 
 #include "intel_dsi.h"
 
+static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	enum port port;
+	u32 tmp;
+	int lane;
+
+	for_each_dsi_port(port, intel_dsi->ports) {
+
+		/* Bspec: set scaling mode to 0x6 */
+		tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
+		tmp |= SCALING_MODE_SEL(6);
+		I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
+		tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
+		tmp |= SCALING_MODE_SEL(6);
+		I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
+		tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
+		tmp |= TAP2_DISABLE | TAP3_DISABLE;
+		I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
+		tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
+		tmp |= TAP2_DISABLE | TAP3_DISABLE;
+		I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
+
+		/*
+		 * swing and scaling values are taken from DSI
+		 * table under vswing programming sequence for
+		 * combo phy ddi in BSPEC.
+		 * program swing values
+		 */
+		tmp = I915_READ(ICL_PORT_TX_DW2_LN0(port));
+		tmp |= SWING_SEL_UPPER(0x2);
+		tmp |= SWING_SEL_LOWER(0x2);
+		tmp |= RCOMP_SCALAR(0x98);
+		I915_WRITE(ICL_PORT_TX_DW2_GRP(port), tmp);
+		tmp = I915_READ(ICL_PORT_TX_DW2_AUX(port));
+		tmp |= SWING_SEL_UPPER(0x2);
+		tmp |= SWING_SEL_LOWER(0x2);
+		tmp |= RCOMP_SCALAR(0x98);
+		I915_WRITE(ICL_PORT_TX_DW2_AUX(port), tmp);
+
+		/* program scaling values */
+		tmp = I915_READ(ICL_PORT_TX_DW4_AUX(port));
+		tmp |= POST_CURSOR_1(0x0);
+		tmp |= POST_CURSOR_2(0x0);
+		tmp |= CURSOR_COEFF(0x18);
+		I915_WRITE(ICL_PORT_TX_DW4_AUX(port), tmp);
+
+		for (lane = 0; lane <= 3; lane++) {
+			/* Bspec: must not use GRP register for write */
+			tmp = I915_READ(ICL_PORT_TX_DW4_LN(port, lane));
+			tmp |= POST_CURSOR_1(0x0);
+			tmp |= POST_CURSOR_2(0x0);
+			tmp |= CURSOR_COEFF(0x18);
+			I915_WRITE(ICL_PORT_TX_DW4_LN(port, lane), tmp);
+		}
+	}
+}
+
 static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -140,6 +199,58 @@ static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
 	}
 }
 
+static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	u32 tmp;
+	enum port port;
+
+	/* Step C.1:clear common keeper enable bit */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		tmp = I915_READ(ICL_PORT_PCS_DW1_LN0(port));
+		tmp &= ~COMMON_KEEPER_EN;
+		I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), tmp);
+		tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(port));
+		tmp &= ~COMMON_KEEPER_EN;
+		I915_WRITE(ICL_PORT_PCS_DW1_AUX(port), tmp);
+	}
+
+	/*
+	 * Step C.3: Set SUS Clock Config bitfield to 11b
+	 * Note: Step C.2 (loadgen select program) is done
+	 * as part of lane phy sequence configuration
+	 */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		tmp = I915_READ(ICL_PORT_CL_DW5(port));
+		tmp |= SUS_CLOCK_CONFIG;
+		I915_WRITE(ICL_PORT_CL_DW5(port), tmp);
+	}
+
+	/* Step C.4: Clear training enable to change swing values */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
+		tmp &= ~TX_TRAINING_EN;
+		I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
+		tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
+		tmp &= ~TX_TRAINING_EN;
+		I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
+	}
+
+	/* Step C.5: Program swing and de-emphasis */
+	dsi_program_swing_and_deemphasis(encoder);
+
+	/* Step: C.6: Set training enable to trigger update */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
+		tmp |= TX_TRAINING_EN;
+		I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
+		tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
+		tmp |= TX_TRAINING_EN;
+		I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
+	}
+}
+
 static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
 {
 	/* step 4a: power up all lanes of the DDI used by DSI */
@@ -147,6 +258,9 @@ static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
 
 	/* step 4b: configure lane sequencing of the Combo-PHY transmitters */
 	gen11_dsi_config_phy_lanes_sequence(encoder);
+
+	/* step 4c: configure voltage swing and skew */
+	gen11_dsi_voltage_swing_program_seq(encoder);
 }
 
 static void __attribute__((unused))
-- 
2.7.4

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[PATCH v2 10/20] drm/i915/icl: Enable DDI Buffer

[Madhav Chauhan]

This patch enables DDI buffer by writing to DDI_BUF_CTL
register and wait for DDI status to be *not idle* for a
port.

v2: Rebase

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_new.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dsi_new.c b/drivers/gpu/drm/i915/intel_dsi_new.c
index 45420f2..0f481af 100644
--- a/drivers/gpu/drm/i915/intel_dsi_new.c
+++ b/drivers/gpu/drm/i915/intel_dsi_new.c
@@ -251,6 +251,25 @@ static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder)
 	}
 }
 
+static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	u32 tmp;
+	enum port port;
+
+	for_each_dsi_port(port, intel_dsi->ports) {
+		tmp = I915_READ(DDI_BUF_CTL(port));
+		tmp |= DDI_BUF_CTL_ENABLE;
+		I915_WRITE(DDI_BUF_CTL(port), tmp);
+
+		if (wait_for_us(!(I915_READ(DDI_BUF_CTL(port)) &
+				  DDI_BUF_IS_IDLE),
+				  500))
+			DRM_ERROR("DDI port:%c buffer idle\n", port_name(port));
+	}
+}
+
 static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
 {
 	/* step 4a: power up all lanes of the DDI used by DSI */
@@ -261,6 +280,9 @@ static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
 
 	/* step 4c: configure voltage swing and skew */
 	gen11_dsi_voltage_swing_program_seq(encoder);
+
+	/* step 4d: enable DDI buffer */
+	gen11_dsi_enable_ddi_buffer(encoder);
 }
 
 static void __attribute__((unused))
-- 
2.7.4

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[PATCH v2 11/20] drm/i915/icl: Define T_INIT_MASTER registers

[Madhav Chauhan]

This patch defines DSI_T_INIT_MASTER register for DSI ports
0/1 which will be used in dphy programming.

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d3ce1a9..d6acd42 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10052,6 +10052,12 @@ enum skl_power_gate {
 #define  PREPARE_COUNT_SHIFT				0
 #define  PREPARE_COUNT_MASK				(0x3f << 0)
 
+#define _ICL_DSI_T_INIT_MASTER_0	0x6b088
+#define _ICL_DSI_T_INIT_MASTER_1	0x6b888
+#define ICL_DSI_T_INIT_MASTER(port)	_MMIO_PORT(port,	\
+						   _ICL_DSI_T_INIT_MASTER_0,\
+						   _ICL_DSI_T_INIT_MASTER_1)
+
 /* bits 31:0 */
 #define _MIPIA_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb084)
 #define _MIPIC_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb884)
-- 
2.7.4

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[PATCH v2 12/20] drm/i915/icl: Program T_INIT_MASTER registers

[Madhav Chauhan]

This patch programs the time (in escape clocks) to drive
the link in the initialization (i.e. LP-11) state.

v2: Rebase

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_new.c | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dsi_new.c b/drivers/gpu/drm/i915/intel_dsi_new.c
index 0f481af..db65633 100644
--- a/drivers/gpu/drm/i915/intel_dsi_new.c
+++ b/drivers/gpu/drm/i915/intel_dsi_new.c
@@ -270,6 +270,22 @@ static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder)
 	}
 }
 
+static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	u32 tmp;
+	enum port port;
+
+	/* Program T-INIT master registers */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		tmp = I915_READ(ICL_DSI_T_INIT_MASTER(port));
+		tmp &= ~MASTER_INIT_TIMER_MASK;
+		tmp |= intel_dsi->init_count;
+		I915_WRITE(ICL_DSI_T_INIT_MASTER(port), tmp);
+	}
+}
+
 static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
 {
 	/* step 4a: power up all lanes of the DDI used by DSI */
@@ -283,6 +299,9 @@ static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
 
 	/* step 4d: enable DDI buffer */
 	gen11_dsi_enable_ddi_buffer(encoder);
+
+	/* step 4e: setup D-PHY timings */
+	gen11_dsi_setup_dphy_timings(encoder);
 }
 
 static void __attribute__((unused))
-- 
2.7.4

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[PATCH v2 13/20] drm/i915/icl: Define data/clock lanes dphy timing registers

[Madhav Chauhan]

This patch defines DSI_CLK_TIMING_PARAM, DPHY_CLK_TIMING_PARAM,
DSI_DATA_TIMING_PARAM, DPHY_DATA_TIMING_PARAM register used in
dphy programming.

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 40 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d6acd42..9c5d8c1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10058,6 +10058,46 @@ enum skl_power_gate {
 						   _ICL_DSI_T_INIT_MASTER_0,\
 						   _ICL_DSI_T_INIT_MASTER_1)
 
+#define _DPHY_CLK_TIMING_PARAM_0	0x162180
+#define _DPHY_CLK_TIMING_PARAM_1	0x6c180
+#define DPHY_CLK_TIMING_PARAM(port)	_MMIO_PORT(port,	\
+						   _DPHY_CLK_TIMING_PARAM_0,\
+						   _DPHY_CLK_TIMING_PARAM_1)
+#define _DSI_CLK_TIMING_PARAM_0		0x6b080
+#define _DSI_CLK_TIMING_PARAM_1		0x6b880
+#define DSI_CLK_TIMING_PARAM(port)	_MMIO_PORT(port,	\
+						   _DSI_CLK_TIMING_PARAM_0,\
+						   _DSI_CLK_TIMING_PARAM_1)
+#define  CLK_PREP_OVERRIDE		(1 << 31)
+#define  CLK_PREP_TIME(x)		(x << 28)
+#define  CLK_ZERO_OVERRIDE		(1 << 27)
+#define  CLK_ZERO_TIME(x)		(x << 20)
+#define  CLK_PRE_OVERRIDE		(1 << 19)
+#define  CLK_PRE_TIME(x)		(x << 16)
+#define  CLK_POST_OVERRIDE		(1 << 15)
+#define  CLK_POST_TIME(x)		(x << 8)
+#define  CLK_TRAIL_OVERRIDE		(1 << 7)
+#define  CLK_TRAIL_TIME(x)		(x << 0)
+
+#define _DPHY_DATA_TIMING_PARAM_0	0x162184
+#define _DPHY_DATA_TIMING_PARAM_1	0x6c184
+#define DPHY_DATA_TIMING_PARAM(port)	_MMIO_PORT(port,	\
+						   _DPHY_DATA_TIMING_PARAM_0,\
+						   _DPHY_DATA_TIMING_PARAM_1)
+#define _DSI_DATA_TIMING_PARAM_0	0x6B084
+#define _DSI_DATA_TIMING_PARAM_1	0x6B884
+#define DSI_DATA_TIMING_PARAM(port)	_MMIO_PORT(port,	\
+						   _DSI_DATA_TIMING_PARAM_0,\
+						   _DSI_DATA_TIMING_PARAM_1)
+#define  HS_PREP_OVERRIDE		(1 << 31)
+#define  HS_PREP_TIME(x)		(x << 24)
+#define  HS_ZERO_OVERRIDE		(1 << 23)
+#define  HS_ZERO_TIME(x)		(x << 16)
+#define  HS_TRAIL_OVERRIDE		(1 << 15)
+#define  HS_TRAIL_TIME(x)		(x << 8)
+#define  HS_EXIT_OVERRIDE		(1 << 7)
+#define  HS_EXIT_TIME(x)		(x << 0)
+
 /* bits 31:0 */
 #define _MIPIA_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb084)
 #define _MIPIC_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb884)
-- 
2.7.4

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[PATCH v2 14/20] drm/i915/icl: Program DSI clock and data lane timing params

[Madhav Chauhan]

This patch programs D-PHY timing parameters for the
clock and data lane (in escape clocks) of DSI
controller (DSI port 0 and 1).
These programmed timings would be used by DSI Controller
to calculate link transition latencies of the data and
clock lanes.

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.h     |   3 +
 drivers/gpu/drm/i915/intel_dsi_new.c |  18 ++++
 drivers/gpu/drm/i915/intel_dsi_vbt.c | 200 +++++++++++++++++++++++++----------
 3 files changed, 165 insertions(+), 56 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 7afeb95..12a8154 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -85,6 +85,9 @@ struct intel_dsi {
 	u32 port_bits;
 	u32 bw_timer;
 	u32 dphy_reg;
+
+	/* data lanes dphy timing */
+	u32 dphy_data_lane_reg;
 	u32 video_frmt_cfg_bits;
 	u16 lp_byte_clk;
 
diff --git a/drivers/gpu/drm/i915/intel_dsi_new.c b/drivers/gpu/drm/i915/intel_dsi_new.c
index db65633..ffc17d1 100644
--- a/drivers/gpu/drm/i915/intel_dsi_new.c
+++ b/drivers/gpu/drm/i915/intel_dsi_new.c
@@ -284,6 +284,24 @@ static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
 		tmp |= intel_dsi->init_count;
 		I915_WRITE(ICL_DSI_T_INIT_MASTER(port), tmp);
 	}
+
+	/* Program DPHY clock lanes timings */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		I915_WRITE(DPHY_CLK_TIMING_PARAM(port), intel_dsi->dphy_reg);
+
+		/* shadow register inside display core */
+		I915_WRITE(DSI_CLK_TIMING_PARAM(port), intel_dsi->dphy_reg);
+	}
+
+	/* Program DPHY data lanes timings */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		I915_WRITE(DPHY_DATA_TIMING_PARAM(port),
+			   intel_dsi->dphy_data_lane_reg);
+
+		/* shadow register inside display core */
+		I915_WRITE(DSI_DATA_TIMING_PARAM(port),
+			   intel_dsi->dphy_data_lane_reg);
+	}
 }
 
 static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
index 4d6ffa7..5cc3dd0 100644
--- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
@@ -509,7 +509,9 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
 	u32 bpp;
 	u32 tlpx_ns, extra_byte_count, bitrate, tlpx_ui;
 	u32 ui_num, ui_den;
-	u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
+	u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt, hs_zero_cnt;
+	u32 tclk_pre_cnt, tclk_post_cnt;
+	u32 tclk_pre_ns, tclk_post_ns;
 	u32 ths_prepare_ns, tclk_trail_ns;
 	u32 tclk_prepare_clkzero, ths_prepare_hszero;
 	u32 lp_to_hs_switch, hs_to_lp_switch;
@@ -624,76 +626,157 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
 
 	tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero;
 	ths_prepare_hszero = mipi_config->ths_prepare_hszero;
-
+	tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
+	ths_prepare_ns = max(mipi_config->ths_prepare,
+				mipi_config->tclk_prepare);
 	/*
 	 * B060
 	 * LP byte clock = TLPX/ (8UI)
 	 */
 	intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num);
 
-	/* DDR clock period = 2 * UI
-	 * UI(sec) = 1/(bitrate * 10^3) (bitrate is in KHZ)
-	 * UI(nsec) = 10^6 / bitrate
-	 * DDR clock period (nsec) = 2 * UI = (2 * 10^6)/ bitrate
-	 * DDR clock count  = ns_value / DDR clock period
-	 *
+	/*
 	 * For GEMINILAKE dphy_param_reg will be programmed in terms of
 	 * HS byte clock count for other platform in HS ddr clock count
 	 */
 	mul = IS_GEMINILAKE(dev_priv) ? 8 : 2;
-	ths_prepare_ns = max(mipi_config->ths_prepare,
-			     mipi_config->tclk_prepare);
 
-	/* prepare count */
-	prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * mul);
+	if (IS_ICELAKE(dev_priv)) {
+		/*
+		 * prepare cnt in escape clocks
+		 * this field represents a hexadecimal value with a precision
+		 * of 1.2 – i.e. the most significant bit is the integer
+		 * and the least significant 2 bits are fraction bits.
+		 * so, the field can represent a range of 0.25 to 1.75
+		 */
+		prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * 4, tlpx_ns);
+
+		/* clk zero count in escape clocks */
+		clk_zero_cnt = DIV_ROUND_UP(
+					(tclk_prepare_clkzero - ths_prepare_ns),
+					tlpx_ns);
+
+		/* trail cnt in escape clocks*/
+		trail_cnt = DIV_ROUND_UP(tclk_trail_ns, tlpx_ns);
+
+		/* tclk pre/post count in escape clocks */
+		tclk_post_ns = mipi_config->tclk_post;
+		tclk_pre_ns = mipi_config->tclk_pre;
+		tclk_pre_cnt = DIV_ROUND_UP(tclk_pre_ns, tlpx_ns);
+		tclk_post_cnt = DIV_ROUND_UP(tclk_post_ns, tlpx_ns);
+
+		/* hs zero cnt in escape clocks */
+		hs_zero_cnt = DIV_ROUND_UP(
+					(ths_prepare_hszero - ths_prepare_ns),
+					tlpx_ns);
+
+		/* hs exit zero cnt in escape clocks */
+		exit_zero_cnt = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns);
+
+		if (prepare_cnt > 0x7 ||
+		    clk_zero_cnt > 0xF ||
+		    tclk_pre_cnt > 0x3 ||
+		    tclk_post_cnt > 0x7 ||
+		    trail_cnt > 0x7 ||
+		    hs_zero_cnt > 0xF ||
+		    exit_zero_cnt > 0x7) {
+			DRM_DEBUG_DRIVER("DPHY values crossing max limits,");
+			DRM_DEBUG_DRIVER("restricting to max values\n");
+		}
+
+		prepare_cnt = (prepare_cnt > 0x7) ? 0x7 : prepare_cnt;
+		clk_zero_cnt = (clk_zero_cnt > 0xF) ? 0xF : clk_zero_cnt;
+		tclk_pre_cnt = (tclk_pre_cnt > 0x3) ? 0x3 : tclk_pre_cnt;
+		tclk_post_cnt = (tclk_post_cnt > 0x7) ? 0x7 : tclk_post_cnt;
+		trail_cnt = (trail_cnt > 0x7) ? 0x7 : trail_cnt;
+		hs_zero_cnt = (hs_zero_cnt > 0xF) ? 0xF : hs_zero_cnt;
+		exit_zero_cnt = (exit_zero_cnt > 0x7) ? 0x7 : exit_zero_cnt;
+
+		/* clock lane dphy timings */
+		intel_dsi->dphy_reg |= (CLK_PREP_OVERRIDE |
+					CLK_PREP_TIME(prepare_cnt) |
+					CLK_ZERO_OVERRIDE |
+					CLK_ZERO_TIME(clk_zero_cnt) |
+					CLK_PRE_OVERRIDE |
+					CLK_PRE_TIME(tclk_pre_cnt) |
+					CLK_POST_OVERRIDE |
+					CLK_POST_TIME(tclk_post_cnt) |
+					CLK_TRAIL_OVERRIDE |
+					CLK_TRAIL_TIME(trail_cnt));
+
+		/* data lanes dphy timings */
+		intel_dsi->dphy_data_lane_reg = HS_PREP_OVERRIDE |
+						HS_PREP_TIME(prepare_cnt) |
+						HS_ZERO_OVERRIDE |
+						HS_ZERO_TIME(hs_zero_cnt) |
+						HS_TRAIL_OVERRIDE |
+						HS_TRAIL_TIME(trail_cnt) |
+						HS_EXIT_OVERRIDE |
+						HS_EXIT_TIME(exit_zero_cnt);
+	} else {
+		/*
+		 * DDR clock period = 2 * UI
+		 * UI(sec) = 1/(bitrate * 10^3) (bitrate is in KHZ)
+		 * UI(nsec) = 10^6 / bitrate
+		 * DDR clock period (nsec) = 2 * UI = (2 * 10^6)/ bitrate
+		 * DDR clock count  = ns_value / DDR clock period
+		 */
 
-	if (prepare_cnt > PREPARE_CNT_MAX) {
-		DRM_DEBUG_KMS("prepare count too high %u\n", prepare_cnt);
-		prepare_cnt = PREPARE_CNT_MAX;
-	}
+		/* prepare count */
+		prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den,
+							ui_num * mul);
 
-	/* exit zero count */
-	exit_zero_cnt = DIV_ROUND_UP(
+		if (prepare_cnt > PREPARE_CNT_MAX) {
+			DRM_DEBUG_KMS("prepare count too high %u\n",
+								prepare_cnt);
+			prepare_cnt = PREPARE_CNT_MAX;
+		}
+
+		/* exit zero count */
+		exit_zero_cnt = DIV_ROUND_UP(
 				(ths_prepare_hszero - ths_prepare_ns) * ui_den,
 				ui_num * mul
 				);
 
-	/*
-	 * Exit zero is unified val ths_zero and ths_exit
-	 * minimum value for ths_exit = 110ns
-	 * min (exit_zero_cnt * 2) = 110/UI
-	 * exit_zero_cnt = 55/UI
-	 */
-	if (exit_zero_cnt < (55 * ui_den / ui_num) && (55 * ui_den) % ui_num)
-		exit_zero_cnt += 1;
-
-	if (exit_zero_cnt > EXIT_ZERO_CNT_MAX) {
-		DRM_DEBUG_KMS("exit zero count too high %u\n", exit_zero_cnt);
-		exit_zero_cnt = EXIT_ZERO_CNT_MAX;
-	}
+		/*
+		 * Exit zero is unified val ths_zero and ths_exit
+		 * minimum value for ths_exit = 110ns
+		 * min (exit_zero_cnt * 2) = 110/UI
+		 * exit_zero_cnt = 55/UI
+		 */
+		if (exit_zero_cnt < (55 * ui_den / ui_num) &&
+					(55 * ui_den) % ui_num)
+			exit_zero_cnt += 1;
+
+		if (exit_zero_cnt > EXIT_ZERO_CNT_MAX) {
+			DRM_DEBUG_KMS("exit zero count too high %u\n",
+								exit_zero_cnt);
+			exit_zero_cnt = EXIT_ZERO_CNT_MAX;
+		}
 
-	/* clk zero count */
-	clk_zero_cnt = DIV_ROUND_UP(
-				(tclk_prepare_clkzero -	ths_prepare_ns)
-				* ui_den, ui_num * mul);
+		/* clk zero count */
+		clk_zero_cnt = DIV_ROUND_UP((tclk_prepare_clkzero -
+						ths_prepare_ns)
+						* ui_den, ui_num * mul);
 
-	if (clk_zero_cnt > CLK_ZERO_CNT_MAX) {
-		DRM_DEBUG_KMS("clock zero count too high %u\n", clk_zero_cnt);
-		clk_zero_cnt = CLK_ZERO_CNT_MAX;
-	}
+		if (clk_zero_cnt > CLK_ZERO_CNT_MAX) {
+			DRM_DEBUG_KMS("clock zero count too high %u\n",
+								clk_zero_cnt);
+			clk_zero_cnt = CLK_ZERO_CNT_MAX;
+		}
 
-	/* trail count */
-	tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
-	trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, ui_num * mul);
+		/* trail cnt */
+		trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, ui_num * mul);
 
-	if (trail_cnt > TRAIL_CNT_MAX) {
-		DRM_DEBUG_KMS("trail count too high %u\n", trail_cnt);
-		trail_cnt = TRAIL_CNT_MAX;
-	}
+		if (trail_cnt > TRAIL_CNT_MAX) {
+			DRM_DEBUG_KMS("trail count too high %u\n", trail_cnt);
+			trail_cnt = TRAIL_CNT_MAX;
+		}
 
-	/* B080 */
-	intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 |
+		/* B080 */
+		intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 |
 						clk_zero_cnt << 8 | prepare_cnt;
+	}
 
 	/*
 	 * LP to HS switch count = 4TLPX + PREP_COUNT * mul + EXIT_ZERO_COUNT *
@@ -707,9 +790,10 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
 	 */
 	tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num);
 
-	/* B044 */
-	/* FIXME:
-	 * The comment above does not match with the code */
+	/*
+	 * B044
+	 * FIXME: comment above does not match with the code
+	 */
 	lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * mul +
 						exit_zero_cnt * mul + 10, 8);
 
@@ -718,8 +802,9 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
 	intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch);
 	intel_dsi->hs_to_lp_count += extra_byte_count;
 
-	/* B088 */
-	/* LP -> HS for clock lanes
+	/*
+	 * B088
+	 * LP -> HS for clock lanes
 	 * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero +
 	 *						extra byte count
 	 * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt *
@@ -735,7 +820,8 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
 
 	intel_dsi->clk_lp_to_hs_count += extra_byte_count;
 
-	/* HS->LP for Clock Lanes
+	/*
+	 * HS->LP for Clock Lanes
 	 * Low Power clock synchronisations + 1Tx byteclk + tclk_trail +
 	 *						Extra byte count
 	 * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count
@@ -782,9 +868,11 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
 	DRM_DEBUG_KMS("BTA %s\n",
 			enableddisabled(!(intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA)));
 
-	/* delays in VBT are in unit of 100us, so need to convert
+	/*
+	 * delays in VBT are in unit of 100us, so need to convert
 	 * here in ms
-	 * Delay (100us) * 100 /1000 = Delay / 10 (ms) */
+	 * Delay (100us) * 100 /1000 = Delay / 10 (ms)
+	 */
 	intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10;
 	intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10;
 	intel_dsi->panel_on_delay = pps->panel_on_delay / 10;
-- 
2.7.4

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[PATCH v2 15/20] drm/i915/icl: Define TA_TIMING_PARAM registers

[Madhav Chauhan]

This patch defines DSI_TA_TIMING_PARAM and
DPHY_TA_TIMING_PARAM registers used in
dphy programming.

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9c5d8c1..2d9ffae 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10098,6 +10098,20 @@ enum skl_power_gate {
 #define  HS_EXIT_OVERRIDE		(1 << 7)
 #define  HS_EXIT_TIME(x)		(x << 0)
 
+#define _DPHY_TA_TIMING_PARAM_0		0x162188
+#define _DPHY_TA_TIMING_PARAM_1		0x6c188
+#define DPHY_TA_TIMING_PARAM(port)	_MMIO_PORT(port,	\
+						   _DPHY_TA_TIMING_PARAM_0,\
+						   _DPHY_TA_TIMING_PARAM_1)
+#define _DSI_TA_TIMING_PARAM_0		0x6b098
+#define _DSI_TA_TIMING_PARAM_1		0x6b898
+#define DSI_TA_TIMING_PARAM(port)	_MMIO_PORT(port,	\
+						   _DSI_TA_TIMING_PARAM_0,\
+						   _DSI_TA_TIMING_PARAM_1)
+#define  TA_SURE_OVERRIDE		(1 << 31)
+#define  TA_SURE_TIME(x)		(x << 16)
+#define  TA_SURE_TIME_MASK		(0x1f << 16)
+
 /* bits 31:0 */
 #define _MIPIA_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb084)
 #define _MIPIC_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb884)
-- 
2.7.4

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[PATCH v2 16/20] drm/i915/icl: Program TA_TIMING_PARAM registers

[Madhav Chauhan]

This patch programs D-PHY timing parameters for the
bus turn around flow(in escape clocks) only if dsi link
frequency <=800 MHz using DPHY_TA_TIMING_PARAM and its
identical register DSI_TA_TIMING_PARAM (inside DSI
Controller within the Display Core).

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.h     |  1 +
 drivers/gpu/drm/i915/intel_dsi_new.c | 21 +++++++++++++++++++++
 drivers/gpu/drm/i915/intel_dsi_vbt.c |  1 +
 3 files changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 12a8154..16964c2 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -101,6 +101,7 @@ struct intel_dsi {
 
 	u16 init_count;
 	u32 pclk;
+	u32 bitrate_khz;
 	u16 burst_mode_ratio;
 
 	/* all delays in ms */
diff --git a/drivers/gpu/drm/i915/intel_dsi_new.c b/drivers/gpu/drm/i915/intel_dsi_new.c
index ffc17d1..54077f8 100644
--- a/drivers/gpu/drm/i915/intel_dsi_new.c
+++ b/drivers/gpu/drm/i915/intel_dsi_new.c
@@ -302,6 +302,27 @@ static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
 		I915_WRITE(DSI_DATA_TIMING_PARAM(port),
 			   intel_dsi->dphy_data_lane_reg);
 	}
+
+	/*
+	 * If DSI link operating at or below an 800 MHz,
+	 * TA_SURE should be override and programmed to
+	 * a value '0' inside TA_PARAM_REGISTERS otherwise
+	 * leave all fields at HW default values.
+	 */
+	if (intel_dsi->bitrate_khz <= KHz(800)) {
+		for_each_dsi_port(port, intel_dsi->ports) {
+			tmp = I915_READ(DPHY_TA_TIMING_PARAM(port));
+			tmp &= ~TA_SURE_TIME_MASK;
+			tmp |= (TA_SURE_OVERRIDE | TA_SURE_TIME(0));
+			I915_WRITE(DPHY_TA_TIMING_PARAM(port), tmp);
+
+			/* shadow register inside display core */
+			tmp = I915_READ(DSI_TA_TIMING_PARAM(port));
+			tmp &= ~TA_SURE_TIME_MASK;
+			tmp |= (TA_SURE_OVERRIDE | TA_SURE_TIME(0));
+			I915_WRITE(DSI_TA_TIMING_PARAM(port), tmp);
+		}
+	}
 }
 
 static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
index 5cc3dd0..a3d71fb 100644
--- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
@@ -589,6 +589,7 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
 	intel_dsi->pclk = pclk;
 
 	bitrate = (pclk * bpp) / intel_dsi->lane_count;
+	intel_dsi->bitrate_khz = bitrate;
 
 	switch (intel_dsi->escape_clk_div) {
 	case 0:
-- 
2.7.4

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[PATCH v2 17/20] drm/i915/icl: Get DSI transcoder for a given port

[Madhav Chauhan]

This patch adds a helper function to retrieve DSI
transcoder for a given DSI port using newly defined
enum names for DSI transcoders.

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/intel_display.h | 6 ++++--
 drivers/gpu/drm/i915/intel_dsi_new.c | 9 +++++++++
 2 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h
index a77dd29..8104c410 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -43,8 +43,10 @@ enum transcoder {
 	TRANSCODER_B,
 	TRANSCODER_C,
 	TRANSCODER_EDP,
-	TRANSCODER_DSI_A,
-	TRANSCODER_DSI_C,
+	TRANSCODER_DSI_0,
+	TRANSCODER_DSI_1,
+	TRANSCODER_DSI_A = TRANSCODER_DSI_0,	/* legacy DSI */
+	TRANSCODER_DSI_C = TRANSCODER_DSI_1,	/* legacy DSI */
 
 	I915_MAX_TRANSCODERS
 };
diff --git a/drivers/gpu/drm/i915/intel_dsi_new.c b/drivers/gpu/drm/i915/intel_dsi_new.c
index 54077f8..97b9b1e 100644
--- a/drivers/gpu/drm/i915/intel_dsi_new.c
+++ b/drivers/gpu/drm/i915/intel_dsi_new.c
@@ -27,6 +27,15 @@
 
 #include "intel_dsi.h"
 
+static enum transcoder __attribute__((unused)) dsi_port_to_transcoder(
+								enum port port)
+{
+	if (port == PORT_A)
+		return TRANSCODER_DSI_0;
+	else
+		return TRANSCODER_DSI_1;
+}
+
 static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-- 
2.7.4

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[PATCH v2 18/20] drm/i915/icl: Add macros for MMIO of DSI transcoder registers

[Madhav Chauhan]

This patch adds _MMIO_DSI and _DSI_TRANS macros for accessing
DSI transcoder registers.

Credits-to: Jani N

Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2d9ffae..0171b09 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9559,6 +9559,11 @@ enum skl_power_gate {
 #define _MIPI_PORT(port, a, c)	(((port) == PORT_A) ? a : c)	/* ports A and C only */
 #define _MMIO_MIPI(port, a, c)	_MMIO(_MIPI_PORT(port, a, c))
 
+/* gen11 DSI */
+#define _DSI_TRANS(tc, dsi0, dsi1)	(((tc) == TRANSCODER_DSI_0) ?	\
+					 (dsi0) : (dsi1))
+#define _MMIO_DSI(tc, dsi0, dsi1)	_MMIO(_DSI_TRANS(tc, dsi0, dsi1))
+
 #define MIPIO_TXESC_CLK_DIV1			_MMIO(0x160004)
 #define  GLK_TX_ESC_CLK_DIV1_MASK			0x3FF
 #define MIPIO_TXESC_CLK_DIV2			_MMIO(0x160008)
-- 
2.7.4

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[PATCH v2 19/20] drm/i915/icl: Define TRANS_DSI_FUNC_CONF register

[Madhav Chauhan]

This patch defines transcoder function configuration
registers and its bitfields for both DSI ports.
Used while programming/enabling DSI transcoder.

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 47 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0171b09..b44a9a8d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10117,6 +10117,53 @@ enum skl_power_gate {
 #define  TA_SURE_TIME(x)		(x << 16)
 #define  TA_SURE_TIME_MASK		(0x1f << 16)
 
+/* DSI transcoder configuration */
+#define _DSI_TRANS_FUNC_CONF_0		0x6b030
+#define _DSI_TRANS_FUNC_CONF_1		0x6b830
+#define DSI_TRANS_FUNC_CONF(tc)		_MMIO_DSI(tc,	\
+						  _DSI_TRANS_FUNC_CONF_0,\
+						  _DSI_TRANS_FUNC_CONF_1)
+#define  OP_MODE(x)			(x << 28)
+#define  OP_MODE_MASK			(0x3 << 28)
+#define  CMD_MODE_NO_GATE		0x0
+#define  CMD_MODE_TE_GATE		0x1
+#define  VIDEO_MODE_SYNC_EVENT		0x2
+#define  VIDEO_MODE_SYNC_PULSE		0x3
+#define  LINK_READY			(1 << 20)
+#define  PIX_FMT(x)			(x << 16)
+#define  PIX_FMT_MASK			(0x3 << 16)
+#define  PIX_FMT_RGB565		0x0
+#define  PIX_FMT_RGB666_PACKED		0x1
+#define  PIX_FMT_RGB666_LOOSE		0x2
+#define  PIX_FMT_RGB888		0x3
+#define  PIX_FMT_RGB101010		0x4
+#define  PIX_FMT_RGB121212		0x5
+#define  PIX_FMT_COMPRESSED		0x6
+#define  BGR_TRANSMISSION		(1 << 15)
+#define  PIX_VIRT_CHAN(x)		(x << 12)
+#define  PIX_VIRT_CHAN_MASK		(0x3 << 12)
+#define  PIX_BUF_THRESHOLD(x)		((x & 0x3) << 10)
+#define  PIX_BUF_THRESHOLD_MASK	(0x3 << 10)
+#define  PIX_BUF_THRESHOLD_1_4		0x0
+#define  PIX_BUF_THRESHOLD_1_2		0x1
+#define  PIX_BUF_THRESHOLD_3_4		0x2
+#define  PIX_BUF_THRESHOLD_FULL	0x3
+#define  CONTINUOUS_CLK(x)		(x << 8)
+#define  CONTINUOUS_CLK_MASK		(0x3 << 8)
+#define  CLK_ENTER_LP_AFTER_DATA	0x0
+#define  CLK_HS_OR_LP			0x2
+#define  CLK_HS_CONTINUOUS		0x3
+#define  LINK_CALIBRATION(x)		(x << 4)
+#define  LINK_CALIBRATION_MASK		(0x3 << 4)
+#define  CALIBRATION_DISABLED		0x0
+#define  CALIBRATION_ENABLED_INITIAL_ONLY	0x2
+#define  CALIBRATION_ENABLED_INITIAL_PERIODIC	0x3
+#define  S3D_ORIENTATION(x)		(x << 1)
+#define  S3D_ORIENTATION_MASK		(0x1 << 1)
+#define  S3D_ORIENTATION_PORTRAIT	0x0
+#define  S3D_ORIENTATION_LANDSCAPE	0x1
+#define  EOTP_DISABLED			(1 << 0)
+
 /* bits 31:0 */
 #define _MIPIA_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb084)
 #define _MIPIC_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb884)
-- 
2.7.4

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[PATCH v2 20/20] drm/i915/icl: Configure DSI transcoders

[Madhav Chauhan]

This patch programs DSI operation mode, pixel format,
BGR info, link calibration etc for the DSI transcoder.
This patch also extract BGR info of the DSI panel from
VBT and save it inside struct intel_dsi which used for
configuring DSI transcoder.

v2: Rebase

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.h     |  3 ++
 drivers/gpu/drm/i915/intel_dsi_new.c | 87 +++++++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_dsi_vbt.c |  1 +
 3 files changed, 89 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 16964c2..fdde724 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -81,6 +81,9 @@ struct intel_dsi {
 	u16 dcs_backlight_ports;
 	u16 dcs_cabc_ports;
 
+	/* RGB or BGR */
+	unsigned int bgr_enabled;
+
 	u8 pixel_overlap;
 	u32 port_bits;
 	u32 bw_timer;
diff --git a/drivers/gpu/drm/i915/intel_dsi_new.c b/drivers/gpu/drm/i915/intel_dsi_new.c
index 97b9b1e..9b4743e 100644
--- a/drivers/gpu/drm/i915/intel_dsi_new.c
+++ b/drivers/gpu/drm/i915/intel_dsi_new.c
@@ -27,8 +27,7 @@
 
 #include "intel_dsi.h"
 
-static enum transcoder __attribute__((unused)) dsi_port_to_transcoder(
-								enum port port)
+static enum transcoder dsi_port_to_transcoder(enum port port)
 {
 	if (port == PORT_A)
 		return TRANSCODER_DSI_0;
@@ -334,6 +333,87 @@ static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
 	}
 }
 
+static void gen11_dsi_configure_transcoder(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	u32 tmp;
+	enum port port;
+	enum transcoder dsi_trans;
+
+	for_each_dsi_port(port, intel_dsi->ports) {
+		dsi_trans = dsi_port_to_transcoder(port);
+		tmp = I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans));
+
+		if (intel_dsi->eotp_pkt == 0)
+			tmp |= EOTP_DISABLED;
+		else
+			tmp &= ~EOTP_DISABLED;
+
+		/* enable link calibration if freq > 1.5Gbps */
+		if (intel_dsi->bitrate_khz >= (1500 * 1000)) {
+			tmp &= ~LINK_CALIBRATION_MASK;
+			tmp |= LINK_CALIBRATION(
+					CALIBRATION_ENABLED_INITIAL_ONLY);
+		}
+
+		/* configure continuous clock */
+		tmp &= ~CONTINUOUS_CLK_MASK;
+		if (intel_dsi->clock_stop)
+			tmp |= CONTINUOUS_CLK(CLK_ENTER_LP_AFTER_DATA);
+		else
+			tmp |= CONTINUOUS_CLK(CLK_HS_CONTINUOUS);
+
+		/* configure buffer threshold limit to minimum */
+		tmp &= ~PIX_BUF_THRESHOLD_MASK;
+		tmp |= PIX_BUF_THRESHOLD(PIX_BUF_THRESHOLD_1_4);
+
+		/* set virtual channel to '0' */
+		tmp &= ~PIX_VIRT_CHAN_MASK;
+		tmp |= PIX_VIRT_CHAN(0x0);
+
+		/* program BGR transmission */
+		if (intel_dsi->bgr_enabled)
+			tmp |= BGR_TRANSMISSION;
+
+		/* select pixel format */
+		tmp &= ~PIX_FMT_MASK;
+
+		switch (intel_dsi->pixel_format) {
+		case MIPI_DSI_FMT_RGB888:
+			tmp |= PIX_FMT(PIX_FMT_RGB888);
+			break;
+		case MIPI_DSI_FMT_RGB666:
+			tmp |= PIX_FMT(PIX_FMT_RGB666_LOOSE);
+			break;
+		case MIPI_DSI_FMT_RGB666_PACKED:
+			tmp |= PIX_FMT(PIX_FMT_RGB666_PACKED);
+			break;
+		case MIPI_DSI_FMT_RGB565:
+			tmp |= PIX_FMT(PIX_FMT_RGB565);
+			break;
+		default:
+			DRM_ERROR("DSI pixel format unsupported\n");
+		}
+
+		/* program DSI operation mode */
+		if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) {
+			tmp &= ~OP_MODE_MASK;
+			if (intel_dsi->video_mode_format ==
+					VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE) {
+				tmp |= OP_MODE(VIDEO_MODE_SYNC_PULSE);
+			} else if (intel_dsi->video_mode_format ==
+					VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS) {
+				tmp |= OP_MODE(VIDEO_MODE_SYNC_EVENT);
+			} else {
+				DRM_ERROR("DSI Video Mode unsupported\n");
+			}
+		}
+
+		I915_WRITE(DSI_TRANS_FUNC_CONF(dsi_trans), tmp);
+	}
+}
+
 static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
 {
 	/* step 4a: power up all lanes of the DDI used by DSI */
@@ -350,6 +430,9 @@ static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
 
 	/* step 4e: setup D-PHY timings */
 	gen11_dsi_setup_dphy_timings(encoder);
+
+	/* Step (4h, 4i, 4j, 4k): Configure transcoder */
+	gen11_dsi_configure_transcoder(encoder);
 }
 
 static void __attribute__((unused))
diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
index a3d71fb..57a44a2 100644
--- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
@@ -542,6 +542,7 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
 	intel_dsi->bw_timer = mipi_config->dbi_bw_timer;
 	intel_dsi->video_frmt_cfg_bits =
 		mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0;
+	intel_dsi->bgr_enabled = mipi_config->rgb_flip;
 
 	pclk = mode->clock;
 
-- 
2.7.4

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✗ Fi.CI.CHECKPATCH: warning for ICELAKE DSI DRIVER (rev2)

[Patchwork]

== Series Details ==

Series: ICELAKE DSI DRIVER (rev2)
URL   : https://patchwork.freedesktop.org/series/44823/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
2fb3a21077c4 drm/i915/icl: Define register for DSI PLL
5d1f14446c69 drm/i915/icl: Program DSI Escape clock Divider
-:40: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#40: 
new file mode 100644

-:45: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1
#45: FILE: drivers/gpu/drm/i915/intel_dsi_new.c:1:
+/*

-:90: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#90: FILE: drivers/gpu/drm/i915/intel_dsi_new.c:46:
+		I915_WRITE(ICL_DSI_ESC_CLK_DIV(port),
+				esc_clk_div_m & ICL_ESC_CLK_DIV_MASK);

-:96: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#96: FILE: drivers/gpu/drm/i915/intel_dsi_new.c:52:
+		I915_WRITE(ICL_DPHY_ESC_CLK_DIV(port),
+				esc_clk_div_m & ICL_ESC_CLK_DIV_MASK);

-:103: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#103: FILE: drivers/gpu/drm/i915/intel_dsi_new.c:59:
+gen11_dsi_pre_enable(struct intel_encoder *encoder,
+		const struct intel_crtc_state *pipe_config,

total: 0 errors, 2 warnings, 3 checks, 78 lines checked
bd698aa15977 drm/i915/icl: Define DSI mode ctl register
f42b0a7ec096 drm/i915/icl: Enable DSI IO power
a5a0e7ef8798 drm/i915/icl: Define PORT_CL_DW_10 register
c03cde1bb29b drm/i915/icl: Power down unused DSI lanes
3338fcea233b drm/i915/icl: Define AUX lane registers for Port A/B
9f6dbc7b8083 drm/i915/icl: Configure lane sequencing of combo phy transmitter
4e884239f1e1 drm/i915/icl: DSI vswing programming sequence
-:33: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#33: FILE: drivers/gpu/drm/i915/intel_dsi_new.c:39:
+	for_each_dsi_port(port, intel_dsi->ports) {
+

total: 0 errors, 0 warnings, 1 checks, 132 lines checked
3dda606aeffa drm/i915/icl: Enable DDI Buffer
bcc53825cc97 drm/i915/icl: Define T_INIT_MASTER registers
8f2580e74e6e drm/i915/icl: Program T_INIT_MASTER registers
a3ec308da955 drm/i915/icl: Define data/clock lanes dphy timing registers
-:31: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#31: FILE: drivers/gpu/drm/i915/i915_reg.h:10089:
+#define  CLK_PREP_TIME(x)		(x << 28)

-:33: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#33: FILE: drivers/gpu/drm/i915/i915_reg.h:10091:
+#define  CLK_ZERO_TIME(x)		(x << 20)

-:35: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#35: FILE: drivers/gpu/drm/i915/i915_reg.h:10093:
+#define  CLK_PRE_TIME(x)		(x << 16)

-:37: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#37: FILE: drivers/gpu/drm/i915/i915_reg.h:10095:
+#define  CLK_POST_TIME(x)		(x << 8)

-:39: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#39: FILE: drivers/gpu/drm/i915/i915_reg.h:10097:
+#define  CLK_TRAIL_TIME(x)		(x << 0)

-:52: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#52: FILE: drivers/gpu/drm/i915/i915_reg.h:10110:
+#define  HS_PREP_TIME(x)		(x << 24)

-:54: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#54: FILE: drivers/gpu/drm/i915/i915_reg.h:10112:
+#define  HS_ZERO_TIME(x)		(x << 16)

-:56: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#56: FILE: drivers/gpu/drm/i915/i915_reg.h:10114:
+#define  HS_TRAIL_TIME(x)		(x << 8)

-:58: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#58: FILE: drivers/gpu/drm/i915/i915_reg.h:10116:
+#define  HS_EXIT_TIME(x)		(x << 0)

total: 0 errors, 0 warnings, 9 checks, 46 lines checked
17de6721e0a6 drm/i915/icl: Program DSI clock and data lane timing params
-:80: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#80: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:631:
+	ths_prepare_ns = max(mipi_config->ths_prepare,
+				mipi_config->tclk_prepare);

-:114: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#114: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:655:
+		clk_zero_cnt = DIV_ROUND_UP(

-:128: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#128: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:669:
+		hs_zero_cnt = DIV_ROUND_UP(

-:190: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#190: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:727:
+		prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den,
+							ui_num * mul);

-:196: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#196: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:731:
+			DRM_DEBUG_KMS("prepare count too high %u\n",
+								prepare_cnt);

-:201: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#201: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:736:
+		exit_zero_cnt = DIV_ROUND_UP(

-:226: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#226: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:748:
+		if (exit_zero_cnt < (55 * ui_den / ui_num) &&
+					(55 * ui_den) % ui_num)

-:231: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#231: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:753:
+			DRM_DEBUG_KMS("exit zero count too high %u\n",
+								exit_zero_cnt);

-:250: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#250: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:764:
+			DRM_DEBUG_KMS("clock zero count too high %u\n",
+								clk_zero_cnt);

total: 0 errors, 0 warnings, 9 checks, 293 lines checked
a9e9217a3bd3 drm/i915/icl: Define TA_TIMING_PARAM registers
-:31: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#31: FILE: drivers/gpu/drm/i915/i915_reg.h:10129:
+#define  TA_SURE_TIME(x)		(x << 16)

total: 0 errors, 0 warnings, 1 checks, 20 lines checked
4760909d3125 drm/i915/icl: Program TA_TIMING_PARAM registers
c7b18a81b3c5 drm/i915/icl: Get DSI transcoder for a given port
-:37: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#37: FILE: drivers/gpu/drm/i915/intel_dsi_new.c:30:
+static enum transcoder __attribute__((unused)) dsi_port_to_transcoder(

total: 0 errors, 0 warnings, 1 checks, 27 lines checked
9ef3b3bf6808 drm/i915/icl: Add macros for MMIO of DSI transcoder registers
114939859df1 drm/i915/icl: Define TRANS_DSI_FUNC_CONF register
-:26: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#26: FILE: drivers/gpu/drm/i915/i915_reg.h:10143:
+#define  OP_MODE(x)			(x << 28)

-:33: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#33: FILE: drivers/gpu/drm/i915/i915_reg.h:10150:
+#define  PIX_FMT(x)			(x << 16)

-:43: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#43: FILE: drivers/gpu/drm/i915/i915_reg.h:10160:
+#define  PIX_VIRT_CHAN(x)		(x << 12)

-:45: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#45: FILE: drivers/gpu/drm/i915/i915_reg.h:10162:
+#define  PIX_BUF_THRESHOLD(x)		((x & 0x3) << 10)

-:51: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#51: FILE: drivers/gpu/drm/i915/i915_reg.h:10168:
+#define  CONTINUOUS_CLK(x)		(x << 8)

-:56: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#56: FILE: drivers/gpu/drm/i915/i915_reg.h:10173:
+#define  LINK_CALIBRATION(x)		(x << 4)

-:61: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#61: FILE: drivers/gpu/drm/i915/i915_reg.h:10178:
+#define  S3D_ORIENTATION(x)		(x << 1)

total: 0 errors, 0 warnings, 7 checks, 53 lines checked
cd40dd3bd259 drm/i915/icl: Configure DSI transcoders
-:68: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#68: FILE: drivers/gpu/drm/i915/intel_dsi_new.c:356:
+			tmp |= LINK_CALIBRATION(

total: 0 errors, 0 warnings, 1 checks, 121 lines checked

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✗ Fi.CI.SPARSE: warning for ICELAKE DSI DRIVER (rev2)

[Patchwork]

== Series Details ==

Series: ICELAKE DSI DRIVER (rev2)
URL   : https://patchwork.freedesktop.org/series/44823/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Commit: drm/i915/icl: Define register for DSI PLL
Okay!

Commit: drm/i915/icl: Program DSI Escape clock Divider
Okay!

Commit: drm/i915/icl: Define DSI mode ctl register
Okay!

Commit: drm/i915/icl: Enable DSI IO power
Okay!

Commit: drm/i915/icl: Define PORT_CL_DW_10 register
Okay!

Commit: drm/i915/icl: Power down unused DSI lanes
Okay!

Commit: drm/i915/icl: Define AUX lane registers for Port A/B
Okay!

Commit: drm/i915/icl: Configure lane sequencing of combo phy transmitter
Okay!

Commit: drm/i915/icl: DSI vswing programming sequence
Okay!

Commit: drm/i915/icl: Enable DDI Buffer
Okay!

Commit: drm/i915/icl: Define T_INIT_MASTER registers
Okay!

Commit: drm/i915/icl: Program T_INIT_MASTER registers
Okay!

Commit: drm/i915/icl: Define data/clock lanes dphy timing registers
Okay!

Commit: drm/i915/icl: Program DSI clock and data lane timing params
-O:drivers/gpu/drm/i915/intel_dsi_vbt.c:644:26: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_dsi_vbt.c:644:26: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_dsi_vbt.c:686:25: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_dsi_vbt.c:686:25: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_dsi_vbt.c:718:37: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_dsi_vbt.c:718:37: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dsi_vbt.c:629:25: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dsi_vbt.c:629:25: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dsi_vbt.c:630:26: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dsi_vbt.c:630:26: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dsi_vbt.c:802:37: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dsi_vbt.c:802:37: warning: expression using sizeof(void)

Commit: drm/i915/icl: Define TA_TIMING_PARAM registers
Okay!

Commit: drm/i915/icl: Program TA_TIMING_PARAM registers
Okay!

Commit: drm/i915/icl: Get DSI transcoder for a given port
Okay!

Commit: drm/i915/icl: Add macros for MMIO of DSI transcoder registers
Okay!

Commit: drm/i915/icl: Define TRANS_DSI_FUNC_CONF register
Okay!

Commit: drm/i915/icl: Configure DSI transcoders
Okay!

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✓ Fi.CI.BAT: success for ICELAKE DSI DRIVER (rev2)

[Patchwork]

== Series Details ==

Series: ICELAKE DSI DRIVER (rev2)
URL   : https://patchwork.freedesktop.org/series/44823/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4423 -> Patchwork_9509 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/44823/revisions/2/mbox/

== Known issues ==

  Here are the changes found in Patchwork_9509 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
      fi-bxt-dsi:         NOTRUN -> INCOMPLETE (fdo#103927)

    
    ==== Possible fixes ====

    igt@gem_exec_suspend@basic-s3:
      {fi-cfl-8109u}:     INCOMPLETE -> PASS

    igt@kms_chamelium@dp-edid-read:
      fi-kbl-7500u:       FAIL (fdo#103841) -> PASS

    
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927


== Participating hosts (45 -> 41) ==

  Additional (1): fi-bxt-dsi 
  Missing    (5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u 


== Build changes ==

    * Linux: CI_DRM_4423 -> Patchwork_9509

  CI_DRM_4423: 9b9b45349fe3a36d41586992426d03a238396531 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4533: 199220052af977598033d3810ffb4cc32d377522 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9509: cd40dd3bd2598cdfec11b40ea20f131ac7744690 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

cd40dd3bd259 drm/i915/icl: Configure DSI transcoders
114939859df1 drm/i915/icl: Define TRANS_DSI_FUNC_CONF register
9ef3b3bf6808 drm/i915/icl: Add macros for MMIO of DSI transcoder registers
c7b18a81b3c5 drm/i915/icl: Get DSI transcoder for a given port
4760909d3125 drm/i915/icl: Program TA_TIMING_PARAM registers
a9e9217a3bd3 drm/i915/icl: Define TA_TIMING_PARAM registers
17de6721e0a6 drm/i915/icl: Program DSI clock and data lane timing params
a3ec308da955 drm/i915/icl: Define data/clock lanes dphy timing registers
8f2580e74e6e drm/i915/icl: Program T_INIT_MASTER registers
bcc53825cc97 drm/i915/icl: Define T_INIT_MASTER registers
3dda606aeffa drm/i915/icl: Enable DDI Buffer
4e884239f1e1 drm/i915/icl: DSI vswing programming sequence
9f6dbc7b8083 drm/i915/icl: Configure lane sequencing of combo phy transmitter
3338fcea233b drm/i915/icl: Define AUX lane registers for Port A/B
c03cde1bb29b drm/i915/icl: Power down unused DSI lanes
a5a0e7ef8798 drm/i915/icl: Define PORT_CL_DW_10 register
f42b0a7ec096 drm/i915/icl: Enable DSI IO power
bd698aa15977 drm/i915/icl: Define DSI mode ctl register
5d1f14446c69 drm/i915/icl: Program DSI Escape clock Divider
2fb3a21077c4 drm/i915/icl: Define register for DSI PLL

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9509/issues.html
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✓ Fi.CI.IGT: success for ICELAKE DSI DRIVER (rev2)

[Patchwork]

== Series Details ==

Series: ICELAKE DSI DRIVER (rev2)
URL   : https://patchwork.freedesktop.org/series/44823/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4423_full -> Patchwork_9509_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_9509_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9509_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_9509_full:

  === IGT changes ===

    ==== Warnings ====

    igt@gem_exec_schedule@deep-render:
      shard-kbl:          SKIP -> PASS

    igt@gem_mocs_settings@mocs-rc6-ctx-dirty-render:
      shard-kbl:          PASS -> SKIP +2

    
== Known issues ==

  Here are the changes found in Patchwork_9509_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@kms_flip_tiling@flip-to-x-tiled:
      shard-glk:          PASS -> FAIL (fdo#104724) +2

    
    ==== Possible fixes ====

    igt@drv_selftest@live_gtt:
      shard-glk:          INCOMPLETE (fdo#103359, k.org#198133) -> PASS

    igt@gem_ppgtt@blt-vs-render-ctxn:
      shard-kbl:          INCOMPLETE (fdo#103665, fdo#106023) -> PASS

    igt@kms_flip@2x-plain-flip-ts-check:
      shard-glk:          FAIL (fdo#100368) -> PASS +1

    igt@kms_flip_tiling@flip-to-y-tiled:
      shard-glk:          FAIL (fdo#103822, fdo#104724) -> PASS

    igt@kms_vblank@pipe-a-ts-continuation-suspend:
      shard-hsw:          FAIL (fdo#104894) -> PASS

    igt@perf@polling:
      shard-hsw:          FAIL (fdo#102252) -> PASS

    
  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
  fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
  fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
  fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
  fdo#104894 https://bugs.freedesktop.org/show_bug.cgi?id=104894
  fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023
  k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133


== Participating hosts (5 -> 5) ==

  No changes in participating hosts


== Build changes ==

    * Linux: CI_DRM_4423 -> Patchwork_9509

  CI_DRM_4423: 9b9b45349fe3a36d41586992426d03a238396531 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4533: 199220052af977598033d3810ffb4cc32d377522 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9509: cd40dd3bd2598cdfec11b40ea20f131ac7744690 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9509/shards.html
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Re: [PATCH v2 05/20] drm/i915/icl: Define PORT_CL_DW_10 register

[Jani Nikula]

On Tue, 03 Jul 2018, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> This register used to power down individual lanes for
> DDI/DSI ports. Bitfields to power up/down various
> combinations of lanes are also added in this patch.
>
> v2: Review comments from Jani N
>     - Use override instead of "override" for bitfields
>     - Define mask for override bitfield
>     - Define PWR_DOWN_LN* macros shifted in place
>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index dfd603c..3fa8f02 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1704,6 +1704,26 @@ enum i915_power_well_id {
>  #define ICL_PORT_CL_DW5(port)	_MMIO_PORT(port, _ICL_PORT_CL_DW5_A, \
>  						 _ICL_PORT_CL_DW5_B)
>  
> +#define _CNL_PORT_CL_DW10_A		0x162028
> +#define _ICL_PORT_CL_DW10_B		0x6c028
> +#define ICL_PORT_CL_DW10(port)		_MMIO_PORT(port,	\
> +						   _CNL_PORT_CL_DW10_A, \
> +						   _ICL_PORT_CL_DW10_B)
> +#define  PG_SEQ_DELAY_OVERRIDE_MASK	(3 << 25)
> +#define  PG_SEQ_DELAY_OVERRIDE_SHIFT	25
> +#define  PG_SEQ_DELAY_OVERRIDE_ENABLE	(1 << 24)
> +#define  PWR_UP_ALL_LANES		(0x0 << 4)
> +#define  PWR_DOWN_LN_3_2_1		(0xe << 4)
> +#define  PWR_DOWN_LN_3_2		(0xc << 4)
> +#define  PWR_DOWN_LN_3			(0x8 << 4)
> +#define  PWR_DOWN_LN_2_1_0		(0x7 << 4)
> +#define  PWR_DOWN_LN_1_0		(0x3 << 4)
> +#define  PWR_DOWN_LN_1			(0x2 << 4)
> +#define  PWR_DOWN_LN_3_1		(0xa << 4)
> +#define  PWR_DOWN_LN_3_1_0		(0xb << 4)
> +#define  PWR_DOWN_LN_MASK		(0xf0 << 4)

Should be (0xf << 4).

With that fixed,

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> +#define  PWR_DOWN_LN_SHIFT		4
> +
>  #define _PORT_CL1CM_DW9_A		0x162024
>  #define _PORT_CL1CM_DW9_BC		0x6C024
>  #define   IREF0RC_OFFSET_SHIFT		8

-- 
Jani Nikula, Intel Open Source Graphics Center
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Re: [PATCH v2 07/20] drm/i915/icl: Define AUX lane registers for Port A/B

[Jani Nikula]

On Tue, 03 Jul 2018, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> This patch defines AUX lane registers for PORT_PCS_DW1,
> PORT_TX_DW2, PORT_TX_DW4, PORT_TX_DW5 used during
> dsi enabling.
>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3fa8f02..d3ce1a9 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1780,16 +1780,21 @@ enum i915_power_well_id {
>  						    _CNL_PORT_PCS_DW1_LN0_D, \
>  						    _CNL_PORT_PCS_DW1_LN0_AE, \
>  						    _CNL_PORT_PCS_DW1_LN0_F))
> +
>  #define _ICL_PORT_PCS_DW1_GRP_A		0x162604
>  #define _ICL_PORT_PCS_DW1_GRP_B		0x6C604
>  #define _ICL_PORT_PCS_DW1_LN0_A		0x162804
>  #define _ICL_PORT_PCS_DW1_LN0_B		0x6C804
> +#define _ICL_PORT_PCS_DW1_AUX_B		0x6c304
>  #define ICL_PORT_PCS_DW1_GRP(port)	_MMIO_PORT(port,\
>  						   _ICL_PORT_PCS_DW1_GRP_A, \
>  						   _ICL_PORT_PCS_DW1_GRP_B)
>  #define ICL_PORT_PCS_DW1_LN0(port)	_MMIO_PORT(port, \
>  						   _ICL_PORT_PCS_DW1_LN0_A, \
>  						   _ICL_PORT_PCS_DW1_LN0_B)
> +#define ICL_PORT_PCS_DW1_AUX(port)	_MMIO_PORT(port, \
> +						   _CNL_PORT_PCS_DW1_GRP_AE, \

I think for consistency with the rest of the registers here you should
add 0x162304 as _ICL_PORT_PCS_DW1_AUX_A. Clearly that's been decided for
the rest of these registers.

> +						   _ICL_PORT_PCS_DW1_AUX_B)
>  #define   COMMON_KEEPER_EN		(1 << 26)
>  
>  /* CNL Port TX registers */
> @@ -1826,16 +1831,23 @@ enum i915_power_well_id {
>  #define _ICL_PORT_TX_DW2_GRP_B		0x6C688
>  #define _ICL_PORT_TX_DW2_LN0_A		0x162888
>  #define _ICL_PORT_TX_DW2_LN0_B		0x6C888
> +#define _ICL_PORT_TX_DW2_AUX_A		0x162388
> +#define _ICL_PORT_TX_DW2_AUX_B		0x6c388
>  #define ICL_PORT_TX_DW2_GRP(port)	_MMIO_PORT(port, \
>  						   _ICL_PORT_TX_DW2_GRP_A, \
>  						   _ICL_PORT_TX_DW2_GRP_B)
>  #define ICL_PORT_TX_DW2_LN0(port)	_MMIO_PORT(port, \
>  						   _ICL_PORT_TX_DW2_LN0_A, \
>  						   _ICL_PORT_TX_DW2_LN0_B)
> +#define ICL_PORT_TX_DW2_AUX(port)	_MMIO_PORT(port, \
> +						   _ICL_PORT_TX_DW2_AUX_A, \
> +						   _ICL_PORT_TX_DW2_AUX_B)
>  #define   SWING_SEL_UPPER(x)		(((x) >> 3) << 15)
>  #define   SWING_SEL_UPPER_MASK		(1 << 15)
>  #define   SWING_SEL_LOWER(x)		(((x) & 0x7) << 11)
>  #define   SWING_SEL_LOWER_MASK		(0x7 << 11)
> +#define  FRC_LATENCY_OPTIM_MASK	(0x7 << 8)
> +#define  FRC_LATENCY_OPTIM_VAL(x)	((x) << 8)
          ^^^

Three spaces like the rest of them.

With the above two things fixed,

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


>  #define   RCOMP_SCALAR(x)		((x) << 0)
>  #define   RCOMP_SCALAR_MASK		(0xFF << 0)
>  
> @@ -1851,6 +1863,8 @@ enum i915_power_well_id {
>  #define _ICL_PORT_TX_DW4_LN0_A		0x162890
>  #define _ICL_PORT_TX_DW4_LN1_A		0x162990
>  #define _ICL_PORT_TX_DW4_LN0_B		0x6C890
> +#define _ICL_PORT_TX_DW4_AUX_A		0x162390
> +#define _ICL_PORT_TX_DW4_AUX_B		0x6c390
>  #define ICL_PORT_TX_DW4_GRP(port)	_MMIO_PORT(port, \
>  						   _ICL_PORT_TX_DW4_GRP_A, \
>  						   _ICL_PORT_TX_DW4_GRP_B)
> @@ -1859,6 +1873,9 @@ enum i915_power_well_id {
>  						   _ICL_PORT_TX_DW4_LN0_B) + \
>  					     ((ln) * (_ICL_PORT_TX_DW4_LN1_A - \
>  						      _ICL_PORT_TX_DW4_LN0_A)))
> +#define ICL_PORT_TX_DW4_AUX(port)	_MMIO_PORT(port, \
> +						   _ICL_PORT_TX_DW4_AUX_A, \
> +						   _ICL_PORT_TX_DW4_AUX_B)
>  #define   LOADGEN_SELECT		(1 << 31)
>  #define   POST_CURSOR_1(x)		((x) << 12)
>  #define   POST_CURSOR_1_MASK		(0x3F << 12)
> @@ -1873,12 +1890,17 @@ enum i915_power_well_id {
>  #define _ICL_PORT_TX_DW5_GRP_B		0x6C694
>  #define _ICL_PORT_TX_DW5_LN0_A		0x162894
>  #define _ICL_PORT_TX_DW5_LN0_B		0x6C894
> +#define _ICL_PORT_TX_DW5_AUX_A		0x162394
> +#define _ICL_PORT_TX_DW5_AUX_B		0x6c394
>  #define ICL_PORT_TX_DW5_GRP(port)	_MMIO_PORT(port, \
>  						   _ICL_PORT_TX_DW5_GRP_A, \
>  						   _ICL_PORT_TX_DW5_GRP_B)
>  #define ICL_PORT_TX_DW5_LN0(port)	_MMIO_PORT(port, \
>  						   _ICL_PORT_TX_DW5_LN0_A, \
>  						   _ICL_PORT_TX_DW5_LN0_B)
> +#define ICL_PORT_TX_DW5_AUX(port)	_MMIO_PORT(port, \
> +						   _ICL_PORT_TX_DW5_AUX_A, \
> +						   _ICL_PORT_TX_DW5_AUX_B)
>  #define   TX_TRAINING_EN		(1 << 31)
>  #define   TAP2_DISABLE			(1 << 30)
>  #define   TAP3_DISABLE			(1 << 29)

-- 
Jani Nikula, Intel Open Source Graphics Center
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Re: [PATCH v2 05/20] drm/i915/icl: Define PORT_CL_DW_10 register

[Chauhan, Madhav]

> -----Original Message-----
> From: Nikula, Jani
> Sent: Wednesday, July 4, 2018 8:08 PM
> To: Chauhan, Madhav <madhav.chauhan@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Vivi, Rodrigo <rodrigo.vivi@intel.com>; Zanoni, Paulo R
> <paulo.r.zanoni@intel.com>; Shankar, Uma <uma.shankar@intel.com>;
> Chauhan, Madhav <madhav.chauhan@intel.com>
> Subject: Re: [PATCH v2 05/20] drm/i915/icl: Define PORT_CL_DW_10 register
> 
> On Tue, 03 Jul 2018, Madhav Chauhan <madhav.chauhan@intel.com>
> wrote:
> > This register used to power down individual lanes for DDI/DSI ports.
> > Bitfields to power up/down various combinations of lanes are also
> > added in this patch.
> >
> > v2: Review comments from Jani N
> >     - Use override instead of "override" for bitfields
> >     - Define mask for override bitfield
> >     - Define PWR_DOWN_LN* macros shifted in place
> >
> > Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h | 20 ++++++++++++++++++++
> >  1 file changed, 20 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index dfd603c..3fa8f02 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1704,6 +1704,26 @@ enum i915_power_well_id {
> >  #define ICL_PORT_CL_DW5(port)	_MMIO_PORT(port,
> _ICL_PORT_CL_DW5_A, \
> >  						 _ICL_PORT_CL_DW5_B)
> >
> > +#define _CNL_PORT_CL_DW10_A		0x162028
> > +#define _ICL_PORT_CL_DW10_B		0x6c028
> > +#define ICL_PORT_CL_DW10(port)		_MMIO_PORT(port,	\
> > +						   _CNL_PORT_CL_DW10_A, \
> > +						   _ICL_PORT_CL_DW10_B)
> > +#define  PG_SEQ_DELAY_OVERRIDE_MASK	(3 << 25)
> > +#define  PG_SEQ_DELAY_OVERRIDE_SHIFT	25
> > +#define  PG_SEQ_DELAY_OVERRIDE_ENABLE	(1 << 24)
> > +#define  PWR_UP_ALL_LANES		(0x0 << 4)
> > +#define  PWR_DOWN_LN_3_2_1		(0xe << 4)
> > +#define  PWR_DOWN_LN_3_2		(0xc << 4)
> > +#define  PWR_DOWN_LN_3			(0x8 << 4)
> > +#define  PWR_DOWN_LN_2_1_0		(0x7 << 4)
> > +#define  PWR_DOWN_LN_1_0		(0x3 << 4)
> > +#define  PWR_DOWN_LN_1			(0x2 << 4)
> > +#define  PWR_DOWN_LN_3_1		(0xa << 4)
> > +#define  PWR_DOWN_LN_3_1_0		(0xb << 4)
> > +#define  PWR_DOWN_LN_MASK		(0xf0 << 4)
> 
> Should be (0xf << 4).

Right, my bad. Will fix it in next version.

Regards,
Madhav

> 
> With that fixed,
> 
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> 
> 
> > +#define  PWR_DOWN_LN_SHIFT		4
> > +
> >  #define _PORT_CL1CM_DW9_A		0x162024
> >  #define _PORT_CL1CM_DW9_BC		0x6C024
> >  #define   IREF0RC_OFFSET_SHIFT		8
> 
> --
> Jani Nikula, Intel Open Source Graphics Center
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Re: [PATCH v2 07/20] drm/i915/icl: Define AUX lane registers for Port A/B

[Chauhan, Madhav]

> -----Original Message-----
> From: Nikula, Jani
> Sent: Wednesday, July 4, 2018 8:25 PM
> To: Chauhan, Madhav <madhav.chauhan@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Vivi, Rodrigo <rodrigo.vivi@intel.com>; Zanoni, Paulo R
> <paulo.r.zanoni@intel.com>; Shankar, Uma <uma.shankar@intel.com>;
> Chauhan, Madhav <madhav.chauhan@intel.com>
> Subject: Re: [PATCH v2 07/20] drm/i915/icl: Define AUX lane registers for Port
> A/B
> 
> On Tue, 03 Jul 2018, Madhav Chauhan <madhav.chauhan@intel.com>
> wrote:
> > This patch defines AUX lane registers for PORT_PCS_DW1, PORT_TX_DW2,
> > PORT_TX_DW4, PORT_TX_DW5 used during dsi enabling.
> >
> > Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h | 22 ++++++++++++++++++++++
> >  1 file changed, 22 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index 3fa8f02..d3ce1a9 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1780,16 +1780,21 @@ enum i915_power_well_id {
> >
> _CNL_PORT_PCS_DW1_LN0_D, \
> >
> _CNL_PORT_PCS_DW1_LN0_AE, \
> >
> _CNL_PORT_PCS_DW1_LN0_F))
> > +
> >  #define _ICL_PORT_PCS_DW1_GRP_A		0x162604
> >  #define _ICL_PORT_PCS_DW1_GRP_B		0x6C604
> >  #define _ICL_PORT_PCS_DW1_LN0_A		0x162804
> >  #define _ICL_PORT_PCS_DW1_LN0_B		0x6C804
> > +#define _ICL_PORT_PCS_DW1_AUX_B		0x6c304
> >  #define ICL_PORT_PCS_DW1_GRP(port)	_MMIO_PORT(port,\
> >
> _ICL_PORT_PCS_DW1_GRP_A, \
> >
> _ICL_PORT_PCS_DW1_GRP_B)
> >  #define ICL_PORT_PCS_DW1_LN0(port)	_MMIO_PORT(port, \
> >
> _ICL_PORT_PCS_DW1_LN0_A, \
> >
> _ICL_PORT_PCS_DW1_LN0_B)
> > +#define ICL_PORT_PCS_DW1_AUX(port)	_MMIO_PORT(port, \
> > +
> _CNL_PORT_PCS_DW1_GRP_AE, \
> 
> I think for consistency with the rest of the registers here you should add
> 0x162304 as _ICL_PORT_PCS_DW1_AUX_A. Clearly that's been decided for
> the rest of these registers.
> 
> > +
> _ICL_PORT_PCS_DW1_AUX_B)
> >  #define   COMMON_KEEPER_EN		(1 << 26)
> >
> >  /* CNL Port TX registers */
> > @@ -1826,16 +1831,23 @@ enum i915_power_well_id {
> >  #define _ICL_PORT_TX_DW2_GRP_B		0x6C688
> >  #define _ICL_PORT_TX_DW2_LN0_A		0x162888
> >  #define _ICL_PORT_TX_DW2_LN0_B		0x6C888
> > +#define _ICL_PORT_TX_DW2_AUX_A		0x162388
> > +#define _ICL_PORT_TX_DW2_AUX_B		0x6c388
> >  #define ICL_PORT_TX_DW2_GRP(port)	_MMIO_PORT(port, \
> >
> _ICL_PORT_TX_DW2_GRP_A, \
> >
> _ICL_PORT_TX_DW2_GRP_B)
> >  #define ICL_PORT_TX_DW2_LN0(port)	_MMIO_PORT(port, \
> >
> _ICL_PORT_TX_DW2_LN0_A, \
> >
> _ICL_PORT_TX_DW2_LN0_B)
> > +#define ICL_PORT_TX_DW2_AUX(port)	_MMIO_PORT(port, \
> > +
> _ICL_PORT_TX_DW2_AUX_A, \
> > +
> _ICL_PORT_TX_DW2_AUX_B)
> >  #define   SWING_SEL_UPPER(x)		(((x) >> 3) << 15)
> >  #define   SWING_SEL_UPPER_MASK		(1 << 15)
> >  #define   SWING_SEL_LOWER(x)		(((x) & 0x7) << 11)
> >  #define   SWING_SEL_LOWER_MASK		(0x7 << 11)
> > +#define  FRC_LATENCY_OPTIM_MASK	(0x7 << 8)
> > +#define  FRC_LATENCY_OPTIM_VAL(x)	((x) << 8)
>           ^^^
> 
> Three spaces like the rest of them.
> 
> With the above two things fixed,
> 
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>

Ok. Thanks!!

Regards,
Madhav

> 
> 
> >  #define   RCOMP_SCALAR(x)		((x) << 0)
> >  #define   RCOMP_SCALAR_MASK		(0xFF << 0)
> >
> > @@ -1851,6 +1863,8 @@ enum i915_power_well_id {
> >  #define _ICL_PORT_TX_DW4_LN0_A		0x162890
> >  #define _ICL_PORT_TX_DW4_LN1_A		0x162990
> >  #define _ICL_PORT_TX_DW4_LN0_B		0x6C890
> > +#define _ICL_PORT_TX_DW4_AUX_A		0x162390
> > +#define _ICL_PORT_TX_DW4_AUX_B		0x6c390
> >  #define ICL_PORT_TX_DW4_GRP(port)	_MMIO_PORT(port, \
> >
> _ICL_PORT_TX_DW4_GRP_A, \
> >
> _ICL_PORT_TX_DW4_GRP_B)
> > @@ -1859,6 +1873,9 @@ enum i915_power_well_id {
> >
> _ICL_PORT_TX_DW4_LN0_B) + \
> >  					     ((ln) *
> (_ICL_PORT_TX_DW4_LN1_A - \
> >
> _ICL_PORT_TX_DW4_LN0_A)))
> > +#define ICL_PORT_TX_DW4_AUX(port)	_MMIO_PORT(port, \
> > +
> _ICL_PORT_TX_DW4_AUX_A, \
> > +
> _ICL_PORT_TX_DW4_AUX_B)
> >  #define   LOADGEN_SELECT		(1 << 31)
> >  #define   POST_CURSOR_1(x)		((x) << 12)
> >  #define   POST_CURSOR_1_MASK		(0x3F << 12)
> > @@ -1873,12 +1890,17 @@ enum i915_power_well_id {
> >  #define _ICL_PORT_TX_DW5_GRP_B		0x6C694
> >  #define _ICL_PORT_TX_DW5_LN0_A		0x162894
> >  #define _ICL_PORT_TX_DW5_LN0_B		0x6C894
> > +#define _ICL_PORT_TX_DW5_AUX_A		0x162394
> > +#define _ICL_PORT_TX_DW5_AUX_B		0x6c394
> >  #define ICL_PORT_TX_DW5_GRP(port)	_MMIO_PORT(port, \
> >
> _ICL_PORT_TX_DW5_GRP_A, \
> >
> _ICL_PORT_TX_DW5_GRP_B)
> >  #define ICL_PORT_TX_DW5_LN0(port)	_MMIO_PORT(port, \
> >
> _ICL_PORT_TX_DW5_LN0_A, \
> >
> _ICL_PORT_TX_DW5_LN0_B)
> > +#define ICL_PORT_TX_DW5_AUX(port)	_MMIO_PORT(port, \
> > +
> _ICL_PORT_TX_DW5_AUX_A, \
> > +
> _ICL_PORT_TX_DW5_AUX_B)
> >  #define   TX_TRAINING_EN		(1 << 31)
> >  #define   TAP2_DISABLE			(1 << 30)
> >  #define   TAP3_DISABLE			(1 << 29)
> 
> --
> Jani Nikula, Intel Open Source Graphics Center
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