[PATCH v2 00/18] Some cleanups

[PATCH v2 00/18] Some cleanups

[Sergio Paracuellos]

This patch series clean up a bit mt7621-pci driver.

Changes from v2:
    - It includes new 17 patches from PATCH 2 to PATCH 18
    - PATCH 1 was send before alone and is being included
      as it is in this new series.

Hope this helps.

Best regards,
    Sergio Paracuellos

Sergio Paracuellos (18):
  staging: mt7621-pci: refactor pci related read and writes functions
  staging: mt7621-pci: simplify pci dependant registers arithmetics
  staging: mt7621-pci: avoid pointer arithmetics in some macros
  staging: mt7621-pci: use BIT macro in definitions
  staging: mt7621-pci: use read and writes in set_pcie_phy function
  staging: mt7621-pci: make ASSERT_SYSRST_PCIE and DEASSERT_SYSRST_PCIE
    inline functions
  staging: mt7621-pci: rewrite [read|write]_config functions
  staging: mt7621-pci: factor out mt7621_pci_enable_irqs and
    mt7621_pci_disable
  staging: mt7621-pci: minor refactor in duplicated code
  staging: mt7621-pci: factor out mt7621_pci_enable function
  staging: mt7621-pci: factor out mt7621_pci_configure function
  staging: mt7621-pci: add blank line between declarations and code
    statements
  staging: mt7621-pci: remove unused preprocessor defines
  staging: mt7621-pci: rename RALINK_PCI_CONFIG_DATA_VIRTUAL_REG
    definition
  staging: mt7621-pci: add some common calculations to
    mt7621_pci_get_cfgaddr
  staging: mt7621-pci: fix and remove some comments
  staging: mt7621-pci: factor out mt7621_pci_init_gpios function
  staging: mt7621-pci: add SPDX identifier

 drivers/staging/mt7621-pci/pci-mt7621.c | 706 ++++++++++++++------------------
 1 file changed, 305 insertions(+), 401 deletions(-)

-- 
2.7.4

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[PATCH v2 01/18] staging: mt7621-pci: refactor pci related read and writes functions

[Sergio Paracuellos]

This commit simplifies and clean a lot of stuff related with pci
reads and writes. It deletes a lot of not needed at all functions
and use kernel arch operations read[b,w,l] and write[b,w,l] instead
of use custom macros. It also include one function helper called
'mt7621_pci_get_cfgaddr' to easily obtain config address. Also to
get pci base address a global 'mt7621_pci_base' variable has been
included and initialized as a pointer to RALINK_PCI_BASE in driver
probe function. With this changes LOC is clearly decreased and
readability is increased.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 178 +++++++++++---------------------
 1 file changed, 58 insertions(+), 120 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index c12447d..dabe5c4 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -113,23 +113,6 @@
 #define RALINK_PCIEPHY_P0P1_CTL_OFFSET	(RALINK_PCI_BASE + 0x9000)
 #define RALINK_PCIEPHY_P2_CTL_OFFSET	(RALINK_PCI_BASE + 0xA000)
 
-#define MV_WRITE(ofs, data)	\
-	*(volatile u32 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le32(data)
-#define MV_READ(ofs, data)	\
-	*(data) = le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
-#define MV_READ_DATA(ofs)	\
-	le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
-
-#define MV_WRITE_16(ofs, data)	\
-	*(volatile u16 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le16(data)
-#define MV_READ_16(ofs, data)	\
-	*(data) = le16_to_cpu(*(volatile u16 *)(RALINK_PCI_BASE+(ofs)))
-
-#define MV_WRITE_8(ofs, data)	\
-	*(volatile u8 *)(RALINK_PCI_BASE+(ofs)) = data
-#define MV_READ_8(ofs, data)	\
-	*(data) = *(volatile u8 *)(RALINK_PCI_BASE+(ofs))
-
 #define RALINK_PCI_MM_MAP_BASE		0x60000000
 #define RALINK_PCI_IO_MAP_BASE		0x1e160000
 
@@ -173,123 +156,75 @@
 #define MEMORY_BASE 0x0
 static int pcie_link_status = 0;
 
-#define PCI_ACCESS_READ_1  0
-#define PCI_ACCESS_READ_2  1
-#define PCI_ACCESS_READ_4  2
-#define PCI_ACCESS_WRITE_1 3
-#define PCI_ACCESS_WRITE_2 4
-#define PCI_ACCESS_WRITE_4 5
+static void __iomem *mt7621_pci_base;
 
-static int config_access(unsigned char access_type, struct pci_bus *bus,
-			unsigned int devfn, unsigned int where, u32 *data)
+static inline u32 mt7621_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
+					 unsigned int func, unsigned int where)
 {
-	unsigned int slot = PCI_SLOT(devfn);
-	u8 func = PCI_FUNC(devfn);
-	uint32_t address_reg, data_reg;
-	unsigned int address;
+	return ((bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) |
+		0x80000000);
+}
+
+static int
+pci_config_read(struct pci_bus *bus, unsigned int devfn,
+		int where, int size, u32 *val)
+{
+	u32 address_reg, data_reg;
+	u32 address;
 
 	address_reg = RALINK_PCI_CONFIG_ADDR;
 	data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
 
-	address = (((where&0xF00)>>8)<<24) |(bus->number << 16) | (slot << 11) |
-				(func << 8) | (where & 0xfc) | 0x80000000;
-	MV_WRITE(address_reg, address);
+	address = (((where & 0xF00) >> 8) << 24) |
+		   mt7621_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
+					  PCI_FUNC(devfn), where);
 
-	switch (access_type) {
-	case PCI_ACCESS_WRITE_1:
-		MV_WRITE_8(data_reg+(where&0x3), *data);
-		break;
-	case PCI_ACCESS_WRITE_2:
-		MV_WRITE_16(data_reg+(where&0x3), *data);
-		break;
-	case PCI_ACCESS_WRITE_4:
-		MV_WRITE(data_reg, *data);
-		break;
-	case PCI_ACCESS_READ_1:
-		MV_READ_8(data_reg+(where&0x3), data);
-		break;
-	case PCI_ACCESS_READ_2:
-		MV_READ_16(data_reg+(where&0x3), data);
+	writel(address, mt7621_pci_base + address_reg);
+
+	switch (size) {
+	case 1:
+		*val = readb(mt7621_pci_base + data_reg + (where & 0x3));
 		break;
-	case PCI_ACCESS_READ_4:
-		MV_READ(data_reg, data);
+	case 2:
+		*val = readw(mt7621_pci_base + data_reg + (where & 0x3));
 		break;
-	default:
-		printk("no specify access type\n");
+	case 4:
+		*val = readl(mt7621_pci_base + data_reg);
 		break;
 	}
-	return 0;
-}
-
-static int
-read_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 *val)
-{
-	return config_access(PCI_ACCESS_READ_1, bus, devfn, (unsigned int)where, (u32 *)val);
-}
-
-static int
-read_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 *val)
-{
-	return config_access(PCI_ACCESS_READ_2, bus, devfn, (unsigned int)where, (u32 *)val);
-}
-
-static int
-read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 *val)
-{
-	return config_access(PCI_ACCESS_READ_4, bus, devfn, (unsigned int)where, (u32 *)val);
-}
-
-static int
-write_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 val)
-{
-	if (config_access(PCI_ACCESS_WRITE_1, bus, devfn, (unsigned int)where, (u32 *)&val))
-		return -1;
 
 	return PCIBIOS_SUCCESSFUL;
 }
 
 static int
-write_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 val)
+pci_config_write(struct pci_bus *bus, unsigned int devfn,
+		 int where, int size, u32 val)
 {
-	if (config_access(PCI_ACCESS_WRITE_2, bus, devfn, where, (u32 *)&val))
-		return -1;
+	u32 address_reg, data_reg;
+	u32 address;
 
-	return PCIBIOS_SUCCESSFUL;
-}
+	address_reg = RALINK_PCI_CONFIG_ADDR;
+	data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
 
-static int
-write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 val)
-{
-	if (config_access(PCI_ACCESS_WRITE_4, bus, devfn, where, &val))
-		return -1;
+	address = (((where & 0xF00) >> 8) << 24) |
+		   mt7621_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
+					  PCI_FUNC(devfn), where);
 
-	return PCIBIOS_SUCCESSFUL;
-}
+	writel(address, mt7621_pci_base + address_reg);
 
-static int
-pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val)
-{
 	switch (size) {
 	case 1:
-		return read_config_byte(bus, devfn, where, (u8 *) val);
+		writeb((u8)val, mt7621_pci_base + data_reg + (where & 0x3));
+		break;
 	case 2:
-		return read_config_word(bus, devfn, where, (u16 *) val);
-	default:
-		return read_config_dword(bus, devfn, where, val);
+		writew((u16)val, mt7621_pci_base + data_reg + (where & 0x3));
+		break;
+	case 4:
+		writel(val, mt7621_pci_base + data_reg);
+		break;
 	}
-}
 
-static int
-pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
-{
-	switch (size) {
-	case 1:
-		return write_config_byte(bus, devfn, where, (u8) val);
-	case 2:
-		return write_config_word(bus, devfn, where, (u16) val);
-	default:
-		return write_config_dword(bus, devfn, where, val);
-	}
+	return PCIBIOS_SUCCESSFUL;
 }
 
 struct pci_ops mt7621_pci_ops = {
@@ -306,29 +241,31 @@ static struct pci_controller mt7621_controller = {
 };
 
 static void
-read_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long *val)
+read_config(unsigned long bus, unsigned long dev, unsigned long func,
+	    unsigned long reg, unsigned long *val)
 {
-	unsigned int address_reg, data_reg, address;
+	u32 address_reg, data_reg, address;
 
 	address_reg = RALINK_PCI_CONFIG_ADDR;
 	data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
-	address = (((reg & 0xF00)>>8)<<24) | (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000 ;
-	MV_WRITE(address_reg, address);
-	MV_READ(data_reg, val);
-	return;
+	address = (((reg & 0xF00) >> 8) << 24) |
+		   mt7621_pci_get_cfgaddr(bus, dev, func, reg);
+	writel(address, mt7621_pci_base + address_reg);
+	*val = readl(mt7621_pci_base + data_reg);
 }
 
 static void
-write_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long val)
+write_config(unsigned long bus, unsigned long dev, unsigned long func,
+	     unsigned long reg, unsigned long val)
 {
-	unsigned int address_reg, data_reg, address;
+	u32 address_reg, data_reg, address;
 
 	address_reg = RALINK_PCI_CONFIG_ADDR;
 	data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
-	address = (((reg & 0xF00)>>8)<<24) | (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000 ;
-	MV_WRITE(address_reg, address);
-	MV_WRITE(data_reg, val);
-	return;
+	address = (((reg & 0xF00) >> 8) << 24) |
+		   mt7621_pci_get_cfgaddr(bus, dev, func, reg);
+	writel(address, mt7621_pci_base + address_reg);
+	writel(val, mt7621_pci_base + data_reg);
 }
 
 int
@@ -479,6 +416,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 {
 	unsigned long val = 0;
 
+	mt7621_pci_base = (void __iomem *)RALINK_PCI_BASE;
 	iomem_resource.start = 0;
 	iomem_resource.end = ~0;
 	ioport_resource.start = 0;
-- 
2.7.4

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[PATCH v2 02/18] staging: mt7621-pci: simplify pci dependant registers arithmetics

[Sergio Paracuellos]

PCI controller dependant register was handled with different
custom macros including very ugly pointer aritmethics. Simplify
them adding an array of offset per controller and a macro to get
the relative offset for each register for the controller. To avoid
arithmetics add two simple mt7621_pci_reg_[read|write] functions
where the base is neing taking into account to get and do the correct
operations. Register useds along the code modified to use the new
approach.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 81 ++++++++++++++++-----------------
 1 file changed, 39 insertions(+), 42 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index dabe5c4..32c37e8 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -79,36 +79,20 @@
 #define RALINK_PCI_BASE	0xBE140000
 
 #define RALINK_PCIEPHY_P0P1_CTL_OFFSET	(RALINK_PCI_BASE + 0x9000)
-#define RT6855_PCIE0_OFFSET		0x2000
-#define RT6855_PCIE1_OFFSET		0x3000
-#define RT6855_PCIE2_OFFSET		0x4000
-
-#define RALINK_PCI0_BAR0SETUP_ADDR	*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0010)
-#define RALINK_PCI0_IMBASEBAR0_ADDR	*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0018)
-#define RALINK_PCI0_ID			*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0030)
-#define RALINK_PCI0_CLASS		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0034)
-#define RALINK_PCI0_SUBID		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0038)
-#define RALINK_PCI0_STATUS		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0050)
-#define RALINK_PCI0_DERR		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0060)
-#define RALINK_PCI0_ECRC		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0064)
-
-#define RALINK_PCI1_BAR0SETUP_ADDR	*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0010)
-#define RALINK_PCI1_IMBASEBAR0_ADDR	*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0018)
-#define RALINK_PCI1_ID			*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0030)
-#define RALINK_PCI1_CLASS		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0034)
-#define RALINK_PCI1_SUBID		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0038)
-#define RALINK_PCI1_STATUS		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0050)
-#define RALINK_PCI1_DERR		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0060)
-#define RALINK_PCI1_ECRC		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0064)
-
-#define RALINK_PCI2_BAR0SETUP_ADDR	*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0010)
-#define RALINK_PCI2_IMBASEBAR0_ADDR	*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0018)
-#define RALINK_PCI2_ID			*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0030)
-#define RALINK_PCI2_CLASS		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0034)
-#define RALINK_PCI2_SUBID		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0038)
-#define RALINK_PCI2_STATUS		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0050)
-#define RALINK_PCI2_DERR		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0060)
-#define RALINK_PCI2_ECRC		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0064)
+
+static u16 pcie_controller_offsets[] = {
+	0x2000, 0x3000, 0x4000,
+};
+
+#define RALINK_PCI_BAR0SETUP_ADDR(dev)	(pcie_controller_offsets[(dev)] + 0x0010)
+#define RALINK_PCI_IMBASEBAR0_ADDR(dev)	(pcie_controller_offsets[(dev)] + 0x0018)
+#define RALINK_PCI_ID(dev)		(pcie_controller_offsets[(dev)] + 0x0030)
+#define RALINK_PCI_CLASS(dev)		(pcie_controller_offsets[(dev)] + 0x0034)
+#define RALINK_PCI_SUBID(dev)		(pcie_controller_offsets[(dev)] + 0x0038)
+#define RALINK_PCI_STATUS(dev)		(pcie_controller_offsets[(dev)] + 0x0050)
+#define RALINK_PCI_DERR(dev)		(pcie_controller_offsets[(dev)] + 0x0060)
+#define RALINK_PCI_ECRC(dev)		(pcie_controller_offsets[(dev)] + 0x0064)
+
 
 #define RALINK_PCIEPHY_P0P1_CTL_OFFSET	(RALINK_PCI_BASE + 0x9000)
 #define RALINK_PCIEPHY_P2_CTL_OFFSET	(RALINK_PCI_BASE + 0xA000)
@@ -158,6 +142,16 @@ static int pcie_link_status = 0;
 
 static void __iomem *mt7621_pci_base;
 
+static u32 mt7621_pci_reg_read(u32 reg)
+{
+	return readl(mt7621_pci_base + reg);
+}
+
+static void mt7621_pci_reg_write(u32 val, u32 reg)
+{
+	writel(val, mt7621_pci_base + reg);
+}
+
 static inline u32 mt7621_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
 					 unsigned int func, unsigned int where)
 {
@@ -470,7 +464,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 	*(unsigned int *)(0xbe000620) |= 0x1<<19 | 0x1<<8 | 0x1<<7;		// set DATA
 	mdelay(1000);
 
-	if ((RALINK_PCI0_STATUS & 0x1) == 0) {
+	if ((mt7621_pci_reg_read(RALINK_PCI_STATUS(0)) & 0x1) == 0) {
 		printk("PCIE0 no card, disable it(RST&CLK)\n");
 		ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST);
 		rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
@@ -480,7 +474,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 		RALINK_PCI_PCIMSK_ADDR |= (1<<20); // enable pcie1 interrupt
 	}
 
-	if ((RALINK_PCI1_STATUS & 0x1) == 0) {
+	if ((mt7621_pci_reg_read(RALINK_PCI_STATUS(1)) & 0x1) == 0) {
 		printk("PCIE1 no card, disable it(RST&CLK)\n");
 		ASSERT_SYSRST_PCIE(RALINK_PCIE1_RST);
 		rt_sysc_m32(RALINK_PCIE1_CLK_EN, 0, RALINK_CLKCFG1);
@@ -490,7 +484,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 		RALINK_PCI_PCIMSK_ADDR |= (1<<21); // enable pcie1 interrupt
 	}
 
-	if ((RALINK_PCI2_STATUS & 0x1) == 0) {
+	if ((mt7621_pci_reg_read(RALINK_PCI_STATUS(2)) & 0x1) == 0) {
 		printk("PCIE2 no card, disable it(RST&CLK)\n");
 		ASSERT_SYSRST_PCIE(RALINK_PCIE2_RST);
 		rt_sysc_m32(RALINK_PCIE2_CLK_EN, 0, RALINK_CLKCFG1);
@@ -550,25 +544,28 @@ pcie(2/1/0) link status	pcie2_num	pcie1_num	pcie0_num
 
 	//PCIe0
 	if ((pcie_link_status & 0x1) != 0) {
-		RALINK_PCI0_BAR0SETUP_ADDR = 0x7FFF0001;	//open 7FFF:2G; ENABLE
-		RALINK_PCI0_IMBASEBAR0_ADDR = MEMORY_BASE;
-		RALINK_PCI0_CLASS = 0x06040001;
+		/* open 7FFF:2G; ENABLE */
+		mt7621_pci_reg_write(0x7FFF0001, RALINK_PCI_BAR0SETUP_ADDR(0));
+		mt7621_pci_reg_write(MEMORY_BASE, RALINK_PCI_IMBASEBAR0_ADDR(0));
+		mt7621_pci_reg_write(0x06040001, RALINK_PCI_CLASS(0));
 		printk("PCIE0 enabled\n");
 	}
 
 	//PCIe1
 	if ((pcie_link_status & 0x2) != 0) {
-		RALINK_PCI1_BAR0SETUP_ADDR = 0x7FFF0001;	//open 7FFF:2G; ENABLE
-		RALINK_PCI1_IMBASEBAR0_ADDR = MEMORY_BASE;
-		RALINK_PCI1_CLASS = 0x06040001;
+		/* open 7FFF:2G; ENABLE */
+		mt7621_pci_reg_write(0x7FFF0001, RALINK_PCI_BAR0SETUP_ADDR(1));
+		mt7621_pci_reg_write(MEMORY_BASE, RALINK_PCI_IMBASEBAR0_ADDR(1));
+		mt7621_pci_reg_write(0x06040001, RALINK_PCI_CLASS(1));
 		printk("PCIE1 enabled\n");
 	}
 
 	//PCIe2
 	if ((pcie_link_status & 0x4) != 0) {
-		RALINK_PCI2_BAR0SETUP_ADDR = 0x7FFF0001;	//open 7FFF:2G; ENABLE
-		RALINK_PCI2_IMBASEBAR0_ADDR = MEMORY_BASE;
-		RALINK_PCI2_CLASS = 0x06040001;
+		/* open 7FFF:2G; ENABLE */
+		mt7621_pci_reg_write(0x7FFF0001, RALINK_PCI_BAR0SETUP_ADDR(2));
+		mt7621_pci_reg_write(MEMORY_BASE, RALINK_PCI_IMBASEBAR0_ADDR(2));
+		mt7621_pci_reg_write(0x06040001, RALINK_PCI_CLASS(2));
 		printk("PCIE2 enabled\n");
 	}
 
-- 
2.7.4

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[PATCH v2 03/18] staging: mt7621-pci: avoid pointer arithmetics in some macros

[Sergio Paracuellos]

RALINK_PCI_MEMBASE, RALINK_PCI_IOBASE, RALINK_PCI_PCICFG_ADDR and
RALINK_PCI_PCIMSK_ADDR are using very ugly pointer arithmetics to
read and write along the code. Instead of doing this, use the
mt7621_pci_reg_read and mt7621_pci_reg_write functions making
this a bit cleaner.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 59 ++++++++++++++-------------------
 1 file changed, 25 insertions(+), 34 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 32c37e8..f7defa7 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -68,14 +68,14 @@
 
 #define RALINK_PCI_CONFIG_ADDR		0x20
 #define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG	0x24
-#define RALINK_PCI_MEMBASE		*(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
-#define RALINK_PCI_IOBASE		*(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
+#define RALINK_PCI_MEMBASE		0x0028
+#define RALINK_PCI_IOBASE		0x002C
 #define RALINK_PCIE0_RST		(1<<24)
 #define RALINK_PCIE1_RST		(1<<25)
 #define RALINK_PCIE2_RST		(1<<26)
 
-#define RALINK_PCI_PCICFG_ADDR		*(volatile u32 *)(RALINK_PCI_BASE + 0x0000)
-#define RALINK_PCI_PCIMSK_ADDR		*(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
+#define RALINK_PCI_PCICFG_ADDR		0x0000
+#define RALINK_PCI_PCIMSK_ADDR		0x000C
 #define RALINK_PCI_BASE	0xBE140000
 
 #define RALINK_PCIEPHY_P0P1_CTL_OFFSET	(RALINK_PCI_BASE + 0x9000)
@@ -408,6 +408,7 @@ void setup_cm_memory_region(struct resource *mem_resource)
 
 static int mt7621_pci_probe(struct platform_device *pdev)
 {
+	u32 mask;
 	unsigned long val = 0;
 
 	mt7621_pci_base = (void __iomem *)RALINK_PCI_BASE;
@@ -471,7 +472,9 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 		pcie_link_status &= ~(1<<0);
 	} else {
 		pcie_link_status |= 1<<0;
-		RALINK_PCI_PCIMSK_ADDR |= (1<<20); // enable pcie1 interrupt
+		mask = mt7621_pci_reg_read(RALINK_PCI_PCIMSK_ADDR);
+		mask |= (1<<20); // enable pcie1 interrupt
+		mt7621_pci_reg_write(mask, RALINK_PCI_PCIMSK_ADDR);
 	}
 
 	if ((mt7621_pci_reg_read(RALINK_PCI_STATUS(1)) & 0x1) == 0) {
@@ -481,7 +484,9 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 		pcie_link_status &= ~(1<<1);
 	} else {
 		pcie_link_status |= 1<<1;
-		RALINK_PCI_PCIMSK_ADDR |= (1<<21); // enable pcie1 interrupt
+		mask = mt7621_pci_reg_read(RALINK_PCI_PCIMSK_ADDR);
+		mask |= (1<<21); // enable pcie1 interrupt
+		mt7621_pci_reg_write(mask, RALINK_PCI_PCIMSK_ADDR);
 	}
 
 	if ((mt7621_pci_reg_read(RALINK_PCI_STATUS(2)) & 0x1) == 0) {
@@ -491,7 +496,9 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 		pcie_link_status &= ~(1<<2);
 	} else {
 		pcie_link_status |= 1<<2;
-		RALINK_PCI_PCIMSK_ADDR |= (1<<22); // enable pcie2 interrupt
+		mask = mt7621_pci_reg_read(RALINK_PCI_PCIMSK_ADDR);
+		mask |= (1<<22); // enable pcie2 interrupt
+		mt7621_pci_reg_write(mask, RALINK_PCI_PCIMSK_ADDR);
 	}
 
 	if (pcie_link_status == 0)
@@ -508,39 +515,23 @@ pcie(2/1/0) link status	pcie2_num	pcie1_num	pcie0_num
 3'b110			1		0		x
 3'b111			2		1		0
 */
-	switch (pcie_link_status) {
-	case 2:
-		RALINK_PCI_PCICFG_ADDR &= ~0x00ff0000;
-		RALINK_PCI_PCICFG_ADDR |= 0x1 << 16;	//port0
-		RALINK_PCI_PCICFG_ADDR |= 0x0 << 20;	//port1
-		break;
-	case 4:
-		RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
-		RALINK_PCI_PCICFG_ADDR |= 0x1 << 16;	//port0
-		RALINK_PCI_PCICFG_ADDR |= 0x2 << 20;	//port1
-		RALINK_PCI_PCICFG_ADDR |= 0x0 << 24;	//port2
-		break;
-	case 5:
-		RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
-		RALINK_PCI_PCICFG_ADDR |= 0x0 << 16;	//port0
-		RALINK_PCI_PCICFG_ADDR |= 0x2 << 20;	//port1
-		RALINK_PCI_PCICFG_ADDR |= 0x1 << 24;	//port2
-		break;
-	case 6:
-		RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
-		RALINK_PCI_PCICFG_ADDR |= 0x2 << 16;	//port0
-		RALINK_PCI_PCICFG_ADDR |= 0x0 << 20;	//port1
-		RALINK_PCI_PCICFG_ADDR |= 0x1 << 24;	//port2
-		break;
-	}
+	mask = mt7621_pci_reg_read(RALINK_PCI_PCICFG_ADDR);
+	mask &= ~0x00ff0000;
+	mask |= (0x1 << 16); // port0
+	mask |= (0x0 << 20); // port1
+
+	if (pcie_link_status != 2)
+		mask |= (0x1 << 24); // port2
+
+	mt7621_pci_reg_write(mask, RALINK_PCI_PCICFG_ADDR);
 
 /*
 	ioport_resource.start = mt7621_res_pci_io1.start;
 	ioport_resource.end = mt7621_res_pci_io1.end;
 */
 
-	RALINK_PCI_MEMBASE = 0xffffffff; //RALINK_PCI_MM_MAP_BASE;
-	RALINK_PCI_IOBASE = RALINK_PCI_IO_MAP_BASE;
+	mt7621_pci_reg_write(0xffffffff, RALINK_PCI_MEMBASE); //RALINK_PCI_MM_MAP_BASE;
+	mt7621_pci_reg_write(RALINK_PCI_IO_MAP_BASE, RALINK_PCI_IOBASE);
 
 	//PCIe0
 	if ((pcie_link_status & 0x1) != 0) {
-- 
2.7.4

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[PATCH v2 04/18] staging: mt7621-pci: use BIT macro in definitions

[Sergio Paracuellos]

There are some definitions which are using its custom
implementation of BIT macro. Just just BIT macro instead.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 31 ++++++++++++++++---------------
 1 file changed, 16 insertions(+), 15 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index f7defa7..904181c 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -39,6 +39,7 @@
  **************************************************************************
  */
 
+#include <linux/bitops.h>
 #include <linux/types.h>
 #include <linux/pci.h>
 #include <linux/kernel.h>
@@ -62,17 +63,17 @@
  * devices.
  */
 
-#define RALINK_PCIE0_CLK_EN		(1<<24)
-#define RALINK_PCIE1_CLK_EN		(1<<25)
-#define RALINK_PCIE2_CLK_EN		(1<<26)
+#define RALINK_PCIE0_CLK_EN		BIT(24)
+#define RALINK_PCIE1_CLK_EN		BIT(25)
+#define RALINK_PCIE2_CLK_EN		BIT(26)
 
 #define RALINK_PCI_CONFIG_ADDR		0x20
 #define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG	0x24
 #define RALINK_PCI_MEMBASE		0x0028
 #define RALINK_PCI_IOBASE		0x002C
-#define RALINK_PCIE0_RST		(1<<24)
-#define RALINK_PCIE1_RST		(1<<25)
-#define RALINK_PCIE2_RST		(1<<26)
+#define RALINK_PCIE0_RST		BIT(24)
+#define RALINK_PCIE1_RST		BIT(25)
+#define RALINK_PCIE2_RST		BIT(26)
 
 #define RALINK_PCI_PCICFG_ADDR		0x0000
 #define RALINK_PCI_PCIMSK_ADDR		0x000C
@@ -122,20 +123,20 @@ static u16 pcie_controller_offsets[] = {
 #define PPLL_CFG1			0x9c
 #define PPLL_DRV			0xa0
 /* SYSC_REG_SYSTEM_CONFIG1 bits */
-#define RALINK_PCI_HOST_MODE_EN		(1<<7)
-#define RALINK_PCIE_RC_MODE_EN		(1<<8)
+#define RALINK_PCI_HOST_MODE_EN		BIT(7)
+#define RALINK_PCIE_RC_MODE_EN		BIT(8)
 //RALINK_RSTCTRL bit
-#define RALINK_PCIE_RST			(1<<23)
-#define RALINK_PCI_RST			(1<<24)
+#define RALINK_PCIE_RST			BIT(23)
+#define RALINK_PCI_RST			BIT(24)
 //RALINK_CLKCFG1 bit
-#define RALINK_PCI_CLK_EN		(1<<19)
-#define RALINK_PCIE_CLK_EN		(1<<21)
+#define RALINK_PCI_CLK_EN		BIT(19)
+#define RALINK_PCIE_CLK_EN		BIT(21)
 //RALINK_GPIOMODE bit
-#define PCI_SLOTx2			(1<<11)
+#define PCI_SLOTx2			BIT(11)
 #define PCI_SLOTx1			(2<<11)
 //MTK PCIE PLL bit
-#define PDRV_SW_SET			(1<<31)
-#define LC_CKDRVPD_			(1<<19)
+#define PDRV_SW_SET			BIT(31)
+#define LC_CKDRVPD_			BIT(19)
 
 #define MEMORY_BASE 0x0
 static int pcie_link_status = 0;
-- 
2.7.4

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[PATCH v2 05/18] staging: mt7621-pci: use read and writes in set_pcie_phy function

[Sergio Paracuellos]

set_pcie_phy can be refactor to use mt7621_pci_reg_write and
mt7621_pci_reg_read functions intead of use pointer arithmetics.
Use them and simplify implicated calls and definitions along the
code.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 122 ++++++++++++++++----------------
 1 file changed, 62 insertions(+), 60 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 904181c..897485a 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -79,7 +79,6 @@
 #define RALINK_PCI_PCIMSK_ADDR		0x000C
 #define RALINK_PCI_BASE	0xBE140000
 
-#define RALINK_PCIEPHY_P0P1_CTL_OFFSET	(RALINK_PCI_BASE + 0x9000)
 
 static u16 pcie_controller_offsets[] = {
 	0x2000, 0x3000, 0x4000,
@@ -95,8 +94,8 @@ static u16 pcie_controller_offsets[] = {
 #define RALINK_PCI_ECRC(dev)		(pcie_controller_offsets[(dev)] + 0x0064)
 
 
-#define RALINK_PCIEPHY_P0P1_CTL_OFFSET	(RALINK_PCI_BASE + 0x9000)
-#define RALINK_PCIEPHY_P2_CTL_OFFSET	(RALINK_PCI_BASE + 0xA000)
+#define RALINK_PCIEPHY_P0P1_CTL_OFFSET	0x9000
+#define RALINK_PCIEPHY_P2_CTL_OFFSET	0xA000
 
 #define RALINK_PCI_MM_MAP_BASE		0x60000000
 #define RALINK_PCI_IO_MAP_BASE		0x1e160000
@@ -289,24 +288,27 @@ pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 }
 
 void
-set_pcie_phy(u32 *addr, int start_b, int bits, int val)
+set_pcie_phy(u32 offset, int start_b, int bits, int val)
 {
-	*(unsigned int *)(addr) &= ~(((1<<bits) - 1)<<start_b);
-	*(unsigned int *)(addr) |= val << start_b;
+	u32 reg = mt7621_pci_reg_read(offset);
+
+	reg &= ~(((1 << bits) - 1) << start_b);
+	reg |= val << start_b;
+	mt7621_pci_reg_write(reg, offset);
 }
 
 void
 bypass_pipe_rst(void)
 {
 	/* PCIe Port 0 */
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c), 12, 1, 0x01);	// rg_pe1_pipe_rst_b
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c),  4, 1, 0x01);	// rg_pe1_pipe_cmd_frc[4]
+	set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c), 12, 1, 0x01);	// rg_pe1_pipe_rst_b
+	set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c),  4, 1, 0x01);	// rg_pe1_pipe_cmd_frc[4]
 	/* PCIe Port 1 */
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c), 12, 1, 0x01);	// rg_pe1_pipe_rst_b
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c),  4, 1, 0x01);	// rg_pe1_pipe_cmd_frc[4]
+	set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c), 12, 1, 0x01);	// rg_pe1_pipe_rst_b
+	set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c),  4, 1, 0x01);	// rg_pe1_pipe_cmd_frc[4]
 	/* PCIe Port 2 */
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c), 12, 1, 0x01);	// rg_pe1_pipe_rst_b
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c),  4, 1, 0x01);	// rg_pe1_pipe_cmd_frc[4]
+	set_pcie_phy((RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c), 12, 1, 0x01);	// rg_pe1_pipe_rst_b
+	set_pcie_phy((RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c),  4, 1, 0x01);	// rg_pe1_pipe_cmd_frc[4]
 }
 
 void
@@ -317,77 +319,77 @@ set_phy_for_ssc(void)
 	reg = (reg >> 6) & 0x7;
 	/* Set PCIe Port0 & Port1 PHY to disable SSC */
 	/* Debug Xtal Type */
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400),  8, 1, 0x01);	// rg_pe1_frc_h_xtal_type
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400),  9, 2, 0x00);	// rg_pe1_h_xtal_type
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  4, 1, 0x01);	// rg_pe1_frc_phy_en	//Force Port 0 enable control
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  4, 1, 0x01);	// rg_pe1_frc_phy_en	//Force Port 1 enable control
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  5, 1, 0x00);	// rg_pe1_phy_en	//Port 0 disable
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  5, 1, 0x00);	// rg_pe1_phy_en	//Port 1 disable
+	set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400),  8, 1, 0x01);	// rg_pe1_frc_h_xtal_type
+	set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400),  9, 2, 0x00);	// rg_pe1_h_xtal_type
+	set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  4, 1, 0x01);	// rg_pe1_frc_phy_en	//Force Port 0 enable control
+	set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  4, 1, 0x01);	// rg_pe1_frc_phy_en	//Force Port 1 enable control
+	set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  5, 1, 0x00);	// rg_pe1_phy_en	//Port 0 disable
+	set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  5, 1, 0x00);	// rg_pe1_phy_en	//Port 1 disable
 	if (reg <= 5 && reg >= 3) {	// 40MHz Xtal
-		set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  6, 2, 0x01);	// RG_PE1_H_PLL_PREDIV	//Pre-divider ratio (for host mode)
+		set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  6, 2, 0x01);	// RG_PE1_H_PLL_PREDIV	//Pre-divider ratio (for host mode)
 		printk("***** Xtal 40MHz *****\n");
 	} else {			// 25MHz | 20MHz Xtal
-		set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  6, 2, 0x00);	// RG_PE1_H_PLL_PREDIV	//Pre-divider ratio (for host mode)
+		set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  6, 2, 0x00);	// RG_PE1_H_PLL_PREDIV	//Pre-divider ratio (for host mode)
 		if (reg >= 6) {
 			printk("***** Xtal 25MHz *****\n");
-			set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4bc),  4, 2, 0x01);	// RG_PE1_H_PLL_FBKSEL	//Feedback clock select
-			set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x49c),  0, 31, 0x18000000);	// RG_PE1_H_LCDDS_PCW_NCPO	//DDS NCPO PCW (for host mode)
-			set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a4),  0, 16, 0x18d);	// RG_PE1_H_LCDDS_SSC_PRD	//DDS SSC dither period control
-			set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8),  0, 12, 0x4a);	// RG_PE1_H_LCDDS_SSC_DELTA	//DDS SSC dither amplitude control
-			set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 16, 12, 0x4a);	// RG_PE1_H_LCDDS_SSC_DELTA1	//DDS SSC dither amplitude control for initial
+			set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4bc),  4, 2, 0x01);	// RG_PE1_H_PLL_FBKSEL	//Feedback clock select
+			set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x49c),  0, 31, 0x18000000);	// RG_PE1_H_LCDDS_PCW_NCPO	//DDS NCPO PCW (for host mode)
+			set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a4),  0, 16, 0x18d);	// RG_PE1_H_LCDDS_SSC_PRD	//DDS SSC dither period control
+			set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8),  0, 12, 0x4a);	// RG_PE1_H_LCDDS_SSC_DELTA	//DDS SSC dither amplitude control
+			set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 16, 12, 0x4a);	// RG_PE1_H_LCDDS_SSC_DELTA1	//DDS SSC dither amplitude control for initial
 		} else {
 			printk("***** Xtal 20MHz *****\n");
 		}
 	}
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a0),  5, 1, 0x01);	// RG_PE1_LCDDS_CLK_PH_INV	//DDS clock inversion
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 22, 2, 0x02);	// RG_PE1_H_PLL_BC
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 18, 4, 0x06);	// RG_PE1_H_PLL_BP
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 12, 4, 0x02);	// RG_PE1_H_PLL_IR
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  8, 4, 0x01);	// RG_PE1_H_PLL_IC
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4ac), 16, 3, 0x00);	// RG_PE1_H_PLL_BR
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  1, 3, 0x02);	// RG_PE1_PLL_DIVEN
+	set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a0),  5, 1, 0x01);	// RG_PE1_LCDDS_CLK_PH_INV	//DDS clock inversion
+	set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 22, 2, 0x02);	// RG_PE1_H_PLL_BC
+	set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 18, 4, 0x06);	// RG_PE1_H_PLL_BP
+	set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 12, 4, 0x02);	// RG_PE1_H_PLL_IR
+	set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  8, 4, 0x01);	// RG_PE1_H_PLL_IC
+	set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4ac), 16, 3, 0x00);	// RG_PE1_H_PLL_BR
+	set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  1, 3, 0x02);	// RG_PE1_PLL_DIVEN
 	if (reg <= 5 && reg >= 3) {	// 40MHz Xtal
-		set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414),  6, 2, 0x01);	// rg_pe1_mstckdiv		//value of da_pe1_mstckdiv when force mode enable
-		set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414),  5, 1, 0x01);	// rg_pe1_frc_mstckdiv	//force mode enable of da_pe1_mstckdiv
+		set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414),  6, 2, 0x01);	// rg_pe1_mstckdiv		//value of da_pe1_mstckdiv when force mode enable
+		set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414),  5, 1, 0x01);	// rg_pe1_frc_mstckdiv	//force mode enable of da_pe1_mstckdiv
 	}
 	/* Enable PHY and disable force mode */
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  5, 1, 0x01);	// rg_pe1_phy_en	//Port 0 enable
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  5, 1, 0x01);	// rg_pe1_phy_en	//Port 1 enable
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  4, 1, 0x00);	// rg_pe1_frc_phy_en	//Force Port 0 disable control
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  4, 1, 0x00);	// rg_pe1_frc_phy_en	//Force Port 1 disable control
+	set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  5, 1, 0x01);	// rg_pe1_phy_en	//Port 0 enable
+	set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  5, 1, 0x01);	// rg_pe1_phy_en	//Port 1 enable
+	set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  4, 1, 0x00);	// rg_pe1_frc_phy_en	//Force Port 0 disable control
+	set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  4, 1, 0x00);	// rg_pe1_frc_phy_en	//Force Port 1 disable control
 
 	/* Set PCIe Port2 PHY to disable SSC */
 	/* Debug Xtal Type */
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400),  8, 1, 0x01);	// rg_pe1_frc_h_xtal_type
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400),  9, 2, 0x00);	// rg_pe1_h_xtal_type
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  4, 1, 0x01);	// rg_pe1_frc_phy_en	//Force Port 0 enable control
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  5, 1, 0x00);	// rg_pe1_phy_en	//Port 0 disable
+	set_pcie_phy((RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400),  8, 1, 0x01);	// rg_pe1_frc_h_xtal_type
+	set_pcie_phy((RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400),  9, 2, 0x00);	// rg_pe1_h_xtal_type
+	set_pcie_phy((RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  4, 1, 0x01);	// rg_pe1_frc_phy_en	//Force Port 0 enable control
+	set_pcie_phy((RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  5, 1, 0x00);	// rg_pe1_phy_en	//Port 0 disable
 	if (reg <= 5 && reg >= 3) {	// 40MHz Xtal
-		set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  6, 2, 0x01);	// RG_PE1_H_PLL_PREDIV	//Pre-divider ratio (for host mode)
+		set_pcie_phy((RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  6, 2, 0x01);	// RG_PE1_H_PLL_PREDIV	//Pre-divider ratio (for host mode)
 	} else {			// 25MHz | 20MHz Xtal
-		set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  6, 2, 0x00);	// RG_PE1_H_PLL_PREDIV	//Pre-divider ratio (for host mode)
+		set_pcie_phy((RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  6, 2, 0x00);	// RG_PE1_H_PLL_PREDIV	//Pre-divider ratio (for host mode)
 		if (reg >= 6) {		// 25MHz Xtal
-			set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4bc),  4, 2, 0x01);	// RG_PE1_H_PLL_FBKSEL	//Feedback clock select
-			set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x49c),  0, 31, 0x18000000);	// RG_PE1_H_LCDDS_PCW_NCPO	//DDS NCPO PCW (for host mode)
-			set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a4),  0, 16, 0x18d);	// RG_PE1_H_LCDDS_SSC_PRD	//DDS SSC dither period control
-			set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8),  0, 12, 0x4a);	// RG_PE1_H_LCDDS_SSC_DELTA	//DDS SSC dither amplitude control
-			set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 16, 12, 0x4a);	// RG_PE1_H_LCDDS_SSC_DELTA1	//DDS SSC dither amplitude control for initial
+			set_pcie_phy((RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4bc),  4, 2, 0x01);	// RG_PE1_H_PLL_FBKSEL	//Feedback clock select
+			set_pcie_phy((RALINK_PCIEPHY_P2_CTL_OFFSET + 0x49c),  0, 31, 0x18000000);	// RG_PE1_H_LCDDS_PCW_NCPO	//DDS NCPO PCW (for host mode)
+			set_pcie_phy((RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a4),  0, 16, 0x18d);	// RG_PE1_H_LCDDS_SSC_PRD	//DDS SSC dither period control
+			set_pcie_phy((RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8),  0, 12, 0x4a);	// RG_PE1_H_LCDDS_SSC_DELTA	//DDS SSC dither amplitude control
+			set_pcie_phy((RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 16, 12, 0x4a);	// RG_PE1_H_LCDDS_SSC_DELTA1	//DDS SSC dither amplitude control for initial
 		}
 	}
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a0),  5, 1, 0x01);	// RG_PE1_LCDDS_CLK_PH_INV	//DDS clock inversion
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 22, 2, 0x02);	// RG_PE1_H_PLL_BC
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 18, 4, 0x06);	// RG_PE1_H_PLL_BP
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 12, 4, 0x02);	// RG_PE1_H_PLL_IR
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  8, 4, 0x01);	// RG_PE1_H_PLL_IC
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4ac), 16, 3, 0x00);	// RG_PE1_H_PLL_BR
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  1, 3, 0x02);	// RG_PE1_PLL_DIVEN
+	set_pcie_phy((RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a0),  5, 1, 0x01);	// RG_PE1_LCDDS_CLK_PH_INV	//DDS clock inversion
+	set_pcie_phy((RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 22, 2, 0x02);	// RG_PE1_H_PLL_BC
+	set_pcie_phy((RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 18, 4, 0x06);	// RG_PE1_H_PLL_BP
+	set_pcie_phy((RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 12, 4, 0x02);	// RG_PE1_H_PLL_IR
+	set_pcie_phy((RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  8, 4, 0x01);	// RG_PE1_H_PLL_IC
+	set_pcie_phy((RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4ac), 16, 3, 0x00);	// RG_PE1_H_PLL_BR
+	set_pcie_phy((RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  1, 3, 0x02);	// RG_PE1_PLL_DIVEN
 	if (reg <= 5 && reg >= 3) {	// 40MHz Xtal
-		set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414),  6, 2, 0x01);	// rg_pe1_mstckdiv		//value of da_pe1_mstckdiv when force mode enable
-		set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414),  5, 1, 0x01);	// rg_pe1_frc_mstckdiv	//force mode enable of da_pe1_mstckdiv
+		set_pcie_phy((RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414),  6, 2, 0x01);	// rg_pe1_mstckdiv		//value of da_pe1_mstckdiv when force mode enable
+		set_pcie_phy((RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414),  5, 1, 0x01);	// rg_pe1_frc_mstckdiv	//force mode enable of da_pe1_mstckdiv
 	}
 	/* Enable PHY and disable force mode */
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  5, 1, 0x01);	// rg_pe1_phy_en	//Port 0 enable
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  4, 1, 0x00);	// rg_pe1_frc_phy_en	//Force Port 0 disable control
+	set_pcie_phy((RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  5, 1, 0x01);	// rg_pe1_phy_en	//Port 0 enable
+	set_pcie_phy((RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  4, 1, 0x00);	// rg_pe1_frc_phy_en	//Force Port 0 disable control
 }
 
 void setup_cm_memory_region(struct resource *mem_resource)
-- 
2.7.4

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[PATCH v2 06/18] staging: mt7621-pci: make ASSERT_SYSRST_PCIE and DEASSERT_SYSRST_PCIE inline functions

[Sergio Paracuellos]

ASSERT_SYSRST_PCIE and DEASSERT_SYSRST_PCIE are defined as preprocessor
macros and can be defined as inline functions instead which are preferred.
Do it and rename to mt7621_pcie_assert_sysrst and mt7621_pcie_deassert_sysrst
respectively.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 41 +++++++++++++++++----------------
 1 file changed, 21 insertions(+), 20 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 897485a..afbd278 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -93,27 +93,12 @@ static u16 pcie_controller_offsets[] = {
 #define RALINK_PCI_DERR(dev)		(pcie_controller_offsets[(dev)] + 0x0060)
 #define RALINK_PCI_ECRC(dev)		(pcie_controller_offsets[(dev)] + 0x0064)
 
-
 #define RALINK_PCIEPHY_P0P1_CTL_OFFSET	0x9000
 #define RALINK_PCIEPHY_P2_CTL_OFFSET	0xA000
 
 #define RALINK_PCI_MM_MAP_BASE		0x60000000
 #define RALINK_PCI_IO_MAP_BASE		0x1e160000
 
-#define ASSERT_SYSRST_PCIE(val)		\
-	do {								\
-		if (rt_sysc_r32(SYSC_REG_CHIP_REV) == 0x00030101)	\
-			rt_sysc_m32(0, val, RALINK_RSTCTRL);		\
-		else							\
-			rt_sysc_m32(val, 0, RALINK_RSTCTRL);		\
-	} while (0)
-#define DEASSERT_SYSRST_PCIE(val)	\
-	do {								\
-		if (rt_sysc_r32(SYSC_REG_CHIP_REV) == 0x00030101)	\
-			rt_sysc_m32(val, 0, RALINK_RSTCTRL);		\
-		else							\
-			rt_sysc_m32(0, val, RALINK_RSTCTRL);		\
-	} while (0)
 #define RALINK_CLKCFG1			0x30
 #define RALINK_RSTCTRL			0x34
 #define RALINK_GPIOMODE			0x60
@@ -142,6 +127,22 @@ static int pcie_link_status = 0;
 
 static void __iomem *mt7621_pci_base;
 
+static inline void mt7621_pcie_assert_sysrst(u32 val)
+{
+	if (rt_sysc_r32(SYSC_REG_CHIP_REV) == 0x00030101)
+		rt_sysc_m32(0, val, RALINK_RSTCTRL);
+	else
+		rt_sysc_m32(val, 0, RALINK_RSTCTRL);
+}
+
+static inline void mt7621_pcie_deassert_sysrst(u32 val)
+{
+	if (rt_sysc_r32(SYSC_REG_CHIP_REV) == 0x00030101)
+		rt_sysc_m32(val, 0, RALINK_RSTCTRL);
+	else
+		rt_sysc_m32(0, val, RALINK_RSTCTRL);
+}
+
 static u32 mt7621_pci_reg_read(u32 reg)
 {
 	return readl(mt7621_pci_base + reg);
@@ -424,7 +425,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 	val |= RALINK_PCIE1_RST;
 	val |= RALINK_PCIE2_RST;
 
-	ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST | RALINK_PCIE1_RST | RALINK_PCIE2_RST);
+	mt7621_pcie_assert_sysrst(RALINK_PCIE0_RST | RALINK_PCIE1_RST | RALINK_PCIE2_RST);
 
 	*(unsigned int *)(0xbe000060) &= ~(0x3<<10 | 0x3<<3);
 	*(unsigned int *)(0xbe000060) |= 0x1<<10 | 0x1<<3;
@@ -439,7 +440,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 	val |= RALINK_PCIE1_RST;
 	val |= RALINK_PCIE2_RST;
 
-	DEASSERT_SYSRST_PCIE(val);
+	mt7621_pcie_deassert_sysrst(val);
 
 	if ((*(unsigned int *)(0xbe00000c)&0xFFFF) == 0x0101) // MT7621 E2
 		bypass_pipe_rst();
@@ -470,7 +471,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 
 	if ((mt7621_pci_reg_read(RALINK_PCI_STATUS(0)) & 0x1) == 0) {
 		printk("PCIE0 no card, disable it(RST&CLK)\n");
-		ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST);
+		mt7621_pcie_assert_sysrst(RALINK_PCIE0_RST);
 		rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
 		pcie_link_status &= ~(1<<0);
 	} else {
@@ -482,7 +483,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 
 	if ((mt7621_pci_reg_read(RALINK_PCI_STATUS(1)) & 0x1) == 0) {
 		printk("PCIE1 no card, disable it(RST&CLK)\n");
-		ASSERT_SYSRST_PCIE(RALINK_PCIE1_RST);
+		mt7621_pcie_assert_sysrst(RALINK_PCIE1_RST);
 		rt_sysc_m32(RALINK_PCIE1_CLK_EN, 0, RALINK_CLKCFG1);
 		pcie_link_status &= ~(1<<1);
 	} else {
@@ -494,7 +495,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 
 	if ((mt7621_pci_reg_read(RALINK_PCI_STATUS(2)) & 0x1) == 0) {
 		printk("PCIE2 no card, disable it(RST&CLK)\n");
-		ASSERT_SYSRST_PCIE(RALINK_PCIE2_RST);
+		mt7621_pcie_assert_sysrst(RALINK_PCIE2_RST);
 		rt_sysc_m32(RALINK_PCIE2_CLK_EN, 0, RALINK_CLKCFG1);
 		pcie_link_status &= ~(1<<2);
 	} else {
-- 
2.7.4

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[PATCH v2 07/18] staging: mt7621-pci: rewrite [read|write]_config functions

[Sergio Paracuellos]

This two functions are called with bus and func being always 0.
Remove non sensense 'bus' and 'func' parameters and pass '0' to
other calls inside the function. Review return and parameter types
also to be more proper with the rest of the code. Adapt properly
calls to those function to match the new prototypes.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 56 ++++++++++++++++-----------------
 1 file changed, 27 insertions(+), 29 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index afbd278..39efde1 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -235,30 +235,28 @@ static struct pci_controller mt7621_controller = {
 	.io_resource	= &mt7621_res_pci_io1,
 };
 
-static void
-read_config(unsigned long bus, unsigned long dev, unsigned long func,
-	    unsigned long reg, unsigned long *val)
+static u32
+read_config(unsigned int dev, u32 reg)
 {
 	u32 address_reg, data_reg, address;
 
 	address_reg = RALINK_PCI_CONFIG_ADDR;
 	data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
 	address = (((reg & 0xF00) >> 8) << 24) |
-		   mt7621_pci_get_cfgaddr(bus, dev, func, reg);
+		   mt7621_pci_get_cfgaddr(0, dev, 0, reg);
 	writel(address, mt7621_pci_base + address_reg);
-	*val = readl(mt7621_pci_base + data_reg);
+	return readl(mt7621_pci_base + data_reg);
 }
 
 static void
-write_config(unsigned long bus, unsigned long dev, unsigned long func,
-	     unsigned long reg, unsigned long val)
+write_config(unsigned int dev, u32 reg, u32 val)
 {
 	u32 address_reg, data_reg, address;
 
 	address_reg = RALINK_PCI_CONFIG_ADDR;
 	data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
 	address = (((reg & 0xF00) >> 8) << 24) |
-		   mt7621_pci_get_cfgaddr(bus, dev, func, reg);
+		   mt7621_pci_get_cfgaddr(0, dev, 0, reg);
 	writel(address, mt7621_pci_base + address_reg);
 	writel(val, mt7621_pci_base + data_reg);
 }
@@ -271,8 +269,8 @@ pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 	int irq;
 
 	if (dev->bus->number == 0) {
-		write_config(0, slot, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
-		read_config(0, slot, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
+		write_config(slot, PCI_BASE_ADDRESS_0, MEMORY_BASE);
+		val = read_config(slot, PCI_BASE_ADDRESS_0);
 		printk("BAR0 at slot %d = %x\n", slot, val);
 	}
 
@@ -413,7 +411,7 @@ void setup_cm_memory_region(struct resource *mem_resource)
 static int mt7621_pci_probe(struct platform_device *pdev)
 {
 	u32 mask;
-	unsigned long val = 0;
+	u32 val;
 
 	mt7621_pci_base = (void __iomem *)RALINK_PCI_BASE;
 	iomem_resource.start = 0;
@@ -446,14 +444,14 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 		bypass_pipe_rst();
 	set_phy_for_ssc();
 
-	read_config(0, 0, 0, 0x70c, &val);
-	printk("Port 0 N_FTS = %x\n", (unsigned int)val);
+	val = read_config(0, 0x70c);
+	printk("Port 0 N_FTS = %x\n", val);
 
-	read_config(0, 1, 0, 0x70c, &val);
-	printk("Port 1 N_FTS = %x\n", (unsigned int)val);
+	val= read_config(1, 0x70c);
+	printk("Port 1 N_FTS = %x\n", val);
 
-	read_config(0, 2, 0, 0x70c, &val);
-	printk("Port 2 N_FTS = %x\n", (unsigned int)val);
+	val = read_config(2, 0x70c);
+	printk("Port 2 N_FTS = %x\n", val);
 
 	rt_sysc_m32(0, RALINK_PCIE_RST, RALINK_RSTCTRL);
 	rt_sysc_m32(0x30, 2 << 4, SYSC_REG_SYSTEM_CONFIG1);
@@ -566,28 +564,28 @@ pcie(2/1/0) link status	pcie2_num	pcie1_num	pcie0_num
 
 	switch (pcie_link_status) {
 	case 7:
-		read_config(0, 2, 0, 0x4, &val);
-		write_config(0, 2, 0, 0x4, val|0x4);
-		read_config(0, 2, 0, 0x70c, &val);
+		val = read_config(2, 0x4);
+		write_config(2, 0x4, (val | 0x4));
+		val = read_config(2, 0x70c);
 		val &= ~(0xff)<<8;
 		val |= 0x50<<8;
-		write_config(0, 2, 0, 0x70c, val);
+		write_config(2, 0x70c, val);
 	case 3:
 	case 5:
 	case 6:
-		read_config(0, 1, 0, 0x4, &val);
-		write_config(0, 1, 0, 0x4, val|0x4);
-		read_config(0, 1, 0, 0x70c, &val);
+		val = read_config(1, 0x4);
+		write_config(1, 0x4, (val | 0x4));
+		val = read_config(1, 0x70c);
 		val &= ~(0xff)<<8;
 		val |= 0x50<<8;
-		write_config(0, 1, 0, 0x70c, val);
+		write_config(1, 0x70c, val);
 	default:
-		read_config(0, 0, 0, 0x4, &val);
-		write_config(0, 0, 0, 0x4, val|0x4); //bus master enable
-		read_config(0, 0, 0, 0x70c, &val);
+		val = read_config(0, 0x4);
+		write_config(0, 0x4, (val | 0x4)); //bus master enable
+		val = read_config(0, 0x70c);
 		val &= ~(0xff)<<8;
 		val |= 0x50<<8;
-		write_config(0, 0, 0, 0x70c, val);
+		write_config(0, 0x70c, val);
 	}
 
 	pci_load_of_ranges(&mt7621_controller, pdev->dev.of_node);
-- 
2.7.4

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[PATCH v2 08/18] staging: mt7621-pci: factor out mt7621_pci_enable_irqs and mt7621_pci_disable

[Sergio Paracuellos]

Driver probe function is a mess and need a very big refactor.
Factor out mt7621_pci_enable_irqs and mt7621_pci_disable to
handle interrupts if pci status is as expected. To get the correct
bits for each controller define a new 'pcie_controller_data'
including clk_en, rst, irq and offset fields. Controller number
will be the array index 'pcie_controllers' which subs the 'offsets'
array.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 120 ++++++++++++++++++--------------
 1 file changed, 67 insertions(+), 53 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 39efde1..7a8b97a 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -63,6 +63,8 @@
  * devices.
  */
 
+#define PCI_MAX_CONTROLLERS		3
+
 #define RALINK_PCIE0_CLK_EN		BIT(24)
 #define RALINK_PCIE1_CLK_EN		BIT(25)
 #define RALINK_PCIE2_CLK_EN		BIT(26)
@@ -74,24 +76,50 @@
 #define RALINK_PCIE0_RST		BIT(24)
 #define RALINK_PCIE1_RST		BIT(25)
 #define RALINK_PCIE2_RST		BIT(26)
+#define RALINK_PCIE0_IRQ		BIT(20)
+#define RALINK_PCIE1_IRQ		BIT(21)
+#define RALINK_PCIE2_IRQ		BIT(22)
 
 #define RALINK_PCI_PCICFG_ADDR		0x0000
 #define RALINK_PCI_PCIMSK_ADDR		0x000C
 #define RALINK_PCI_BASE	0xBE140000
 
+struct pcie_controller_data {
+	u32 offset;
+	u32 clk_en;
+	u32 rst;
+	u32 irq;
+};
 
-static u16 pcie_controller_offsets[] = {
-	0x2000, 0x3000, 0x4000,
+static struct pcie_controller_data pcie_controllers[] = {
+	{
+		.offset = 0x2000,
+		.clk_en = RALINK_PCIE0_CLK_EN,
+		.rst = RALINK_PCIE0_RST,
+		.irq = RALINK_PCIE0_IRQ,
+	},
+	{
+		.offset = 0x3000,
+		.clk_en = RALINK_PCIE1_CLK_EN,
+		.rst = RALINK_PCIE1_RST,
+		.irq = RALINK_PCIE1_IRQ,
+	},
+	{
+		.offset = 0x4000,
+		.clk_en = RALINK_PCIE2_CLK_EN,
+		.rst = RALINK_PCIE2_RST,
+		.irq = RALINK_PCIE2_IRQ,
+	},
 };
 
-#define RALINK_PCI_BAR0SETUP_ADDR(dev)	(pcie_controller_offsets[(dev)] + 0x0010)
-#define RALINK_PCI_IMBASEBAR0_ADDR(dev)	(pcie_controller_offsets[(dev)] + 0x0018)
-#define RALINK_PCI_ID(dev)		(pcie_controller_offsets[(dev)] + 0x0030)
-#define RALINK_PCI_CLASS(dev)		(pcie_controller_offsets[(dev)] + 0x0034)
-#define RALINK_PCI_SUBID(dev)		(pcie_controller_offsets[(dev)] + 0x0038)
-#define RALINK_PCI_STATUS(dev)		(pcie_controller_offsets[(dev)] + 0x0050)
-#define RALINK_PCI_DERR(dev)		(pcie_controller_offsets[(dev)] + 0x0060)
-#define RALINK_PCI_ECRC(dev)		(pcie_controller_offsets[(dev)] + 0x0064)
+#define RALINK_PCI_BAR0SETUP_ADDR(dev)	(pcie_controllers[(dev)].offset + 0x0010)
+#define RALINK_PCI_IMBASEBAR0_ADDR(dev)	(pcie_controllers[(dev)].offset + 0x0018)
+#define RALINK_PCI_ID(dev)		(pcie_controllers[(dev)].offset + 0x0030)
+#define RALINK_PCI_CLASS(dev)		(pcie_controllers[(dev)].offset + 0x0034)
+#define RALINK_PCI_SUBID(dev)		(pcie_controllers[(dev)].offset + 0x0038)
+#define RALINK_PCI_STATUS(dev)		(pcie_controllers[(dev)].offset + 0x0050)
+#define RALINK_PCI_DERR(dev)		(pcie_controllers[(dev)].offset + 0x0060)
+#define RALINK_PCI_ECRC(dev)		(pcie_controllers[(dev)].offset + 0x0064)
 
 #define RALINK_PCIEPHY_P0P1_CTL_OFFSET	0x9000
 #define RALINK_PCIEPHY_P2_CTL_OFFSET	0xA000
@@ -408,8 +436,32 @@ void setup_cm_memory_region(struct resource *mem_resource)
 	}
 }
 
+static void mt7621_pci_disable(u8 controller)
+{
+	mt7621_pcie_assert_sysrst(pcie_controllers[controller].rst);
+	rt_sysc_m32(pcie_controllers[controller].clk_en, 0, RALINK_CLKCFG1);
+	pcie_link_status &= ~(1 << controller);
+}
+
+static void mt7621_pci_enable_irqs(u8 controller)
+{
+	u32 mask;
+
+	if ((mt7621_pci_reg_read(RALINK_PCI_STATUS(controller)) & 0x1) == 0) {
+		printk("PCIE0 no card, disable it(RST&CLK)\n");
+		mt7621_pci_disable(controller);
+		return;
+	}
+
+	pcie_link_status |= (1 << controller);
+	mask = mt7621_pci_reg_read(RALINK_PCI_PCIMSK_ADDR);
+	mask |= pcie_controllers[controller].irq;
+	mt7621_pci_reg_write(mask, RALINK_PCI_PCIMSK_ADDR);
+}
+
 static int mt7621_pci_probe(struct platform_device *pdev)
 {
+	int i;
 	u32 mask;
 	u32 val;
 
@@ -419,11 +471,8 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 	ioport_resource.start = 0;
 	ioport_resource.end = ~0;
 
-	val = RALINK_PCIE0_RST;
-	val |= RALINK_PCIE1_RST;
-	val |= RALINK_PCIE2_RST;
-
-	mt7621_pcie_assert_sysrst(RALINK_PCIE0_RST | RALINK_PCIE1_RST | RALINK_PCIE2_RST);
+	val = (RALINK_PCIE0_RST | RALINK_PCIE1_RST | RALINK_PCIE2_RST);
+	mt7621_pcie_assert_sysrst(val);
 
 	*(unsigned int *)(0xbe000060) &= ~(0x3<<10 | 0x3<<3);
 	*(unsigned int *)(0xbe000060) |= 0x1<<10 | 0x1<<3;
@@ -434,10 +483,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 
 	mdelay(100);
 
-	val = RALINK_PCIE0_RST;
-	val |= RALINK_PCIE1_RST;
-	val |= RALINK_PCIE2_RST;
-
+	val = (RALINK_PCIE0_RST | RALINK_PCIE1_RST | RALINK_PCIE2_RST);
 	mt7621_pcie_deassert_sysrst(val);
 
 	if ((*(unsigned int *)(0xbe00000c)&0xFFFF) == 0x0101) // MT7621 E2
@@ -467,41 +513,9 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 	*(unsigned int *)(0xbe000620) |= 0x1<<19 | 0x1<<8 | 0x1<<7;		// set DATA
 	mdelay(1000);
 
-	if ((mt7621_pci_reg_read(RALINK_PCI_STATUS(0)) & 0x1) == 0) {
-		printk("PCIE0 no card, disable it(RST&CLK)\n");
-		mt7621_pcie_assert_sysrst(RALINK_PCIE0_RST);
-		rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
-		pcie_link_status &= ~(1<<0);
-	} else {
-		pcie_link_status |= 1<<0;
-		mask = mt7621_pci_reg_read(RALINK_PCI_PCIMSK_ADDR);
-		mask |= (1<<20); // enable pcie1 interrupt
-		mt7621_pci_reg_write(mask, RALINK_PCI_PCIMSK_ADDR);
-	}
 
-	if ((mt7621_pci_reg_read(RALINK_PCI_STATUS(1)) & 0x1) == 0) {
-		printk("PCIE1 no card, disable it(RST&CLK)\n");
-		mt7621_pcie_assert_sysrst(RALINK_PCIE1_RST);
-		rt_sysc_m32(RALINK_PCIE1_CLK_EN, 0, RALINK_CLKCFG1);
-		pcie_link_status &= ~(1<<1);
-	} else {
-		pcie_link_status |= 1<<1;
-		mask = mt7621_pci_reg_read(RALINK_PCI_PCIMSK_ADDR);
-		mask |= (1<<21); // enable pcie1 interrupt
-		mt7621_pci_reg_write(mask, RALINK_PCI_PCIMSK_ADDR);
-	}
-
-	if ((mt7621_pci_reg_read(RALINK_PCI_STATUS(2)) & 0x1) == 0) {
-		printk("PCIE2 no card, disable it(RST&CLK)\n");
-		mt7621_pcie_assert_sysrst(RALINK_PCIE2_RST);
-		rt_sysc_m32(RALINK_PCIE2_CLK_EN, 0, RALINK_CLKCFG1);
-		pcie_link_status &= ~(1<<2);
-	} else {
-		pcie_link_status |= 1<<2;
-		mask = mt7621_pci_reg_read(RALINK_PCI_PCIMSK_ADDR);
-		mask |= (1<<22); // enable pcie2 interrupt
-		mt7621_pci_reg_write(mask, RALINK_PCI_PCIMSK_ADDR);
-	}
+	for (i = 0; i < PCI_MAX_CONTROLLERS; i++)
+		mt7621_pci_enable_irqs(i);
 
 	if (pcie_link_status == 0)
 		return 0;
-- 
2.7.4

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[PATCH v2 09/18] staging: mt7621-pci: minor refactor in duplicated code

[Sergio Paracuellos]

Use a for loop to check pci port N_FTS in each controller.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 12 ++++--------
 1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 7a8b97a..f882d41 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -490,14 +490,10 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 		bypass_pipe_rst();
 	set_phy_for_ssc();
 
-	val = read_config(0, 0x70c);
-	printk("Port 0 N_FTS = %x\n", val);
-
-	val= read_config(1, 0x70c);
-	printk("Port 1 N_FTS = %x\n", val);
-
-	val = read_config(2, 0x70c);
-	printk("Port 2 N_FTS = %x\n", val);
+	for (i = 0; i < PCI_MAX_CONTROLLERS; i++) {
+		val = read_config(0, 0x70c);
+		printk("Port %d N_FTS = %x\n", i, val);
+	}
 
 	rt_sysc_m32(0, RALINK_PCIE_RST, RALINK_RSTCTRL);
 	rt_sysc_m32(0x30, 2 << 4, SYSC_REG_SYSTEM_CONFIG1);
-- 
2.7.4

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[PATCH v2 10/18] staging: mt7621-pci: factor out mt7621_pci_enable function

[Sergio Paracuellos]

Factor out mt7621_pci_enable function to avoid duplicate code
in driver probe function. This increase readability.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 36 ++++++++++++++-------------------
 1 file changed, 15 insertions(+), 21 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index f882d41..c41fc18 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -459,6 +459,15 @@ static void mt7621_pci_enable_irqs(u8 controller)
 	mt7621_pci_reg_write(mask, RALINK_PCI_PCIMSK_ADDR);
 }
 
+static void mt7621_pci_enable(u8 controller)
+{
+	/* open 7FFF:2G; ENABLE */
+	mt7621_pci_reg_write(0x7FFF0001, RALINK_PCI_BAR0SETUP_ADDR(controller));
+	mt7621_pci_reg_write(MEMORY_BASE, RALINK_PCI_IMBASEBAR0_ADDR(controller));
+	mt7621_pci_reg_write(0x06040001, RALINK_PCI_CLASS(controller));
+	printk("PCIE%d enabled\n", controller);
+}
+
 static int mt7621_pci_probe(struct platform_device *pdev)
 {
 	int i;
@@ -546,31 +555,16 @@ pcie(2/1/0) link status	pcie2_num	pcie1_num	pcie0_num
 	mt7621_pci_reg_write(RALINK_PCI_IO_MAP_BASE, RALINK_PCI_IOBASE);
 
 	//PCIe0
-	if ((pcie_link_status & 0x1) != 0) {
-		/* open 7FFF:2G; ENABLE */
-		mt7621_pci_reg_write(0x7FFF0001, RALINK_PCI_BAR0SETUP_ADDR(0));
-		mt7621_pci_reg_write(MEMORY_BASE, RALINK_PCI_IMBASEBAR0_ADDR(0));
-		mt7621_pci_reg_write(0x06040001, RALINK_PCI_CLASS(0));
-		printk("PCIE0 enabled\n");
-	}
+	if ((pcie_link_status & 0x1) != 0)
+		mt7621_pci_enable(0);
 
 	//PCIe1
-	if ((pcie_link_status & 0x2) != 0) {
-		/* open 7FFF:2G; ENABLE */
-		mt7621_pci_reg_write(0x7FFF0001, RALINK_PCI_BAR0SETUP_ADDR(1));
-		mt7621_pci_reg_write(MEMORY_BASE, RALINK_PCI_IMBASEBAR0_ADDR(1));
-		mt7621_pci_reg_write(0x06040001, RALINK_PCI_CLASS(1));
-		printk("PCIE1 enabled\n");
-	}
+	if ((pcie_link_status & 0x2) != 0)
+		mt7621_pci_enable(1);
 
 	//PCIe2
-	if ((pcie_link_status & 0x4) != 0) {
-		/* open 7FFF:2G; ENABLE */
-		mt7621_pci_reg_write(0x7FFF0001, RALINK_PCI_BAR0SETUP_ADDR(2));
-		mt7621_pci_reg_write(MEMORY_BASE, RALINK_PCI_IMBASEBAR0_ADDR(2));
-		mt7621_pci_reg_write(0x06040001, RALINK_PCI_CLASS(2));
-		printk("PCIE2 enabled\n");
-	}
+	if ((pcie_link_status & 0x4) != 0)
+		mt7621_pci_enable(2);
 
 	switch (pcie_link_status) {
 	case 7:
-- 
2.7.4

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[PATCH v2 11/18] staging: mt7621-pci: factor out mt7621_pci_configure function

[Sergio Paracuellos]

Factor out mt7621_pci_configure function to avoid a lot of
duplicated code in driver probe function.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 35 ++++++++++++++++-----------------
 1 file changed, 17 insertions(+), 18 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index c41fc18..5d56f84 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -468,6 +468,18 @@ static void mt7621_pci_enable(u8 controller)
 	printk("PCIE%d enabled\n", controller);
 }
 
+static void mt7621_pci_configure(u8 controller)
+{
+	u32 val;
+
+	val = read_config(controller, 0x4);
+	write_config(controller, 0x4, (val | 0x4));
+	val = read_config(controller, 0x70c);
+	val &= ~(0xff) << 8;
+	val |= 0x50 << 8;
+	write_config(controller, 0x70c, val);
+}
+
 static int mt7621_pci_probe(struct platform_device *pdev)
 {
 	int i;
@@ -568,28 +580,15 @@ pcie(2/1/0) link status	pcie2_num	pcie1_num	pcie0_num
 
 	switch (pcie_link_status) {
 	case 7:
-		val = read_config(2, 0x4);
-		write_config(2, 0x4, (val | 0x4));
-		val = read_config(2, 0x70c);
-		val &= ~(0xff)<<8;
-		val |= 0x50<<8;
-		write_config(2, 0x70c, val);
+		mt7621_pci_configure(2);
+		break;
 	case 3:
 	case 5:
 	case 6:
-		val = read_config(1, 0x4);
-		write_config(1, 0x4, (val | 0x4));
-		val = read_config(1, 0x70c);
-		val &= ~(0xff)<<8;
-		val |= 0x50<<8;
-		write_config(1, 0x70c, val);
+		mt7621_pci_configure(1);
+		break;
 	default:
-		val = read_config(0, 0x4);
-		write_config(0, 0x4, (val | 0x4)); //bus master enable
-		val = read_config(0, 0x70c);
-		val &= ~(0xff)<<8;
-		val |= 0x50<<8;
-		write_config(0, 0x70c, val);
+		mt7621_pci_configure(0);
 	}
 
 	pci_load_of_ranges(&mt7621_controller, pdev->dev.of_node);
-- 
2.7.4

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[PATCH v2 12/18] staging: mt7621-pci: add blank line between declarations and code statements

[Sergio Paracuellos]

There was a missing line between declarations and code statements in function
setup_cm_memory_region. this improves readability.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 5d56f84..5871e32 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -422,6 +422,7 @@ set_phy_for_ssc(void)
 void setup_cm_memory_region(struct resource *mem_resource)
 {
 	resource_size_t mask;
+
 	if (mips_cps_numiocu(0)) {
 		/* FIXME: hardware doesn't accept mask values with 1s after
 		 * 0s (e.g. 0xffef), so it would be great to warn if that's
-- 
2.7.4

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[PATCH v2 13/18] staging: mt7621-pci: remove unused preprocessor defines

[Sergio Paracuellos]

There are a lot of definitions that are not being used at all.
Just remove them cleaning the code a bit.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 20 ++------------------
 1 file changed, 2 insertions(+), 18 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 5871e32..114e831 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -116,10 +116,7 @@ static struct pcie_controller_data pcie_controllers[] = {
 #define RALINK_PCI_IMBASEBAR0_ADDR(dev)	(pcie_controllers[(dev)].offset + 0x0018)
 #define RALINK_PCI_ID(dev)		(pcie_controllers[(dev)].offset + 0x0030)
 #define RALINK_PCI_CLASS(dev)		(pcie_controllers[(dev)].offset + 0x0034)
-#define RALINK_PCI_SUBID(dev)		(pcie_controllers[(dev)].offset + 0x0038)
 #define RALINK_PCI_STATUS(dev)		(pcie_controllers[(dev)].offset + 0x0050)
-#define RALINK_PCI_DERR(dev)		(pcie_controllers[(dev)].offset + 0x0060)
-#define RALINK_PCI_ECRC(dev)		(pcie_controllers[(dev)].offset + 0x0064)
 
 #define RALINK_PCIEPHY_P0P1_CTL_OFFSET	0x9000
 #define RALINK_PCIEPHY_P2_CTL_OFFSET	0xA000
@@ -132,25 +129,12 @@ static struct pcie_controller_data pcie_controllers[] = {
 #define RALINK_GPIOMODE			0x60
 #define RALINK_PCIE_CLK_GEN		0x7c
 #define RALINK_PCIE_CLK_GEN1		0x80
-#define PPLL_CFG1			0x9c
-#define PPLL_DRV			0xa0
-/* SYSC_REG_SYSTEM_CONFIG1 bits */
-#define RALINK_PCI_HOST_MODE_EN		BIT(7)
-#define RALINK_PCIE_RC_MODE_EN		BIT(8)
+
 //RALINK_RSTCTRL bit
 #define RALINK_PCIE_RST			BIT(23)
-#define RALINK_PCI_RST			BIT(24)
-//RALINK_CLKCFG1 bit
-#define RALINK_PCI_CLK_EN		BIT(19)
-#define RALINK_PCIE_CLK_EN		BIT(21)
-//RALINK_GPIOMODE bit
-#define PCI_SLOTx2			BIT(11)
-#define PCI_SLOTx1			(2<<11)
-//MTK PCIE PLL bit
-#define PDRV_SW_SET			BIT(31)
-#define LC_CKDRVPD_			BIT(19)
 
 #define MEMORY_BASE 0x0
+
 static int pcie_link_status = 0;
 
 static void __iomem *mt7621_pci_base;
-- 
2.7.4

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[PATCH v2 14/18] staging: mt7621-pci: rename RALINK_PCI_CONFIG_DATA_VIRTUAL_REG definition

[Sergio Paracuellos]

RALINK_PCI_CONFIG_DATA_VIRTUAL_REG is a very long name and makes
lines to be very long when it is used. Rename it to a shorter one
RALINK_PCI_CONFIG_DATA.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 114e831..55b9342 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -70,7 +70,7 @@
 #define RALINK_PCIE2_CLK_EN		BIT(26)
 
 #define RALINK_PCI_CONFIG_ADDR		0x20
-#define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG	0x24
+#define RALINK_PCI_CONFIG_DATA		0x24
 #define RALINK_PCI_MEMBASE		0x0028
 #define RALINK_PCI_IOBASE		0x002C
 #define RALINK_PCIE0_RST		BIT(24)
@@ -180,7 +180,7 @@ pci_config_read(struct pci_bus *bus, unsigned int devfn,
 	u32 address;
 
 	address_reg = RALINK_PCI_CONFIG_ADDR;
-	data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
+	data_reg = RALINK_PCI_CONFIG_DATA;
 
 	address = (((where & 0xF00) >> 8) << 24) |
 		   mt7621_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
@@ -211,7 +211,7 @@ pci_config_write(struct pci_bus *bus, unsigned int devfn,
 	u32 address;
 
 	address_reg = RALINK_PCI_CONFIG_ADDR;
-	data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
+	data_reg = RALINK_PCI_CONFIG_DATA;
 
 	address = (((where & 0xF00) >> 8) << 24) |
 		   mt7621_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
@@ -253,7 +253,7 @@ read_config(unsigned int dev, u32 reg)
 	u32 address_reg, data_reg, address;
 
 	address_reg = RALINK_PCI_CONFIG_ADDR;
-	data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
+	data_reg = RALINK_PCI_CONFIG_DATA;
 	address = (((reg & 0xF00) >> 8) << 24) |
 		   mt7621_pci_get_cfgaddr(0, dev, 0, reg);
 	writel(address, mt7621_pci_base + address_reg);
@@ -266,7 +266,7 @@ write_config(unsigned int dev, u32 reg, u32 val)
 	u32 address_reg, data_reg, address;
 
 	address_reg = RALINK_PCI_CONFIG_ADDR;
-	data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
+	data_reg = RALINK_PCI_CONFIG_DATA;
 	address = (((reg & 0xF00) >> 8) << 24) |
 		   mt7621_pci_get_cfgaddr(0, dev, 0, reg);
 	writel(address, mt7621_pci_base + address_reg);
-- 
2.7.4

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[PATCH v2 15/18] staging: mt7621-pci: add some common calculations to mt7621_pci_get_cfgaddr

[Sergio Paracuellos]

In places where function mt7621_pci_get_cfgaddr is being used, there
is a common pattern that could be included inside mt7621_pci_get_cfgaddr.
Include it improving readability.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 20 ++++++++------------
 1 file changed, 8 insertions(+), 12 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 55b9342..6286762 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -168,8 +168,8 @@ static void mt7621_pci_reg_write(u32 val, u32 reg)
 static inline u32 mt7621_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
 					 unsigned int func, unsigned int where)
 {
-	return ((bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) |
-		0x80000000);
+	return ((((where & 0xF00) >> 8) << 24) | (bus << 16) | (slot << 11) |
+		(func << 8) | (where & 0xfc) | 0x80000000);
 }
 
 static int
@@ -182,9 +182,8 @@ pci_config_read(struct pci_bus *bus, unsigned int devfn,
 	address_reg = RALINK_PCI_CONFIG_ADDR;
 	data_reg = RALINK_PCI_CONFIG_DATA;
 
-	address = (((where & 0xF00) >> 8) << 24) |
-		   mt7621_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
-					  PCI_FUNC(devfn), where);
+	address = mt7621_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
+					 PCI_FUNC(devfn), where);
 
 	writel(address, mt7621_pci_base + address_reg);
 
@@ -213,9 +212,8 @@ pci_config_write(struct pci_bus *bus, unsigned int devfn,
 	address_reg = RALINK_PCI_CONFIG_ADDR;
 	data_reg = RALINK_PCI_CONFIG_DATA;
 
-	address = (((where & 0xF00) >> 8) << 24) |
-		   mt7621_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
-					  PCI_FUNC(devfn), where);
+	address = mt7621_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
+					 PCI_FUNC(devfn), where);
 
 	writel(address, mt7621_pci_base + address_reg);
 
@@ -254,8 +252,7 @@ read_config(unsigned int dev, u32 reg)
 
 	address_reg = RALINK_PCI_CONFIG_ADDR;
 	data_reg = RALINK_PCI_CONFIG_DATA;
-	address = (((reg & 0xF00) >> 8) << 24) |
-		   mt7621_pci_get_cfgaddr(0, dev, 0, reg);
+	address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
 	writel(address, mt7621_pci_base + address_reg);
 	return readl(mt7621_pci_base + data_reg);
 }
@@ -267,8 +264,7 @@ write_config(unsigned int dev, u32 reg, u32 val)
 
 	address_reg = RALINK_PCI_CONFIG_ADDR;
 	data_reg = RALINK_PCI_CONFIG_DATA;
-	address = (((reg & 0xF00) >> 8) << 24) |
-		   mt7621_pci_get_cfgaddr(0, dev, 0, reg);
+	address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
 	writel(address, mt7621_pci_base + address_reg);
 	writel(val, mt7621_pci_base + data_reg);
 }
-- 
2.7.4

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[PATCH v2 16/18] staging: mt7621-pci: fix and remove some comments

[Sergio Paracuellos]

There are some comments not needed at all. Remove them.
Adjust one comment to follow kernel style.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 6286762..87c8df4 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -130,7 +130,6 @@ static struct pcie_controller_data pcie_controllers[] = {
 #define RALINK_PCIE_CLK_GEN		0x7c
 #define RALINK_PCIE_CLK_GEN1		0x80
 
-//RALINK_RSTCTRL bit
 #define RALINK_PCIE_RST			BIT(23)
 
 #define MEMORY_BASE 0x0
@@ -282,8 +281,8 @@ pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 		printk("BAR0 at slot %d = %x\n", slot, val);
 	}
 
-	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14);  //configure cache line size 0x14
-	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xFF);  //configure latency timer 0x10
+	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14);
+	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xFF);
 	pci_read_config_word(dev, PCI_COMMAND, &cmd);
 	cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
 	pci_write_config_word(dev, PCI_COMMAND, cmd);
@@ -404,9 +403,11 @@ void setup_cm_memory_region(struct resource *mem_resource)
 	resource_size_t mask;
 
 	if (mips_cps_numiocu(0)) {
-		/* FIXME: hardware doesn't accept mask values with 1s after
+		/*
+	 	 * FIXME: hardware doesn't accept mask values with 1s after
 		 * 0s (e.g. 0xffef), so it would be great to warn if that's
-		 * about to happen */
+		 * about to happen
+		 */
 		mask = ~(mem_resource->end - mem_resource->start);
 
 		write_gcr_reg1_base(mem_resource->start);
-- 
2.7.4

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[PATCH v2 17/18] staging: mt7621-pci: factor out mt7621_pci_init_gpios function

[Sergio Paracuellos]

In driver probe function there are some ugly initialization to
use gpios. Factor out to mt7621_pci_init_gpios function making
use of readl and writel to read and write memory.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 35 +++++++++++++++++++++++----------
 1 file changed, 25 insertions(+), 10 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 87c8df4..b4e049a 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -462,6 +462,26 @@ static void mt7621_pci_configure(u8 controller)
 	write_config(controller, 0x70c, val);
 }
 
+static void mt7621_pci_init_gpios(void)
+{
+	u32 val = readl((u32 *)0xbe000060);
+
+	val &= ~(0x3 << 10 | 0x3 << 3);
+	val |= (0x1 << 10 | 0x1 << 3);
+	writel(val, (u32 *)0xbe000060);
+	mdelay(100);
+	val = readl((u32 *)0xbe000600);
+	/* use GPIO19/GPIO8/GPIO7 (PERST_N/UART_RXD3/UART_TXD3) */
+	val |= (0x1 << 19 | 0x1 << 8 | 0x1 << 7);
+	writel(val, (u32 *)0xbe000600);
+	mdelay(100);
+	val = readl((u32 *)0xbe000620);
+	/* clear DATA */
+	val &= ~(0x1 << 19 | 0x1 << 8 | 0x1 << 7);
+	writel(val, (u32 *)0xbe000620);
+	mdelay(100);
+}
+
 static int mt7621_pci_probe(struct platform_device *pdev)
 {
 	int i;
@@ -477,14 +497,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 	val = (RALINK_PCIE0_RST | RALINK_PCIE1_RST | RALINK_PCIE2_RST);
 	mt7621_pcie_assert_sysrst(val);
 
-	*(unsigned int *)(0xbe000060) &= ~(0x3<<10 | 0x3<<3);
-	*(unsigned int *)(0xbe000060) |= 0x1<<10 | 0x1<<3;
-	mdelay(100);
-	*(unsigned int *)(0xbe000600) |= 0x1<<19 | 0x1<<8 | 0x1<<7; // use GPIO19/GPIO8/GPIO7 (PERST_N/UART_RXD3/UART_TXD3)
-	mdelay(100);
-	*(unsigned int *)(0xbe000620) &= ~(0x1<<19 | 0x1<<8 | 0x1<<7);		// clear DATA
-
-	mdelay(100);
+	mt7621_pci_init_gpios();
 
 	val = (RALINK_PCIE0_RST | RALINK_PCIE1_RST | RALINK_PCIE2_RST);
 	mt7621_pcie_deassert_sysrst(val);
@@ -509,10 +522,12 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 	rt_sysc_m32(RALINK_PCIE_RST, 0, RALINK_RSTCTRL);
 
 	/* Use GPIO control instead of PERST_N */
-	*(unsigned int *)(0xbe000620) |= 0x1<<19 | 0x1<<8 | 0x1<<7;		// set DATA
+	val = readl((u32 *)0xbe000620);
+	/* set DATA */
+	val |= (0x1 << 19 | 0x1 << 8 | 0x1 << 7);
+	writel(val, (u32 *)0xbe000620);
 	mdelay(1000);
 
-
 	for (i = 0; i < PCI_MAX_CONTROLLERS; i++)
 		mt7621_pci_enable_irqs(i);
 
-- 
2.7.4

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[PATCH v2 18/18] staging: mt7621-pci: add SPDX identifier

[Sergio Paracuellos]

It's good to have SPDX identifiers in driver files to make it easier to
audit the kernel tree for correct licenses.

Fix up the one of staging pci-mt7621.c file to have a proper SPDX
identifier, based on the license text in the file itself. The SPDX
identifier is a legally binding shorthand, which can be used instead of
the full boiler plate text.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 28 ++--------------------------
 1 file changed, 2 insertions(+), 26 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index b4e049a..d92df91 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -1,32 +1,10 @@
-/**************************************************************************
- *
+// SPDX-License-Identifier: GPL-2.0
+/*
  *  BRIEF MODULE DESCRIPTION
  *     PCI init for Ralink RT2880 solution
  *
  *  Copyright 2007 Ralink Inc. (bruce_chang@ralinktech.com.tw)
  *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- *
- *
- **************************************************************************
  * May 2007 Bruce Chang
  * Initial Release
  *
@@ -35,8 +13,6 @@
  *
  * May 2011 Bruce Chang
  * support RT6855/MT7620 PCIe
- *
- **************************************************************************
  */
 
 #include <linux/bitops.h>
-- 
2.7.4

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Re: [PATCH v2 00/18] Some cleanups

[Greg KH]

On Sun, Jul 08, 2018 at 02:57:08PM +0200, Sergio Paracuellos wrote:
> This patch series clean up a bit mt7621-pci driver.

Your subject line for the 00/XX email needs some work (like putting what
driver and subsystem it is for in it please...)

For future patch series.

thanks,

greg k-h
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Re: [PATCH v2 18/18] staging: mt7621-pci: add SPDX identifier

[Greg KH]

On Sun, Jul 08, 2018 at 02:57:26PM +0200, Sergio Paracuellos wrote:
> It's good to have SPDX identifiers in driver files to make it easier to
> audit the kernel tree for correct licenses.
> 
> Fix up the one of staging pci-mt7621.c file to have a proper SPDX
> identifier, based on the license text in the file itself. The SPDX
> identifier is a legally binding shorthand, which can be used instead of
> the full boiler plate text.
> 
> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
> ---
>  drivers/staging/mt7621-pci/pci-mt7621.c | 28 ++--------------------------
>  1 file changed, 2 insertions(+), 26 deletions(-)
> 
> diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
> index b4e049a..d92df91 100644
> --- a/drivers/staging/mt7621-pci/pci-mt7621.c
> +++ b/drivers/staging/mt7621-pci/pci-mt7621.c
> @@ -1,32 +1,10 @@
> -/**************************************************************************
> - *
> +// SPDX-License-Identifier: GPL-2.0

Ok, but:

> - *  This program is free software; you can redistribute  it and/or modify it
> - *  under  the terms of  the GNU General  Public License as published by the
> - *  Free Software Foundation;  either version 2 of the  License, or (at your
> - *  option) any later version.

You used the wrong license for the SPDX line :(

PLEASE be careful about this, it matters as it is a legal thing you are
dealing with.

If you don't know how to read licenses, just leave it all alone and do
not guess.

greg k-h
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Re: [PATCH v2 00/18] Some cleanups

[Sergio Paracuellos]

On Sun, Jul 8, 2018 at 3:14 PM, Greg KH <gregkh@linuxfoundation.org> wrote:
> On Sun, Jul 08, 2018 at 02:57:08PM +0200, Sergio Paracuellos wrote:
>> This patch series clean up a bit mt7621-pci driver.
>
> Your subject line for the 00/XX email needs some work (like putting what
> driver and subsystem it is for in it please...)

Sorry Greg, I miss that in the cover letter :-(.

>
> For future patch series.

I'll be more careful from now.
>
> thanks,
>
> greg k-h


Best regards,
    Sergio Paracuellos
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Re: [PATCH v2 18/18] staging: mt7621-pci: add SPDX identifier

[Sergio Paracuellos]

On Sun, Jul 8, 2018 at 3:16 PM, Greg KH <gregkh@linuxfoundation.org> wrote:
> On Sun, Jul 08, 2018 at 02:57:26PM +0200, Sergio Paracuellos wrote:
>> It's good to have SPDX identifiers in driver files to make it easier to
>> audit the kernel tree for correct licenses.
>>
>> Fix up the one of staging pci-mt7621.c file to have a proper SPDX
>> identifier, based on the license text in the file itself. The SPDX
>> identifier is a legally binding shorthand, which can be used instead of
>> the full boiler plate text.
>>
>> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
>> ---
>>  drivers/staging/mt7621-pci/pci-mt7621.c | 28 ++--------------------------
>>  1 file changed, 2 insertions(+), 26 deletions(-)
>>
>> diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
>> index b4e049a..d92df91 100644
>> --- a/drivers/staging/mt7621-pci/pci-mt7621.c
>> +++ b/drivers/staging/mt7621-pci/pci-mt7621.c
>> @@ -1,32 +1,10 @@
>> -/**************************************************************************
>> - *
>> +// SPDX-License-Identifier: GPL-2.0
>
> Ok, but:
>
>> - *  This program is free software; you can redistribute  it and/or modify it
>> - *  under  the terms of  the GNU General  Public License as published by the
>> - *  Free Software Foundation;  either version 2 of the  License, or (at your
>> - *  option) any later version.
>
> You used the wrong license for the SPDX line :(
>
> PLEASE be careful about this, it matters as it is a legal thing you are
> dealing with.

I see. Sorry I misunderstood the "any later version" part. So I
suppose the correct
line should be GPL-2.0+.

>
> If you don't know how to read licenses, just leave it all alone and do
> not guess.

Skip this in the series, please. I will send the proper one in next cleanups.

>
> greg k-h

Best regards,
    Sergio Paracuellos
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Re: [PATCH v2 18/18] staging: mt7621-pci: add SPDX identifier

[Greg KH]

On Sun, Jul 08, 2018 at 04:06:08PM +0200, Sergio Paracuellos wrote:
> On Sun, Jul 8, 2018 at 3:16 PM, Greg KH <gregkh@linuxfoundation.org> wrote:
> > On Sun, Jul 08, 2018 at 02:57:26PM +0200, Sergio Paracuellos wrote:
> >> It's good to have SPDX identifiers in driver files to make it easier to
> >> audit the kernel tree for correct licenses.
> >>
> >> Fix up the one of staging pci-mt7621.c file to have a proper SPDX
> >> identifier, based on the license text in the file itself. The SPDX
> >> identifier is a legally binding shorthand, which can be used instead of
> >> the full boiler plate text.
> >>
> >> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
> >> ---
> >>  drivers/staging/mt7621-pci/pci-mt7621.c | 28 ++--------------------------
> >>  1 file changed, 2 insertions(+), 26 deletions(-)
> >>
> >> diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
> >> index b4e049a..d92df91 100644
> >> --- a/drivers/staging/mt7621-pci/pci-mt7621.c
> >> +++ b/drivers/staging/mt7621-pci/pci-mt7621.c
> >> @@ -1,32 +1,10 @@
> >> -/**************************************************************************
> >> - *
> >> +// SPDX-License-Identifier: GPL-2.0
> >
> > Ok, but:
> >
> >> - *  This program is free software; you can redistribute  it and/or modify it
> >> - *  under  the terms of  the GNU General  Public License as published by the
> >> - *  Free Software Foundation;  either version 2 of the  License, or (at your
> >> - *  option) any later version.
> >
> > You used the wrong license for the SPDX line :(
> >
> > PLEASE be careful about this, it matters as it is a legal thing you are
> > dealing with.
> 
> I see. Sorry I misunderstood the "any later version" part. So I
> suppose the correct line should be GPL-2.0+.

Don't "suppose" when dealing with legal issues.  Please leave these
types of changes to the type of people who know licenses and the issues
surrounding them.

thanks,

greg k-h
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Re: [PATCH v2 18/18] staging: mt7621-pci: add SPDX identifier

[Sergio Paracuellos]

On Sun, Jul 8, 2018 at 4:22 PM, Greg KH <gregkh@linuxfoundation.org> wrote:
> On Sun, Jul 08, 2018 at 04:06:08PM +0200, Sergio Paracuellos wrote:
>> On Sun, Jul 8, 2018 at 3:16 PM, Greg KH <gregkh@linuxfoundation.org> wrote:
>> > On Sun, Jul 08, 2018 at 02:57:26PM +0200, Sergio Paracuellos wrote:
>> >> It's good to have SPDX identifiers in driver files to make it easier to
>> >> audit the kernel tree for correct licenses.
>> >>
>> >> Fix up the one of staging pci-mt7621.c file to have a proper SPDX
>> >> identifier, based on the license text in the file itself. The SPDX
>> >> identifier is a legally binding shorthand, which can be used instead of
>> >> the full boiler plate text.
>> >>
>> >> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
>> >> ---
>> >>  drivers/staging/mt7621-pci/pci-mt7621.c | 28 ++--------------------------
>> >>  1 file changed, 2 insertions(+), 26 deletions(-)
>> >>
>> >> diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
>> >> index b4e049a..d92df91 100644
>> >> --- a/drivers/staging/mt7621-pci/pci-mt7621.c
>> >> +++ b/drivers/staging/mt7621-pci/pci-mt7621.c
>> >> @@ -1,32 +1,10 @@
>> >> -/**************************************************************************
>> >> - *
>> >> +// SPDX-License-Identifier: GPL-2.0
>> >
>> > Ok, but:
>> >
>> >> - *  This program is free software; you can redistribute  it and/or modify it
>> >> - *  under  the terms of  the GNU General  Public License as published by the
>> >> - *  Free Software Foundation;  either version 2 of the  License, or (at your
>> >> - *  option) any later version.
>> >
>> > You used the wrong license for the SPDX line :(
>> >
>> > PLEASE be careful about this, it matters as it is a legal thing you are
>> > dealing with.
>>
>> I see. Sorry I misunderstood the "any later version" part. So I
>> suppose the correct line should be GPL-2.0+.
>
> Don't "suppose" when dealing with legal issues.  Please leave these
> types of changes to the type of people who know licenses and the issues
> surrounding them.

Ok, I will. Thanks for pointing this out. Sorry for inconvenience and noise.

>
> thanks,
>
> greg k-h

Best regards,
    Sergio Paracuellos
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Re: [PATCH v2 03/18] staging: mt7621-pci: avoid pointer arithmetics in some macros

[NeilBrown]

[-- Attachment #1: Type: text/plain, Size: 6082 bytes --]

On Sun, Jul 08 2018, Sergio Paracuellos wrote:

> RALINK_PCI_MEMBASE, RALINK_PCI_IOBASE, RALINK_PCI_PCICFG_ADDR and
> RALINK_PCI_PCIMSK_ADDR are using very ugly pointer arithmetics to
> read and write along the code. Instead of doing this, use the
> mt7621_pci_reg_read and mt7621_pci_reg_write functions making
> this a bit cleaner.
>
> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
> ---
>  drivers/staging/mt7621-pci/pci-mt7621.c | 59 ++++++++++++++-------------------
>  1 file changed, 25 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
> index 32c37e8..f7defa7 100644
> --- a/drivers/staging/mt7621-pci/pci-mt7621.c
> +++ b/drivers/staging/mt7621-pci/pci-mt7621.c
> @@ -68,14 +68,14 @@
>  
>  #define RALINK_PCI_CONFIG_ADDR		0x20
>  #define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG	0x24
> -#define RALINK_PCI_MEMBASE		*(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
> -#define RALINK_PCI_IOBASE		*(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
> +#define RALINK_PCI_MEMBASE		0x0028
> +#define RALINK_PCI_IOBASE		0x002C
>  #define RALINK_PCIE0_RST		(1<<24)
>  #define RALINK_PCIE1_RST		(1<<25)
>  #define RALINK_PCIE2_RST		(1<<26)
>  
> -#define RALINK_PCI_PCICFG_ADDR		*(volatile u32 *)(RALINK_PCI_BASE + 0x0000)
> -#define RALINK_PCI_PCIMSK_ADDR		*(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
> +#define RALINK_PCI_PCICFG_ADDR		0x0000
> +#define RALINK_PCI_PCIMSK_ADDR		0x000C
>  #define RALINK_PCI_BASE	0xBE140000
>  
>  #define RALINK_PCIEPHY_P0P1_CTL_OFFSET	(RALINK_PCI_BASE + 0x9000)
> @@ -408,6 +408,7 @@ void setup_cm_memory_region(struct resource *mem_resource)
>  
>  static int mt7621_pci_probe(struct platform_device *pdev)
>  {
> +	u32 mask;
>  	unsigned long val = 0;
>  
>  	mt7621_pci_base = (void __iomem *)RALINK_PCI_BASE;
> @@ -471,7 +472,9 @@ static int mt7621_pci_probe(struct platform_device *pdev)
>  		pcie_link_status &= ~(1<<0);
>  	} else {
>  		pcie_link_status |= 1<<0;
> -		RALINK_PCI_PCIMSK_ADDR |= (1<<20); // enable pcie1 interrupt
> +		mask = mt7621_pci_reg_read(RALINK_PCI_PCIMSK_ADDR);
> +		mask |= (1<<20); // enable pcie1 interrupt
> +		mt7621_pci_reg_write(mask, RALINK_PCI_PCIMSK_ADDR);
>  	}
>  
>  	if ((mt7621_pci_reg_read(RALINK_PCI_STATUS(1)) & 0x1) == 0) {
> @@ -481,7 +484,9 @@ static int mt7621_pci_probe(struct platform_device *pdev)
>  		pcie_link_status &= ~(1<<1);
>  	} else {
>  		pcie_link_status |= 1<<1;
> -		RALINK_PCI_PCIMSK_ADDR |= (1<<21); // enable pcie1 interrupt
> +		mask = mt7621_pci_reg_read(RALINK_PCI_PCIMSK_ADDR);
> +		mask |= (1<<21); // enable pcie1 interrupt
> +		mt7621_pci_reg_write(mask, RALINK_PCI_PCIMSK_ADDR);
>  	}
>  
>  	if ((mt7621_pci_reg_read(RALINK_PCI_STATUS(2)) & 0x1) == 0) {
> @@ -491,7 +496,9 @@ static int mt7621_pci_probe(struct platform_device *pdev)
>  		pcie_link_status &= ~(1<<2);
>  	} else {
>  		pcie_link_status |= 1<<2;
> -		RALINK_PCI_PCIMSK_ADDR |= (1<<22); // enable pcie2 interrupt
> +		mask = mt7621_pci_reg_read(RALINK_PCI_PCIMSK_ADDR);
> +		mask |= (1<<22); // enable pcie2 interrupt
> +		mt7621_pci_reg_write(mask, RALINK_PCI_PCIMSK_ADDR);
>  	}
>  
>  	if (pcie_link_status == 0)
> @@ -508,39 +515,23 @@ pcie(2/1/0) link status	pcie2_num	pcie1_num	pcie0_num
>  3'b110			1		0		x
>  3'b111			2		1		0
>  */
> -	switch (pcie_link_status) {
> -	case 2:
> -		RALINK_PCI_PCICFG_ADDR &= ~0x00ff0000;
> -		RALINK_PCI_PCICFG_ADDR |= 0x1 << 16;	//port0
> -		RALINK_PCI_PCICFG_ADDR |= 0x0 << 20;	//port1
> -		break;
> -	case 4:
> -		RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
> -		RALINK_PCI_PCICFG_ADDR |= 0x1 << 16;	//port0
> -		RALINK_PCI_PCICFG_ADDR |= 0x2 << 20;	//port1
> -		RALINK_PCI_PCICFG_ADDR |= 0x0 << 24;	//port2
> -		break;
> -	case 5:
> -		RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
> -		RALINK_PCI_PCICFG_ADDR |= 0x0 << 16;	//port0
> -		RALINK_PCI_PCICFG_ADDR |= 0x2 << 20;	//port1
> -		RALINK_PCI_PCICFG_ADDR |= 0x1 << 24;	//port2
> -		break;
> -	case 6:
> -		RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
> -		RALINK_PCI_PCICFG_ADDR |= 0x2 << 16;	//port0
> -		RALINK_PCI_PCICFG_ADDR |= 0x0 << 20;	//port1
> -		RALINK_PCI_PCICFG_ADDR |= 0x1 << 24;	//port2
> -		break;
> -	}
> +	mask = mt7621_pci_reg_read(RALINK_PCI_PCICFG_ADDR);
> +	mask &= ~0x00ff0000;
> +	mask |= (0x1 << 16); // port0
> +	mask |= (0x0 << 20); // port1
> +
> +	if (pcie_link_status != 2)
> +		mask |= (0x1 << 24); // port2
> +
> +	mt7621_pci_reg_write(mask, RALINK_PCI_PCICFG_ADDR);

You've discarded the switch statement, and not replaced much of it.
There were two different masks applied to RALINK_PCI_CFG_ADDR (one with
2 'f's, one with 3) but you now only have the one with ff.
The values <<16 is sometimes 0, sometimes 1, sometimes 2. etc.

I think you really need that switch statement back.

Below is what I'm working with

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index d92df914b16f..3d4c0fa27481 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -522,12 +522,33 @@ pcie(2/1/0) link status	pcie2_num	pcie1_num	pcie0_num
 3'b111			2		1		0
 */
 	mask = mt7621_pci_reg_read(RALINK_PCI_PCICFG_ADDR);
-	mask &= ~0x00ff0000;
-	mask |= (0x1 << 16); // port0
-	mask |= (0x0 << 20); // port1
+	switch (pcie_link_status) {
+	case 2:
+		mask &= ~0x00ff0000;
+		mask |= (0x1 << 16); // port0
+		mask |= (0x0 << 20); // port1
+		break;
 
-	if (pcie_link_status != 2)
+	case 4:
+		mask &= ~0x0fff0000;
+		mask |= (0x1 << 16); // port0
+		mask |= (0x2 << 20); // port1
+		break;
+
+	case 5:
+		mask &= ~0x0fff0000;
+		mask |= (0x0 << 16); // port0
+		mask |= (0x2 << 20); // port1
 		mask |= (0x1 << 24); // port2
+		break;
+
+	case 6:
+		mask &= ~0x0fff0000;
+		mask |= (0x2 << 16); // port0
+		mask |= (0x0 << 20); // port1
+		mask |= (0x1 << 24); // port2
+		break;
+	}
 
 	mt7621_pci_reg_write(mask, RALINK_PCI_PCICFG_ADDR);
 

Thanks,
NeilBrown

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Re: [PATCH v2 00/18] Some cleanups

[NeilBrown]

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On Sun, Jul 08 2018, Sergio Paracuellos wrote:

> This patch series clean up a bit mt7621-pci driver.
>
> Changes from v2:
>     - It includes new 17 patches from PATCH 2 to PATCH 18
>     - PATCH 1 was send before alone and is being included
>       as it is in this new series.
>
> Hope this helps.

Thanks,
I haven't looked though the patches yet, only tested them.
With the two fixed to pinctrl that I posted together
with the change to "avoid pointer arithmetics in some macros"
in this series, they appear to work.  So

  Tested-by: NeilBrown <neil@brown.name>

I may actually look a them later.

Thanks,
NeilBrown

>
> Best regards,
>     Sergio Paracuellos
>
> Sergio Paracuellos (18):
>   staging: mt7621-pci: refactor pci related read and writes functions
>   staging: mt7621-pci: simplify pci dependant registers arithmetics
>   staging: mt7621-pci: avoid pointer arithmetics in some macros
>   staging: mt7621-pci: use BIT macro in definitions
>   staging: mt7621-pci: use read and writes in set_pcie_phy function
>   staging: mt7621-pci: make ASSERT_SYSRST_PCIE and DEASSERT_SYSRST_PCIE
>     inline functions
>   staging: mt7621-pci: rewrite [read|write]_config functions
>   staging: mt7621-pci: factor out mt7621_pci_enable_irqs and
>     mt7621_pci_disable
>   staging: mt7621-pci: minor refactor in duplicated code
>   staging: mt7621-pci: factor out mt7621_pci_enable function
>   staging: mt7621-pci: factor out mt7621_pci_configure function
>   staging: mt7621-pci: add blank line between declarations and code
>     statements
>   staging: mt7621-pci: remove unused preprocessor defines
>   staging: mt7621-pci: rename RALINK_PCI_CONFIG_DATA_VIRTUAL_REG
>     definition
>   staging: mt7621-pci: add some common calculations to
>     mt7621_pci_get_cfgaddr
>   staging: mt7621-pci: fix and remove some comments
>   staging: mt7621-pci: factor out mt7621_pci_init_gpios function
>   staging: mt7621-pci: add SPDX identifier
>
>  drivers/staging/mt7621-pci/pci-mt7621.c | 706 ++++++++++++++------------------
>  1 file changed, 305 insertions(+), 401 deletions(-)
>
> -- 
> 2.7.4

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Re: [PATCH v2 03/18] staging: mt7621-pci: avoid pointer arithmetics in some macros

[Sergio Paracuellos]

On Mon, Jul 09, 2018 at 09:13:02AM +1000, NeilBrown wrote:
> On Sun, Jul 08 2018, Sergio Paracuellos wrote:
> 
> > RALINK_PCI_MEMBASE, RALINK_PCI_IOBASE, RALINK_PCI_PCICFG_ADDR and
> > RALINK_PCI_PCIMSK_ADDR are using very ugly pointer arithmetics to
> > read and write along the code. Instead of doing this, use the
> > mt7621_pci_reg_read and mt7621_pci_reg_write functions making
> > this a bit cleaner.
> >
> > Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
> > ---
> >  drivers/staging/mt7621-pci/pci-mt7621.c | 59 ++++++++++++++-------------------
> >  1 file changed, 25 insertions(+), 34 deletions(-)
> >
> > diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
> > index 32c37e8..f7defa7 100644
> > --- a/drivers/staging/mt7621-pci/pci-mt7621.c
> > +++ b/drivers/staging/mt7621-pci/pci-mt7621.c
> > @@ -68,14 +68,14 @@
> >  
> >  #define RALINK_PCI_CONFIG_ADDR		0x20
> >  #define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG	0x24
> > -#define RALINK_PCI_MEMBASE		*(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
> > -#define RALINK_PCI_IOBASE		*(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
> > +#define RALINK_PCI_MEMBASE		0x0028
> > +#define RALINK_PCI_IOBASE		0x002C
> >  #define RALINK_PCIE0_RST		(1<<24)
> >  #define RALINK_PCIE1_RST		(1<<25)
> >  #define RALINK_PCIE2_RST		(1<<26)
> >  
> > -#define RALINK_PCI_PCICFG_ADDR		*(volatile u32 *)(RALINK_PCI_BASE + 0x0000)
> > -#define RALINK_PCI_PCIMSK_ADDR		*(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
> > +#define RALINK_PCI_PCICFG_ADDR		0x0000
> > +#define RALINK_PCI_PCIMSK_ADDR		0x000C
> >  #define RALINK_PCI_BASE	0xBE140000
> >  
> >  #define RALINK_PCIEPHY_P0P1_CTL_OFFSET	(RALINK_PCI_BASE + 0x9000)
> > @@ -408,6 +408,7 @@ void setup_cm_memory_region(struct resource *mem_resource)
> >  
> >  static int mt7621_pci_probe(struct platform_device *pdev)
> >  {
> > +	u32 mask;
> >  	unsigned long val = 0;
> >  
> >  	mt7621_pci_base = (void __iomem *)RALINK_PCI_BASE;
> > @@ -471,7 +472,9 @@ static int mt7621_pci_probe(struct platform_device *pdev)
> >  		pcie_link_status &= ~(1<<0);
> >  	} else {
> >  		pcie_link_status |= 1<<0;
> > -		RALINK_PCI_PCIMSK_ADDR |= (1<<20); // enable pcie1 interrupt
> > +		mask = mt7621_pci_reg_read(RALINK_PCI_PCIMSK_ADDR);
> > +		mask |= (1<<20); // enable pcie1 interrupt
> > +		mt7621_pci_reg_write(mask, RALINK_PCI_PCIMSK_ADDR);
> >  	}
> >  
> >  	if ((mt7621_pci_reg_read(RALINK_PCI_STATUS(1)) & 0x1) == 0) {
> > @@ -481,7 +484,9 @@ static int mt7621_pci_probe(struct platform_device *pdev)
> >  		pcie_link_status &= ~(1<<1);
> >  	} else {
> >  		pcie_link_status |= 1<<1;
> > -		RALINK_PCI_PCIMSK_ADDR |= (1<<21); // enable pcie1 interrupt
> > +		mask = mt7621_pci_reg_read(RALINK_PCI_PCIMSK_ADDR);
> > +		mask |= (1<<21); // enable pcie1 interrupt
> > +		mt7621_pci_reg_write(mask, RALINK_PCI_PCIMSK_ADDR);
> >  	}
> >  
> >  	if ((mt7621_pci_reg_read(RALINK_PCI_STATUS(2)) & 0x1) == 0) {
> > @@ -491,7 +496,9 @@ static int mt7621_pci_probe(struct platform_device *pdev)
> >  		pcie_link_status &= ~(1<<2);
> >  	} else {
> >  		pcie_link_status |= 1<<2;
> > -		RALINK_PCI_PCIMSK_ADDR |= (1<<22); // enable pcie2 interrupt
> > +		mask = mt7621_pci_reg_read(RALINK_PCI_PCIMSK_ADDR);
> > +		mask |= (1<<22); // enable pcie2 interrupt
> > +		mt7621_pci_reg_write(mask, RALINK_PCI_PCIMSK_ADDR);
> >  	}
> >  
> >  	if (pcie_link_status == 0)
> > @@ -508,39 +515,23 @@ pcie(2/1/0) link status	pcie2_num	pcie1_num	pcie0_num
> >  3'b110			1		0		x
> >  3'b111			2		1		0
> >  */
> > -	switch (pcie_link_status) {
> > -	case 2:
> > -		RALINK_PCI_PCICFG_ADDR &= ~0x00ff0000;
> > -		RALINK_PCI_PCICFG_ADDR |= 0x1 << 16;	//port0
> > -		RALINK_PCI_PCICFG_ADDR |= 0x0 << 20;	//port1
> > -		break;
> > -	case 4:
> > -		RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
> > -		RALINK_PCI_PCICFG_ADDR |= 0x1 << 16;	//port0
> > -		RALINK_PCI_PCICFG_ADDR |= 0x2 << 20;	//port1
> > -		RALINK_PCI_PCICFG_ADDR |= 0x0 << 24;	//port2
> > -		break;
> > -	case 5:
> > -		RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
> > -		RALINK_PCI_PCICFG_ADDR |= 0x0 << 16;	//port0
> > -		RALINK_PCI_PCICFG_ADDR |= 0x2 << 20;	//port1
> > -		RALINK_PCI_PCICFG_ADDR |= 0x1 << 24;	//port2
> > -		break;
> > -	case 6:
> > -		RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
> > -		RALINK_PCI_PCICFG_ADDR |= 0x2 << 16;	//port0
> > -		RALINK_PCI_PCICFG_ADDR |= 0x0 << 20;	//port1
> > -		RALINK_PCI_PCICFG_ADDR |= 0x1 << 24;	//port2
> > -		break;
> > -	}
> > +	mask = mt7621_pci_reg_read(RALINK_PCI_PCICFG_ADDR);
> > +	mask &= ~0x00ff0000;
> > +	mask |= (0x1 << 16); // port0
> > +	mask |= (0x0 << 20); // port1
> > +
> > +	if (pcie_link_status != 2)
> > +		mask |= (0x1 << 24); // port2
> > +
> > +	mt7621_pci_reg_write(mask, RALINK_PCI_PCICFG_ADDR);
> 
> You've discarded the switch statement, and not replaced much of it.
> There were two different masks applied to RALINK_PCI_CFG_ADDR (one with
> 2 'f's, one with 3) but you now only have the one with ff.
> The values <<16 is sometimes 0, sometimes 1, sometimes 2. etc.
> 
> I think you really need that switch statement back.

My eyes said to my head all the mask were the same :-). You
are totally right I need the switch statement back. I'll
re-do this in a proper way.

Thanks,

> 
> Below is what I'm working with
> 
> diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
> index d92df914b16f..3d4c0fa27481 100644
> --- a/drivers/staging/mt7621-pci/pci-mt7621.c
> +++ b/drivers/staging/mt7621-pci/pci-mt7621.c
> @@ -522,12 +522,33 @@ pcie(2/1/0) link status	pcie2_num	pcie1_num	pcie0_num
>  3'b111			2		1		0
>  */
>  	mask = mt7621_pci_reg_read(RALINK_PCI_PCICFG_ADDR);
> -	mask &= ~0x00ff0000;
> -	mask |= (0x1 << 16); // port0
> -	mask |= (0x0 << 20); // port1
> +	switch (pcie_link_status) {
> +	case 2:
> +		mask &= ~0x00ff0000;
> +		mask |= (0x1 << 16); // port0
> +		mask |= (0x0 << 20); // port1
> +		break;
>  
> -	if (pcie_link_status != 2)
> +	case 4:
> +		mask &= ~0x0fff0000;
> +		mask |= (0x1 << 16); // port0
> +		mask |= (0x2 << 20); // port1
> +		break;
> +
> +	case 5:
> +		mask &= ~0x0fff0000;
> +		mask |= (0x0 << 16); // port0
> +		mask |= (0x2 << 20); // port1
>  		mask |= (0x1 << 24); // port2
> +		break;
> +
> +	case 6:
> +		mask &= ~0x0fff0000;
> +		mask |= (0x2 << 16); // port0
> +		mask |= (0x0 << 20); // port1
> +		mask |= (0x1 << 24); // port2
> +		break;
> +	}
>  
>  	mt7621_pci_reg_write(mask, RALINK_PCI_PCICFG_ADDR);
>  
> 
> Thanks,
> NeilBrown

Best regards,
    Sergio Paracuellos


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Re: [PATCH v2 00/18] Some cleanups

[Sergio Paracuellos]

On Mon, Jul 09, 2018 at 11:08:58AM +1000, NeilBrown wrote:
> On Sun, Jul 08 2018, Sergio Paracuellos wrote:
> 
> > This patch series clean up a bit mt7621-pci driver.
> >
> > Changes from v2:
> >     - It includes new 17 patches from PATCH 2 to PATCH 18
> >     - PATCH 1 was send before alone and is being included
> >       as it is in this new series.
> >
> > Hope this helps.
> 
> Thanks,
> I haven't looked though the patches yet, only tested them.
> With the two fixed to pinctrl that I posted together
> with the change to "avoid pointer arithmetics in some macros"
> in this series, they appear to work.  So
> 
>   Tested-by: NeilBrown <neil@brown.name>
> 
> I may actually look a them later.

Thanks for testing this. Greg, I think is still neccessary to split up
patch 1 for better reviewing. If not, please let me know. I'll
try to do that hopefully tonight.

> 
> Thanks,
> NeilBrown

Thanks for your effort and support, Neil.

Best regards,
    Sergio Paracuellos
> 
> >
> > Best regards,
> >     Sergio Paracuellos
> >
> > Sergio Paracuellos (18):
> >   staging: mt7621-pci: refactor pci related read and writes functions
> >   staging: mt7621-pci: simplify pci dependant registers arithmetics
> >   staging: mt7621-pci: avoid pointer arithmetics in some macros
> >   staging: mt7621-pci: use BIT macro in definitions
> >   staging: mt7621-pci: use read and writes in set_pcie_phy function
> >   staging: mt7621-pci: make ASSERT_SYSRST_PCIE and DEASSERT_SYSRST_PCIE
> >     inline functions
> >   staging: mt7621-pci: rewrite [read|write]_config functions
> >   staging: mt7621-pci: factor out mt7621_pci_enable_irqs and
> >     mt7621_pci_disable
> >   staging: mt7621-pci: minor refactor in duplicated code
> >   staging: mt7621-pci: factor out mt7621_pci_enable function
> >   staging: mt7621-pci: factor out mt7621_pci_configure function
> >   staging: mt7621-pci: add blank line between declarations and code
> >     statements
> >   staging: mt7621-pci: remove unused preprocessor defines
> >   staging: mt7621-pci: rename RALINK_PCI_CONFIG_DATA_VIRTUAL_REG
> >     definition
> >   staging: mt7621-pci: add some common calculations to
> >     mt7621_pci_get_cfgaddr
> >   staging: mt7621-pci: fix and remove some comments
> >   staging: mt7621-pci: factor out mt7621_pci_init_gpios function
> >   staging: mt7621-pci: add SPDX identifier
> >
> >  drivers/staging/mt7621-pci/pci-mt7621.c | 706 ++++++++++++++------------------
> >  1 file changed, 305 insertions(+), 401 deletions(-)
> >
> > -- 
> > 2.7.4

Re: [PATCH v2 00/18] Some cleanups

[Greg KH]

On Mon, Jul 09, 2018 at 06:41:15AM +0200, Sergio Paracuellos wrote:
> On Mon, Jul 09, 2018 at 11:08:58AM +1000, NeilBrown wrote:
> > On Sun, Jul 08 2018, Sergio Paracuellos wrote:
> > 
> > > This patch series clean up a bit mt7621-pci driver.
> > >
> > > Changes from v2:
> > >     - It includes new 17 patches from PATCH 2 to PATCH 18
> > >     - PATCH 1 was send before alone and is being included
> > >       as it is in this new series.
> > >
> > > Hope this helps.
> > 
> > Thanks,
> > I haven't looked though the patches yet, only tested them.
> > With the two fixed to pinctrl that I posted together
> > with the change to "avoid pointer arithmetics in some macros"
> > in this series, they appear to work.  So
> > 
> >   Tested-by: NeilBrown <neil@brown.name>
> > 
> > I may actually look a them later.
> 
> Thanks for testing this. Greg, I think is still neccessary to split up
> patch 1 for better reviewing. If not, please let me know. I'll
> try to do that hopefully tonight.

Yes please, I'll drop this series and wait for your next one.

thanks,

greg k-h
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Re: [PATCH v2 00/18] Some cleanups

[Sergio Paracuellos]

On Mon, Jul 09, 2018 at 09:38:59AM +0200, Greg KH wrote:
> On Mon, Jul 09, 2018 at 06:41:15AM +0200, Sergio Paracuellos wrote:
> > On Mon, Jul 09, 2018 at 11:08:58AM +1000, NeilBrown wrote:
> > > On Sun, Jul 08 2018, Sergio Paracuellos wrote:
> > > 
> > > > This patch series clean up a bit mt7621-pci driver.
> > > >
> > > > Changes from v2:
> > > >     - It includes new 17 patches from PATCH 2 to PATCH 18
> > > >     - PATCH 1 was send before alone and is being included
> > > >       as it is in this new series.
> > > >
> > > > Hope this helps.
> > > 
> > > Thanks,
> > > I haven't looked though the patches yet, only tested them.
> > > With the two fixed to pinctrl that I posted together
> > > with the change to "avoid pointer arithmetics in some macros"
> > > in this series, they appear to work.  So
> > > 
> > >   Tested-by: NeilBrown <neil@brown.name>
> > > 
> > > I may actually look a them later.
> > 
> > Thanks for testing this. Greg, I think is still neccessary to split up
> > patch 1 for better reviewing. If not, please let me know. I'll
> > try to do that hopefully tonight.
> 
> Yes please, I'll drop this series and wait for your next one.

Ok, thanks for let me know.
> 
> thanks,
> 
> greg k-h

Best regards,
    Sergio Paracuellos
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