From: Madhav Chauhan <madhav.chauhan@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: jani.nikula@intel.com, paulo.r.zanoni@intel.com, rodrigo.vivi@intel.com
Subject: [PATCH v5 12/13] drm/i915/icl: Define TRANS_DSI_FUNC_CONF register
Date: Tue, 10 Jul 2018 15:10:13 +0530 [thread overview]
Message-ID: <1531215614-6828-13-git-send-email-madhav.chauhan@intel.com> (raw)
In-Reply-To: <1531215614-6828-1-git-send-email-madhav.chauhan@intel.com>
This patch defines transcoder function configuration
registers and its bitfields for both DSI ports.
Used while programming/enabling DSI transcoder.
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 47 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 47 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 62bc76e..71ce6ba 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10134,6 +10134,53 @@ enum skl_power_gate {
#define TA_SURE_TIME(x) (x << 16)
#define TA_SURE_TIME_MASK (0x1f << 16)
+/* DSI transcoder configuration */
+#define _DSI_TRANS_FUNC_CONF_0 0x6b030
+#define _DSI_TRANS_FUNC_CONF_1 0x6b830
+#define DSI_TRANS_FUNC_CONF(tc) _MMIO_DSI(tc, \
+ _DSI_TRANS_FUNC_CONF_0,\
+ _DSI_TRANS_FUNC_CONF_1)
+#define OP_MODE(x) (x << 28)
+#define OP_MODE_MASK (0x3 << 28)
+#define CMD_MODE_NO_GATE 0x0
+#define CMD_MODE_TE_GATE 0x1
+#define VIDEO_MODE_SYNC_EVENT 0x2
+#define VIDEO_MODE_SYNC_PULSE 0x3
+#define LINK_READY (1 << 20)
+#define PIX_FMT(x) (x << 16)
+#define PIX_FMT_MASK (0x3 << 16)
+#define PIX_FMT_RGB565 0x0
+#define PIX_FMT_RGB666_PACKED 0x1
+#define PIX_FMT_RGB666_LOOSE 0x2
+#define PIX_FMT_RGB888 0x3
+#define PIX_FMT_RGB101010 0x4
+#define PIX_FMT_RGB121212 0x5
+#define PIX_FMT_COMPRESSED 0x6
+#define BGR_TRANSMISSION (1 << 15)
+#define PIX_VIRT_CHAN(x) (x << 12)
+#define PIX_VIRT_CHAN_MASK (0x3 << 12)
+#define PIX_BUF_THRESHOLD(x) ((x & 0x3) << 10)
+#define PIX_BUF_THRESHOLD_MASK (0x3 << 10)
+#define PIX_BUF_THRESHOLD_1_4 0x0
+#define PIX_BUF_THRESHOLD_1_2 0x1
+#define PIX_BUF_THRESHOLD_3_4 0x2
+#define PIX_BUF_THRESHOLD_FULL 0x3
+#define CONTINUOUS_CLK(x) (x << 8)
+#define CONTINUOUS_CLK_MASK (0x3 << 8)
+#define CLK_ENTER_LP_AFTER_DATA 0x0
+#define CLK_HS_OR_LP 0x2
+#define CLK_HS_CONTINUOUS 0x3
+#define LINK_CALIBRATION(x) (x << 4)
+#define LINK_CALIBRATION_MASK (0x3 << 4)
+#define CALIBRATION_DISABLED 0x0
+#define CALIBRATION_ENABLED_INITIAL_ONLY 0x2
+#define CALIBRATION_ENABLED_INITIAL_PERIODIC 0x3
+#define S3D_ORIENTATION(x) (x << 1)
+#define S3D_ORIENTATION_MASK (0x1 << 1)
+#define S3D_ORIENTATION_PORTRAIT 0x0
+#define S3D_ORIENTATION_LANDSCAPE 0x1
+#define EOTP_DISABLED (1 << 0)
+
/* bits 31:0 */
#define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084)
#define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884)
--
2.7.4
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next prev parent reply other threads:[~2018-07-10 9:50 UTC|newest]
Thread overview: 63+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-10 9:40 [PATCH v5 00/13] ICELAKE DSI DRIVER Madhav Chauhan
2018-07-10 9:40 ` [PATCH v5 01/13] drm/i915/icl: Configure lane sequencing of combo phy transmitter Madhav Chauhan
2018-07-19 16:11 ` Ville Syrjälä
2018-07-19 18:35 ` Chauhan, Madhav
2018-07-27 11:57 ` Chauhan, Madhav
2018-09-11 17:46 ` Jani Nikula
2018-09-12 6:32 ` Madhav Chauhan
2018-09-10 12:20 ` Lisovskiy, Stanislav
2018-09-10 15:27 ` Madhav Chauhan
2018-09-11 8:08 ` Lisovskiy, Stanislav
2018-07-10 9:40 ` [PATCH v5 02/13] drm/i915/icl: DSI vswing programming sequence Madhav Chauhan
2018-09-06 14:01 ` [v5, " Kulkarni, Vandita
2018-09-10 7:43 ` Madhav Chauhan
2018-09-11 18:16 ` Jani Nikula
2018-09-12 6:34 ` Madhav Chauhan
2018-09-11 18:50 ` [PATCH v5 " Jani Nikula
2018-09-12 9:03 ` Madhav Chauhan
2018-09-12 9:10 ` Jani Nikula
2018-07-10 9:40 ` [PATCH v5 03/13] drm/i915/icl: Enable DDI Buffer Madhav Chauhan
2018-09-11 18:54 ` Jani Nikula
2018-09-12 9:06 ` Madhav Chauhan
2018-09-12 9:10 ` Jani Nikula
2018-07-10 9:40 ` [PATCH v5 04/13] drm/i915/icl: Define T_INIT_MASTER registers Madhav Chauhan
2018-09-11 19:18 ` Jani Nikula
2018-07-10 9:40 ` [PATCH v5 05/13] drm/i915/icl: Program " Madhav Chauhan
2018-09-11 19:17 ` Jani Nikula
2018-07-10 9:40 ` [PATCH v5 06/13] drm/i915/icl: Define data/clock lanes dphy timing registers Madhav Chauhan
2018-09-11 19:14 ` Jani Nikula
2018-09-12 9:11 ` Madhav Chauhan
2018-07-10 9:40 ` [PATCH v5 07/13] drm/i915/icl: Program DSI clock and data lane timing params Madhav Chauhan
2018-07-19 16:17 ` Ville Syrjälä
2018-07-10 9:40 ` [PATCH v5 08/13] drm/i915/icl: Define TA_TIMING_PARAM registers Madhav Chauhan
2018-09-11 19:23 ` Jani Nikula
2018-09-12 9:13 ` Madhav Chauhan
2018-07-10 9:40 ` [PATCH v5 09/13] drm/i915/icl: Program " Madhav Chauhan
2018-07-19 16:21 ` Ville Syrjälä
2018-07-20 8:08 ` Chauhan, Madhav
2018-09-11 19:26 ` Jani Nikula
2018-09-12 9:25 ` Madhav Chauhan
2018-09-12 9:39 ` Jani Nikula
2018-07-10 9:40 ` [PATCH v5 10/13] drm/i915/icl: Get DSI transcoder for a given port Madhav Chauhan
2018-07-10 9:40 ` [PATCH v5 11/13] drm/i915/icl: Add macros for MMIO of DSI transcoder registers Madhav Chauhan
2018-07-19 16:22 ` Ville Syrjälä
2018-07-20 8:55 ` Chauhan, Madhav
2018-09-12 9:36 ` Madhav Chauhan
2018-09-12 18:00 ` Ville Syrjälä
2018-09-14 6:12 ` Madhav Chauhan
2018-09-14 12:25 ` Ville Syrjälä
2018-09-14 13:06 ` Madhav Chauhan
2018-09-14 13:27 ` Madhav Chauhan
2018-09-14 13:41 ` Ville Syrjälä
2018-07-10 9:40 ` Madhav Chauhan [this message]
2018-09-11 19:30 ` [PATCH v5 12/13] drm/i915/icl: Define TRANS_DSI_FUNC_CONF register Jani Nikula
2018-09-12 9:35 ` Madhav Chauhan
2018-09-12 9:47 ` Jani Nikula
2018-07-10 9:40 ` [PATCH v5 13/13] drm/i915/icl: Configure DSI transcoders Madhav Chauhan
2018-07-10 10:46 ` ✗ Fi.CI.CHECKPATCH: warning for ICELAKE DSI DRIVER (rev5) Patchwork
2018-07-10 10:51 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-07-10 11:04 ` ✓ Fi.CI.BAT: success " Patchwork
2018-07-10 16:28 ` ✓ Fi.CI.IGT: " Patchwork
2018-09-11 19:35 ` [PATCH v5 00/13] ICELAKE DSI DRIVER Jani Nikula
2018-09-12 6:16 ` Madhav Chauhan
2018-09-12 7:31 ` Jani Nikula
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