* [U-Boot] [PATCH 2/6] stm32mp1: clk: add common function pll_get_fvco
2018-07-16 8:41 [U-Boot] [PATCH 1/6] stm32mp1: clk: define RCC_PLLNCFGR2_SHIFT macro Patrick Delaunay
@ 2018-07-16 8:41 ` Patrick Delaunay
2018-07-20 22:36 ` [U-Boot] [U-Boot, " Tom Rini
2018-07-16 8:41 ` [U-Boot] [PATCH 3/6] stm32mp1: clk: add LDTC and DSI clock support Patrick Delaunay
` (5 subsequent siblings)
6 siblings, 1 reply; 13+ messages in thread
From: Patrick Delaunay @ 2018-07-16 8:41 UTC (permalink / raw)
To: u-boot
the function compute the VCO PLL freq, used in
- stm32mp1_read_pll_freq()
- pll_set_rate()
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
# Conflicts:
# drivers/clk/clk_stm32mp1.c
---
drivers/clk/clk_stm32mp1.c | 91 +++++++++++++++++++++++++++++++---------------
1 file changed, 61 insertions(+), 30 deletions(-)
diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c
index 5177758..710633f 100644
--- a/drivers/clk/clk_stm32mp1.c
+++ b/drivers/clk/clk_stm32mp1.c
@@ -808,56 +808,87 @@ static int stm32mp1_clk_get_parent(struct stm32mp1_clk_priv *priv,
return -EINVAL;
}
-static ulong stm32mp1_read_pll_freq(struct stm32mp1_clk_priv *priv,
- int pll_id, int div_id)
+static ulong pll_get_fref_ck(struct stm32mp1_clk_priv *priv,
+ int pll_id)
{
const struct stm32mp1_clk_pll *pll = priv->data->pll;
- int divm, divn, divy, src;
- ulong refclk, dfout;
- u32 selr, cfgr1, cfgr2, fracr;
-
- debug("%s(%d, %d)\n", __func__, pll_id, div_id);
- if (div_id > _DIV_NB)
- return 0;
+ u32 selr;
+ int src;
+ ulong refclk;
+ /* Get current refclk */
selr = readl(priv->base + pll[pll_id].rckxselr);
+ src = selr & RCC_SELR_SRC_MASK;
+
+ refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]);
+ debug("PLL%d : selr=%x refclk = %d kHz\n",
+ pll_id, selr, (u32)(refclk / 1000));
+
+ return refclk;
+}
+
+/*
+ * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL
+ * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1)
+ * - PLL3 & PLL4 => return VCO with Fpll_y_ck = FVCO / (DIVy + 1)
+ * => in all the case Fpll_y_ck = pll_get_fvco() / (DIVy + 1)
+ */
+static ulong pll_get_fvco(struct stm32mp1_clk_priv *priv,
+ int pll_id)
+{
+ const struct stm32mp1_clk_pll *pll = priv->data->pll;
+ int divm, divn;
+ ulong refclk, fvco;
+ u32 cfgr1, fracr;
+
cfgr1 = readl(priv->base + pll[pll_id].pllxcfgr1);
- cfgr2 = readl(priv->base + pll[pll_id].pllxcfgr2);
fracr = readl(priv->base + pll[pll_id].pllxfracr);
- debug("PLL%d : selr=%x cfgr1=%x cfgr2=%x fracr=%x\n",
- pll_id, selr, cfgr1, cfgr2, fracr);
-
divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT;
divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK;
- divy = (cfgr2 >> RCC_PLLNCFGR2_SHIFT(div_id)) & RCC_PLLNCFGR2_DIVX_MASK;
- debug(" DIVN=%d DIVM=%d DIVY=%d\n", divn, divm, divy);
+ debug("PLL%d : cfgr1=%x fracr=%x DIVN=%d DIVM=%d\n",
+ pll_id, cfgr1, fracr, divn, divm);
- src = selr & RCC_SELR_SRC_MASK;
- refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]);
+ refclk = pll_get_fref_ck(priv, pll_id);
- debug(" refclk = %d kHz\n", (u32)(refclk / 1000));
-
- /*
- * For: PLL1 & PLL2 => VCO is * 2 but ck_pll_y is also / 2
- * So same final result than PLL2 et 4
- * with FRACV :
- * Fck_pll_y = Fck_ref * ((DIVN + 1) + FRACV / 2^13)
- * / (DIVM + 1) * (DIVy + 1)
+ /* with FRACV :
+ * Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1)
* without FRACV
- * Fck_pll_y = Fck_ref * ((DIVN + 1) / (DIVM + 1) *(DIVy + 1)
+ * Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1)
*/
if (fracr & RCC_PLLNFRACR_FRACLE) {
u32 fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK)
>> RCC_PLLNFRACR_FRACV_SHIFT;
- dfout = (ulong)lldiv((unsigned long long)refclk *
+ fvco = (ulong)lldiv((unsigned long long)refclk *
(((divn + 1) << 13) + fracv),
- ((unsigned long long)(divm + 1) *
- (divy + 1)) << 13);
+ ((unsigned long long)(divm + 1)) << 13);
} else {
- dfout = (ulong)(refclk * (divn + 1) / (divm + 1) * (divy + 1));
+ fvco = (ulong)(refclk * (divn + 1) / (divm + 1));
}
+ debug("PLL%d : %s = %ld\n", pll_id, __func__, fvco);
+
+ return fvco;
+}
+
+static ulong stm32mp1_read_pll_freq(struct stm32mp1_clk_priv *priv,
+ int pll_id, int div_id)
+{
+ const struct stm32mp1_clk_pll *pll = priv->data->pll;
+ int divy;
+ ulong dfout;
+ u32 cfgr2;
+
+ debug("%s(%d, %d)\n", __func__, pll_id, div_id);
+ if (div_id >= _DIV_NB)
+ return 0;
+
+ cfgr2 = readl(priv->base + pll[pll_id].pllxcfgr2);
+ divy = (cfgr2 >> RCC_PLLNCFGR2_SHIFT(div_id)) & RCC_PLLNCFGR2_DIVX_MASK;
+
+ debug("PLL%d : cfgr2=%x DIVY=%d\n", pll_id, cfgr2, divy);
+
+ dfout = pll_get_fvco(priv, pll_id) / (divy + 1);
debug(" => dfout = %d kHz\n", (u32)(dfout / 1000));
return dfout;
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread* [U-Boot] [PATCH 3/6] stm32mp1: clk: add LDTC and DSI clock support
2018-07-16 8:41 [U-Boot] [PATCH 1/6] stm32mp1: clk: define RCC_PLLNCFGR2_SHIFT macro Patrick Delaunay
2018-07-16 8:41 ` [U-Boot] [PATCH 2/6] stm32mp1: clk: add common function pll_get_fvco Patrick Delaunay
@ 2018-07-16 8:41 ` Patrick Delaunay
2018-07-20 22:36 ` [U-Boot] [U-Boot, " Tom Rini
2018-07-16 8:41 ` [U-Boot] [PATCH 4/6] stm32mp1: clk: update Ethernet clock gating Patrick Delaunay
` (4 subsequent siblings)
6 siblings, 1 reply; 13+ messages in thread
From: Patrick Delaunay @ 2018-07-16 8:41 UTC (permalink / raw)
To: u-boot
This patch add clk_enable/clk_disable/clk_get_rate support for
- DSI_PX
- LTDC_PX
- DSI_K (only get rate)
These clocks are needed for LTDC and DSI drivers with latest device tree.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
---
drivers/clk/clk_stm32mp1.c | 96 ++++++++++++++++++++++++++++++++++++++++++++--
1 file changed, 93 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c
index 710633f..6202ebe 100644
--- a/drivers/clk/clk_stm32mp1.c
+++ b/drivers/clk/clk_stm32mp1.c
@@ -98,6 +98,7 @@
#define RCC_QSPICKSELR 0x900
#define RCC_FMCCKSELR 0x904
#define RCC_USBCKSELR 0x91C
+#define RCC_DSICKSELR 0x924
#define RCC_MP_APB1ENSETR 0xA00
#define RCC_MP_APB2ENSETR 0XA08
#define RCC_MP_APB3ENSETR 0xA10
@@ -267,6 +268,7 @@ enum stm32mp1_parent_id {
_CK_PER,
_CK_MPU,
_CK_MCU,
+ _DSI_PHY,
_PARENT_NB,
_UNKNOWN_ID = 0xff,
};
@@ -287,6 +289,7 @@ enum stm32mp1_parent_sel {
_USBPHY_SEL,
_USBO_SEL,
_STGEN_SEL,
+ _DSI_SEL,
_PARENT_SEL_NB,
_UNKNOWN_SEL = 0xff,
};
@@ -512,6 +515,9 @@ static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
STM32MP1_CLK_SET_CLR_F(RCC_MP_APB3ENSETR, 13, VREF, _PCLK3),
+ STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 0, LTDC_PX, _PLL4_Q),
+ STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 4, DSI_PX, _PLL4_Q),
+ STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 4, DSI_K, _DSI_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL),
@@ -569,6 +575,7 @@ static const u8 fmc_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
static const u8 usbphy_parents[] = {_HSE_KER, _PLL4_R, _HSE_KER_DIV2};
static const u8 usbo_parents[] = {_PLL4_R, _USB_PHY_48};
static const u8 stgen_parents[] = {_HSI_KER, _HSE_KER};
+static const u8 dsi_parents[] = {_DSI_PHY, _PLL4_P};
static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
STM32MP1_CLK_PARENT(_I2C12_SEL, RCC_I2C12CKSELR, 0, 0x7, i2c12_parents),
@@ -591,6 +598,7 @@ static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
STM32MP1_CLK_PARENT(_USBPHY_SEL, RCC_USBCKSELR, 0, 0x3, usbphy_parents),
STM32MP1_CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents),
STM32MP1_CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents),
+ STM32MP1_CLK_PARENT(_DSI_SEL, RCC_DSICKSELR, 0, 0x1, dsi_parents),
};
#ifdef STM32MP1_CLOCK_TREE_INIT
@@ -682,7 +690,8 @@ char * const stm32mp1_clk_parent_name[_PARENT_NB] = {
[_CK_PER] = "CK_PER",
[_CK_MPU] = "CK_MPU",
[_CK_MCU] = "CK_MCU",
- [_USB_PHY_48] = "USB_PHY_48"
+ [_USB_PHY_48] = "USB_PHY_48",
+ [_DSI_PHY] = "DSI_PHY_PLL",
};
static const __maybe_unused
@@ -701,7 +710,8 @@ char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = {
[_FMC_SEL] = "FMC",
[_USBPHY_SEL] = "USBPHY",
[_USBO_SEL] = "USBO",
- [_STGEN_SEL] = "STGEN"
+ [_STGEN_SEL] = "STGEN",
+ [_DSI_SEL] = "DSI",
};
static const struct stm32mp1_clk_data stm32mp1_data = {
@@ -1060,7 +1070,22 @@ static ulong stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p)
case _USB_PHY_48:
clock = stm32mp1_clk_get_fixed(priv, _USB_PHY_48);
break;
-
+ case _DSI_PHY:
+ {
+ struct clk clk;
+ struct udevice *dev = NULL;
+
+ if (!uclass_get_device_by_name(UCLASS_CLK, "ck_dsi_phy",
+ &dev)) {
+ if (clk_request(dev, &clk)) {
+ pr_err("ck_dsi_phy request");
+ } else {
+ clk.id = 0;
+ clock = clk_get_rate(&clk);
+ }
+ }
+ break;
+ }
default:
break;
}
@@ -1723,6 +1748,70 @@ static int stm32mp1_clktree(struct udevice *dev)
}
#endif /* STM32MP1_CLOCK_TREE_INIT */
+static int pll_set_output_rate(struct udevice *dev,
+ int pll_id,
+ int div_id,
+ unsigned long clk_rate)
+{
+ struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
+ const struct stm32mp1_clk_pll *pll = priv->data->pll;
+ u32 pllxcr = priv->base + pll[pll_id].pllxcr;
+ int div;
+ ulong fvco;
+
+ if (div_id > _DIV_NB)
+ return -EINVAL;
+
+ fvco = pll_get_fvco(priv, pll_id);
+
+ if (fvco <= clk_rate)
+ div = 1;
+ else
+ div = DIV_ROUND_UP(fvco, clk_rate);
+
+ if (div > 128)
+ div = 128;
+
+ debug("fvco = %ld, clk_rate = %ld, div=%d\n", fvco, clk_rate, div);
+ /* stop the requested output */
+ clrbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT);
+ /* change divider */
+ clrsetbits_le32(priv->base + pll[pll_id].pllxcfgr2,
+ RCC_PLLNCFGR2_DIVX_MASK << RCC_PLLNCFGR2_SHIFT(div_id),
+ (div - 1) << RCC_PLLNCFGR2_SHIFT(div_id));
+ /* start the requested output */
+ setbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT);
+
+ return 0;
+}
+
+static ulong stm32mp1_clk_set_rate(struct clk *clk, unsigned long clk_rate)
+{
+ struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
+ int p;
+
+ switch (clk->id) {
+ case LTDC_PX:
+ case DSI_PX:
+ break;
+ default:
+ pr_err("not supported");
+ return -EINVAL;
+ }
+
+ p = stm32mp1_clk_get_parent(priv, clk->id);
+ if (p < 0)
+ return -EINVAL;
+
+ switch (p) {
+ case _PLL4_Q:
+ /* for LTDC_PX and DSI_PX case */
+ return pll_set_output_rate(clk->dev, _PLL4, _DIV_Q, clk_rate);
+ }
+
+ return -EINVAL;
+}
+
static void stm32mp1_osc_clk_init(const char *name,
struct stm32mp1_clk_priv *priv,
int index)
@@ -1846,6 +1935,7 @@ static const struct clk_ops stm32mp1_clk_ops = {
.enable = stm32mp1_clk_enable,
.disable = stm32mp1_clk_disable,
.get_rate = stm32mp1_clk_get_rate,
+ .set_rate = stm32mp1_clk_set_rate,
};
U_BOOT_DRIVER(stm32mp1_clock) = {
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread* [U-Boot] [PATCH 4/6] stm32mp1: clk: update Ethernet clock gating
2018-07-16 8:41 [U-Boot] [PATCH 1/6] stm32mp1: clk: define RCC_PLLNCFGR2_SHIFT macro Patrick Delaunay
2018-07-16 8:41 ` [U-Boot] [PATCH 2/6] stm32mp1: clk: add common function pll_get_fvco Patrick Delaunay
2018-07-16 8:41 ` [U-Boot] [PATCH 3/6] stm32mp1: clk: add LDTC and DSI clock support Patrick Delaunay
@ 2018-07-16 8:41 ` Patrick Delaunay
2018-07-20 22:36 ` [U-Boot] [U-Boot, " Tom Rini
2018-07-16 8:41 ` [U-Boot] [PATCH 5/6] stm32mp1: clk: add ADC " Patrick Delaunay
` (3 subsequent siblings)
6 siblings, 1 reply; 13+ messages in thread
From: Patrick Delaunay @ 2018-07-16 8:41 UTC (permalink / raw)
To: u-boot
Alignment with kernel clock driver
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
---
drivers/clk/clk_stm32mp1.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c
index 6202ebe..0641dfa 100644
--- a/drivers/clk/clk_stm32mp1.c
+++ b/drivers/clk/clk_stm32mp1.c
@@ -542,10 +542,9 @@ static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 0, GPIOZ, _UNKNOWN_SEL),
- STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 7, ETHCK, _UNKNOWN_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 7, ETHCK, _ETH_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 8, ETHTX, _UNKNOWN_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 9, ETHRX, _UNKNOWN_SEL),
- STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 10, ETHMAC_K, _ETH_SEL),
STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB6ENSETR, 10, ETHMAC, _ACLK),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL),
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread* [U-Boot] [PATCH 5/6] stm32mp1: clk: add ADC clock gating
2018-07-16 8:41 [U-Boot] [PATCH 1/6] stm32mp1: clk: define RCC_PLLNCFGR2_SHIFT macro Patrick Delaunay
` (2 preceding siblings ...)
2018-07-16 8:41 ` [U-Boot] [PATCH 4/6] stm32mp1: clk: update Ethernet clock gating Patrick Delaunay
@ 2018-07-16 8:41 ` Patrick Delaunay
2018-07-20 22:36 ` [U-Boot] [U-Boot,5/6] " Tom Rini
2018-07-16 8:41 ` [U-Boot] [PATCH 6/6] stm32mp1: clk: support digital bypass Patrick Delaunay
` (2 subsequent siblings)
6 siblings, 1 reply; 13+ messages in thread
From: Patrick Delaunay @ 2018-07-16 8:41 UTC (permalink / raw)
To: u-boot
Add ADC clock gating, that may be used by STM32 ADC.
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
---
drivers/clk/clk_stm32mp1.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c
index 0641dfa..fc97642 100644
--- a/drivers/clk/clk_stm32mp1.c
+++ b/drivers/clk/clk_stm32mp1.c
@@ -99,6 +99,7 @@
#define RCC_FMCCKSELR 0x904
#define RCC_USBCKSELR 0x91C
#define RCC_DSICKSELR 0x924
+#define RCC_ADCCKSELR 0x928
#define RCC_MP_APB1ENSETR 0xA00
#define RCC_MP_APB2ENSETR 0XA08
#define RCC_MP_APB3ENSETR 0xA10
@@ -290,6 +291,7 @@ enum stm32mp1_parent_sel {
_USBO_SEL,
_STGEN_SEL,
_DSI_SEL,
+ _ADC12_SEL,
_PARENT_SEL_NB,
_UNKNOWN_SEL = 0xff,
};
@@ -525,6 +527,8 @@ static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL),
+ STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB2ENSETR, 5, ADC12, _HCLK2),
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 5, ADC12_K, _ADC12_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL),
@@ -575,6 +579,7 @@ static const u8 usbphy_parents[] = {_HSE_KER, _PLL4_R, _HSE_KER_DIV2};
static const u8 usbo_parents[] = {_PLL4_R, _USB_PHY_48};
static const u8 stgen_parents[] = {_HSI_KER, _HSE_KER};
static const u8 dsi_parents[] = {_DSI_PHY, _PLL4_P};
+static const u8 adc_parents[] = {_PLL4_R, _CK_PER, _PLL3_Q};
static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
STM32MP1_CLK_PARENT(_I2C12_SEL, RCC_I2C12CKSELR, 0, 0x7, i2c12_parents),
@@ -598,6 +603,7 @@ static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
STM32MP1_CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents),
STM32MP1_CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents),
STM32MP1_CLK_PARENT(_DSI_SEL, RCC_DSICKSELR, 0, 0x1, dsi_parents),
+ STM32MP1_CLK_PARENT(_ADC12_SEL, RCC_ADCCKSELR, 0, 0x1, adc_parents),
};
#ifdef STM32MP1_CLOCK_TREE_INIT
@@ -711,6 +717,7 @@ char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = {
[_USBO_SEL] = "USBO",
[_STGEN_SEL] = "STGEN",
[_DSI_SEL] = "DSI",
+ [_ADC12_SEL] = "ADC12",
};
static const struct stm32mp1_clk_data stm32mp1_data = {
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread* [U-Boot] [PATCH 6/6] stm32mp1: clk: support digital bypass
2018-07-16 8:41 [U-Boot] [PATCH 1/6] stm32mp1: clk: define RCC_PLLNCFGR2_SHIFT macro Patrick Delaunay
` (3 preceding siblings ...)
2018-07-16 8:41 ` [U-Boot] [PATCH 5/6] stm32mp1: clk: add ADC " Patrick Delaunay
@ 2018-07-16 8:41 ` Patrick Delaunay
2018-07-20 22:36 ` [U-Boot] [U-Boot,6/6] " Tom Rini
2018-07-16 18:30 ` [U-Boot] [PATCH 1/6] stm32mp1: clk: define RCC_PLLNCFGR2_SHIFT macro Vikas Manocha
2018-07-20 22:36 ` [U-Boot] [U-Boot, " Tom Rini
6 siblings, 1 reply; 13+ messages in thread
From: Patrick Delaunay @ 2018-07-16 8:41 UTC (permalink / raw)
To: u-boot
HSE and LSE bypass shall support both analog and digital signals.
This patch add a way to select digital bypas case in the device tree
and set the associated bit DIGBYP in RCC_BDCR and RCC_OCEN register
during clock tree initialization.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
---
doc/device-tree-bindings/clock/st,stm32mp1.txt | 4 +++-
drivers/clk/clk_stm32mp1.c | 27 +++++++++++++++++---------
2 files changed, 21 insertions(+), 10 deletions(-)
diff --git a/doc/device-tree-bindings/clock/st,stm32mp1.txt b/doc/device-tree-bindings/clock/st,stm32mp1.txt
index c29d90f..6a9397e 100644
--- a/doc/device-tree-bindings/clock/st,stm32mp1.txt
+++ b/doc/device-tree-bindings/clock/st,stm32mp1.txt
@@ -170,8 +170,10 @@ Optional properties :
a) for external oscillator: "clk-lse", "clk-hse"
- 3 optional fields are managed
+ 4 optional fields are managed
- "st,bypass" Configure the oscillator bypass mode (HSEBYP, LSEBYP)
+ - "st,digbypass" Configure the bypass mode as full-swing digital signal
+ (DIGBYP)
- "st,css" Activate the clock security system (HSECSSON, LSECSSON)
- "st,drive" (only for LSE) value of the drive for the oscillator
(see LSEDRV_ define in the file dt-bindings/clock/stm32mp1-clksrc.h)
diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c
index fc97642..45c417e 100644
--- a/drivers/clk/clk_stm32mp1.c
+++ b/drivers/clk/clk_stm32mp1.c
@@ -149,6 +149,7 @@
#define RCC_BDCR_LSEON BIT(0)
#define RCC_BDCR_LSEBYP BIT(1)
#define RCC_BDCR_LSERDY BIT(2)
+#define RCC_BDCR_DIGBYP BIT(3)
#define RCC_BDCR_LSEDRV_MASK GENMASK(5, 4)
#define RCC_BDCR_LSEDRV_SHIFT 4
#define RCC_BDCR_LSECSSON BIT(8)
@@ -203,6 +204,7 @@
/* used for RCC_OCENSETR and RCC_OCENCLRR registers */
#define RCC_OCENR_HSION BIT(0)
#define RCC_OCENR_CSION BIT(4)
+#define RCC_OCENR_DIGBYP BIT(7)
#define RCC_OCENR_HSEON BIT(8)
#define RCC_OCENR_HSEBYP BIT(10)
#define RCC_OCENR_HSECSSON BIT(11)
@@ -1202,11 +1204,15 @@ static int stm32mp1_osc_wait(int enable, fdt_addr_t rcc, u32 offset,
return ret;
}
-static void stm32mp1_lse_enable(fdt_addr_t rcc, int bypass, int lsedrv)
+static void stm32mp1_lse_enable(fdt_addr_t rcc, int bypass, int digbyp,
+ int lsedrv)
{
u32 value;
- if (bypass)
+ if (digbyp)
+ setbits_le32(rcc + RCC_BDCR, RCC_BDCR_DIGBYP);
+
+ if (bypass || digbyp)
setbits_le32(rcc + RCC_BDCR, RCC_BDCR_LSEBYP);
/*
@@ -1241,9 +1247,11 @@ static void stm32mp1_lsi_set(fdt_addr_t rcc, int enable)
stm32mp1_osc_wait(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSIRDY);
}
-static void stm32mp1_hse_enable(fdt_addr_t rcc, int bypass, int css)
+static void stm32mp1_hse_enable(fdt_addr_t rcc, int bypass, int digbyp, int css)
{
- if (bypass)
+ if (digbyp)
+ setbits_le32(rcc + RCC_OCENSETR, RCC_OCENR_DIGBYP);
+ if (bypass || digbyp)
setbits_le32(rcc + RCC_OCENSETR, RCC_OCENR_HSEBYP);
stm32mp1_hs_ocs_set(1, rcc, RCC_OCENR_HSEON);
@@ -1606,26 +1614,27 @@ static int stm32mp1_clktree(struct udevice *dev)
stm32mp1_lsi_set(rcc, 1);
if (priv->osc[_LSE]) {
- int bypass;
- int lsedrv;
+ int bypass, digbyp, lsedrv;
struct udevice *dev = priv->osc_dev[_LSE];
bypass = dev_read_bool(dev, "st,bypass");
+ digbyp = dev_read_bool(dev, "st,digbypass");
lse_css = dev_read_bool(dev, "st,css");
lsedrv = dev_read_u32_default(dev, "st,drive",
LSEDRV_MEDIUM_HIGH);
- stm32mp1_lse_enable(rcc, bypass, lsedrv);
+ stm32mp1_lse_enable(rcc, bypass, digbyp, lsedrv);
}
if (priv->osc[_HSE]) {
- int bypass, css;
+ int bypass, digbyp, css;
struct udevice *dev = priv->osc_dev[_HSE];
bypass = dev_read_bool(dev, "st,bypass");
+ digbyp = dev_read_bool(dev, "st,digbypass");
css = dev_read_bool(dev, "st,css");
- stm32mp1_hse_enable(rcc, bypass, css);
+ stm32mp1_hse_enable(rcc, bypass, digbyp, css);
}
/* CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR)
* => switch on CSI even if node is not present in device tree
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread* [U-Boot] [PATCH 1/6] stm32mp1: clk: define RCC_PLLNCFGR2_SHIFT macro
2018-07-16 8:41 [U-Boot] [PATCH 1/6] stm32mp1: clk: define RCC_PLLNCFGR2_SHIFT macro Patrick Delaunay
` (4 preceding siblings ...)
2018-07-16 8:41 ` [U-Boot] [PATCH 6/6] stm32mp1: clk: support digital bypass Patrick Delaunay
@ 2018-07-16 18:30 ` Vikas Manocha
2018-07-20 22:36 ` [U-Boot] [U-Boot, " Tom Rini
6 siblings, 0 replies; 13+ messages in thread
From: Vikas Manocha @ 2018-07-16 18:30 UTC (permalink / raw)
To: u-boot
Hi,
On 07/16/2018 01:41 AM, Patrick Delaunay wrote:
> This patch define RCC_PLLNCFGR2_SHIFT to reuse it in
> the pll function for set rate.
>
> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
Cheers,
Vikas
> ---
>
> drivers/clk/clk_stm32mp1.c | 15 ++++++---------
> 1 file changed, 6 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c
> index 3f00c198..5177758 100644
> --- a/drivers/clk/clk_stm32mp1.c
> +++ b/drivers/clk/clk_stm32mp1.c
> @@ -175,13 +175,14 @@
> #define RCC_PLLNCFGR1_IFRGE_SHIFT 24
> #define RCC_PLLNCFGR1_IFRGE_MASK GENMASK(25, 24)
>
> -/* used for ALL PLLNCFGR2 registers */
> +/* used for ALL PLLNCFGR2 registers , using stm32mp1_div_id */
> +#define RCC_PLLNCFGR2_SHIFT(div_id) ((div_id) * 8)
> #define RCC_PLLNCFGR2_DIVX_MASK GENMASK(6, 0)
> -#define RCC_PLLNCFGR2_DIVP_SHIFT 0
> +#define RCC_PLLNCFGR2_DIVP_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_P)
> #define RCC_PLLNCFGR2_DIVP_MASK GENMASK(6, 0)
> -#define RCC_PLLNCFGR2_DIVQ_SHIFT 8
> +#define RCC_PLLNCFGR2_DIVQ_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_Q)
> #define RCC_PLLNCFGR2_DIVQ_MASK GENMASK(14, 8)
> -#define RCC_PLLNCFGR2_DIVR_SHIFT 16
> +#define RCC_PLLNCFGR2_DIVR_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_R)
> #define RCC_PLLNCFGR2_DIVR_MASK GENMASK(22, 16)
>
> /* used for ALL PLLNFRACR registers */
> @@ -814,10 +815,6 @@ static ulong stm32mp1_read_pll_freq(struct stm32mp1_clk_priv *priv,
> int divm, divn, divy, src;
> ulong refclk, dfout;
> u32 selr, cfgr1, cfgr2, fracr;
> - const u8 shift[_DIV_NB] = {
> - [_DIV_P] = RCC_PLLNCFGR2_DIVP_SHIFT,
> - [_DIV_Q] = RCC_PLLNCFGR2_DIVQ_SHIFT,
> - [_DIV_R] = RCC_PLLNCFGR2_DIVR_SHIFT };
>
> debug("%s(%d, %d)\n", __func__, pll_id, div_id);
> if (div_id > _DIV_NB)
> @@ -833,7 +830,7 @@ static ulong stm32mp1_read_pll_freq(struct stm32mp1_clk_priv *priv,
>
> divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT;
> divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK;
> - divy = (cfgr2 >> shift[div_id]) & RCC_PLLNCFGR2_DIVX_MASK;
> + divy = (cfgr2 >> RCC_PLLNCFGR2_SHIFT(div_id)) & RCC_PLLNCFGR2_DIVX_MASK;
>
> debug(" DIVN=%d DIVM=%d DIVY=%d\n", divn, divm, divy);
>
>
^ permalink raw reply [flat|nested] 13+ messages in thread* [U-Boot] [U-Boot, 1/6] stm32mp1: clk: define RCC_PLLNCFGR2_SHIFT macro
2018-07-16 8:41 [U-Boot] [PATCH 1/6] stm32mp1: clk: define RCC_PLLNCFGR2_SHIFT macro Patrick Delaunay
` (5 preceding siblings ...)
2018-07-16 18:30 ` [U-Boot] [PATCH 1/6] stm32mp1: clk: define RCC_PLLNCFGR2_SHIFT macro Vikas Manocha
@ 2018-07-20 22:36 ` Tom Rini
6 siblings, 0 replies; 13+ messages in thread
From: Tom Rini @ 2018-07-20 22:36 UTC (permalink / raw)
To: u-boot
On Mon, Jul 16, 2018 at 10:41:41AM +0200, Patrick Delaunay wrote:
> This patch define RCC_PLLNCFGR2_SHIFT to reuse it in
> the pll function for set rate.
>
> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
Applied to u-boot/master, thanks!
--
Tom
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