[PATCH 1/2] drm/amd/pp: Set Max clock level to display by default

[PATCH 1/2] drm/amd/pp: Set Max clock level to display by default

[Rex Zhu]

avoid the error in dmesg:
[drm:dm_pp_get_static_clocks]
*ERROR* DM_PPLIB: invalid powerlevel state: 0!

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 75c2082..63adcd1 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -998,7 +998,7 @@ static int pp_get_display_power_level(void *handle,
 static int pp_get_current_clocks(void *handle,
 		struct amd_pp_clock_info *clocks)
 {
-	struct amd_pp_simple_clock_info simple_clocks;
+	struct amd_pp_simple_clock_info simple_clocks = { 0 };
 	struct pp_clock_info hw_clocks;
 	struct pp_hwmgr *hwmgr = handle;
 	int ret = 0;
@@ -1034,7 +1034,8 @@ static int pp_get_current_clocks(void *handle,
 	clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
 	clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
 
-	clocks->max_clocks_state = simple_clocks.level;
+	if (simple_clocks.level == 0)
+		clocks->max_clocks_state = PP_DAL_POWERLEVEL_7;
 
 	if (0 == phm_get_current_shallow_sleep_clocks(hwmgr, &hwmgr->current_ps->hardware, &hw_clocks)) {
 		clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
@@ -1137,6 +1138,8 @@ static int pp_get_display_mode_validation_clocks(void *handle,
 	if (!hwmgr || !hwmgr->pm_en ||!clocks)
 		return -EINVAL;
 
+	clocks->level = PP_DAL_POWERLEVEL_7;
+
 	mutex_lock(&hwmgr->smu_lock);
 
 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DynamicPatchPowerState))
-- 
1.9.1

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[PATCH 2/2] drm/amd/display: Convert 10kHz clks from PPLib into kHz

[Rex Zhu]

Except special naming as *_in_khz, The default clock unit in powerplay
is in 10KHz. so need to * 10 as expecting clock frequency in display
is in kHz.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
index c69ae78..fbe878a 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
@@ -469,8 +469,8 @@ bool dm_pp_get_static_clocks(
 		return false;
 
 	static_clk_info->max_clocks_state = pp_to_dc_powerlevel_state(pp_clk_info.max_clocks_state);
-	static_clk_info->max_mclk_khz = pp_clk_info.max_memory_clock;
-	static_clk_info->max_sclk_khz = pp_clk_info.max_engine_clock;
+	static_clk_info->max_mclk_khz = pp_clk_info.max_memory_clock * 10;
+	static_clk_info->max_sclk_khz = pp_clk_info.max_engine_clock * 10;
 
 	return true;
 }
-- 
1.9.1

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Re: [PATCH 2/2] drm/amd/display: Convert 10kHz clks from PPLib into kHz

[Alex Deucher]

On Tue, Jul 17, 2018 at 8:36 AM, Rex Zhu <rex.zhu@amd.com> wrote:
> Except special naming as *_in_khz, The default clock unit in powerplay
> is in 10KHz. so need to * 10 as expecting clock frequency in display
> is in kHz.
>
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>

Series is:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
> index c69ae78..fbe878a 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
> @@ -469,8 +469,8 @@ bool dm_pp_get_static_clocks(
>                 return false;
>
>         static_clk_info->max_clocks_state = pp_to_dc_powerlevel_state(pp_clk_info.max_clocks_state);
> -       static_clk_info->max_mclk_khz = pp_clk_info.max_memory_clock;
> -       static_clk_info->max_sclk_khz = pp_clk_info.max_engine_clock;
> +       static_clk_info->max_mclk_khz = pp_clk_info.max_memory_clock * 10;
> +       static_clk_info->max_sclk_khz = pp_clk_info.max_engine_clock * 10;
>
>         return true;
>  }
> --
> 1.9.1
>
> _______________________________________________
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> amd-gfx@lists.freedesktop.org
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Re: [PATCH 1/2] drm/amd/pp: Set Max clock level to display by default

[Harry Wentland]

On 2018-07-17 08:36 AM, Rex Zhu wrote:
> avoid the error in dmesg:
> [drm:dm_pp_get_static_clocks]
> *ERROR* DM_PPLIB: invalid powerlevel state: 0!
> 
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
> ---
>  drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 7 +++++--
>  1 file changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> index 75c2082..63adcd1 100644
> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> @@ -998,7 +998,7 @@ static int pp_get_display_power_level(void *handle,
>  static int pp_get_current_clocks(void *handle,
>  		struct amd_pp_clock_info *clocks)
>  {
> -	struct amd_pp_simple_clock_info simple_clocks;
> +	struct amd_pp_simple_clock_info simple_clocks = { 0 };
>  	struct pp_clock_info hw_clocks;
>  	struct pp_hwmgr *hwmgr = handle;
>  	int ret = 0;
> @@ -1034,7 +1034,8 @@ static int pp_get_current_clocks(void *handle,
>  	clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
>  	clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
>  
> -	clocks->max_clocks_state = simple_clocks.level;
> +	if (simple_clocks.level == 0)
> +		clocks->max_clocks_state = PP_DAL_POWERLEVEL_7;

shouldn't we still assign simple_clocks.level to clocks->max_clocks_state if it's non-zero?

Harry

>  
>  	if (0 == phm_get_current_shallow_sleep_clocks(hwmgr, &hwmgr->current_ps->hardware, &hw_clocks)) {
>  		clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
> @@ -1137,6 +1138,8 @@ static int pp_get_display_mode_validation_clocks(void *handle,
>  	if (!hwmgr || !hwmgr->pm_en ||!clocks)
>  		return -EINVAL;
>  
> +	clocks->level = PP_DAL_POWERLEVEL_7;
> +
>  	mutex_lock(&hwmgr->smu_lock);
>  
>  	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DynamicPatchPowerState))
> 
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Re: [PATCH 2/2] drm/amd/display: Convert 10kHz clks from PPLib into kHz

[Harry Wentland]

On 2018-07-17 08:36 AM, Rex Zhu wrote:
> Except special naming as *_in_khz, The default clock unit in powerplay
> is in 10KHz. so need to * 10 as expecting clock frequency in display
> is in kHz.
> 
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>

Reviewed-by: Harry Wentland <harry.wentland@amd.com>

Harry

> ---
>  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
> index c69ae78..fbe878a 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
> @@ -469,8 +469,8 @@ bool dm_pp_get_static_clocks(
>  		return false;
>  
>  	static_clk_info->max_clocks_state = pp_to_dc_powerlevel_state(pp_clk_info.max_clocks_state);
> -	static_clk_info->max_mclk_khz = pp_clk_info.max_memory_clock;
> -	static_clk_info->max_sclk_khz = pp_clk_info.max_engine_clock;
> +	static_clk_info->max_mclk_khz = pp_clk_info.max_memory_clock * 10;
> +	static_clk_info->max_sclk_khz = pp_clk_info.max_engine_clock * 10;
>  
>  	return true;
>  }
> 
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Re: [PATCH 1/2] drm/amd/pp: Set Max clock level to display by default

[Zhu, Rex]

[-- Attachment #1.1: Type: text/plain, Size: 2468 bytes --]

>shouldn't we still assign simple_clocks.level to clocks->max_clocks_state if it's non-zero?

Yes, Thanks for your reminding.


Best Regards

Rex



________________________________
From: Wentland, Harry
Sent: Wednesday, July 18, 2018 2:29 AM
To: Zhu, Rex; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: Re: [PATCH 1/2] drm/amd/pp: Set Max clock level to display by default



On 2018-07-17 08:36 AM, Rex Zhu wrote:
> avoid the error in dmesg:
> [drm:dm_pp_get_static_clocks]
> *ERROR* DM_PPLIB: invalid powerlevel state: 0!
>
> Signed-off-by: Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
> ---
>  drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 7 +++++--
>  1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> index 75c2082..63adcd1 100644
> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> @@ -998,7 +998,7 @@ static int pp_get_display_power_level(void *handle,
>  static int pp_get_current_clocks(void *handle,
>                struct amd_pp_clock_info *clocks)
>  {
> -     struct amd_pp_simple_clock_info simple_clocks;
> +     struct amd_pp_simple_clock_info simple_clocks = { 0 };
>        struct pp_clock_info hw_clocks;
>        struct pp_hwmgr *hwmgr = handle;
>        int ret = 0;
> @@ -1034,7 +1034,8 @@ static int pp_get_current_clocks(void *handle,
>        clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
>        clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
>
> -     clocks->max_clocks_state = simple_clocks.level;
> +     if (simple_clocks.level == 0)
> +             clocks->max_clocks_state = PP_DAL_POWERLEVEL_7;

shouldn't we still assign simple_clocks.level to clocks->max_clocks_state if it's non-zero?

Harry

>
>        if (0 == phm_get_current_shallow_sleep_clocks(hwmgr, &hwmgr->current_ps->hardware, &hw_clocks)) {
>                clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
> @@ -1137,6 +1138,8 @@ static int pp_get_display_mode_validation_clocks(void *handle,
>        if (!hwmgr || !hwmgr->pm_en ||!clocks)
>                return -EINVAL;
>
> +     clocks->level = PP_DAL_POWERLEVEL_7;
> +
>        mutex_lock(&hwmgr->smu_lock);
>
>        if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DynamicPatchPowerState))
>

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