From: Pu Wen <puwen@hygon.cn> To: tglx@linutronix.de, bp@alien8.de, thomas.lendacky@amd.com, mingo@redhat.com, hpa@zytor.com, peterz@infradead.org, tony.luck@intel.com, pbonzini@redhat.com, rkrcmar@redhat.com, boris.ostrovsky@oracle.com, jgross@suse.com, rjw@rjwysocki.net, lenb@kernel.org, viresh.kumar@linaro.org, mchehab@kernel.org, trenn@suse.com, shuah@kernel.org, JBeulich@suse.com, x86@kernel.org Cc: linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, kvm@vger.kernel.org, xen-devel@lists.xenproject.org Subject: [PATCH v2 02/17] x86/cache: get Dhyana cache size/leaves and setup cache cpumap Date: Mon, 23 Jul 2018 21:20:22 +0800 [thread overview] Message-ID: <1532352037-7151-3-git-send-email-puwen@hygon.cn> (raw) In-Reply-To: <1532352037-7151-1-git-send-email-puwen@hygon.cn> Hygon Dhyana processor has the topology extensions bit in CPUID. With this bit kernel can get the cache info. So add support in cpuid4_cache_lookup_regs() to get the correct cache size. Dhyana also find num_cache_leaves via CPUID leaf 0x8000001d, so add Hygon support in find_num_cache_leaves(). Also add cacheinfo_hygon_init_llc_id() and init_hygon_cacheinfo() functions to initialize Dhyana cache info. Setup cache cpumap in the same way as AMD does. Signed-off-by: Pu Wen <puwen@hygon.cn> --- arch/x86/include/asm/cacheinfo.h | 1 + arch/x86/kernel/cpu/cacheinfo.c | 31 +++++++++++++++++++++++++++++-- arch/x86/kernel/cpu/cpu.h | 1 + arch/x86/kernel/cpu/hygon.c | 3 +++ 4 files changed, 34 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/cacheinfo.h b/arch/x86/include/asm/cacheinfo.h index e958e28..86b63c7 100644 --- a/arch/x86/include/asm/cacheinfo.h +++ b/arch/x86/include/asm/cacheinfo.h @@ -3,5 +3,6 @@ #define _ASM_X86_CACHEINFO_H void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, int cpu, u8 node_id); +void cacheinfo_hygon_init_llc_id(struct cpuinfo_x86 *c, int cpu, u8 node_id); #endif /* _ASM_X86_CACHEINFO_H */ diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinfo.c index 0c5fcbd..dc1b934 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -602,6 +602,10 @@ cpuid4_cache_lookup_regs(int index, struct _cpuid4_info_regs *this_leaf) else amd_cpuid4(index, &eax, &ebx, &ecx); amd_init_l3_cache(this_leaf, index); + } else if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) { + cpuid_count(0x8000001d, index, &eax.full, + &ebx.full, &ecx.full, &edx); + amd_init_l3_cache(this_leaf, index); } else { cpuid_count(4, index, &eax.full, &ebx.full, &ecx.full, &edx); } @@ -625,7 +629,8 @@ static int find_num_cache_leaves(struct cpuinfo_x86 *c) union _cpuid4_leaf_eax cache_eax; int i = -1; - if (c->x86_vendor == X86_VENDOR_AMD) + if (c->x86_vendor == X86_VENDOR_AMD || + c->x86_vendor == X86_VENDOR_HYGON) op = 0x8000001d; else op = 4; @@ -678,6 +683,22 @@ void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, int cpu, u8 node_id) } } +void cacheinfo_hygon_init_llc_id(struct cpuinfo_x86 *c, int cpu, u8 node_id) +{ + /* + * We may have multiple LLCs if L3 caches exist, so check if we + * have an L3 cache by looking at the L3 cache CPUID leaf. + */ + if (!cpuid_edx(0x80000006)) + return; + + /* + * LLC is at the core complex level. + * Core complex ID is ApicId[3] for these processors. + */ + per_cpu(cpu_llc_id, cpu) = c->apicid >> 3; +} + void init_amd_cacheinfo(struct cpuinfo_x86 *c) { @@ -691,6 +712,11 @@ void init_amd_cacheinfo(struct cpuinfo_x86 *c) } } +void init_hygon_cacheinfo(struct cpuinfo_x86 *c) +{ + num_cache_leaves = find_num_cache_leaves(c); +} + void init_intel_cacheinfo(struct cpuinfo_x86 *c) { /* Cache sizes */ @@ -913,7 +939,8 @@ static void __cache_cpumap_setup(unsigned int cpu, int index, int index_msb, i; struct cpuinfo_x86 *c = &cpu_data(cpu); - if (c->x86_vendor == X86_VENDOR_AMD) { + if (c->x86_vendor == X86_VENDOR_AMD || + c->x86_vendor == X86_VENDOR_HYGON) { if (__cache_amd_cpumap_setup(cpu, index, base)) return; } diff --git a/arch/x86/kernel/cpu/cpu.h b/arch/x86/kernel/cpu/cpu.h index 38216f6..c2ba596 100644 --- a/arch/x86/kernel/cpu/cpu.h +++ b/arch/x86/kernel/cpu/cpu.h @@ -53,6 +53,7 @@ extern u32 get_scattered_cpuid_leaf(unsigned int level, enum cpuid_regs_idx reg); extern void init_intel_cacheinfo(struct cpuinfo_x86 *c); extern void init_amd_cacheinfo(struct cpuinfo_x86 *c); +extern void init_hygon_cacheinfo(struct cpuinfo_x86 *c); extern void detect_num_cpu_cores(struct cpuinfo_x86 *c); extern int detect_extended_topology(struct cpuinfo_x86 *c); diff --git a/arch/x86/kernel/cpu/hygon.c b/arch/x86/kernel/cpu/hygon.c index cc296e5..0d77b91 100644 --- a/arch/x86/kernel/cpu/hygon.c +++ b/arch/x86/kernel/cpu/hygon.c @@ -85,6 +85,7 @@ static void hygon_get_topology(struct cpuinfo_x86 *c) if (!err) c->x86_coreid_bits = get_count_order(c->x86_max_cores); + cacheinfo_amd_init_llc_id(c, cpu, node_id); } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) { u64 value; @@ -315,6 +316,8 @@ static void init_hygon(struct cpuinfo_x86 *c) srat_detect_node(c); } + init_hygon_cacheinfo(c); + set_cpu_cap(c, X86_FEATURE_K8); if (cpu_has(c, X86_FEATURE_XMM2)) { -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Pu Wen <puwen@hygon.cn> To: tglx@linutronix.de, bp@alien8.de, thomas.lendacky@amd.com, mingo@redhat.com, hpa@zytor.com, peterz@infradead.org, tony.luck@intel.com, pbonzini@redhat.com, rkrcmar@redhat.com, boris.ostrovsky@oracle.com, jgross@suse.com, rjw@rjwysocki.net, lenb@kernel.org, viresh.kumar@linaro.org, mchehab@kernel.org, trenn@suse.com, shuah@kernel.org, JBeulich@suse.com, x86@kernel.org Cc: linux-arch@vger.kernel.org, xen-devel@lists.xenproject.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Subject: [PATCH v2 02/17] x86/cache: get Dhyana cache size/leaves and setup cache cpumap Date: Mon, 23 Jul 2018 21:20:22 +0800 [thread overview] Message-ID: <1532352037-7151-3-git-send-email-puwen@hygon.cn> (raw) In-Reply-To: <1532352037-7151-1-git-send-email-puwen@hygon.cn> Hygon Dhyana processor has the topology extensions bit in CPUID. With this bit kernel can get the cache info. So add support in cpuid4_cache_lookup_regs() to get the correct cache size. Dhyana also find num_cache_leaves via CPUID leaf 0x8000001d, so add Hygon support in find_num_cache_leaves(). Also add cacheinfo_hygon_init_llc_id() and init_hygon_cacheinfo() functions to initialize Dhyana cache info. Setup cache cpumap in the same way as AMD does. Signed-off-by: Pu Wen <puwen@hygon.cn> --- arch/x86/include/asm/cacheinfo.h | 1 + arch/x86/kernel/cpu/cacheinfo.c | 31 +++++++++++++++++++++++++++++-- arch/x86/kernel/cpu/cpu.h | 1 + arch/x86/kernel/cpu/hygon.c | 3 +++ 4 files changed, 34 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/cacheinfo.h b/arch/x86/include/asm/cacheinfo.h index e958e28..86b63c7 100644 --- a/arch/x86/include/asm/cacheinfo.h +++ b/arch/x86/include/asm/cacheinfo.h @@ -3,5 +3,6 @@ #define _ASM_X86_CACHEINFO_H void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, int cpu, u8 node_id); +void cacheinfo_hygon_init_llc_id(struct cpuinfo_x86 *c, int cpu, u8 node_id); #endif /* _ASM_X86_CACHEINFO_H */ diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinfo.c index 0c5fcbd..dc1b934 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -602,6 +602,10 @@ cpuid4_cache_lookup_regs(int index, struct _cpuid4_info_regs *this_leaf) else amd_cpuid4(index, &eax, &ebx, &ecx); amd_init_l3_cache(this_leaf, index); + } else if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) { + cpuid_count(0x8000001d, index, &eax.full, + &ebx.full, &ecx.full, &edx); + amd_init_l3_cache(this_leaf, index); } else { cpuid_count(4, index, &eax.full, &ebx.full, &ecx.full, &edx); } @@ -625,7 +629,8 @@ static int find_num_cache_leaves(struct cpuinfo_x86 *c) union _cpuid4_leaf_eax cache_eax; int i = -1; - if (c->x86_vendor == X86_VENDOR_AMD) + if (c->x86_vendor == X86_VENDOR_AMD || + c->x86_vendor == X86_VENDOR_HYGON) op = 0x8000001d; else op = 4; @@ -678,6 +683,22 @@ void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, int cpu, u8 node_id) } } +void cacheinfo_hygon_init_llc_id(struct cpuinfo_x86 *c, int cpu, u8 node_id) +{ + /* + * We may have multiple LLCs if L3 caches exist, so check if we + * have an L3 cache by looking at the L3 cache CPUID leaf. + */ + if (!cpuid_edx(0x80000006)) + return; + + /* + * LLC is at the core complex level. + * Core complex ID is ApicId[3] for these processors. + */ + per_cpu(cpu_llc_id, cpu) = c->apicid >> 3; +} + void init_amd_cacheinfo(struct cpuinfo_x86 *c) { @@ -691,6 +712,11 @@ void init_amd_cacheinfo(struct cpuinfo_x86 *c) } } +void init_hygon_cacheinfo(struct cpuinfo_x86 *c) +{ + num_cache_leaves = find_num_cache_leaves(c); +} + void init_intel_cacheinfo(struct cpuinfo_x86 *c) { /* Cache sizes */ @@ -913,7 +939,8 @@ static void __cache_cpumap_setup(unsigned int cpu, int index, int index_msb, i; struct cpuinfo_x86 *c = &cpu_data(cpu); - if (c->x86_vendor == X86_VENDOR_AMD) { + if (c->x86_vendor == X86_VENDOR_AMD || + c->x86_vendor == X86_VENDOR_HYGON) { if (__cache_amd_cpumap_setup(cpu, index, base)) return; } diff --git a/arch/x86/kernel/cpu/cpu.h b/arch/x86/kernel/cpu/cpu.h index 38216f6..c2ba596 100644 --- a/arch/x86/kernel/cpu/cpu.h +++ b/arch/x86/kernel/cpu/cpu.h @@ -53,6 +53,7 @@ extern u32 get_scattered_cpuid_leaf(unsigned int level, enum cpuid_regs_idx reg); extern void init_intel_cacheinfo(struct cpuinfo_x86 *c); extern void init_amd_cacheinfo(struct cpuinfo_x86 *c); +extern void init_hygon_cacheinfo(struct cpuinfo_x86 *c); extern void detect_num_cpu_cores(struct cpuinfo_x86 *c); extern int detect_extended_topology(struct cpuinfo_x86 *c); diff --git a/arch/x86/kernel/cpu/hygon.c b/arch/x86/kernel/cpu/hygon.c index cc296e5..0d77b91 100644 --- a/arch/x86/kernel/cpu/hygon.c +++ b/arch/x86/kernel/cpu/hygon.c @@ -85,6 +85,7 @@ static void hygon_get_topology(struct cpuinfo_x86 *c) if (!err) c->x86_coreid_bits = get_count_order(c->x86_max_cores); + cacheinfo_amd_init_llc_id(c, cpu, node_id); } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) { u64 value; @@ -315,6 +316,8 @@ static void init_hygon(struct cpuinfo_x86 *c) srat_detect_node(c); } + init_hygon_cacheinfo(c); + set_cpu_cap(c, X86_FEATURE_K8); if (cpu_has(c, X86_FEATURE_XMM2)) { -- 2.7.4 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel
next prev parent reply other threads:[~2018-07-23 13:29 UTC|newest] Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-07-23 13:20 [PATCH v2 00/17] Add support for Hygon Dhyana Family 18h processor Pu Wen 2018-07-23 13:20 ` Pu Wen 2018-07-23 13:20 ` [PATCH v2 01/17] x86/cpu: create Dhyana init file and register new cpu_dev to system Pu Wen 2018-07-23 13:20 ` Pu Wen 2018-07-24 18:14 ` Paolo Bonzini [not found] ` <201807290021145963620@hygon.cn> 2018-07-28 23:42 ` Paolo Bonzini 2018-07-30 16:42 ` Pu Wen 2018-07-24 18:14 ` Paolo Bonzini 2018-07-23 13:20 ` Pu Wen [this message] 2018-07-23 13:20 ` [PATCH v2 02/17] x86/cache: get Dhyana cache size/leaves and setup cache cpumap Pu Wen 2018-07-23 13:20 ` [PATCH v2 03/17] x86/mtrr: get MTRR number and support TOP_MEM2 Pu Wen 2018-07-23 13:20 ` Pu Wen 2018-07-23 13:20 ` [PATCH v2 04/17] x86/smpboot: smp init nodelay and no flush caches before sleep Pu Wen 2018-07-23 13:20 ` Pu Wen 2018-07-23 13:20 ` [PATCH v2 05/17] x86/perfctr: return perf counter and event selection bit offset Pu Wen 2018-07-23 13:20 ` Pu Wen 2018-07-23 13:20 ` [PATCH v2 06/17] x86/nops: init ideal_nops for Hygon Pu Wen 2018-07-23 13:20 ` Pu Wen 2018-07-23 13:20 ` [PATCH v2 07/17] x86/pci: add Hygon PCI vendor and northbridge support Pu Wen 2018-07-23 13:20 ` Pu Wen 2018-07-23 13:20 ` [PATCH v2 08/17] x86/apic: add modern APIC support for Hygon Pu Wen 2018-07-23 13:20 ` Pu Wen 2018-07-23 13:20 ` [PATCH v2 09/17] x86/bugs: add lfence mitigation to spectre v2 and no meltdown " Pu Wen 2018-07-23 13:20 ` Pu Wen 2018-07-23 13:20 ` [PATCH v2 10/17] x86/events: enable Hygon support to PMU infrastructure Pu Wen 2018-07-23 13:20 ` Pu Wen 2018-07-23 13:20 ` [PATCH v2 11/17] x86/mce: enable Hygon support to MCE infrastructure Pu Wen 2018-07-23 13:20 ` Pu Wen 2018-07-23 13:20 ` [PATCH v2 12/17] x86/kvm: enable Hygon support to KVM infrastructure Pu Wen 2018-07-23 13:20 ` Pu Wen 2018-07-23 13:20 ` [PATCH v2 13/17] x86/xen: enable Hygon support to Xen Pu Wen 2018-07-23 13:20 ` Pu Wen 2018-07-23 13:20 ` [PATCH v2 14/17] driver/acpi: enable Hygon support to ACPI driver Pu Wen 2018-07-23 13:20 ` Pu Wen 2018-07-23 13:20 ` [PATCH v2 15/17] driver/cpufreq: enable Hygon support to cpufreq driver Pu Wen 2018-07-23 13:20 ` Pu Wen 2018-07-23 13:20 ` [PATCH v2 16/17] driver/edac: enable Hygon support to AMD64 EDAC driver Pu Wen 2018-07-23 13:20 ` Pu Wen 2018-07-28 23:42 ` Paolo Bonzini 2018-07-30 16:43 ` Pu Wen 2018-07-31 7:38 ` Paolo Bonzini 2018-07-31 10:46 ` Pu Wen 2018-07-28 23:42 ` Paolo Bonzini
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