* [PATCH 1/2] drm/i915/icl: Add TBT checks for PLL calculations
@ 2018-07-26 23:35 Anusha Srivatsa
2018-07-26 23:35 ` [PATCH 2/2] drm/i915/icl: Set TBT IO in Aux transaction Anusha Srivatsa
` (4 more replies)
0 siblings, 5 replies; 10+ messages in thread
From: Anusha Srivatsa @ 2018-07-26 23:35 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, Paulo Zanoni
Add missing TBT check in the Pll calculation.
v2: do not use a auxiliary function to check if status is
TBT or not. (Paulo)
v3: Code style changes. (Paulo)
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 7e5e6eb..20c9068 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -2866,6 +2866,8 @@ static struct intel_shared_dpll *
icl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
struct intel_encoder *encoder)
{
+ struct intel_digital_port *intel_dig_port =
+ enc_to_dig_port(&encoder->base);
struct intel_shared_dpll *pll;
struct intel_dpll_hw_state pll_state = {};
enum port port = encoder->port;
@@ -2885,7 +2887,7 @@ icl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
case PORT_D:
case PORT_E:
case PORT_F:
- if (0 /* TODO: TBT PLLs */) {
+ if (intel_dig_port->tc_type == TC_PORT_TBT) {
min = DPLL_ID_ICL_TBTPLL;
max = min;
ret = icl_calc_dpll_state(crtc_state, encoder, clock,
--
2.7.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 2/2] drm/i915/icl: Set TBT IO in Aux transaction
2018-07-26 23:35 [PATCH 1/2] drm/i915/icl: Add TBT checks for PLL calculations Anusha Srivatsa
@ 2018-07-26 23:35 ` Anusha Srivatsa
2018-07-27 20:57 ` Paulo Zanoni
2018-07-27 0:18 ` ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/icl: Add TBT checks for PLL calculations Patchwork
` (3 subsequent siblings)
4 siblings, 1 reply; 10+ messages in thread
From: Anusha Srivatsa @ 2018-07-26 23:35 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
For a TBT sequence, we need to set the IO type to TBT
in DDI_AUX_CTL.
v2: Avoid duplications.(Paulo)
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_dp.c | 26 +++++++++++++++++---------
2 files changed, 18 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5530c47..7bdc214 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5558,6 +5558,7 @@ enum {
#define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL (1 << 14)
#define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL (1 << 13)
#define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL (1 << 12)
+#define DP_AUX_CH_CTL_TBT_IO (1 << 11)
#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5)
#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
#define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index cc33d7c..7c60e17 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1208,15 +1208,23 @@ static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
int send_bytes,
uint32_t unused)
{
- return DP_AUX_CH_CTL_SEND_BUSY |
- DP_AUX_CH_CTL_DONE |
- DP_AUX_CH_CTL_INTERRUPT |
- DP_AUX_CH_CTL_TIME_OUT_ERROR |
- DP_AUX_CH_CTL_TIME_OUT_MAX |
- DP_AUX_CH_CTL_RECEIVE_ERROR |
- (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
- DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
- DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ uint32_t ret;
+
+ ret = DP_AUX_CH_CTL_SEND_BUSY |
+ DP_AUX_CH_CTL_DONE |
+ DP_AUX_CH_CTL_INTERRUPT |
+ DP_AUX_CH_CTL_TIME_OUT_ERROR |
+ DP_AUX_CH_CTL_TIME_OUT_MAX |
+ DP_AUX_CH_CTL_RECEIVE_ERROR |
+ (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
+ DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
+ DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
+
+ if (intel_dig_port->tc_type == TC_PORT_TBT)
+ ret |= DP_AUX_CH_CTL_TBT_IO;
+
+ return ret;
}
static int
--
2.7.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread
* ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/icl: Add TBT checks for PLL calculations
2018-07-26 23:35 [PATCH 1/2] drm/i915/icl: Add TBT checks for PLL calculations Anusha Srivatsa
2018-07-26 23:35 ` [PATCH 2/2] drm/i915/icl: Set TBT IO in Aux transaction Anusha Srivatsa
@ 2018-07-27 0:18 ` Patchwork
2018-07-27 20:56 ` [PATCH 1/2] " Paulo Zanoni
` (2 subsequent siblings)
4 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2018-07-27 0:18 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915/icl: Add TBT checks for PLL calculations
URL : https://patchwork.freedesktop.org/series/47309/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4554 -> Patchwork_9786 =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_9786 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_9786, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/47309/revisions/1/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_9786:
=== IGT changes ===
==== Possible regressions ====
igt@drv_getparams_basic@basic-eu-total:
fi-kbl-7560u: PASS -> INCOMPLETE
== Known issues ==
Here are the changes found in Patchwork_9786 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@drv_selftest@live_workarounds:
fi-skl-6700hq: PASS -> DMESG-FAIL (fdo#107292)
igt@kms_busy@basic-flip-a:
fi-kbl-r: PASS -> DMESG-WARN (fdo#105602)
==== Possible fixes ====
igt@kms_chamelium@dp-edid-read:
fi-kbl-7500u: FAIL (fdo#103841) -> PASS
igt@kms_flip@basic-flip-vs-modeset:
fi-skl-6700hq: DMESG-WARN (fdo#105998) -> PASS
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
fi-snb-2520m: INCOMPLETE (fdo#103713) -> PASS
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841
fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602
fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998
fdo#107292 https://bugs.freedesktop.org/show_bug.cgi?id=107292
== Participating hosts (50 -> 43) ==
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-icl-u fi-byt-clapper
== Build changes ==
* Linux: CI_DRM_4554 -> Patchwork_9786
CI_DRM_4554: 5ce2e0fe88bd5a3615abb7289ab98d487201c450 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4576: bcb37a9b20eeec97f15fac2222408cc2e0b77631 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9786: d10692dfab80c00fe4aca1c39f38ffeacb5962f3 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
d10692dfab80 drm/i915/icl: Set TBT IO in Aux transaction
f3a6b3c581eb drm/i915/icl: Add TBT checks for PLL calculations
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9786/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/2] drm/i915/icl: Add TBT checks for PLL calculations
2018-07-26 23:35 [PATCH 1/2] drm/i915/icl: Add TBT checks for PLL calculations Anusha Srivatsa
2018-07-26 23:35 ` [PATCH 2/2] drm/i915/icl: Set TBT IO in Aux transaction Anusha Srivatsa
2018-07-27 0:18 ` ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/icl: Add TBT checks for PLL calculations Patchwork
@ 2018-07-27 20:56 ` Paulo Zanoni
2018-07-27 22:52 ` ✓ Fi.CI.BAT: success for series starting with [1/2] " Patchwork
2018-07-28 2:10 ` ✓ Fi.CI.IGT: " Patchwork
4 siblings, 0 replies; 10+ messages in thread
From: Paulo Zanoni @ 2018-07-27 20:56 UTC (permalink / raw)
To: Anusha Srivatsa, intel-gfx; +Cc: Lucas De Marchi
Em Qui, 2018-07-26 às 16:35 -0700, Anusha Srivatsa escreveu:
> Add missing TBT check in the Pll calculation.
>
> v2: do not use a auxiliary function to check if status is
> TBT or not. (Paulo)
>
> v3: Code style changes. (Paulo)
>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 7e5e6eb..20c9068 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -2866,6 +2866,8 @@ static struct intel_shared_dpll *
> icl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state
> *crtc_state,
> struct intel_encoder *encoder)
> {
> + struct intel_digital_port *intel_dig_port =
> + enc_to_dig_port(&encoder->base);
> struct intel_shared_dpll *pll;
> struct intel_dpll_hw_state pll_state = {};
> enum port port = encoder->port;
> @@ -2885,7 +2887,7 @@ icl_get_dpll(struct intel_crtc *crtc, struct
> intel_crtc_state *crtc_state,
> case PORT_D:
> case PORT_E:
> case PORT_F:
> - if (0 /* TODO: TBT PLLs */) {
> + if (intel_dig_port->tc_type == TC_PORT_TBT) {
> min = DPLL_ID_ICL_TBTPLL;
> max = min;
> ret = icl_calc_dpll_state(crtc_state,
> encoder, clock,
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 2/2] drm/i915/icl: Set TBT IO in Aux transaction
2018-07-26 23:35 ` [PATCH 2/2] drm/i915/icl: Set TBT IO in Aux transaction Anusha Srivatsa
@ 2018-07-27 20:57 ` Paulo Zanoni
0 siblings, 0 replies; 10+ messages in thread
From: Paulo Zanoni @ 2018-07-27 20:57 UTC (permalink / raw)
To: Anusha Srivatsa, intel-gfx
Em Qui, 2018-07-26 às 16:35 -0700, Anusha Srivatsa escreveu:
> For a TBT sequence, we need to set the IO type to TBT
> in DDI_AUX_CTL.
>
> v2: Avoid duplications.(Paulo)
>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_dp.c | 26 +++++++++++++++++---------
> 2 files changed, 18 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 5530c47..7bdc214 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5558,6 +5558,7 @@ enum {
> #define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL (1 << 14)
> #define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL (1 << 13)
> #define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL (1 << 12)
> +#define DP_AUX_CH_CTL_TBT_IO (1 << 11)
> #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5)
> #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
> #define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1)
> diff --git a/drivers/gpu/drm/i915/intel_dp.c
> b/drivers/gpu/drm/i915/intel_dp.c
> index cc33d7c..7c60e17 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1208,15 +1208,23 @@ static uint32_t skl_get_aux_send_ctl(struct
> intel_dp *intel_dp,
> int send_bytes,
> uint32_t unused)
> {
> - return DP_AUX_CH_CTL_SEND_BUSY |
> - DP_AUX_CH_CTL_DONE |
> - DP_AUX_CH_CTL_INTERRUPT |
> - DP_AUX_CH_CTL_TIME_OUT_ERROR |
> - DP_AUX_CH_CTL_TIME_OUT_MAX |
> - DP_AUX_CH_CTL_RECEIVE_ERROR |
> - (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
> - DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
> - DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
> + struct intel_digital_port *intel_dig_port =
> dp_to_dig_port(intel_dp);
> + uint32_t ret;
> +
> + ret = DP_AUX_CH_CTL_SEND_BUSY |
> + DP_AUX_CH_CTL_DONE |
> + DP_AUX_CH_CTL_INTERRUPT |
> + DP_AUX_CH_CTL_TIME_OUT_ERROR |
> + DP_AUX_CH_CTL_TIME_OUT_MAX |
> + DP_AUX_CH_CTL_RECEIVE_ERROR |
> + (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
> + DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
> + DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
> +
> + if (intel_dig_port->tc_type == TC_PORT_TBT)
> + ret |= DP_AUX_CH_CTL_TBT_IO;
> +
> + return ret;
> }
>
> static int
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/icl: Add TBT checks for PLL calculations
2018-07-26 23:35 [PATCH 1/2] drm/i915/icl: Add TBT checks for PLL calculations Anusha Srivatsa
` (2 preceding siblings ...)
2018-07-27 20:56 ` [PATCH 1/2] " Paulo Zanoni
@ 2018-07-27 22:52 ` Patchwork
2018-07-28 2:10 ` ✓ Fi.CI.IGT: " Patchwork
4 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2018-07-27 22:52 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915/icl: Add TBT checks for PLL calculations
URL : https://patchwork.freedesktop.org/series/47309/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4568 -> Patchwork_9799 =
== Summary - SUCCESS ==
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/47309/revisions/1/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_9799:
=== IGT changes ===
==== Possible regressions ====
igt@drv_selftest@live_requests:
{fi-kbl-8809g}: PASS -> INCOMPLETE
== Known issues ==
Here are the changes found in Patchwork_9799 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@drv_selftest@live_workarounds:
{fi-kbl-8809g}: PASS -> DMESG-FAIL (fdo#107292)
igt@kms_frontbuffer_tracking@basic:
fi-hsw-peppy: PASS -> DMESG-FAIL (fdo#106103, fdo#102614)
==== Possible fixes ====
igt@drv_selftest@live_workarounds:
fi-cfl-8700k: DMESG-FAIL (fdo#107292) -> PASS
{fi-cfl-8109u}: DMESG-FAIL (fdo#107292) -> PASS
igt@prime_vgem@basic-fence-flip:
fi-ilk-650: FAIL (fdo#104008) -> PASS
==== Warnings ====
igt@drv_selftest@live_workarounds:
fi-cnl-psr: DMESG-WARN (fdo#105395) -> DMESG-FAIL (fdo#107292)
{igt@kms_psr@primary_page_flip}:
fi-cnl-psr: DMESG-WARN (fdo#107372) -> DMESG-FAIL (fdo#107372)
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008
fdo#105395 https://bugs.freedesktop.org/show_bug.cgi?id=105395
fdo#106103 https://bugs.freedesktop.org/show_bug.cgi?id=106103
fdo#107292 https://bugs.freedesktop.org/show_bug.cgi?id=107292
fdo#107372 https://bugs.freedesktop.org/show_bug.cgi?id=107372
== Participating hosts (52 -> 46) ==
Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper
== Build changes ==
* Linux: CI_DRM_4568 -> Patchwork_9799
CI_DRM_4568: f679d412a2fad0988a8e7335942fd9fb47d323b8 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4580: f1c868dae24056ebc27e4f3c197724ce9b956a8a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9799: b264f254b534432c8fc7ebabe7a1ec75891a55f5 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
b264f254b534 drm/i915/icl: Set TBT IO in Aux transaction
46d829e29b14 drm/i915/icl: Add TBT checks for PLL calculations
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9799/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/icl: Add TBT checks for PLL calculations
2018-07-26 23:35 [PATCH 1/2] drm/i915/icl: Add TBT checks for PLL calculations Anusha Srivatsa
` (3 preceding siblings ...)
2018-07-27 22:52 ` ✓ Fi.CI.BAT: success for series starting with [1/2] " Patchwork
@ 2018-07-28 2:10 ` Patchwork
4 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2018-07-28 2:10 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915/icl: Add TBT checks for PLL calculations
URL : https://patchwork.freedesktop.org/series/47309/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4568_full -> Patchwork_9799_full =
== Summary - SUCCESS ==
No regressions found.
== Known issues ==
Here are the changes found in Patchwork_9799_full that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
shard-glk: PASS -> FAIL (fdo#105363)
igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
shard-hsw: PASS -> FAIL (fdo#100368)
==== Possible fixes ====
igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
shard-hsw: FAIL (fdo#102887) -> PASS
igt@kms_flip@2x-plain-flip-fb-recreate:
shard-glk: FAIL (fdo#100368) -> PASS
igt@kms_flip@modeset-vs-vblank-race-interruptible:
shard-glk: FAIL (fdo#103060) -> PASS
shard-hsw: FAIL (fdo#103060) -> PASS
igt@kms_flip@plain-flip-fb-recreate-interruptible:
shard-hsw: FAIL (fdo#100368) -> PASS
igt@kms_setmode@basic:
shard-apl: FAIL (fdo#99912) -> PASS
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
== Participating hosts (5 -> 5) ==
No changes in participating hosts
== Build changes ==
* Linux: CI_DRM_4568 -> Patchwork_9799
CI_DRM_4568: f679d412a2fad0988a8e7335942fd9fb47d323b8 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4580: f1c868dae24056ebc27e4f3c197724ce9b956a8a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9799: b264f254b534432c8fc7ebabe7a1ec75891a55f5 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9799/shards.html
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^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/2] drm/i915/icl: Add TBT checks for PLL calculations
2018-07-25 22:41 ` Paulo Zanoni
@ 2018-07-26 23:18 ` Srivatsa, Anusha
0 siblings, 0 replies; 10+ messages in thread
From: Srivatsa, Anusha @ 2018-07-26 23:18 UTC (permalink / raw)
To: Zanoni, Paulo R, intel-gfx; +Cc: De Marchi, Lucas
>-----Original Message-----
>From: Zanoni, Paulo R
>Sent: Wednesday, July 25, 2018 3:41 PM
>To: Srivatsa, Anusha <anusha.srivatsa@intel.com>; intel-
>gfx@lists.freedesktop.org
>Cc: De Marchi, Lucas <lucas.demarchi@intel.com>
>Subject: Re: [PATCH 1/2] drm/i915/icl: Add TBT checks for PLL calculations
>
>Em Qua, 2018-07-25 às 14:28 -0700, Anusha Srivatsa escreveu:
>> Add missing TBT check in the Pll calculation.
>>
>> v2: do not use a auxiliary function to check if status is TBT or not.
>> (Paulo)
>>
>> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
>> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>> ---
>> drivers/gpu/drm/i915/intel_dpll_mgr.c | 6 +++++-
>> 1 file changed, 5 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
>> b/drivers/gpu/drm/i915/intel_dpll_mgr.c
>> index 7e5e6eb..ba49078 100644
>> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
>> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
>> @@ -428,6 +428,7 @@ ibx_get_dpll(struct intel_crtc *crtc, struct
>> intel_crtc_state *crtc_state,
>> struct intel_encoder *encoder)
>> {
>> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> +
>> struct intel_shared_dpll *pll;
>> enum intel_dpll_id i;
>>
>
>This chunk does nothing and the space introduced is even against our coding
>style. Please review your own patches before submitting them to the mailing list:
>this is the kind of error that's very easy to catch by looking at the patch file,
>saving everybody's time.
>
Oops :(
Agreed.
>
>> @@ -2866,6 +2867,9 @@ static struct intel_shared_dpll *
>> icl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state
>> *crtc_state,
>> struct intel_encoder *encoder)
>> {
>> + struct intel_digital_port *intel_dig_port =
>> + enc_to_dig_port(&encoder->base);
>> +
>
>This chunk also adds a blank line that goes against our coding style.
>
Will take care!
Thanks,
Anusha
>
>> struct intel_shared_dpll *pll;
>> struct intel_dpll_hw_state pll_state = {};
>> enum port port = encoder->port;
>> @@ -2885,7 +2889,7 @@ icl_get_dpll(struct intel_crtc *crtc, struct
>> intel_crtc_state *crtc_state,
>> case PORT_D:
>> case PORT_E:
>> case PORT_F:
>> - if (0 /* TODO: TBT PLLs */) {
>> + if (intel_dig_port->tc_type == TC_PORT_TBT) {
>> min = DPLL_ID_ICL_TBTPLL;
>> max = min;
>> ret = icl_calc_dpll_state(crtc_state, encoder, clock,
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^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/2] drm/i915/icl: Add TBT checks for PLL calculations
2018-07-25 21:28 [PATCH 1/2] " Anusha Srivatsa
@ 2018-07-25 22:41 ` Paulo Zanoni
2018-07-26 23:18 ` Srivatsa, Anusha
0 siblings, 1 reply; 10+ messages in thread
From: Paulo Zanoni @ 2018-07-25 22:41 UTC (permalink / raw)
To: Anusha Srivatsa, intel-gfx; +Cc: Lucas De Marchi
Em Qua, 2018-07-25 às 14:28 -0700, Anusha Srivatsa escreveu:
> Add missing TBT check in the Pll calculation.
>
> v2: do not use a auxiliary function to check if status is
> TBT or not. (Paulo)
>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 7e5e6eb..ba49078 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -428,6 +428,7 @@ ibx_get_dpll(struct intel_crtc *crtc, struct
> intel_crtc_state *crtc_state,
> struct intel_encoder *encoder)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +
> struct intel_shared_dpll *pll;
> enum intel_dpll_id i;
>
This chunk does nothing and the space introduced is even against our
coding style. Please review your own patches before submitting them to
the mailing list: this is the kind of error that's very easy to catch
by looking at the patch file, saving everybody's time.
> @@ -2866,6 +2867,9 @@ static struct intel_shared_dpll *
> icl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state
> *crtc_state,
> struct intel_encoder *encoder)
> {
> + struct intel_digital_port *intel_dig_port =
> + enc_to_dig_port(&encoder->base);
> +
This chunk also adds a blank line that goes against our coding style.
> struct intel_shared_dpll *pll;
> struct intel_dpll_hw_state pll_state = {};
> enum port port = encoder->port;
> @@ -2885,7 +2889,7 @@ icl_get_dpll(struct intel_crtc *crtc, struct
> intel_crtc_state *crtc_state,
> case PORT_D:
> case PORT_E:
> case PORT_F:
> - if (0 /* TODO: TBT PLLs */) {
> + if (intel_dig_port->tc_type == TC_PORT_TBT) {
> min = DPLL_ID_ICL_TBTPLL;
> max = min;
> ret = icl_calc_dpll_state(crtc_state,
> encoder, clock,
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^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 1/2] drm/i915/icl: Add TBT checks for PLL calculations
@ 2018-07-25 21:28 Anusha Srivatsa
2018-07-25 22:41 ` Paulo Zanoni
0 siblings, 1 reply; 10+ messages in thread
From: Anusha Srivatsa @ 2018-07-25 21:28 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, Paulo Zanoni
Add missing TBT check in the Pll calculation.
v2: do not use a auxiliary function to check if status is
TBT or not. (Paulo)
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 7e5e6eb..ba49078 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -428,6 +428,7 @@ ibx_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+
struct intel_shared_dpll *pll;
enum intel_dpll_id i;
@@ -2866,6 +2867,9 @@ static struct intel_shared_dpll *
icl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
struct intel_encoder *encoder)
{
+ struct intel_digital_port *intel_dig_port =
+ enc_to_dig_port(&encoder->base);
+
struct intel_shared_dpll *pll;
struct intel_dpll_hw_state pll_state = {};
enum port port = encoder->port;
@@ -2885,7 +2889,7 @@ icl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
case PORT_D:
case PORT_E:
case PORT_F:
- if (0 /* TODO: TBT PLLs */) {
+ if (intel_dig_port->tc_type == TC_PORT_TBT) {
min = DPLL_ID_ICL_TBTPLL;
max = min;
ret = icl_calc_dpll_state(crtc_state, encoder, clock,
--
2.7.4
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^ permalink raw reply related [flat|nested] 10+ messages in thread
end of thread, other threads:[~2018-07-28 2:10 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-07-26 23:35 [PATCH 1/2] drm/i915/icl: Add TBT checks for PLL calculations Anusha Srivatsa
2018-07-26 23:35 ` [PATCH 2/2] drm/i915/icl: Set TBT IO in Aux transaction Anusha Srivatsa
2018-07-27 20:57 ` Paulo Zanoni
2018-07-27 0:18 ` ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/icl: Add TBT checks for PLL calculations Patchwork
2018-07-27 20:56 ` [PATCH 1/2] " Paulo Zanoni
2018-07-27 22:52 ` ✓ Fi.CI.BAT: success for series starting with [1/2] " Patchwork
2018-07-28 2:10 ` ✓ Fi.CI.IGT: " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2018-07-25 21:28 [PATCH 1/2] " Anusha Srivatsa
2018-07-25 22:41 ` Paulo Zanoni
2018-07-26 23:18 ` Srivatsa, Anusha
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