[PATCH 1/2] drm/i915: Unmask user interrupts writes into HWSP on snb/ivb/vlv/hsw

[PATCH 1/2] drm/i915: Unmask user interrupts writes into HWSP on snb/ivb/vlv/hsw

[Chris Wilson]

An oddity occurs on Sandybridge, Ivybridge and Haswell (and presumably
Valleyview) in that for the period following the GPU restart after a
reset, there are no GT interrupts received. From Ville's notes, bit 0 in
the HWSTAM corresponds to the render interrupt, and if we unmask it we
do see immediate resumption of GT interrupt delivery (via the master irq
handler) after the reset.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107500
Fixes: c5498089463b ("drm/i915: Mask everything in ring HWSTAM on gen6+ in ringbuffer mode")
References: d420a50c21ef ("drm/i915: Clean up the HWSTAM mess")
Testcase: igt/gem_eio/reset-stress
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 8003cef767ba..9b526b0f755a 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -388,7 +388,7 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
 	}
 
 	if (INTEL_GEN(dev_priv) >= 6)
-		I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
+		I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xfffffffe);
 
 	I915_WRITE(mmio, engine->status_page.ggtt_offset);
 	POSTING_READ(mmio);
-- 
2.18.0

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[PATCH 2/2] drm/i915: Remove extra waiter kick on legacy resets

[Chris Wilson]

Now with a more efficacious workaround for the lost interrupts after
reset, we can remove the hack of kicking the waiters after reset. The
issue was that the kick only worked for the immediate window after the
reset (those seqno that would complete in the time it took for the
waiter thread to perform its check) but miss any seqno that lacked an
interrupt afterwards.

References: 39f3be162c46 ("drm/i915: Kick waiters on resetting legacy rings")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 9b526b0f755a..2702347f9433 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -527,8 +527,6 @@ static int init_ring_common(struct intel_engine_cs *engine)
 	if (INTEL_GEN(dev_priv) > 2)
 		I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));
 
-	/* Papering over lost _interrupts_ immediately following the restart */
-	intel_engine_wakeup(engine);
 out:
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 
-- 
2.18.0

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✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: Unmask user interrupts writes into HWSP on snb/ivb/vlv/hsw

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915: Unmask user interrupts writes into HWSP on snb/ivb/vlv/hsw
URL   : https://patchwork.freedesktop.org/series/47845/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
6fc98f5ea250 drm/i915: Unmask user interrupts writes into HWSP on snb/ivb/vlv/hsw
-:19: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit d420a50c21ef ("drm/i915: Clean up the HWSTAM mess")'
#19: 
References: d420a50c21ef ("drm/i915: Clean up the HWSTAM mess")

total: 1 errors, 0 warnings, 0 checks, 8 lines checked
76eb69888c0b drm/i915: Remove extra waiter kick on legacy resets
-:16: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#16: 
References: 39f3be162c46 ("drm/i915: Kick waiters on resetting legacy rings")

-:16: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit 39f3be162c46 ("drm/i915: Kick waiters on resetting legacy rings")'
#16: 
References: 39f3be162c46 ("drm/i915: Kick waiters on resetting legacy rings")

total: 1 errors, 1 warnings, 0 checks, 8 lines checked

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✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Unmask user interrupts writes into HWSP on snb/ivb/vlv/hsw

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915: Unmask user interrupts writes into HWSP on snb/ivb/vlv/hsw
URL   : https://patchwork.freedesktop.org/series/47845/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4630 -> Patchwork_9876 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/47845/revisions/1/mbox/

== Known issues ==

  Here are the changes found in Patchwork_9876 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@debugfs_test@read_all_entries:
      fi-snb-2520m:       PASS -> INCOMPLETE (fdo#103713)

    igt@drv_selftest@live_hangcheck:
      fi-skl-6260u:       PASS -> DMESG-FAIL (fdo#106560, fdo#107174)

    igt@drv_selftest@live_workarounds:
      {fi-kbl-8809g}:     PASS -> DMESG-FAIL (fdo#107292)

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
      {fi-byt-clapper}:   PASS -> FAIL (fdo#103191, fdo#107362)

    igt@prime_vgem@basic-fence-flip:
      fi-ilk-650:         PASS -> FAIL (fdo#104008)

    
    ==== Possible fixes ====

    igt@drv_selftest@live_coherency:
      fi-gdg-551:         DMESG-FAIL (fdo#107164) -> PASS

    igt@drv_selftest@live_workarounds:
      {fi-cfl-8109u}:     DMESG-FAIL (fdo#107292) -> PASS

    igt@kms_pipe_crc_basic@read-crc-pipe-b-frame-sequence:
      {fi-byt-clapper}:   FAIL (fdo#103191, fdo#107362) -> PASS

    
    ==== Warnings ====

    {igt@kms_psr@primary_page_flip}:
      fi-cnl-psr:         DMESG-WARN (fdo#107372) -> DMESG-FAIL (fdo#107372)

    
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
  fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008
  fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560
  fdo#107164 https://bugs.freedesktop.org/show_bug.cgi?id=107164
  fdo#107174 https://bugs.freedesktop.org/show_bug.cgi?id=107174
  fdo#107292 https://bugs.freedesktop.org/show_bug.cgi?id=107292
  fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
  fdo#107372 https://bugs.freedesktop.org/show_bug.cgi?id=107372


== Participating hosts (52 -> 48) ==

  Missing    (4): fi-ctg-p8600 fi-ilk-m540 fi-bsw-cyan fi-hsw-4200u 


== Build changes ==

    * Linux: CI_DRM_4630 -> Patchwork_9876

  CI_DRM_4630: c2cb1ea0083a18ca6a3e6aad41fd55b7f7c12af5 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4587: 5d78c73d871525ec9caecd88ad7d9abe36637314 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9876: 76eb69888c0bc0297fcf3af01b911f88130dbdb8 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

76eb69888c0b drm/i915: Remove extra waiter kick on legacy resets
6fc98f5ea250 drm/i915: Unmask user interrupts writes into HWSP on snb/ivb/vlv/hsw

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9876/issues.html
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✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915: Unmask user interrupts writes into HWSP on snb/ivb/vlv/hsw

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915: Unmask user interrupts writes into HWSP on snb/ivb/vlv/hsw
URL   : https://patchwork.freedesktop.org/series/47845/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4630_full -> Patchwork_9876_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_9876_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9876_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_9876_full:

  === IGT changes ===

    ==== Warnings ====

    igt@pm_rc6_residency@rc6-accuracy:
      shard-snb:          PASS -> SKIP

    
== Known issues ==

  Here are the changes found in Patchwork_9876_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@kms_atomic_transition@2x-modeset-transitions-nonblocking:
      shard-hsw:          PASS -> DMESG-WARN (fdo#102614)

    igt@kms_cursor_crc@cursor-128x128-suspend:
      shard-glk:          PASS -> FAIL (fdo#103375)

    igt@kms_cursor_legacy@flip-vs-cursor-atomic:
      shard-glk:          PASS -> FAIL (fdo#102670)

    igt@kms_cursor_legacy@pipe-c-torture-bo:
      shard-glk:          PASS -> DMESG-WARN (fdo#107122)

    igt@kms_flip@flip-vs-expired-vblank-interruptible:
      shard-kbl:          PASS -> FAIL (fdo#105363, fdo#102887)

    igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
      shard-snb:          NOTRUN -> INCOMPLETE (fdo#105411)

    igt@kms_setmode@basic:
      shard-apl:          PASS -> FAIL (fdo#99912)

    igt@perf@polling:
      shard-hsw:          PASS -> FAIL (fdo#102252)

    
    ==== Possible fixes ====

    igt@gem_eio@reset-stress:
      shard-hsw:          FAIL (fdo#107500) -> PASS

    igt@perf_pmu@busy-accuracy-50-bcs0:
      shard-snb:          INCOMPLETE (fdo#105411) -> SKIP

    
  fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
  fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
  fdo#102670 https://bugs.freedesktop.org/show_bug.cgi?id=102670
  fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
  fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411
  fdo#107122 https://bugs.freedesktop.org/show_bug.cgi?id=107122
  fdo#107500 https://bugs.freedesktop.org/show_bug.cgi?id=107500
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (5 -> 5) ==

  No changes in participating hosts


== Build changes ==

    * Linux: CI_DRM_4630 -> Patchwork_9876

  CI_DRM_4630: c2cb1ea0083a18ca6a3e6aad41fd55b7f7c12af5 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4587: 5d78c73d871525ec9caecd88ad7d9abe36637314 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9876: 76eb69888c0bc0297fcf3af01b911f88130dbdb8 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9876/shards.html
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Re: [PATCH 1/2] drm/i915: Unmask user interrupts writes into HWSP on snb/ivb/vlv/hsw

[Mika Kuoppala]

Chris Wilson <chris@chris-wilson.co.uk> writes:

> An oddity occurs on Sandybridge, Ivybridge and Haswell (and presumably
> Valleyview) in that for the period following the GPU restart after a
> reset, there are no GT interrupts received. From Ville's notes, bit 0 in
> the HWSTAM corresponds to the render interrupt, and if we unmask it we
> do see immediate resumption of GT interrupt delivery (via the master irq
> handler) after the reset.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107500
> Fixes: c5498089463b ("drm/i915: Mask everything in ring HWSTAM on gen6+ in ringbuffer mode")
> References: d420a50c21ef ("drm/i915: Clean up the HWSTAM mess")
> Testcase: igt/gem_eio/reset-stress
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 8003cef767ba..9b526b0f755a 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -388,7 +388,7 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
>  	}
>  
>  	if (INTEL_GEN(dev_priv) >= 6)
> -		I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
> +		I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xfffffffe);

Yeah bit 0 is MI_USER_INTERRUPT on render. And execlists keeps all masked.

There are bits for other engines too so add more paranoia?
-Mika
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Re: [PATCH 1/2] drm/i915: Unmask user interrupts writes into HWSP on snb/ivb/vlv/hsw

[Chris Wilson]

Quoting Mika Kuoppala (2018-08-08 09:35:51)
> Chris Wilson <chris@chris-wilson.co.uk> writes:
> 
> > An oddity occurs on Sandybridge, Ivybridge and Haswell (and presumably
> > Valleyview) in that for the period following the GPU restart after a
> > reset, there are no GT interrupts received. From Ville's notes, bit 0 in
> > the HWSTAM corresponds to the render interrupt, and if we unmask it we
> > do see immediate resumption of GT interrupt delivery (via the master irq
> > handler) after the reset.
> >
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107500
> > Fixes: c5498089463b ("drm/i915: Mask everything in ring HWSTAM on gen6+ in ringbuffer mode")
> > References: d420a50c21ef ("drm/i915: Clean up the HWSTAM mess")
> > Testcase: igt/gem_eio/reset-stress
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > index 8003cef767ba..9b526b0f755a 100644
> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > @@ -388,7 +388,7 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
> >       }
> >  
> >       if (INTEL_GEN(dev_priv) >= 6)
> > -             I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
> > +             I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xfffffffe);
> 
> Yeah bit 0 is MI_USER_INTERRUPT on render. And execlists keeps all masked.
> 
> There are bits for other engines too so add more paranoia?

It's per ring though?
-Chris
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Re: [PATCH 1/2] drm/i915: Unmask user interrupts writes into HWSP on snb/ivb/vlv/hsw

[Mika Kuoppala]

Chris Wilson <chris@chris-wilson.co.uk> writes:

> Quoting Mika Kuoppala (2018-08-08 09:35:51)
>> Chris Wilson <chris@chris-wilson.co.uk> writes:
>> 
>> > An oddity occurs on Sandybridge, Ivybridge and Haswell (and presumably
>> > Valleyview) in that for the period following the GPU restart after a
>> > reset, there are no GT interrupts received. From Ville's notes, bit 0 in
>> > the HWSTAM corresponds to the render interrupt, and if we unmask it we
>> > do see immediate resumption of GT interrupt delivery (via the master irq
>> > handler) after the reset.
>> >
>> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107500
>> > Fixes: c5498089463b ("drm/i915: Mask everything in ring HWSTAM on gen6+ in ringbuffer mode")
>> > References: d420a50c21ef ("drm/i915: Clean up the HWSTAM mess")
>> > Testcase: igt/gem_eio/reset-stress
>> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> > ---
>> >  drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +-
>> >  1 file changed, 1 insertion(+), 1 deletion(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
>> > index 8003cef767ba..9b526b0f755a 100644
>> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
>> > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
>> > @@ -388,7 +388,7 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
>> >       }
>> >  
>> >       if (INTEL_GEN(dev_priv) >= 6)
>> > -             I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
>> > +             I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xfffffffe);
>> 
>> Yeah bit 0 is MI_USER_INTERRUPT on render. And execlists keeps all masked.
>> 
>> There are bits for other engines too so add more paranoia?
>
> It's per ring though?

It is, I was reading on wrong era (ilk).
And found a table where the hardware status write isr change bits
are and bit0 is an user interrupt.

This is so unexpected that please add a comment to the code also
that this is for after reset interrupt delivery weirdness.

Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
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Re: [PATCH 2/2] drm/i915: Remove extra waiter kick on legacy resets

[Mika Kuoppala]

Chris Wilson <chris@chris-wilson.co.uk> writes:

> Now with a more efficacious workaround for the lost interrupts after
> reset, we can remove the hack of kicking the waiters after reset. The
> issue was that the kick only worked for the immediate window after the
> reset (those seqno that would complete in the time it took for the
> waiter thread to perform its check) but miss any seqno that lacked an
> interrupt afterwards.
>
> References: 39f3be162c46 ("drm/i915: Kick waiters on resetting legacy rings")
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Matthew Auld <matthew.auld@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>

Hack or a safety mechanism... But if we have straightened out
the dents in here, more strict discipline is ok.

Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 2 --
>  1 file changed, 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 9b526b0f755a..2702347f9433 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -527,8 +527,6 @@ static int init_ring_common(struct intel_engine_cs *engine)
>  	if (INTEL_GEN(dev_priv) > 2)
>  		I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));
>  
> -	/* Papering over lost _interrupts_ immediately following the restart */
> -	intel_engine_wakeup(engine);
>  out:
>  	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
>  
> -- 
> 2.18.0
>
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Re: [PATCH 1/2] drm/i915: Unmask user interrupts writes into HWSP on snb/ivb/vlv/hsw

[Chris Wilson]

Quoting Mika Kuoppala (2018-08-08 09:35:51)
> Chris Wilson <chris@chris-wilson.co.uk> writes:
> 
> > An oddity occurs on Sandybridge, Ivybridge and Haswell (and presumably
> > Valleyview) in that for the period following the GPU restart after a
> > reset, there are no GT interrupts received. From Ville's notes, bit 0 in
> > the HWSTAM corresponds to the render interrupt, and if we unmask it we
> > do see immediate resumption of GT interrupt delivery (via the master irq
> > handler) after the reset.
> >
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107500
> > Fixes: c5498089463b ("drm/i915: Mask everything in ring HWSTAM on gen6+ in ringbuffer mode")
> > References: d420a50c21ef ("drm/i915: Clean up the HWSTAM mess")
> > Testcase: igt/gem_eio/reset-stress
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > index 8003cef767ba..9b526b0f755a 100644
> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > @@ -388,7 +388,7 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
> >       }
> >  
> >       if (INTEL_GEN(dev_priv) >= 6)
> > -             I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
> > +             I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xfffffffe);
> 
> Yeah bit 0 is MI_USER_INTERRUPT on render. And execlists keeps all masked.

Fwiw, I checked to see if this would help speed up interrupt delivery to
userspace; no, no difference as far as I can measure.
-Chris
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