* [U-Boot] [PATCH v4 1/2] armv8: layerscape: move ns_dev[] define from h to c file.
@ 2018-08-10 6:59 Ran Wang
2018-08-10 7:00 ` [U-Boot] [PATCH v4 2/2] armv8: layerscape: Enable EHCI access for LS1012A Ran Wang
2018-08-13 16:35 ` [U-Boot] [PATCH v4 1/2] armv8: layerscape: move ns_dev[] define from h to c file York Sun
0 siblings, 2 replies; 3+ messages in thread
From: Ran Wang @ 2018-08-10 6:59 UTC (permalink / raw)
To: u-boot
Since more c files will include ns_access.h, this move will fix some
compiling warnings and make it sense.
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
---
Change in v4:
- Apply same move for ls102xa
Change in v3:
- New file
.../include/asm/arch-fsl-layerscape/ns_access.h | 80 ----------
arch/arm/include/asm/arch-ls102xa/ns_access.h | 84 -----------
board/freescale/common/ns_access.c | 167 +++++++++++++++++++++
3 files changed, 167 insertions(+), 164 deletions(-)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
index 8ecff4d..2bbfab7 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
@@ -87,84 +87,4 @@ enum csu_cslx_ind {
CSU_CSLX_DSCR = 121,
};
-static struct csu_ns_dev ns_dev[] = {
- {CSU_CSLX_PCIE2_IO, CSU_ALL_RW},
- {CSU_CSLX_PCIE1_IO, CSU_ALL_RW},
- {CSU_CSLX_MG2TPR_IP, CSU_ALL_RW},
- {CSU_CSLX_IFC_MEM, CSU_ALL_RW},
- {CSU_CSLX_OCRAM, CSU_ALL_RW},
- {CSU_CSLX_GIC, CSU_ALL_RW},
- {CSU_CSLX_PCIE1, CSU_ALL_RW},
- {CSU_CSLX_OCRAM2, CSU_ALL_RW},
- {CSU_CSLX_QSPI_MEM, CSU_ALL_RW},
- {CSU_CSLX_PCIE2, CSU_ALL_RW},
- {CSU_CSLX_SATA, CSU_ALL_RW},
- {CSU_CSLX_USB1, CSU_ALL_RW},
- {CSU_CSLX_QM_BM_SWPORTAL, CSU_ALL_RW},
- {CSU_CSLX_PCIE3, CSU_ALL_RW},
- {CSU_CSLX_PCIE3_IO, CSU_ALL_RW},
- {CSU_CSLX_USB3, CSU_ALL_RW},
- {CSU_CSLX_USB2, CSU_ALL_RW},
- {CSU_CSLX_PFE, CSU_ALL_RW},
- {CSU_CSLX_SERDES, CSU_ALL_RW},
- {CSU_CSLX_QDMA, CSU_ALL_RW},
- {CSU_CSLX_LPUART2, CSU_ALL_RW},
- {CSU_CSLX_LPUART1, CSU_ALL_RW},
- {CSU_CSLX_LPUART4, CSU_ALL_RW},
- {CSU_CSLX_LPUART3, CSU_ALL_RW},
- {CSU_CSLX_LPUART6, CSU_ALL_RW},
- {CSU_CSLX_LPUART5, CSU_ALL_RW},
- {CSU_CSLX_DSPI1, CSU_ALL_RW},
- {CSU_CSLX_QSPI, CSU_ALL_RW},
- {CSU_CSLX_ESDHC, CSU_ALL_RW},
- {CSU_CSLX_IFC, CSU_ALL_RW},
- {CSU_CSLX_I2C1, CSU_ALL_RW},
- {CSU_CSLX_I2C3, CSU_ALL_RW},
- {CSU_CSLX_I2C2, CSU_ALL_RW},
- {CSU_CSLX_DUART2, CSU_ALL_RW},
- {CSU_CSLX_DUART1, CSU_ALL_RW},
- {CSU_CSLX_WDT2, CSU_ALL_RW},
- {CSU_CSLX_WDT1, CSU_ALL_RW},
- {CSU_CSLX_EDMA, CSU_ALL_RW},
- {CSU_CSLX_SYS_CNT, CSU_ALL_RW},
- {CSU_CSLX_DMA_MUX2, CSU_ALL_RW},
- {CSU_CSLX_DMA_MUX1, CSU_ALL_RW},
- {CSU_CSLX_DDR, CSU_ALL_RW},
- {CSU_CSLX_QUICC, CSU_ALL_RW},
- {CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW},
- {CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW},
- {CSU_CSLX_SFP, CSU_ALL_RW},
- {CSU_CSLX_TMU, CSU_ALL_RW},
- {CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW},
- {CSU_CSLX_SCFG, CSU_ALL_RW},
- {CSU_CSLX_FM, CSU_ALL_RW},
- {CSU_CSLX_SEC5_5, CSU_ALL_RW},
- {CSU_CSLX_BM, CSU_ALL_RW},
- {CSU_CSLX_QM, CSU_ALL_RW},
- {CSU_CSLX_GPIO2, CSU_ALL_RW},
- {CSU_CSLX_GPIO1, CSU_ALL_RW},
- {CSU_CSLX_GPIO4, CSU_ALL_RW},
- {CSU_CSLX_GPIO3, CSU_ALL_RW},
- {CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW},
- {CSU_CSLX_CSU, CSU_ALL_RW},
- {CSU_CSLX_IIC4, CSU_ALL_RW},
- {CSU_CSLX_WDT4, CSU_ALL_RW},
- {CSU_CSLX_WDT3, CSU_ALL_RW},
- {CSU_CSLX_ESDHC2, CSU_ALL_RW},
- {CSU_CSLX_WDT5, CSU_ALL_RW},
- {CSU_CSLX_SAI2, CSU_ALL_RW},
- {CSU_CSLX_SAI1, CSU_ALL_RW},
- {CSU_CSLX_SAI4, CSU_ALL_RW},
- {CSU_CSLX_SAI3, CSU_ALL_RW},
- {CSU_CSLX_FTM2, CSU_ALL_RW},
- {CSU_CSLX_FTM1, CSU_ALL_RW},
- {CSU_CSLX_FTM4, CSU_ALL_RW},
- {CSU_CSLX_FTM3, CSU_ALL_RW},
- {CSU_CSLX_FTM6, CSU_ALL_RW},
- {CSU_CSLX_FTM5, CSU_ALL_RW},
- {CSU_CSLX_FTM8, CSU_ALL_RW},
- {CSU_CSLX_FTM7, CSU_ALL_RW},
- {CSU_CSLX_DSCR, CSU_ALL_RW},
-};
-
#endif
diff --git a/arch/arm/include/asm/arch-ls102xa/ns_access.h b/arch/arm/include/asm/arch-ls102xa/ns_access.h
index f414b73..b6daf32 100644
--- a/arch/arm/include/asm/arch-ls102xa/ns_access.h
+++ b/arch/arm/include/asm/arch-ls102xa/ns_access.h
@@ -91,88 +91,4 @@ enum csu_cslx_ind {
CSU_CSLX_MAX,
};
-static struct csu_ns_dev ns_dev[] = {
- { CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
- { CSU_CSLX_PCIE1_IO, CSU_ALL_RW },
- { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW },
- { CSU_CSLX_IFC_MEM, CSU_ALL_RW },
- { CSU_CSLX_OCRAM, CSU_ALL_RW },
- { CSU_CSLX_GIC, CSU_ALL_RW },
- { CSU_CSLX_PCIE1, CSU_ALL_RW },
- { CSU_CSLX_OCRAM2, CSU_ALL_RW },
- { CSU_CSLX_QSPI_MEM, CSU_ALL_RW },
- { CSU_CSLX_PCIE2, CSU_ALL_RW },
- { CSU_CSLX_SATA, CSU_ALL_RW },
- { CSU_CSLX_USB3, CSU_ALL_RW },
- { CSU_CSLX_SERDES, CSU_ALL_RW },
- { CSU_CSLX_QDMA, CSU_ALL_RW },
- { CSU_CSLX_LPUART2, CSU_ALL_RW },
- { CSU_CSLX_LPUART1, CSU_ALL_RW },
- { CSU_CSLX_LPUART4, CSU_ALL_RW },
- { CSU_CSLX_LPUART3, CSU_ALL_RW },
- { CSU_CSLX_LPUART6, CSU_ALL_RW },
- { CSU_CSLX_LPUART5, CSU_ALL_RW },
- { CSU_CSLX_DSPI2, CSU_ALL_RW },
- { CSU_CSLX_DSPI1, CSU_ALL_RW },
- { CSU_CSLX_QSPI, CSU_ALL_RW },
- { CSU_CSLX_ESDHC, CSU_ALL_RW },
- { CSU_CSLX_2D_ACE, CSU_ALL_RW },
- { CSU_CSLX_IFC, CSU_ALL_RW },
- { CSU_CSLX_I2C1, CSU_ALL_RW },
- { CSU_CSLX_USB2, CSU_ALL_RW },
- { CSU_CSLX_I2C3, CSU_ALL_RW },
- { CSU_CSLX_I2C2, CSU_ALL_RW },
- { CSU_CSLX_DUART2, CSU_ALL_RW },
- { CSU_CSLX_DUART1, CSU_ALL_RW },
- { CSU_CSLX_WDT2, CSU_ALL_RW },
- { CSU_CSLX_WDT1, CSU_ALL_RW },
- { CSU_CSLX_EDMA, CSU_ALL_RW },
- { CSU_CSLX_SYS_CNT, CSU_ALL_RW },
- { CSU_CSLX_DMA_MUX2, CSU_ALL_RW },
- { CSU_CSLX_DMA_MUX1, CSU_ALL_RW },
- { CSU_CSLX_DDR, CSU_ALL_RW },
- { CSU_CSLX_QUICC, CSU_ALL_RW },
- { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW },
- { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW },
- { CSU_CSLX_SFP, CSU_ALL_RW },
- { CSU_CSLX_TMU, CSU_ALL_RW },
- { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW },
- { CSU_CSLX_RESERVED0, CSU_ALL_RW },
- { CSU_CSLX_ETSEC1, CSU_ALL_RW },
- { CSU_CSLX_SEC5_5, CSU_ALL_RW },
- { CSU_CSLX_ETSEC3, CSU_ALL_RW },
- { CSU_CSLX_ETSEC2, CSU_ALL_RW },
- { CSU_CSLX_GPIO2, CSU_ALL_RW },
- { CSU_CSLX_GPIO1, CSU_ALL_RW },
- { CSU_CSLX_GPIO4, CSU_ALL_RW },
- { CSU_CSLX_GPIO3, CSU_ALL_RW },
- { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW },
- { CSU_CSLX_CSU, CSU_ALL_RW },
- { CSU_CSLX_ASRC, CSU_ALL_RW },
- { CSU_CSLX_SPDIF, CSU_ALL_RW },
- { CSU_CSLX_FLEXCAN2, CSU_ALL_RW },
- { CSU_CSLX_FLEXCAN1, CSU_ALL_RW },
- { CSU_CSLX_FLEXCAN4, CSU_ALL_RW },
- { CSU_CSLX_FLEXCAN3, CSU_ALL_RW },
- { CSU_CSLX_SAI2, CSU_ALL_RW },
- { CSU_CSLX_SAI1, CSU_ALL_RW },
- { CSU_CSLX_SAI4, CSU_ALL_RW },
- { CSU_CSLX_SAI3, CSU_ALL_RW },
- { CSU_CSLX_FTM2, CSU_ALL_RW },
- { CSU_CSLX_FTM1, CSU_ALL_RW },
- { CSU_CSLX_FTM4, CSU_ALL_RW },
- { CSU_CSLX_FTM3, CSU_ALL_RW },
- { CSU_CSLX_FTM6, CSU_ALL_RW },
- { CSU_CSLX_FTM5, CSU_ALL_RW },
- { CSU_CSLX_FTM8, CSU_ALL_RW },
- { CSU_CSLX_FTM7, CSU_ALL_RW },
- { CSU_CSLX_COP_DCSR, CSU_ALL_RW },
- { CSU_CSLX_EPU, CSU_ALL_RW },
- { CSU_CSLX_GDI, CSU_ALL_RW },
- { CSU_CSLX_DDI, CSU_ALL_RW },
- { CSU_CSLX_RESERVED1, CSU_ALL_RW },
- { CSU_CSLX_USB3_PHY, CSU_ALL_RW },
- { CSU_CSLX_RESERVED2, CSU_ALL_RW },
-};
-
#endif
diff --git a/board/freescale/common/ns_access.c b/board/freescale/common/ns_access.c
index 79fa6aa..0e6f213 100644
--- a/board/freescale/common/ns_access.c
+++ b/board/freescale/common/ns_access.c
@@ -9,6 +9,173 @@
#include <asm/arch/ns_access.h>
#include <asm/arch/fsl_serdes.h>
+#ifdef CONFIG_ARCH_LS1021A
+static struct csu_ns_dev ns_dev[] = {
+ { CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
+ { CSU_CSLX_PCIE1_IO, CSU_ALL_RW },
+ { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW },
+ { CSU_CSLX_IFC_MEM, CSU_ALL_RW },
+ { CSU_CSLX_OCRAM, CSU_ALL_RW },
+ { CSU_CSLX_GIC, CSU_ALL_RW },
+ { CSU_CSLX_PCIE1, CSU_ALL_RW },
+ { CSU_CSLX_OCRAM2, CSU_ALL_RW },
+ { CSU_CSLX_QSPI_MEM, CSU_ALL_RW },
+ { CSU_CSLX_PCIE2, CSU_ALL_RW },
+ { CSU_CSLX_SATA, CSU_ALL_RW },
+ { CSU_CSLX_USB3, CSU_ALL_RW },
+ { CSU_CSLX_SERDES, CSU_ALL_RW },
+ { CSU_CSLX_QDMA, CSU_ALL_RW },
+ { CSU_CSLX_LPUART2, CSU_ALL_RW },
+ { CSU_CSLX_LPUART1, CSU_ALL_RW },
+ { CSU_CSLX_LPUART4, CSU_ALL_RW },
+ { CSU_CSLX_LPUART3, CSU_ALL_RW },
+ { CSU_CSLX_LPUART6, CSU_ALL_RW },
+ { CSU_CSLX_LPUART5, CSU_ALL_RW },
+ { CSU_CSLX_DSPI2, CSU_ALL_RW },
+ { CSU_CSLX_DSPI1, CSU_ALL_RW },
+ { CSU_CSLX_QSPI, CSU_ALL_RW },
+ { CSU_CSLX_ESDHC, CSU_ALL_RW },
+ { CSU_CSLX_2D_ACE, CSU_ALL_RW },
+ { CSU_CSLX_IFC, CSU_ALL_RW },
+ { CSU_CSLX_I2C1, CSU_ALL_RW },
+ { CSU_CSLX_USB2, CSU_ALL_RW },
+ { CSU_CSLX_I2C3, CSU_ALL_RW },
+ { CSU_CSLX_I2C2, CSU_ALL_RW },
+ { CSU_CSLX_DUART2, CSU_ALL_RW },
+ { CSU_CSLX_DUART1, CSU_ALL_RW },
+ { CSU_CSLX_WDT2, CSU_ALL_RW },
+ { CSU_CSLX_WDT1, CSU_ALL_RW },
+ { CSU_CSLX_EDMA, CSU_ALL_RW },
+ { CSU_CSLX_SYS_CNT, CSU_ALL_RW },
+ { CSU_CSLX_DMA_MUX2, CSU_ALL_RW },
+ { CSU_CSLX_DMA_MUX1, CSU_ALL_RW },
+ { CSU_CSLX_DDR, CSU_ALL_RW },
+ { CSU_CSLX_QUICC, CSU_ALL_RW },
+ { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW },
+ { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW },
+ { CSU_CSLX_SFP, CSU_ALL_RW },
+ { CSU_CSLX_TMU, CSU_ALL_RW },
+ { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW },
+ { CSU_CSLX_RESERVED0, CSU_ALL_RW },
+ { CSU_CSLX_ETSEC1, CSU_ALL_RW },
+ { CSU_CSLX_SEC5_5, CSU_ALL_RW },
+ { CSU_CSLX_ETSEC3, CSU_ALL_RW },
+ { CSU_CSLX_ETSEC2, CSU_ALL_RW },
+ { CSU_CSLX_GPIO2, CSU_ALL_RW },
+ { CSU_CSLX_GPIO1, CSU_ALL_RW },
+ { CSU_CSLX_GPIO4, CSU_ALL_RW },
+ { CSU_CSLX_GPIO3, CSU_ALL_RW },
+ { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW },
+ { CSU_CSLX_CSU, CSU_ALL_RW },
+ { CSU_CSLX_ASRC, CSU_ALL_RW },
+ { CSU_CSLX_SPDIF, CSU_ALL_RW },
+ { CSU_CSLX_FLEXCAN2, CSU_ALL_RW },
+ { CSU_CSLX_FLEXCAN1, CSU_ALL_RW },
+ { CSU_CSLX_FLEXCAN4, CSU_ALL_RW },
+ { CSU_CSLX_FLEXCAN3, CSU_ALL_RW },
+ { CSU_CSLX_SAI2, CSU_ALL_RW },
+ { CSU_CSLX_SAI1, CSU_ALL_RW },
+ { CSU_CSLX_SAI4, CSU_ALL_RW },
+ { CSU_CSLX_SAI3, CSU_ALL_RW },
+ { CSU_CSLX_FTM2, CSU_ALL_RW },
+ { CSU_CSLX_FTM1, CSU_ALL_RW },
+ { CSU_CSLX_FTM4, CSU_ALL_RW },
+ { CSU_CSLX_FTM3, CSU_ALL_RW },
+ { CSU_CSLX_FTM6, CSU_ALL_RW },
+ { CSU_CSLX_FTM5, CSU_ALL_RW },
+ { CSU_CSLX_FTM8, CSU_ALL_RW },
+ { CSU_CSLX_FTM7, CSU_ALL_RW },
+ { CSU_CSLX_COP_DCSR, CSU_ALL_RW },
+ { CSU_CSLX_EPU, CSU_ALL_RW },
+ { CSU_CSLX_GDI, CSU_ALL_RW },
+ { CSU_CSLX_DDI, CSU_ALL_RW },
+ { CSU_CSLX_RESERVED1, CSU_ALL_RW },
+ { CSU_CSLX_USB3_PHY, CSU_ALL_RW },
+ { CSU_CSLX_RESERVED2, CSU_ALL_RW },
+};
+
+#else
+static struct csu_ns_dev ns_dev[] = {
+ {CSU_CSLX_PCIE2_IO, CSU_ALL_RW},
+ {CSU_CSLX_PCIE1_IO, CSU_ALL_RW},
+ {CSU_CSLX_MG2TPR_IP, CSU_ALL_RW},
+ {CSU_CSLX_IFC_MEM, CSU_ALL_RW},
+ {CSU_CSLX_OCRAM, CSU_ALL_RW},
+ {CSU_CSLX_GIC, CSU_ALL_RW},
+ {CSU_CSLX_PCIE1, CSU_ALL_RW},
+ {CSU_CSLX_OCRAM2, CSU_ALL_RW},
+ {CSU_CSLX_QSPI_MEM, CSU_ALL_RW},
+ {CSU_CSLX_PCIE2, CSU_ALL_RW},
+ {CSU_CSLX_SATA, CSU_ALL_RW},
+ {CSU_CSLX_USB1, CSU_ALL_RW},
+ {CSU_CSLX_QM_BM_SWPORTAL, CSU_ALL_RW},
+ {CSU_CSLX_PCIE3, CSU_ALL_RW},
+ {CSU_CSLX_PCIE3_IO, CSU_ALL_RW},
+ {CSU_CSLX_USB3, CSU_ALL_RW},
+ {CSU_CSLX_USB2, CSU_ALL_RW},
+ {CSU_CSLX_PFE, CSU_ALL_RW},
+ {CSU_CSLX_SERDES, CSU_ALL_RW},
+ {CSU_CSLX_QDMA, CSU_ALL_RW},
+ {CSU_CSLX_LPUART2, CSU_ALL_RW},
+ {CSU_CSLX_LPUART1, CSU_ALL_RW},
+ {CSU_CSLX_LPUART4, CSU_ALL_RW},
+ {CSU_CSLX_LPUART3, CSU_ALL_RW},
+ {CSU_CSLX_LPUART6, CSU_ALL_RW},
+ {CSU_CSLX_LPUART5, CSU_ALL_RW},
+ {CSU_CSLX_DSPI1, CSU_ALL_RW},
+ {CSU_CSLX_QSPI, CSU_ALL_RW},
+ {CSU_CSLX_ESDHC, CSU_ALL_RW},
+ {CSU_CSLX_IFC, CSU_ALL_RW},
+ {CSU_CSLX_I2C1, CSU_ALL_RW},
+ {CSU_CSLX_I2C3, CSU_ALL_RW},
+ {CSU_CSLX_I2C2, CSU_ALL_RW},
+ {CSU_CSLX_DUART2, CSU_ALL_RW},
+ {CSU_CSLX_DUART1, CSU_ALL_RW},
+ {CSU_CSLX_WDT2, CSU_ALL_RW},
+ {CSU_CSLX_WDT1, CSU_ALL_RW},
+ {CSU_CSLX_EDMA, CSU_ALL_RW},
+ {CSU_CSLX_SYS_CNT, CSU_ALL_RW},
+ {CSU_CSLX_DMA_MUX2, CSU_ALL_RW},
+ {CSU_CSLX_DMA_MUX1, CSU_ALL_RW},
+ {CSU_CSLX_DDR, CSU_ALL_RW},
+ {CSU_CSLX_QUICC, CSU_ALL_RW},
+ {CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW},
+ {CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW},
+ {CSU_CSLX_SFP, CSU_ALL_RW},
+ {CSU_CSLX_TMU, CSU_ALL_RW},
+ {CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW},
+ {CSU_CSLX_SCFG, CSU_ALL_RW},
+ {CSU_CSLX_FM, CSU_ALL_RW},
+ {CSU_CSLX_SEC5_5, CSU_ALL_RW},
+ {CSU_CSLX_BM, CSU_ALL_RW},
+ {CSU_CSLX_QM, CSU_ALL_RW},
+ {CSU_CSLX_GPIO2, CSU_ALL_RW},
+ {CSU_CSLX_GPIO1, CSU_ALL_RW},
+ {CSU_CSLX_GPIO4, CSU_ALL_RW},
+ {CSU_CSLX_GPIO3, CSU_ALL_RW},
+ {CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW},
+ {CSU_CSLX_CSU, CSU_ALL_RW},
+ {CSU_CSLX_IIC4, CSU_ALL_RW},
+ {CSU_CSLX_WDT4, CSU_ALL_RW},
+ {CSU_CSLX_WDT3, CSU_ALL_RW},
+ {CSU_CSLX_ESDHC2, CSU_ALL_RW},
+ {CSU_CSLX_WDT5, CSU_ALL_RW},
+ {CSU_CSLX_SAI2, CSU_ALL_RW},
+ {CSU_CSLX_SAI1, CSU_ALL_RW},
+ {CSU_CSLX_SAI4, CSU_ALL_RW},
+ {CSU_CSLX_SAI3, CSU_ALL_RW},
+ {CSU_CSLX_FTM2, CSU_ALL_RW},
+ {CSU_CSLX_FTM1, CSU_ALL_RW},
+ {CSU_CSLX_FTM4, CSU_ALL_RW},
+ {CSU_CSLX_FTM3, CSU_ALL_RW},
+ {CSU_CSLX_FTM6, CSU_ALL_RW},
+ {CSU_CSLX_FTM5, CSU_ALL_RW},
+ {CSU_CSLX_FTM8, CSU_ALL_RW},
+ {CSU_CSLX_FTM7, CSU_ALL_RW},
+ {CSU_CSLX_DSCR, CSU_ALL_RW},
+};
+#endif
+
void set_devices_ns_access(unsigned long index, u16 val)
{
u32 *base = (u32 *)CONFIG_SYS_FSL_CSU_ADDR;
--
2.7.4
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [U-Boot] [PATCH v4 2/2] armv8: layerscape: Enable EHCI access for LS1012A
2018-08-10 6:59 [U-Boot] [PATCH v4 1/2] armv8: layerscape: move ns_dev[] define from h to c file Ran Wang
@ 2018-08-10 7:00 ` Ran Wang
2018-08-13 16:35 ` [U-Boot] [PATCH v4 1/2] armv8: layerscape: move ns_dev[] define from h to c file York Sun
1 sibling, 0 replies; 3+ messages in thread
From: Ran Wang @ 2018-08-10 7:00 UTC (permalink / raw)
To: u-boot
Program Central Security Unit (CSU) to grant access
permission for USB 2.0 controller, otherwiase EHCI funciton will down.
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
---
Change in v4:
- None
Change in v3:
- None
Change in v2:
- Add EL checking code to make sure related programming only happen
in EL3
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 9 +++++++++
arch/arm/include/asm/arch-fsl-layerscape/ns_access.h | 1 +
2 files changed, 10 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 8028d52..4ef6eb6 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -11,6 +11,7 @@
#include <asm/io.h>
#include <asm/global_data.h>
#include <asm/arch-fsl-layerscape/config.h>
+#include <asm/arch-fsl-layerscape/ns_access.h>
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
#include <fsl_csu.h>
#endif
@@ -614,6 +615,14 @@ void fsl_lsch2_early_init_f(void)
CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
}
+ /*
+ * Program Central Security Unit (CSU) to grant access
+ * permission for USB 2.0 controller
+ */
+#if defined(CONFIG_ARCH_LS1012A) && defined(CONFIG_USB_EHCI_FSL)
+ if (current_el() == 3)
+ set_devices_ns_access(CSU_CSLX_USB_2, CSU_ALL_RW);
+#endif
/* Erratum */
erratum_a008850_early(); /* part 1 of 2 */
erratum_a009929();
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
index 2bbfab7..a265106 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
@@ -39,6 +39,7 @@ enum csu_cslx_ind {
CSU_CSLX_ESDHC,
CSU_CSLX_IFC = 45,
CSU_CSLX_I2C1,
+ CSU_CSLX_USB_2,
CSU_CSLX_I2C3 = 48,
CSU_CSLX_I2C2,
CSU_CSLX_DUART2 = 50,
--
2.7.4
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [U-Boot] [PATCH v4 1/2] armv8: layerscape: move ns_dev[] define from h to c file.
2018-08-10 6:59 [U-Boot] [PATCH v4 1/2] armv8: layerscape: move ns_dev[] define from h to c file Ran Wang
2018-08-10 7:00 ` [U-Boot] [PATCH v4 2/2] armv8: layerscape: Enable EHCI access for LS1012A Ran Wang
@ 2018-08-13 16:35 ` York Sun
1 sibling, 0 replies; 3+ messages in thread
From: York Sun @ 2018-08-13 16:35 UTC (permalink / raw)
To: u-boot
On 08/10/2018 12:00 AM, Ran Wang wrote:
> Since more c files will include ns_access.h, this move will fix some
> compiling warnings and make it sense.
>
> Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
> ---
> Change in v4:
> - Apply same move for ls102xa
>
> Change in v3:
> - New file
>
This set is applied to fsl-qoriq master, awaiting upstream.
Thanks.
York
^ permalink raw reply [flat|nested] 3+ messages in thread
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2018-08-10 6:59 [U-Boot] [PATCH v4 1/2] armv8: layerscape: move ns_dev[] define from h to c file Ran Wang
2018-08-10 7:00 ` [U-Boot] [PATCH v4 2/2] armv8: layerscape: Enable EHCI access for LS1012A Ran Wang
2018-08-13 16:35 ` [U-Boot] [PATCH v4 1/2] armv8: layerscape: move ns_dev[] define from h to c file York Sun
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