[PATCH] perf/x86/amd/uncore: Set ThreadMask and SliceMask for L3 Cache perf events

[PATCH] perf/x86/amd/uncore: Set ThreadMask and SliceMask for L3 Cache perf events

[Janakarajan Natarajan]

In Family 17h, some L3 Cache Performance events require the ThreadMask
and SliceMask to be set. For other events, these fields do not affect
the count either way.

Set ThreadMask and SliceMask to 0xFF and 0xF respectively.

Signed-off-by: Janakarajan Natarajan <Janakarajan.Natarajan@amd.com>
---
 arch/x86/events/amd/uncore.c      | 10 ++++++++++
 arch/x86/include/asm/perf_event.h |  8 ++++++++
 2 files changed, 18 insertions(+)

diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c
index 981ba5e..8671de1 100644
--- a/arch/x86/events/amd/uncore.c
+++ b/arch/x86/events/amd/uncore.c
@@ -36,6 +36,7 @@
 
 static int num_counters_llc;
 static int num_counters_nb;
+static bool l3_mask;
 
 static HLIST_HEAD(uncore_unused_list);
 
@@ -209,6 +210,13 @@ static int amd_uncore_event_init(struct perf_event *event)
 	hwc->config = event->attr.config & AMD64_RAW_EVENT_MASK_NB;
 	hwc->idx = -1;
 
+	/*
+	 * SliceMask and ThreadMask need to be set for certain L3 events in
+	 * Family 17h. For other events, the two fields do not affect the count.
+	 */
+	if (l3_mask)
+		hwc->config |= (AMD64_L3_SLICE_MASK | AMD64_L3_THREAD_MASK);
+
 	if (event->cpu < 0)
 		return -EINVAL;
 
@@ -525,6 +533,7 @@ static int __init amd_uncore_init(void)
 		amd_llc_pmu.name	  = "amd_l3";
 		format_attr_event_df.show = &event_show_df;
 		format_attr_event_l3.show = &event_show_l3;
+		l3_mask			  = true;
 	} else {
 		num_counters_nb		  = NUM_COUNTERS_NB;
 		num_counters_llc	  = NUM_COUNTERS_L2;
@@ -532,6 +541,7 @@ static int __init amd_uncore_init(void)
 		amd_llc_pmu.name	  = "amd_l2";
 		format_attr_event_df	  = format_attr_event;
 		format_attr_event_l3	  = format_attr_event;
+		l3_mask			  = false;
 	}
 
 	amd_nb_pmu.attr_groups	= amd_uncore_attr_groups_df;
diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index 12f5408..f15d51b 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -46,6 +46,14 @@
 #define INTEL_ARCH_EVENT_MASK	\
 	(ARCH_PERFMON_EVENTSEL_UMASK | ARCH_PERFMON_EVENTSEL_EVENT)
 
+#define AMD64_L3_SLICE_SHIFT				48
+#define AMD64_L3_SLICE_MASK				\
+	((0xFUL) << AMD64_L3_SLICE_SHIFT)
+
+#define AMD64_L3_THREAD_SHIFT				56
+#define AMD64_L3_THREAD_MASK				\
+	((0xFFUL) << AMD64_L3_THREAD_SHIFT)
+
 #define X86_RAW_EVENT_MASK		\
 	(ARCH_PERFMON_EVENTSEL_EVENT |	\
 	 ARCH_PERFMON_EVENTSEL_UMASK |	\
-- 
2.7.4

Re: [PATCH] perf/x86/amd/uncore: Set ThreadMask and SliceMask for L3 Cache perf events

[kbuild test robot]

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Hi Janakarajan,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on tip/perf/core]
[also build test WARNING on v4.18 next-20180813]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Janakarajan-Natarajan/perf-x86-amd-uncore-Set-ThreadMask-and-SliceMask-for-L3-Cache-perf-events/20180814-064324
config: i386-randconfig-x002-201832 (attached as .config)
compiler: gcc-7 (Debian 7.3.0-16) 7.3.0
reproduce:
        # save the attached .config to linux build tree
        make ARCH=i386 

All warnings (new ones prefixed by >>):

   In file included from include/linux/perf_event.h:25:0,
                    from arch/x86//events/amd/uncore.c:11:
   arch/x86//events/amd/uncore.c: In function 'amd_uncore_event_init':
>> arch/x86/include/asm/perf_event.h:51:11: warning: left shift count >= width of type [-Wshift-count-overflow]
     ((0xFUL) << AMD64_L3_SLICE_SHIFT)
              ^
>> arch/x86//events/amd/uncore.c:218:19: note: in expansion of macro 'AMD64_L3_SLICE_MASK'
      hwc->config |= (AMD64_L3_SLICE_MASK | AMD64_L3_THREAD_MASK);
                      ^~~~~~~~~~~~~~~~~~~
   arch/x86/include/asm/perf_event.h:55:12: warning: left shift count >= width of type [-Wshift-count-overflow]
     ((0xFFUL) << AMD64_L3_THREAD_SHIFT)
               ^
>> arch/x86//events/amd/uncore.c:218:41: note: in expansion of macro 'AMD64_L3_THREAD_MASK'
      hwc->config |= (AMD64_L3_SLICE_MASK | AMD64_L3_THREAD_MASK);
                                            ^~~~~~~~~~~~~~~~~~~~
--
   In file included from include/linux/perf_event.h:25:0,
                    from arch/x86/events/amd/uncore.c:11:
   arch/x86/events/amd/uncore.c: In function 'amd_uncore_event_init':
>> arch/x86/include/asm/perf_event.h:51:11: warning: left shift count >= width of type [-Wshift-count-overflow]
     ((0xFUL) << AMD64_L3_SLICE_SHIFT)
              ^
   arch/x86/events/amd/uncore.c:218:19: note: in expansion of macro 'AMD64_L3_SLICE_MASK'
      hwc->config |= (AMD64_L3_SLICE_MASK | AMD64_L3_THREAD_MASK);
                      ^~~~~~~~~~~~~~~~~~~
   arch/x86/include/asm/perf_event.h:55:12: warning: left shift count >= width of type [-Wshift-count-overflow]
     ((0xFFUL) << AMD64_L3_THREAD_SHIFT)
               ^
   arch/x86/events/amd/uncore.c:218:41: note: in expansion of macro 'AMD64_L3_THREAD_MASK'
      hwc->config |= (AMD64_L3_SLICE_MASK | AMD64_L3_THREAD_MASK);
                                            ^~~~~~~~~~~~~~~~~~~~

vim +51 arch/x86/include/asm/perf_event.h

    39	
    40	#define AMD64_EVENTSEL_INT_CORE_SEL_SHIFT		37
    41	#define AMD64_EVENTSEL_INT_CORE_SEL_MASK		\
    42		(0xFULL << AMD64_EVENTSEL_INT_CORE_SEL_SHIFT)
    43	
    44	#define AMD64_EVENTSEL_EVENT	\
    45		(ARCH_PERFMON_EVENTSEL_EVENT | (0x0FULL << 32))
    46	#define INTEL_ARCH_EVENT_MASK	\
    47		(ARCH_PERFMON_EVENTSEL_UMASK | ARCH_PERFMON_EVENTSEL_EVENT)
    48	
    49	#define AMD64_L3_SLICE_SHIFT				48
    50	#define AMD64_L3_SLICE_MASK				\
  > 51		((0xFUL) << AMD64_L3_SLICE_SHIFT)
    52	

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

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