[U-Boot] [PATCH v1 0/3] Enable all asynchronous abort exceptions taken to EL3

[U-Boot] [PATCH v1 0/3] Enable all asynchronous abort exceptions taken to EL3

[chee.hong.ang at intel.com]

From: "Ang, Chee Hong" <chee.hong.ang@intel.com>

This patchset allow PSCI exception vectors to handle all external abort and
SError exception from all exception levels. This will allow EL3 to handle
asynchronous abort exceptions such as ECC DBE (Double Bit Error) taken from
OS running at lower exception level.

Chee Hong Ang (3):
  ARMv8: Enable all asynchronous abort exceptions taken to EL3
  ARMv8: Add EL3 exception handling for ARMv8's Kconfig
  ARMv8: SError exception handling in PSCI exception vectors

 arch/arm/cpu/armv8/Kconfig    |  7 +++++++
 arch/arm/cpu/armv8/psci.S     | 26 ++++++++++++++++++++++++++
 arch/arm/include/asm/macro.h  |  4 ++++
 arch/arm/include/asm/system.h |  1 +
 4 files changed, 38 insertions(+)

-- 
2.7.4

[U-Boot] [PATCH v1 1/3] ARMv8: Enable all asynchronous abort exceptions taken to EL3

[chee.hong.ang at intel.com]

From: Chee Hong Ang <chee.hong.ang@intel.com>

Allow EL3 to handle all the External Abort and SError interrupt
exception occur in all exception levels.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
---
 arch/arm/include/asm/macro.h  | 4 ++++
 arch/arm/include/asm/system.h | 1 +
 2 files changed, 5 insertions(+)

diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h
index d5a7a8b..bb33b4b 100644
--- a/arch/arm/include/asm/macro.h
+++ b/arch/arm/include/asm/macro.h
@@ -193,6 +193,10 @@ lr	.req	x30
 			SCR_EL3_SMD_DIS | SCR_EL3_RES1 |\
 			SCR_EL3_NS_EN)
 #endif
+
+#ifdef CONFIG_ARMV8_EA_EL3_FIRST
+	orr	\tmp, \tmp, #SCR_EL3_EA_EN
+#endif
 	msr	scr_el3, \tmp
 
 	/* Return to the EL2_SP2 mode from EL3 */
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index c1f87f9..aed2e3c 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -29,6 +29,7 @@
 #define SCR_EL3_HCE_EN		(1 << 8)  /* Hypervisor Call enable          */
 #define SCR_EL3_SMD_DIS		(1 << 7)  /* Secure Monitor Call disable     */
 #define SCR_EL3_RES1		(3 << 4)  /* Reserved, RES1                  */
+#define SCR_EL3_EA_EN		(1 << 3)  /* External aborts taken to EL3    */
 #define SCR_EL3_NS_EN		(1 << 0)  /* EL0 and EL1 in Non-scure state  */
 
 /*
-- 
2.7.4

[U-Boot] [PATCH v1 2/3] ARMv8: Add EL3 exception handling for ARMv8's Kconfig

[chee.hong.ang at intel.com]

From: Chee Hong Ang <chee.hong.ang@intel.com>

Kconfig option to allow all External Abort and SError exception
taken to EL3.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
---
 arch/arm/cpu/armv8/Kconfig | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index c8bebab..ff42791 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -144,6 +144,13 @@ config ARMV8_PSCI_CPUS_PER_CLUSTER
 	  A value 0 or no definition of it works for single cluster system.
 	  System with multi-cluster should difine their own exact value.
 
+config ARMV8_EA_EL3_FIRST
+	bool "External aborts and SError interrupt exception are taken in EL3"
+	default n
+	help
+	  Exception handling at all exception levels for External Abort and
+	  SError interrupt exception are taken in EL3.
+
 if SYS_HAS_ARMV8_SECURE_BASE
 
 config ARMV8_SECURE_BASE
-- 
2.7.4

[U-Boot] [PATCH v1 3/3] ARMv8: SError exception handling in PSCI exception vectors

[chee.hong.ang at intel.com]

From: Chee Hong Ang <chee.hong.ang@intel.com>

Allow platform vendors to handle SError interrupt exceptions from
ARMv8 PSCI exception vectors by overriding this weak function
'plat_error_handler'.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
---
 arch/arm/cpu/armv8/psci.S | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/arch/arm/cpu/armv8/psci.S b/arch/arm/cpu/armv8/psci.S
index 097f91b..358df8f 100644
--- a/arch/arm/cpu/armv8/psci.S
+++ b/arch/arm/cpu/armv8/psci.S
@@ -236,6 +236,28 @@ handle_sync:
 
 	b	unhandled_exception
 
+#ifdef CONFIG_ARMV8_EA_EL3_FIRST
+/*
+ * Override this function if custom error handling is
+ * needed for asynchronous aborts
+ */
+ENTRY(plat_error_handler)
+	ret
+ENDPROC(plat_error_handler)
+.weak plat_error_handler
+
+handle_error:
+	bl	psci_get_cpu_id
+	bl	psci_get_cpu_stack_top
+	mov	x9, #1
+	msr	spsel, x9
+	mov	sp, x0
+
+	bl	plat_error_handler	/* Platform specific error handling */
+deadloop:
+	b	deadloop		/* Never return */
+#endif
+
 	.align	11
 	.globl	el3_exception_vectors
 el3_exception_vectors:
@@ -261,7 +283,11 @@ el3_exception_vectors:
 	.align	7
 	b	unhandled_exception	/* FIQ, Lower EL using AArch64 */
 	.align	7
+#ifdef CONFIG_ARMV8_EA_EL3_FIRST
+	b	handle_error		/* SError, Lower EL using AArch64 */
+#else
 	b	unhandled_exception	/* SError, Lower EL using AArch64 */
+#endif
 	.align	7
 	b	unhandled_exception	/* Sync, Lower EL using AArch32 */
 	.align	7
-- 
2.7.4

[U-Boot] [U-Boot, v1, 1/3] ARMv8: Enable all asynchronous abort exceptions taken to EL3

[Tom Rini]

On Mon, Aug 20, 2018 at 10:57:34AM -0700, chee.hong.ang at intel.com wrote:

> From: Chee Hong Ang <chee.hong.ang@intel.com>
> 
> Allow EL3 to handle all the External Abort and SError interrupt
> exception occur in all exception levels.
> 
> Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>

Applied to u-boot/master, thanks!

-- 
Tom
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 819 bytes
Desc: not available
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20181117/4d46bbb5/attachment.sig>

[U-Boot] [U-Boot, v1, 2/3] ARMv8: Add EL3 exception handling for ARMv8's Kconfig

[Tom Rini]

On Mon, Aug 20, 2018 at 10:57:35AM -0700, chee.hong.ang at intel.com wrote:

> From: Chee Hong Ang <chee.hong.ang@intel.com>
> 
> Kconfig option to allow all External Abort and SError exception
> taken to EL3.
> 
> Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>

Applied to u-boot/master, thanks!

-- 
Tom
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 819 bytes
Desc: not available
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20181117/d6f800aa/attachment.sig>

[U-Boot] [U-Boot, v1, 3/3] ARMv8: SError exception handling in PSCI exception vectors

[Tom Rini]

On Mon, Aug 20, 2018 at 10:57:36AM -0700, chee.hong.ang at intel.com wrote:

> From: Chee Hong Ang <chee.hong.ang@intel.com>
> 
> Allow platform vendors to handle SError interrupt exceptions from
> ARMv8 PSCI exception vectors by overriding this weak function
> 'plat_error_handler'.
> 
> Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>

Applied to u-boot/master, thanks!

-- 
Tom
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 819 bytes
Desc: not available
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20181117/405c3c05/attachment.sig>