From: Julien Thierry <julien.thierry@arm.com> To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, daniel.thompson@linaro.org, joel@joelfernandes.org, marc.zyngier@arm.com, mark.rutland@arm.com, christoffer.dall@arm.com, james.morse@arm.com, catalin.marinas@arm.com, will.deacon@arm.com, Julien Thierry <julien.thierry@arm.com>, Oleg Nesterov <oleg@redhat.com>, Dave Martin <Dave.Martin@arm.com> Subject: [PATCH v5 11/27] arm64: Make PMR part of task context Date: Tue, 28 Aug 2018 16:51:21 +0100 [thread overview] Message-ID: <1535471497-38854-12-git-send-email-julien.thierry@arm.com> (raw) In-Reply-To: <1535471497-38854-1-git-send-email-julien.thierry@arm.com> If ICC_PMR_EL1 is used to mask interrupts, its value should be saved/restored whenever a task is context switched out/in or gets an exception. Add PMR to the registers to save in the pt_regs struct upon kernel entry, and restore it before ERET. Also, initialize it to a sane value when creating new tasks. Tested-by: Daniel Thompson <daniel.thompson@linaro.org> Signed-off-by: Julien Thierry <julien.thierry@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Oleg Nesterov <oleg@redhat.com> Cc: Dave Martin <Dave.Martin@arm.com> --- arch/arm64/include/asm/processor.h | 1 + arch/arm64/include/asm/ptrace.h | 5 ++++- arch/arm64/kernel/asm-offsets.c | 1 + arch/arm64/kernel/entry.S | 16 ++++++++++++++++ arch/arm64/kernel/process.c | 2 ++ 5 files changed, 24 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h index 79657ad..45a2e08 100644 --- a/arch/arm64/include/asm/processor.h +++ b/arch/arm64/include/asm/processor.h @@ -167,6 +167,7 @@ static inline void start_thread_common(struct pt_regs *regs, unsigned long pc) memset(regs, 0, sizeof(*regs)); forget_syscall(regs); regs->pc = pc; + regs->pmr_save = ICC_PMR_EL1_UNMASKED; } static inline void start_thread(struct pt_regs *regs, unsigned long pc, diff --git a/arch/arm64/include/asm/ptrace.h b/arch/arm64/include/asm/ptrace.h index 177b851..29ec217 100644 --- a/arch/arm64/include/asm/ptrace.h +++ b/arch/arm64/include/asm/ptrace.h @@ -25,6 +25,9 @@ #define CurrentEL_EL1 (1 << 2) #define CurrentEL_EL2 (2 << 2) +/* PMR value use to unmask interrupts */ +#define ICC_PMR_EL1_UNMASKED 0xf0 + /* AArch32-specific ptrace requests */ #define COMPAT_PTRACE_GETREGS 12 #define COMPAT_PTRACE_SETREGS 13 @@ -163,7 +166,7 @@ struct pt_regs { #endif u64 orig_addr_limit; - u64 unused; // maintain 16 byte alignment + u64 pmr_save; u64 stackframe[2]; }; diff --git a/arch/arm64/kernel/asm-offsets.c b/arch/arm64/kernel/asm-offsets.c index 323aeb5..bab4122 100644 --- a/arch/arm64/kernel/asm-offsets.c +++ b/arch/arm64/kernel/asm-offsets.c @@ -78,6 +78,7 @@ int main(void) DEFINE(S_ORIG_X0, offsetof(struct pt_regs, orig_x0)); DEFINE(S_SYSCALLNO, offsetof(struct pt_regs, syscallno)); DEFINE(S_ORIG_ADDR_LIMIT, offsetof(struct pt_regs, orig_addr_limit)); + DEFINE(S_PMR_SAVE, offsetof(struct pt_regs, pmr_save)); DEFINE(S_STACKFRAME, offsetof(struct pt_regs, stackframe)); DEFINE(S_FRAME_SIZE, sizeof(struct pt_regs)); BLANK(); diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index 85ce06ac..79b06af 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -249,6 +249,15 @@ alternative_else_nop_endif msr sp_el0, tsk .endif + /* Save pmr */ +alternative_if ARM64_HAS_IRQ_PRIO_MASKING + mrs_s x20, SYS_ICC_PMR_EL1 +alternative_else + /* Keep a sane value in the task context */ + mov x20, ICC_PMR_EL1_UNMASKED +alternative_endif + str x20, [sp, #S_PMR_SAVE] + /* * Registers that may be useful after this macro is invoked: * @@ -269,6 +278,13 @@ alternative_else_nop_endif /* No need to restore UAO, it will be restored from SPSR_EL1 */ .endif + /* Restore pmr */ +alternative_if ARM64_HAS_IRQ_PRIO_MASKING + ldr x20, [sp, #S_PMR_SAVE] + msr_s SYS_ICC_PMR_EL1, x20 + dsb sy +alternative_else_nop_endif + ldp x21, x22, [sp, #S_PC] // load ELR, SPSR .if \el == 0 ct_user_enter diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c index 7f1628e..1f6a4d5 100644 --- a/arch/arm64/kernel/process.c +++ b/arch/arm64/kernel/process.c @@ -230,6 +230,7 @@ void __show_regs(struct pt_regs *regs) } printk("sp : %016llx\n", sp); + printk("pmr_save: %08llx\n", regs->pmr_save); i = top_reg; @@ -355,6 +356,7 @@ int copy_thread(unsigned long clone_flags, unsigned long stack_start, } else { memset(childregs, 0, sizeof(struct pt_regs)); childregs->pstate = PSR_MODE_EL1h; + childregs->pmr_save = ICC_PMR_EL1_UNMASKED; if (IS_ENABLED(CONFIG_ARM64_UAO) && cpus_have_const_cap(ARM64_HAS_UAO)) childregs->pstate |= PSR_UAO_BIT; -- 1.9.1
WARNING: multiple messages have this Message-ID (diff)
From: julien.thierry@arm.com (Julien Thierry) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v5 11/27] arm64: Make PMR part of task context Date: Tue, 28 Aug 2018 16:51:21 +0100 [thread overview] Message-ID: <1535471497-38854-12-git-send-email-julien.thierry@arm.com> (raw) In-Reply-To: <1535471497-38854-1-git-send-email-julien.thierry@arm.com> If ICC_PMR_EL1 is used to mask interrupts, its value should be saved/restored whenever a task is context switched out/in or gets an exception. Add PMR to the registers to save in the pt_regs struct upon kernel entry, and restore it before ERET. Also, initialize it to a sane value when creating new tasks. Tested-by: Daniel Thompson <daniel.thompson@linaro.org> Signed-off-by: Julien Thierry <julien.thierry@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Oleg Nesterov <oleg@redhat.com> Cc: Dave Martin <Dave.Martin@arm.com> --- arch/arm64/include/asm/processor.h | 1 + arch/arm64/include/asm/ptrace.h | 5 ++++- arch/arm64/kernel/asm-offsets.c | 1 + arch/arm64/kernel/entry.S | 16 ++++++++++++++++ arch/arm64/kernel/process.c | 2 ++ 5 files changed, 24 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h index 79657ad..45a2e08 100644 --- a/arch/arm64/include/asm/processor.h +++ b/arch/arm64/include/asm/processor.h @@ -167,6 +167,7 @@ static inline void start_thread_common(struct pt_regs *regs, unsigned long pc) memset(regs, 0, sizeof(*regs)); forget_syscall(regs); regs->pc = pc; + regs->pmr_save = ICC_PMR_EL1_UNMASKED; } static inline void start_thread(struct pt_regs *regs, unsigned long pc, diff --git a/arch/arm64/include/asm/ptrace.h b/arch/arm64/include/asm/ptrace.h index 177b851..29ec217 100644 --- a/arch/arm64/include/asm/ptrace.h +++ b/arch/arm64/include/asm/ptrace.h @@ -25,6 +25,9 @@ #define CurrentEL_EL1 (1 << 2) #define CurrentEL_EL2 (2 << 2) +/* PMR value use to unmask interrupts */ +#define ICC_PMR_EL1_UNMASKED 0xf0 + /* AArch32-specific ptrace requests */ #define COMPAT_PTRACE_GETREGS 12 #define COMPAT_PTRACE_SETREGS 13 @@ -163,7 +166,7 @@ struct pt_regs { #endif u64 orig_addr_limit; - u64 unused; // maintain 16 byte alignment + u64 pmr_save; u64 stackframe[2]; }; diff --git a/arch/arm64/kernel/asm-offsets.c b/arch/arm64/kernel/asm-offsets.c index 323aeb5..bab4122 100644 --- a/arch/arm64/kernel/asm-offsets.c +++ b/arch/arm64/kernel/asm-offsets.c @@ -78,6 +78,7 @@ int main(void) DEFINE(S_ORIG_X0, offsetof(struct pt_regs, orig_x0)); DEFINE(S_SYSCALLNO, offsetof(struct pt_regs, syscallno)); DEFINE(S_ORIG_ADDR_LIMIT, offsetof(struct pt_regs, orig_addr_limit)); + DEFINE(S_PMR_SAVE, offsetof(struct pt_regs, pmr_save)); DEFINE(S_STACKFRAME, offsetof(struct pt_regs, stackframe)); DEFINE(S_FRAME_SIZE, sizeof(struct pt_regs)); BLANK(); diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index 85ce06ac..79b06af 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -249,6 +249,15 @@ alternative_else_nop_endif msr sp_el0, tsk .endif + /* Save pmr */ +alternative_if ARM64_HAS_IRQ_PRIO_MASKING + mrs_s x20, SYS_ICC_PMR_EL1 +alternative_else + /* Keep a sane value in the task context */ + mov x20, ICC_PMR_EL1_UNMASKED +alternative_endif + str x20, [sp, #S_PMR_SAVE] + /* * Registers that may be useful after this macro is invoked: * @@ -269,6 +278,13 @@ alternative_else_nop_endif /* No need to restore UAO, it will be restored from SPSR_EL1 */ .endif + /* Restore pmr */ +alternative_if ARM64_HAS_IRQ_PRIO_MASKING + ldr x20, [sp, #S_PMR_SAVE] + msr_s SYS_ICC_PMR_EL1, x20 + dsb sy +alternative_else_nop_endif + ldp x21, x22, [sp, #S_PC] // load ELR, SPSR .if \el == 0 ct_user_enter diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c index 7f1628e..1f6a4d5 100644 --- a/arch/arm64/kernel/process.c +++ b/arch/arm64/kernel/process.c @@ -230,6 +230,7 @@ void __show_regs(struct pt_regs *regs) } printk("sp : %016llx\n", sp); + printk("pmr_save: %08llx\n", regs->pmr_save); i = top_reg; @@ -355,6 +356,7 @@ int copy_thread(unsigned long clone_flags, unsigned long stack_start, } else { memset(childregs, 0, sizeof(struct pt_regs)); childregs->pstate = PSR_MODE_EL1h; + childregs->pmr_save = ICC_PMR_EL1_UNMASKED; if (IS_ENABLED(CONFIG_ARM64_UAO) && cpus_have_const_cap(ARM64_HAS_UAO)) childregs->pstate |= PSR_UAO_BIT; -- 1.9.1
next prev parent reply other threads:[~2018-08-28 15:52 UTC|newest] Thread overview: 116+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-08-28 15:51 [PATCH v5 00/27] arm64: provide pseudo NMI with GICv3 Julien Thierry 2018-08-28 15:51 ` Julien Thierry 2018-08-28 15:51 ` [PATCH v5 01/27] arm64: cpufeature: Set SYSREG_GIC_CPUIF as a boot system feature Julien Thierry 2018-08-28 15:51 ` Julien Thierry 2018-09-21 15:56 ` Marc Zyngier 2018-09-21 15:56 ` Marc Zyngier 2018-09-25 3:10 ` Yao Lihua 2018-09-25 8:13 ` Marc Zyngier 2018-09-25 8:13 ` Marc Zyngier 2018-09-25 10:39 ` Yao Lihua 2018-08-28 15:51 ` [PATCH v5 02/27] arm64: cpufeature: Use alternatives for VHE cpu_enable Julien Thierry 2018-08-28 15:51 ` Julien Thierry 2018-09-12 10:28 ` James Morse 2018-09-12 10:28 ` James Morse 2018-09-12 12:03 ` Julien Thierry 2018-09-12 12:03 ` Julien Thierry 2018-09-18 17:46 ` James Morse 2018-09-18 17:46 ` James Morse 2018-09-12 12:37 ` Suzuki K Poulose 2018-09-12 12:37 ` Suzuki K Poulose 2018-08-28 15:51 ` [PATCH v5 03/27] arm64: alternative: Apply alternatives early in boot process Julien Thierry 2018-08-28 15:51 ` Julien Thierry 2018-09-12 10:29 ` James Morse 2018-09-12 10:29 ` James Morse 2018-09-12 16:49 ` Julien Thierry 2018-09-12 16:49 ` Julien Thierry 2018-09-17 23:44 ` Daniel Thompson 2018-09-17 23:44 ` Daniel Thompson 2018-09-18 7:37 ` Julien Thierry 2018-09-18 7:37 ` Julien Thierry 2018-09-18 17:47 ` James Morse 2018-09-18 17:47 ` James Morse 2018-09-21 16:05 ` Marc Zyngier 2018-09-21 16:05 ` Marc Zyngier 2018-08-28 15:51 ` [PATCH v5 04/27] arm64: daifflags: Use irqflags functions for daifflags Julien Thierry 2018-08-28 15:51 ` Julien Thierry 2018-09-12 12:28 ` James Morse 2018-09-12 12:28 ` James Morse 2018-10-03 15:09 ` Catalin Marinas 2018-10-03 15:09 ` Catalin Marinas 2018-08-28 15:51 ` [PATCH v5 05/27] arm64: Use daifflag_restore after bp_hardening Julien Thierry 2018-08-28 15:51 ` Julien Thierry 2018-09-12 10:32 ` James Morse 2018-09-12 10:32 ` James Morse 2018-09-12 11:11 ` Julien Thierry 2018-09-12 11:11 ` Julien Thierry 2018-09-12 12:28 ` James Morse 2018-09-12 12:28 ` James Morse 2018-09-12 13:03 ` Julien Thierry 2018-09-12 13:03 ` Julien Thierry 2018-10-03 15:12 ` Catalin Marinas 2018-10-03 15:12 ` Catalin Marinas 2018-08-28 15:51 ` [PATCH v5 06/27] arm64: Delay daif masking for user return Julien Thierry 2018-08-28 15:51 ` Julien Thierry 2018-09-12 10:31 ` James Morse 2018-09-12 10:31 ` James Morse 2018-09-12 13:07 ` Julien Thierry 2018-09-12 13:07 ` Julien Thierry 2018-08-28 15:51 ` [PATCH v5 07/27] arm64: xen: Use existing helper to check interrupt status Julien Thierry 2018-08-28 15:51 ` Julien Thierry 2018-08-29 21:35 ` Stefano Stabellini 2018-08-29 21:35 ` Stefano Stabellini 2018-10-03 15:14 ` Catalin Marinas 2018-10-03 15:14 ` Catalin Marinas 2018-08-28 15:51 ` [PATCH v5 08/27] irqchip/gic: Unify GIC priority definitions Julien Thierry 2018-08-28 15:51 ` Julien Thierry 2018-10-03 9:24 ` Marc Zyngier 2018-10-03 9:24 ` Marc Zyngier 2018-08-28 15:51 ` [PATCH v5 09/27] irqchip/gic: Lower priority of GIC interrupts Julien Thierry 2018-08-28 15:51 ` Julien Thierry 2018-08-28 15:51 ` [PATCH v5 10/27] arm64: cpufeature: Add cpufeature for IRQ priority masking Julien Thierry 2018-08-28 15:51 ` Julien Thierry 2018-08-28 15:51 ` Julien Thierry [this message] 2018-08-28 15:51 ` [PATCH v5 11/27] arm64: Make PMR part of task context Julien Thierry 2018-08-28 15:51 ` [PATCH v5 12/27] arm64: Unmask PMR before going idle Julien Thierry 2018-08-28 15:51 ` Julien Thierry 2018-08-28 15:51 ` [PATCH v5 13/27] arm/arm64: gic-v3: Add helper functions to manage IRQ priorities Julien Thierry 2018-08-28 15:51 ` Julien Thierry 2018-08-28 15:51 ` [PATCH v5 14/27] arm64: kvm: Unmask PMR before entering guest Julien Thierry 2018-08-28 15:51 ` Julien Thierry 2018-08-28 15:51 ` [PATCH v5 15/27] arm64: irqflags: Use ICC_PMR_EL1 for interrupt masking Julien Thierry 2018-08-28 15:51 ` Julien Thierry 2018-09-21 17:39 ` Julien Thierry 2018-09-21 17:39 ` Julien Thierry 2018-09-21 17:55 ` Julien Thierry 2018-09-21 17:55 ` Julien Thierry 2018-08-28 15:51 ` [PATCH v5 16/27] arm64: daifflags: Include PMR in daifflags restore operations Julien Thierry 2018-08-28 15:51 ` Julien Thierry 2018-08-28 15:51 ` [PATCH v5 17/27] irqchip/gic-v3: Factor group0 detection into functions Julien Thierry 2018-08-28 15:51 ` Julien Thierry 2018-08-28 15:51 ` [PATCH v5 18/27] irqchip/gic-v3: Do not overwrite PMR value Julien Thierry 2018-08-28 15:51 ` Julien Thierry 2018-08-28 15:51 ` [PATCH v5 19/27] irqchip/gic-v3: Remove acknowledge loop Julien Thierry 2018-08-28 15:51 ` Julien Thierry 2018-10-03 9:26 ` Marc Zyngier 2018-10-03 9:26 ` Marc Zyngier 2018-08-28 15:51 ` [PATCH v5 20/27] irqchip/gic-v3: Switch to PMR masking after IRQ acknowledge Julien Thierry 2018-08-28 15:51 ` Julien Thierry 2018-08-28 15:51 ` [PATCH v5 21/27] arm64: Switch to PMR masking when starting CPUs Julien Thierry 2018-08-28 15:51 ` Julien Thierry 2018-08-28 15:51 ` [PATCH v5 22/27] arm64: Add build option for IRQ masking via priority Julien Thierry 2018-08-28 15:51 ` Julien Thierry 2018-08-28 15:51 ` [PATCH v5 23/27] arm64: Handle serror in NMI context Julien Thierry 2018-08-28 15:51 ` Julien Thierry 2018-08-28 15:51 ` [PATCH v5 24/27] irqchip/gic-v3: Detect current view of GIC priorities Julien Thierry 2018-08-28 15:51 ` Julien Thierry 2018-08-28 15:51 ` [PATCH v5 25/27] irqchip/gic-v3: Add base support for pseudo-NMI Julien Thierry 2018-08-28 15:51 ` Julien Thierry 2018-08-28 15:51 ` [PATCH v5 26/27] irqchip/gic: Add functions to access irq priorities Julien Thierry 2018-08-28 15:51 ` Julien Thierry 2018-08-28 15:51 ` [PATCH v5 27/27] irqchip/gic-v3: Allow interrupts to be set as pseudo-NMI Julien Thierry 2018-08-28 15:51 ` Julien Thierry 2018-08-29 11:37 ` [PATCH v5 00/27] arm64: provide pseudo NMI with GICv3 Daniel Thompson 2018-08-29 11:37 ` Daniel Thompson 2018-08-29 12:58 ` Julien Thierry 2018-08-29 12:58 ` Julien Thierry
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