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From: Huacai Chen <chenhc@lemote.com>
To: Ralf Baechle <ralf@linux-mips.org>
Cc: Paul Burton <paul.burton@mips.com>,
	James Hogan <jhogan@kernel.org>,
	linux-mips@linux-mips.org, Fuxin Zhang <zhangfx@lemote.com>,
	Zhangjin Wu <wuzhangjin@gmail.com>,
	Huacai Chen <chenhuacai@gmail.com>,
	Huacai Chen <chenhc@lemote.com>
Subject: [PATCH V4 01/10] MIPS: Loongson-3: Enable Store Fill Buffer at runtime
Date: Wed,  5 Sep 2018 17:33:01 +0800	[thread overview]
Message-ID: <1536139990-11665-2-git-send-email-chenhc@lemote.com> (raw)
In-Reply-To: <1536139990-11665-1-git-send-email-chenhc@lemote.com>

New Loongson-3 (Loongson-3A R2, Loongson-3A R3, and newer) has SFB
(Store Fill Buffer) which can improve the performance of memory access.
Now, SFB enablement is controlled by CONFIG_LOONGSON3_ENHANCEMENT, and
the generic kernel has no benefit from SFB (even it is running on a new
Loongson-3 machine). With this patch, we can enable SFB at runtime by
detecting the CPU type (the expense is war_io_reorder_wmb() will always
be a 'sync', which will hurt the performance of old Loongson-3).

Signed-off-by: Huacai Chen <chenhc@lemote.com>
---
 arch/mips/include/asm/io.h                               |  2 +-
 .../mips/include/asm/mach-loongson64/kernel-entry-init.h | 16 ++++++++++++----
 2 files changed, 13 insertions(+), 5 deletions(-)

diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 44f766b..eb357c9 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -289,7 +289,7 @@ static inline void iounmap(const volatile void __iomem *addr)
 #undef __IS_KSEG1
 }
 
-#if defined(CONFIG_CPU_CAVIUM_OCTEON) || defined(CONFIG_LOONGSON3_ENHANCEMENT)
+#if defined(CONFIG_CPU_CAVIUM_OCTEON) || defined(CONFIG_CPU_LOONGSON3)
 #define war_io_reorder_wmb()		wmb()
 #else
 #define war_io_reorder_wmb()		barrier()
diff --git a/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h b/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
index 3127391..cbac603 100644
--- a/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
@@ -11,6 +11,8 @@
 #ifndef __ASM_MACH_LOONGSON64_KERNEL_ENTRY_H
 #define __ASM_MACH_LOONGSON64_KERNEL_ENTRY_H
 
+#include <asm/cpu.h>
+
 /*
  * Override macros used in arch/mips/kernel/head.S.
  */
@@ -26,12 +28,15 @@
 	mfc0	t0, CP0_PAGEGRAIN
 	or	t0, (0x1 << 29)
 	mtc0	t0, CP0_PAGEGRAIN
-#ifdef CONFIG_LOONGSON3_ENHANCEMENT
 	/* Enable STFill Buffer */
+	mfc0	t0, CP0_PRID
+	andi	t0, (PRID_IMP_MASK | PRID_REV_MASK)
+	slti	t0, (PRID_IMP_LOONGSON_64 | PRID_REV_LOONGSON3A_R2)
+	bnez	t0, 1f
 	mfc0	t0, CP0_CONFIG6
 	or	t0, 0x100
 	mtc0	t0, CP0_CONFIG6
-#endif
+1:
 	_ehb
 	.set	pop
 #endif
@@ -52,12 +57,15 @@
 	mfc0	t0, CP0_PAGEGRAIN
 	or	t0, (0x1 << 29)
 	mtc0	t0, CP0_PAGEGRAIN
-#ifdef CONFIG_LOONGSON3_ENHANCEMENT
 	/* Enable STFill Buffer */
+	mfc0	t0, CP0_PRID
+	andi	t0, (PRID_IMP_MASK | PRID_REV_MASK)
+	slti	t0, (PRID_IMP_LOONGSON_64 | PRID_REV_LOONGSON3A_R2)
+	bnez	t0, 1f
 	mfc0	t0, CP0_CONFIG6
 	or	t0, 0x100
 	mtc0	t0, CP0_CONFIG6
-#endif
+1:
 	_ehb
 	.set	pop
 #endif
-- 
2.7.0

  reply	other threads:[~2018-09-05  9:33 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-09-05  9:33 [PATCH V4 00/10] MIPS: Loongson: new features and improvements Huacai Chen
2018-09-05  9:33 ` Huacai Chen [this message]
2018-09-05 16:54   ` [PATCH V4 01/10] MIPS: Loongson-3: Enable Store Fill Buffer at runtime Paul Burton
2018-09-06  1:33     ` Huacai Chen
2018-09-18 23:24       ` Paul Burton
2018-09-05  9:33 ` [PATCH 02/10] MIPS: c-r4k: Add r4k_blast_scache_node for Loongson-3 Huacai Chen
2018-09-26 21:47   ` Paul Burton
2018-09-27  7:25     ` Huacai Chen
2018-09-05  9:33 ` [PATCH V4 03/10] MIPS: Ensure pmd_present() returns false after pmd_mknotpresent() Huacai Chen
2018-09-05  9:33 ` [PATCH V4 04/10] MIPS: Add __cpu_full_name[] to make CPU names more human-readable Huacai Chen
2018-09-05  9:33 ` [PATCH V4 05/10] MIPS: Align kernel load address to 64KB Huacai Chen
2018-09-05  9:33 ` [PATCH V4 06/10] MIPS: Reserve extra memory for crash dump Huacai Chen
2018-09-05  9:33 ` [PATCH V4 07/10] MIPS: Loongson64: Add kexec/kdump support Huacai Chen
2018-09-05  9:33 ` [PATCH V4 08/10] MIPS: Loongson-3: Fix CPU UART irq delivery problem Huacai Chen
2018-09-05  9:33 ` [PATCH V4 09/10] MIPS: Loongson-3: Fix BRIDGE " Huacai Chen
2018-09-05  9:33 ` [PATCH V4 10/10] MIPS: Loongson: Introduce and use WAR_LLSC_MB Huacai Chen

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