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From: Paul Burton <paul.burton@mips.com>
To: Huacai Chen <chenhc@lemote.com>
Cc: Ralf Baechle <ralf@linux-mips.org>,
	James Hogan <jhogan@kernel.org>,
	Linux MIPS Mailing List <linux-mips@linux-mips.org>,
	Fuxin Zhang <zhangfx@lemote.com>,
	Zhangjin Wu <wuzhangjin@gmail.com>
Subject: Re: [PATCH V4 01/10] MIPS: Loongson-3: Enable Store Fill Buffer at runtime
Date: Tue, 18 Sep 2018 23:24:00 +0000	[thread overview]
Message-ID: <20180918232347.cla4bmdiq23qh3jk@pburton-laptop> (raw)
In-Reply-To: <CAAhV-H7vuFKK+H77EnF0P2ae50FMo0DeUniBLoTcagn4xO0QnA@mail.gmail.com>

Hi Huacai,

On Thu, Sep 06, 2018 at 09:33:15AM +0800, Huacai Chen wrote:
> On Thu, Sep 6, 2018 at 12:54 AM, Paul Burton <paul.burton@mips.com> wrote:
> > On Wed, Sep 05, 2018 at 05:33:01PM +0800, Huacai Chen wrote:
> >> New Loongson-3 (Loongson-3A R2, Loongson-3A R3, and newer) has SFB
> >> (Store Fill Buffer) which can improve the performance of memory access.
> >> Now, SFB enablement is controlled by CONFIG_LOONGSON3_ENHANCEMENT, and
> >> the generic kernel has no benefit from SFB (even it is running on a new
> >> Loongson-3 machine). With this patch, we can enable SFB at runtime by
> >> detecting the CPU type (the expense is war_io_reorder_wmb() will always
> >> be a 'sync', which will hurt the performance of old Loongson-3).
> >
> > This looks unchanged since v3, and I didn't see a response to my email
> > here:
> >
> >     https://marc.info/?l=linux-mips&m=153248530725061&w=2
> >
> > I still haven't seen any explanation for why you can't just do this as a
> > one-liner in C, the same way we enable tons of other CPU features during
> > cpu_probe().
> >
> > I'm not saying I'll never accept the assembly version, but I want an
> > explanation for why it's necessary first. If that's not something you
> > can give, at least describe in the commit message what goes wrong when
> > you try to do it in C as justification for not doing it that way.
>
> In practise, I found that sometimes there are boot failures if I
> enable SFB/LPA in cpu_probe(). I don't know why because processorr
> designers also haven't give me an explaination, but I think this may
> have some relationships to speculative execution.

OK, applied to mips-next for 4.20 with that noted in the commit message.

Thanks,
    Paul

  reply	other threads:[~2018-09-18 23:24 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-09-05  9:33 [PATCH V4 00/10] MIPS: Loongson: new features and improvements Huacai Chen
2018-09-05  9:33 ` [PATCH V4 01/10] MIPS: Loongson-3: Enable Store Fill Buffer at runtime Huacai Chen
2018-09-05 16:54   ` Paul Burton
2018-09-06  1:33     ` Huacai Chen
2018-09-18 23:24       ` Paul Burton [this message]
2018-09-05  9:33 ` [PATCH 02/10] MIPS: c-r4k: Add r4k_blast_scache_node for Loongson-3 Huacai Chen
2018-09-26 21:47   ` Paul Burton
2018-09-27  7:25     ` Huacai Chen
2018-09-05  9:33 ` [PATCH V4 03/10] MIPS: Ensure pmd_present() returns false after pmd_mknotpresent() Huacai Chen
2018-09-05  9:33 ` [PATCH V4 04/10] MIPS: Add __cpu_full_name[] to make CPU names more human-readable Huacai Chen
2018-09-05  9:33 ` [PATCH V4 05/10] MIPS: Align kernel load address to 64KB Huacai Chen
2018-09-05  9:33 ` [PATCH V4 06/10] MIPS: Reserve extra memory for crash dump Huacai Chen
2018-09-05  9:33 ` [PATCH V4 07/10] MIPS: Loongson64: Add kexec/kdump support Huacai Chen
2018-09-05  9:33 ` [PATCH V4 08/10] MIPS: Loongson-3: Fix CPU UART irq delivery problem Huacai Chen
2018-09-05  9:33 ` [PATCH V4 09/10] MIPS: Loongson-3: Fix BRIDGE " Huacai Chen
2018-09-05  9:33 ` [PATCH V4 10/10] MIPS: Loongson: Introduce and use WAR_LLSC_MB Huacai Chen

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